drivers/net/cxgbe/cxgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_bus_pci.h>
  24 #include <rte_atomic.h>
  25 #include <rte_branch_prediction.h>
  26 #include <rte_memory.h>
  27 #include <rte_tailq.h>
  28 #include <rte_eal.h>
  29 #include <rte_alarm.h>
  30 #include <rte_ether.h>
  31 #include <rte_ethdev_driver.h>
  32 #include <rte_ethdev_pci.h>
  33 #include <rte_malloc.h>
  34 #include <rte_random.h>
  35 #include <rte_dev.h>
  36
  37 #include "cxgbe.h"
  38 #include "cxgbe_pfvf.h"
  39 #include "cxgbe_flow.h"
  40
  41 /*
  42  * Macros needed to support the PCI Device ID Table ...
  43  */
  44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
  45         static const struct rte_pci_id cxgb4_pci_tbl[] = {
  46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
  47
  48 #define PCI_VENDOR_ID_CHELSIO 0x1425
  49
  50 #define CH_PCI_ID_TABLE_ENTRY(devid) \
  51                 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
  52
  53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
  54                 { .vendor_id = 0, } \
  55         }
  56
  57 /*
  58  *... and the PCI ID Table itself ...
  59  */
  60 #include "base/t4_pci_id_tbl.h"
  61
  62 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
  63                          uint16_t nb_pkts)
  64 {
  65         struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
  66         uint16_t pkts_sent, pkts_remain;
  67         uint16_t total_sent = 0;
  68         uint16_t idx = 0;
  69         int ret = 0;
  70
  71         t4_os_lock(&txq->txq_lock);
  72         /* free up desc from already completed tx */
  73         reclaim_completed_tx(&txq->q);
  74         if (unlikely(!nb_pkts))
  75                 goto out_unlock;
  76
  77         rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *));
  78         while (total_sent < nb_pkts) {
  79                 pkts_remain = nb_pkts - total_sent;
  80
  81                 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
  82                         idx = total_sent + pkts_sent;
  83                         if ((idx + 1) < nb_pkts)
  84                                 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1],
  85                                                         volatile void *));
  86                         ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts);
  87                         if (ret < 0)
  88                                 break;
  89                 }
  90                 if (!pkts_sent)
  91                         break;
  92                 total_sent += pkts_sent;
  93                 /* reclaim as much as possible */
  94                 reclaim_completed_tx(&txq->q);
  95         }
  96
  97 out_unlock:
  98         t4_os_unlock(&txq->txq_lock);
  99         return total_sent;
 100 }
 101
 102 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 103                          uint16_t nb_pkts)
 104 {
 105         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
 106         unsigned int work_done;
 107
 108         if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
 109                 dev_err(adapter, "error in cxgbe poll\n");
 110
 111         return work_done;
 112 }
 113
 114 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
 115                         struct rte_eth_dev_info *device_info)
 116 {
 117         struct port_info *pi = eth_dev->data->dev_private;
 118         struct adapter *adapter = pi->adapter;
 119
 120         static const struct rte_eth_desc_lim cxgbe_desc_lim = {
 121                 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
 122                 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
 123                 .nb_align = 1,
 124         };
 125
 126         device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
 127         device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
 128         device_info->max_rx_queues = adapter->sge.max_ethqsets;
 129         device_info->max_tx_queues = adapter->sge.max_ethqsets;
 130         device_info->max_mac_addrs = 1;
 131         /* XXX: For now we support one MAC/port */
 132         device_info->max_vfs = adapter->params.arch.vfcount;
 133         device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
 134
 135         device_info->rx_queue_offload_capa = 0UL;
 136         device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
 137
 138         device_info->tx_queue_offload_capa = 0UL;
 139         device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
 140
 141         device_info->reta_size = pi->rss_size;
 142         device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
 143         device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
 144
 145         device_info->rx_desc_lim = cxgbe_desc_lim;
 146         device_info->tx_desc_lim = cxgbe_desc_lim;
 147         cxgbe_get_speed_caps(pi, &device_info->speed_capa);
 148
 149         return 0;
 150 }
 151
 152 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
 153 {
 154         struct port_info *pi = eth_dev->data->dev_private;
 155         struct adapter *adapter = pi->adapter;
 156
 157         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 158                              1, -1, 1, -1, false);
 159 }
 160
 161 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
 162 {
 163         struct port_info *pi = eth_dev->data->dev_private;
 164         struct adapter *adapter = pi->adapter;
 165
 166         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 167                              0, -1, 1, -1, false);
 168 }
 169
 170 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
 171 {
 172         struct port_info *pi = eth_dev->data->dev_private;
 173         struct adapter *adapter = pi->adapter;
 174
 175         /* TODO: address filters ?? */
 176
 177         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 178                              -1, 1, 1, -1, false);
 179 }
 180
 181 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
 182 {
 183         struct port_info *pi = eth_dev->data->dev_private;
 184         struct adapter *adapter = pi->adapter;
 185
 186         /* TODO: address filters ?? */
 187
 188         return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
 189                              -1, 0, 1, -1, false);
 190 }
 191
 192 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
 193                           int wait_to_complete)
 194 {
 195         struct port_info *pi = eth_dev->data->dev_private;
 196         struct adapter *adapter = pi->adapter;
 197         struct sge *s = &adapter->sge;
 198         struct rte_eth_link new_link = { 0 };
 199         unsigned int i, work_done, budget = 32;
 200         u8 old_link = pi->link_cfg.link_ok;
 201
 202         for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) {
 203                 if (!s->fw_evtq.desc)
 204                         break;
 205
 206                 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 207
 208                 /* Exit if link status changed or always forced up */
 209                 if (pi->link_cfg.link_ok != old_link ||
 210                     cxgbe_force_linkup(adapter))
 211                         break;
 212
 213                 if (!wait_to_complete)
 214                         break;
 215
 216                 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS);
 217         }
 218
 219         new_link.link_status = cxgbe_force_linkup(adapter) ?
 220                                ETH_LINK_UP : pi->link_cfg.link_ok;
 221         new_link.link_autoneg = pi->link_cfg.autoneg;
 222         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
 223         new_link.link_speed = pi->link_cfg.speed;
 224
 225         return rte_eth_linkstatus_set(eth_dev, &new_link);
 226 }
 227
 228 /**
 229  * Set device link up.
 230  */
 231 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev)
 232 {
 233         struct port_info *pi = dev->data->dev_private;
 234         struct adapter *adapter = pi->adapter;
 235         unsigned int work_done, budget = 32;
 236         struct sge *s = &adapter->sge;
 237         int ret;
 238
 239         if (!s->fw_evtq.desc)
 240                 return -ENOMEM;
 241
 242         /* Flush all link events */
 243         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 244
 245         /* If link already up, nothing to do */
 246         if (pi->link_cfg.link_ok)
 247                 return 0;
 248
 249         ret = cxgbe_set_link_status(pi, true);
 250         if (ret)
 251                 return ret;
 252
 253         cxgbe_dev_link_update(dev, 1);
 254         return 0;
 255 }
 256
 257 /**
 258  * Set device link down.
 259  */
 260 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev)
 261 {
 262         struct port_info *pi = dev->data->dev_private;
 263         struct adapter *adapter = pi->adapter;
 264         unsigned int work_done, budget = 32;
 265         struct sge *s = &adapter->sge;
 266         int ret;
 267
 268         if (!s->fw_evtq.desc)
 269                 return -ENOMEM;
 270
 271         /* Flush all link events */
 272         cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
 273
 274         /* If link already down, nothing to do */
 275         if (!pi->link_cfg.link_ok)
 276                 return 0;
 277
 278         ret = cxgbe_set_link_status(pi, false);
 279         if (ret)
 280                 return ret;
 281
 282         cxgbe_dev_link_update(dev, 0);
 283         return 0;
 284 }
 285
 286 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
 287 {
 288         struct port_info *pi = eth_dev->data->dev_private;
 289         struct adapter *adapter = pi->adapter;
 290         struct rte_eth_dev_info dev_info;
 291         int err;
 292         uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
 293
 294         err = cxgbe_dev_info_get(eth_dev, &dev_info);
 295         if (err != 0)
 296                 return err;
 297
 298         /* Must accommodate at least RTE_ETHER_MIN_MTU */
 299         if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen)
 300                 return -EINVAL;
 301
 302         /* set to jumbo mode if needed */
 303         if (new_mtu > RTE_ETHER_MAX_LEN)
 304                 eth_dev->data->dev_conf.rxmode.offloads |=
 305                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 306         else
 307                 eth_dev->data->dev_conf.rxmode.offloads &=
 308                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 309
 310         err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
 311                             -1, -1, true);
 312         if (!err)
 313                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
 314
 315         return err;
 316 }
 317
 318 /*
 319  * Stop device.
 320  */
 321 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
 322 {
 323         struct port_info *temp_pi, *pi = eth_dev->data->dev_private;
 324         struct adapter *adapter = pi->adapter;
 325         u8 i;
 326
 327         CXGBE_FUNC_TRACE();
 328
 329         if (!(adapter->flags & FULL_INIT_DONE))
 330                 return;
 331
 332         if (!pi->viid)
 333                 return;
 334
 335         cxgbe_down(pi);
 336         t4_sge_eth_release_queues(pi);
 337         t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid);
 338         pi->viid = 0;
 339
 340         /* Free up the adapter-wide resources only after all the ports
 341          * under this PF have been closed.
 342          */
 343         for_each_port(adapter, i) {
 344                 temp_pi = adap2pinfo(adapter, i);
 345                 if (temp_pi->viid)
 346                         return;
 347         }
 348
 349         cxgbe_close(adapter);
 350         rte_free(adapter);
 351 }
 352
 353 /* Start the device.
 354  * It returns 0 on success.
 355  */
 356 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
 357 {
 358         struct port_info *pi = eth_dev->data->dev_private;
 359         struct rte_eth_rxmode *rx_conf = &eth_dev->data->dev_conf.rxmode;
 360         struct adapter *adapter = pi->adapter;
 361         int err = 0, i;
 362
 363         CXGBE_FUNC_TRACE();
 364
 365         /*
 366          * If we don't have a connection to the firmware there's nothing we
 367          * can do.
 368          */
 369         if (!(adapter->flags & FW_OK)) {
 370                 err = -ENXIO;
 371                 goto out;
 372         }
 373
 374         if (!(adapter->flags & FULL_INIT_DONE)) {
 375                 err = cxgbe_up(adapter);
 376                 if (err < 0)
 377                         goto out;
 378         }
 379
 380         if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER)
 381                 eth_dev->data->scattered_rx = 1;
 382         else
 383                 eth_dev->data->scattered_rx = 0;
 384
 385         cxgbe_enable_rx_queues(pi);
 386
 387         err = cxgbe_setup_rss(pi);
 388         if (err)
 389                 goto out;
 390
 391         for (i = 0; i < pi->n_tx_qsets; i++) {
 392                 err = cxgbe_dev_tx_queue_start(eth_dev, i);
 393                 if (err)
 394                         goto out;
 395         }
 396
 397         for (i = 0; i < pi->n_rx_qsets; i++) {
 398                 err = cxgbe_dev_rx_queue_start(eth_dev, i);
 399                 if (err)
 400                         goto out;
 401         }
 402
 403         err = cxgbe_link_start(pi);
 404         if (err)
 405                 goto out;
 406
 407 out:
 408         return err;
 409 }
 410
 411 /*
 412  * Stop device: disable rx and tx functions to allow for reconfiguring.
 413  */
 414 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
 415 {
 416         struct port_info *pi = eth_dev->data->dev_private;
 417         struct adapter *adapter = pi->adapter;
 418
 419         CXGBE_FUNC_TRACE();
 420
 421         if (!(adapter->flags & FULL_INIT_DONE))
 422                 return;
 423
 424         cxgbe_down(pi);
 425
 426         /*
 427          *  We clear queues only if both tx and rx path of the port
 428          *  have been disabled
 429          */
 430         t4_sge_eth_clear_queues(pi);
 431         eth_dev->data->scattered_rx = 0;
 432 }
 433
 434 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
 435 {
 436         struct port_info *pi = eth_dev->data->dev_private;
 437         struct adapter *adapter = pi->adapter;
 438         int err;
 439
 440         CXGBE_FUNC_TRACE();
 441
 442         if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 443                 eth_dev->data->dev_conf.rxmode.offloads |=
 444                         DEV_RX_OFFLOAD_RSS_HASH;
 445
 446         if (!(adapter->flags & FW_QUEUE_BOUND)) {
 447                 err = cxgbe_setup_sge_fwevtq(adapter);
 448                 if (err)
 449                         return err;
 450                 adapter->flags |= FW_QUEUE_BOUND;
 451                 if (is_pf4(adapter)) {
 452                         err = cxgbe_setup_sge_ctrl_txq(adapter);
 453                         if (err)
 454                                 return err;
 455                 }
 456         }
 457
 458         err = cxgbe_cfg_queue_count(eth_dev);
 459         if (err)
 460                 return err;
 461
 462         return 0;
 463 }
 464
 465 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 466 {
 467         int ret;
 468         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 469                                   (eth_dev->data->tx_queues[tx_queue_id]);
 470
 471         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 472
 473         ret = t4_sge_eth_txq_start(txq);
 474         if (ret == 0)
 475                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 476
 477         return ret;
 478 }
 479
 480 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 481 {
 482         int ret;
 483         struct sge_eth_txq *txq = (struct sge_eth_txq *)
 484                                   (eth_dev->data->tx_queues[tx_queue_id]);
 485
 486         dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
 487
 488         ret = t4_sge_eth_txq_stop(txq);
 489         if (ret == 0)
 490                 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 491
 492         return ret;
 493 }
 494
 495 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
 496                              uint16_t queue_idx, uint16_t nb_desc,
 497                              unsigned int socket_id,
 498                              const struct rte_eth_txconf *tx_conf __rte_unused)
 499 {
 500         struct port_info *pi = eth_dev->data->dev_private;
 501         struct adapter *adapter = pi->adapter;
 502         struct sge *s = &adapter->sge;
 503         unsigned int temp_nb_desc;
 504         struct sge_eth_txq *txq;
 505         int err = 0;
 506
 507         txq = &s->ethtxq[pi->first_txqset + queue_idx];
 508         dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
 509                   __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
 510                   socket_id, pi->first_txqset);
 511
 512         /*  Free up the existing queue  */
 513         if (eth_dev->data->tx_queues[queue_idx]) {
 514                 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
 515                 eth_dev->data->tx_queues[queue_idx] = NULL;
 516         }
 517
 518         eth_dev->data->tx_queues[queue_idx] = (void *)txq;
 519
 520         /* Sanity Checking
 521          *
 522          * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
 523          */
 524         temp_nb_desc = nb_desc;
 525         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 526                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 527                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 528                          CXGBE_DEFAULT_TX_DESC_SIZE);
 529                 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
 530         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 531                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 532                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 533                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
 534                 return -(EINVAL);
 535         }
 536
 537         txq->q.size = temp_nb_desc;
 538
 539         err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
 540                                    s->fw_evtq.cntxt_id, socket_id);
 541
 542         dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
 543                   __func__, txq->q.cntxt_id, txq->q.abs_id, err);
 544         return err;
 545 }
 546
 547 void cxgbe_dev_tx_queue_release(void *q)
 548 {
 549         struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
 550
 551         if (txq) {
 552                 struct port_info *pi = (struct port_info *)
 553                                        (txq->eth_dev->data->dev_private);
 554                 struct adapter *adap = pi->adapter;
 555
 556                 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
 557                           __func__, pi->port_id, txq->q.cntxt_id);
 558
 559                 t4_sge_eth_txq_release(adap, txq);
 560         }
 561 }
 562
 563 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 564 {
 565         int ret;
 566         struct port_info *pi = eth_dev->data->dev_private;
 567         struct adapter *adap = pi->adapter;
 568         struct sge_rspq *q;
 569
 570         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 571                   __func__, pi->port_id, rx_queue_id);
 572
 573         q = eth_dev->data->rx_queues[rx_queue_id];
 574
 575         ret = t4_sge_eth_rxq_start(adap, q);
 576         if (ret == 0)
 577                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 578
 579         return ret;
 580 }
 581
 582 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 583 {
 584         int ret;
 585         struct port_info *pi = eth_dev->data->dev_private;
 586         struct adapter *adap = pi->adapter;
 587         struct sge_rspq *q;
 588
 589         dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 590                   __func__, pi->port_id, rx_queue_id);
 591
 592         q = eth_dev->data->rx_queues[rx_queue_id];
 593         ret = t4_sge_eth_rxq_stop(adap, q);
 594         if (ret == 0)
 595                 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 596
 597         return ret;
 598 }
 599
 600 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
 601                              uint16_t queue_idx, uint16_t nb_desc,
 602                              unsigned int socket_id,
 603                              const struct rte_eth_rxconf *rx_conf __rte_unused,
 604                              struct rte_mempool *mp)
 605 {
 606         unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
 607         struct port_info *pi = eth_dev->data->dev_private;
 608         struct adapter *adapter = pi->adapter;
 609         struct rte_eth_dev_info dev_info;
 610         struct sge *s = &adapter->sge;
 611         unsigned int temp_nb_desc;
 612         int err = 0, msi_idx = 0;
 613         struct sge_eth_rxq *rxq;
 614
 615         rxq = &s->ethrxq[pi->first_rxqset + queue_idx];
 616         dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
 617                   __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
 618                   socket_id, mp);
 619
 620         err = cxgbe_dev_info_get(eth_dev, &dev_info);
 621         if (err != 0) {
 622                 dev_err(adap, "%s: error during getting ethernet device info",
 623                         __func__);
 624                 return err;
 625         }
 626
 627         /* Must accommodate at least RTE_ETHER_MIN_MTU */
 628         if ((pkt_len < dev_info.min_rx_bufsize) ||
 629             (pkt_len > dev_info.max_rx_pktlen)) {
 630                 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
 631                         __func__, dev_info.min_rx_bufsize,
 632                         dev_info.max_rx_pktlen);
 633                 return -EINVAL;
 634         }
 635
 636         /*  Free up the existing queue  */
 637         if (eth_dev->data->rx_queues[queue_idx]) {
 638                 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
 639                 eth_dev->data->rx_queues[queue_idx] = NULL;
 640         }
 641
 642         eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
 643
 644         /* Sanity Checking
 645          *
 646          * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
 647          */
 648         temp_nb_desc = nb_desc;
 649         if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
 650                 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
 651                          __func__, CXGBE_MIN_RING_DESC_SIZE,
 652                          CXGBE_DEFAULT_RX_DESC_SIZE);
 653                 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
 654         } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
 655                 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
 656                         __func__, CXGBE_MIN_RING_DESC_SIZE,
 657                         CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
 658                 return -(EINVAL);
 659         }
 660
 661         rxq->rspq.size = temp_nb_desc;
 662         if ((&rxq->fl) != NULL)
 663                 rxq->fl.size = temp_nb_desc;
 664
 665         /* Set to jumbo mode if necessary */
 666         if (pkt_len > RTE_ETHER_MAX_LEN)
 667                 eth_dev->data->dev_conf.rxmode.offloads |=
 668                         DEV_RX_OFFLOAD_JUMBO_FRAME;
 669         else
 670                 eth_dev->data->dev_conf.rxmode.offloads &=
 671                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 672
 673         err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
 674                                &rxq->fl, NULL,
 675                                is_pf4(adapter) ?
 676                                t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
 677                                queue_idx, socket_id);
 678
 679         dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
 680                   __func__, err, pi->port_id, rxq->rspq.cntxt_id,
 681                   rxq->rspq.abs_id);
 682         return err;
 683 }
 684
 685 void cxgbe_dev_rx_queue_release(void *q)
 686 {
 687         struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
 688
 689         if (rxq) {
 690                 struct port_info *pi = (struct port_info *)
 691                                        (rxq->rspq.eth_dev->data->dev_private);
 692                 struct adapter *adap = pi->adapter;
 693
 694                 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
 695                           __func__, pi->port_id, rxq->rspq.cntxt_id);
 696
 697                 t4_sge_eth_rxq_release(adap, rxq);
 698         }
 699 }
 700
 701 /*
 702  * Get port statistics.
 703  */
 704 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
 705                                 struct rte_eth_stats *eth_stats)
 706 {
 707         struct port_info *pi = eth_dev->data->dev_private;
 708         struct adapter *adapter = pi->adapter;
 709         struct sge *s = &adapter->sge;
 710         struct port_stats ps;
 711         unsigned int i;
 712
 713         cxgbe_stats_get(pi, &ps);
 714
 715         /* RX Stats */
 716         eth_stats->imissed  = ps.rx_ovflow0 + ps.rx_ovflow1 +
 717                               ps.rx_ovflow2 + ps.rx_ovflow3 +
 718                               ps.rx_trunc0 + ps.rx_trunc1 +
 719                               ps.rx_trunc2 + ps.rx_trunc3;
 720         eth_stats->ierrors  = ps.rx_symbol_err + ps.rx_fcs_err +
 721                               ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
 722                               ps.rx_len_err;
 723
 724         /* TX Stats */
 725         eth_stats->opackets = ps.tx_frames;
 726         eth_stats->obytes   = ps.tx_octets;
 727         eth_stats->oerrors  = ps.tx_error_frames;
 728
 729         for (i = 0; i < pi->n_rx_qsets; i++) {
 730                 struct sge_eth_rxq *rxq =
 731                         &s->ethrxq[pi->first_rxqset + i];
 732
 733                 eth_stats->q_ipackets[i] = rxq->stats.pkts;
 734                 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
 735                 eth_stats->ipackets += eth_stats->q_ipackets[i];
 736                 eth_stats->ibytes += eth_stats->q_ibytes[i];
 737         }
 738
 739         for (i = 0; i < pi->n_tx_qsets; i++) {
 740                 struct sge_eth_txq *txq =
 741                         &s->ethtxq[pi->first_txqset + i];
 742
 743                 eth_stats->q_opackets[i] = txq->stats.pkts;
 744                 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
 745         }
 746         return 0;
 747 }
 748
 749 /*
 750  * Reset port statistics.
 751  */
 752 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
 753 {
 754         struct port_info *pi = eth_dev->data->dev_private;
 755         struct adapter *adapter = pi->adapter;
 756         struct sge *s = &adapter->sge;
 757         unsigned int i;
 758
 759         cxgbe_stats_reset(pi);
 760         for (i = 0; i < pi->n_rx_qsets; i++) {
 761                 struct sge_eth_rxq *rxq =
 762                         &s->ethrxq[pi->first_rxqset + i];
 763
 764                 rxq->stats.pkts = 0;
 765                 rxq->stats.rx_bytes = 0;
 766         }
 767         for (i = 0; i < pi->n_tx_qsets; i++) {
 768                 struct sge_eth_txq *txq =
 769                         &s->ethtxq[pi->first_txqset + i];
 770
 771                 txq->stats.pkts = 0;
 772                 txq->stats.tx_bytes = 0;
 773                 txq->stats.mapping_err = 0;
 774         }
 775
 776         return 0;
 777 }
 778
 779 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 780                                struct rte_eth_fc_conf *fc_conf)
 781 {
 782         struct port_info *pi = eth_dev->data->dev_private;
 783         struct link_config *lc = &pi->link_cfg;
 784         int rx_pause, tx_pause;
 785
 786         fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
 787         rx_pause = lc->fc & PAUSE_RX;
 788         tx_pause = lc->fc & PAUSE_TX;
 789
 790         if (rx_pause && tx_pause)
 791                 fc_conf->mode = RTE_FC_FULL;
 792         else if (rx_pause)
 793                 fc_conf->mode = RTE_FC_RX_PAUSE;
 794         else if (tx_pause)
 795                 fc_conf->mode = RTE_FC_TX_PAUSE;
 796         else
 797                 fc_conf->mode = RTE_FC_NONE;
 798         return 0;
 799 }
 800
 801 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 802                                struct rte_eth_fc_conf *fc_conf)
 803 {
 804         struct port_info *pi = eth_dev->data->dev_private;
 805         struct adapter *adapter = pi->adapter;
 806         struct link_config *lc = &pi->link_cfg;
 807
 808         if (lc->pcaps & FW_PORT_CAP32_ANEG) {
 809                 if (fc_conf->autoneg)
 810                         lc->requested_fc |= PAUSE_AUTONEG;
 811                 else
 812                         lc->requested_fc &= ~PAUSE_AUTONEG;
 813         }
 814
 815         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 816             (fc_conf->mode & RTE_FC_RX_PAUSE))
 817                 lc->requested_fc |= PAUSE_RX;
 818         else
 819                 lc->requested_fc &= ~PAUSE_RX;
 820
 821         if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
 822             (fc_conf->mode & RTE_FC_TX_PAUSE))
 823                 lc->requested_fc |= PAUSE_TX;
 824         else
 825                 lc->requested_fc &= ~PAUSE_TX;
 826
 827         return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 828                              &pi->link_cfg);
 829 }
 830
 831 const uint32_t *
 832 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 833 {
 834         static const uint32_t ptypes[] = {
 835                 RTE_PTYPE_L3_IPV4,
 836                 RTE_PTYPE_L3_IPV6,
 837                 RTE_PTYPE_UNKNOWN
 838         };
 839
 840         if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
 841                 return ptypes;
 842         return NULL;
 843 }
 844
 845 /* Update RSS hash configuration
 846  */
 847 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
 848                                      struct rte_eth_rss_conf *rss_conf)
 849 {
 850         struct port_info *pi = dev->data->dev_private;
 851         struct adapter *adapter = pi->adapter;
 852         int err;
 853
 854         err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
 855         if (err)
 856                 return err;
 857
 858         pi->rss_hf = rss_conf->rss_hf;
 859
 860         if (rss_conf->rss_key) {
 861                 u32 key[10], mod_key[10];
 862                 int i, j;
 863
 864                 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 865
 866                 for (i = 9, j = 0; i >= 0; i--, j++)
 867                         mod_key[j] = cpu_to_be32(key[i]);
 868
 869                 t4_write_rss_key(adapter, mod_key, -1);
 870         }
 871
 872         return 0;
 873 }
 874
 875 /* Get RSS hash configuration
 876  */
 877 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 878                                        struct rte_eth_rss_conf *rss_conf)
 879 {
 880         struct port_info *pi = dev->data->dev_private;
 881         struct adapter *adapter = pi->adapter;
 882         u64 rss_hf = 0;
 883         u64 flags = 0;
 884         int err;
 885
 886         err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
 887                                     &flags, NULL);
 888
 889         if (err)
 890                 return err;
 891
 892         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
 893                 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK;
 894                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 895                         rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK;
 896         }
 897
 898         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
 899                 rss_hf |= CXGBE_RSS_HF_IPV6_MASK;
 900
 901         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
 902                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
 903                 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
 904                         rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
 905         }
 906
 907         if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
 908                 rss_hf |= CXGBE_RSS_HF_IPV4_MASK;
 909
 910         rss_conf->rss_hf = rss_hf;
 911
 912         if (rss_conf->rss_key) {
 913                 u32 key[10], mod_key[10];
 914                 int i, j;
 915
 916                 t4_read_rss_key(adapter, key);
 917
 918                 for (i = 9, j = 0; i >= 0; i--, j++)
 919                         mod_key[j] = be32_to_cpu(key[i]);
 920
 921                 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
 922         }
 923
 924         return 0;
 925 }
 926
 927 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
 928 {
 929         RTE_SET_USED(dev);
 930         return EEPROMSIZE;
 931 }
 932
 933 /**
 934  * eeprom_ptov - translate a physical EEPROM address to virtual
 935  * @phys_addr: the physical EEPROM address
 936  * @fn: the PCI function number
 937  * @sz: size of function-specific area
 938  *
 939  * Translate a physical EEPROM address to virtual.  The first 1K is
 940  * accessed through virtual addresses starting at 31K, the rest is
 941  * accessed through virtual addresses starting at 0.
 942  *
 943  * The mapping is as follows:
 944  * [0..1K) -> [31K..32K)
 945  * [1K..1K+A) -> [31K-A..31K)
 946  * [1K+A..ES) -> [0..ES-A-1K)
 947  *
 948  * where A = @fn * @sz, and ES = EEPROM size.
 949  */
 950 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
 951 {
 952         fn *= sz;
 953         if (phys_addr < 1024)
 954                 return phys_addr + (31 << 10);
 955         if (phys_addr < 1024 + fn)
 956                 return fn + phys_addr - 1024;
 957         if (phys_addr < EEPROMSIZE)
 958                 return phys_addr - 1024 - fn;
 959         if (phys_addr < EEPROMVSIZE)
 960                 return phys_addr - 1024;
 961         return -EINVAL;
 962 }
 963
 964 /* The next two routines implement eeprom read/write from physical addresses.
 965  */
 966 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
 967 {
 968         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 969
 970         if (vaddr >= 0)
 971                 vaddr = t4_seeprom_read(adap, vaddr, v);
 972         return vaddr < 0 ? vaddr : 0;
 973 }
 974
 975 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
 976 {
 977         int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
 978
 979         if (vaddr >= 0)
 980                 vaddr = t4_seeprom_write(adap, vaddr, v);
 981         return vaddr < 0 ? vaddr : 0;
 982 }
 983
 984 #define EEPROM_MAGIC 0x38E2F10C
 985
 986 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
 987                             struct rte_dev_eeprom_info *e)
 988 {
 989         struct port_info *pi = dev->data->dev_private;
 990         struct adapter *adapter = pi->adapter;
 991         u32 i, err = 0;
 992         u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
 993
 994         if (!buf)
 995                 return -ENOMEM;
 996
 997         e->magic = EEPROM_MAGIC;
 998         for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
 999                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
1000
1001         if (!err)
1002                 rte_memcpy(e->data, buf + e->offset, e->length);
1003         rte_free(buf);
1004         return err;
1005 }
1006
1007 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
1008                             struct rte_dev_eeprom_info *eeprom)
1009 {
1010         struct port_info *pi = dev->data->dev_private;
1011         struct adapter *adapter = pi->adapter;
1012         u8 *buf;
1013         int err = 0;
1014         u32 aligned_offset, aligned_len, *p;
1015
1016         if (eeprom->magic != EEPROM_MAGIC)
1017                 return -EINVAL;
1018
1019         aligned_offset = eeprom->offset & ~3;
1020         aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
1021
1022         if (adapter->pf > 0) {
1023                 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
1024
1025                 if (aligned_offset < start ||
1026                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
1027                         return -EPERM;
1028         }
1029
1030         if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
1031                 /* RMW possibly needed for first or last words.
1032                  */
1033                 buf = rte_zmalloc(NULL, aligned_len, 0);
1034                 if (!buf)
1035                         return -ENOMEM;
1036                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
1037                 if (!err && aligned_len > 4)
1038                         err = eeprom_rd_phys(adapter,
1039                                              aligned_offset + aligned_len - 4,
1040                                              (u32 *)&buf[aligned_len - 4]);
1041                 if (err)
1042                         goto out;
1043                 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
1044                            eeprom->length);
1045         } else {
1046                 buf = eeprom->data;
1047         }
1048
1049         err = t4_seeprom_wp(adapter, false);
1050         if (err)
1051                 goto out;
1052
1053         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
1054                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
1055                 aligned_offset += 4;
1056         }
1057
1058         if (!err)
1059                 err = t4_seeprom_wp(adapter, true);
1060 out:
1061         if (buf != eeprom->data)
1062                 rte_free(buf);
1063         return err;
1064 }
1065
1066 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
1067 {
1068         struct port_info *pi = eth_dev->data->dev_private;
1069         struct adapter *adapter = pi->adapter;
1070
1071         return t4_get_regs_len(adapter) / sizeof(uint32_t);
1072 }
1073
1074 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
1075                           struct rte_dev_reg_info *regs)
1076 {
1077         struct port_info *pi = eth_dev->data->dev_private;
1078         struct adapter *adapter = pi->adapter;
1079
1080         regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1081                 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1082                 (1 << 16);
1083
1084         if (regs->data == NULL) {
1085                 regs->length = cxgbe_get_regs_len(eth_dev);
1086                 regs->width = sizeof(uint32_t);
1087
1088                 return 0;
1089         }
1090
1091         t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1092
1093         return 0;
1094 }
1095
1096 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
1097 {
1098         struct port_info *pi = dev->data->dev_private;
1099         int ret;
1100
1101         ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr);
1102         if (ret < 0) {
1103                 dev_err(adapter, "failed to set mac addr; err = %d\n",
1104                         ret);
1105                 return ret;
1106         }
1107         pi->xact_addr_filt = ret;
1108         return 0;
1109 }
1110
1111 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1112         .dev_start              = cxgbe_dev_start,
1113         .dev_stop               = cxgbe_dev_stop,
1114         .dev_close              = cxgbe_dev_close,
1115         .promiscuous_enable     = cxgbe_dev_promiscuous_enable,
1116         .promiscuous_disable    = cxgbe_dev_promiscuous_disable,
1117         .allmulticast_enable    = cxgbe_dev_allmulticast_enable,
1118         .allmulticast_disable   = cxgbe_dev_allmulticast_disable,
1119         .dev_configure          = cxgbe_dev_configure,
1120         .dev_infos_get          = cxgbe_dev_info_get,
1121         .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1122         .link_update            = cxgbe_dev_link_update,
1123         .dev_set_link_up        = cxgbe_dev_set_link_up,
1124         .dev_set_link_down      = cxgbe_dev_set_link_down,
1125         .mtu_set                = cxgbe_dev_mtu_set,
1126         .tx_queue_setup         = cxgbe_dev_tx_queue_setup,
1127         .tx_queue_start         = cxgbe_dev_tx_queue_start,
1128         .tx_queue_stop          = cxgbe_dev_tx_queue_stop,
1129         .tx_queue_release       = cxgbe_dev_tx_queue_release,
1130         .rx_queue_setup         = cxgbe_dev_rx_queue_setup,
1131         .rx_queue_start         = cxgbe_dev_rx_queue_start,
1132         .rx_queue_stop          = cxgbe_dev_rx_queue_stop,
1133         .rx_queue_release       = cxgbe_dev_rx_queue_release,
1134         .filter_ctrl            = cxgbe_dev_filter_ctrl,
1135         .stats_get              = cxgbe_dev_stats_get,
1136         .stats_reset            = cxgbe_dev_stats_reset,
1137         .flow_ctrl_get          = cxgbe_flow_ctrl_get,
1138         .flow_ctrl_set          = cxgbe_flow_ctrl_set,
1139         .get_eeprom_length      = cxgbe_get_eeprom_length,
1140         .get_eeprom             = cxgbe_get_eeprom,
1141         .set_eeprom             = cxgbe_set_eeprom,
1142         .get_reg                = cxgbe_get_regs,
1143         .rss_hash_update        = cxgbe_dev_rss_hash_update,
1144         .rss_hash_conf_get      = cxgbe_dev_rss_hash_conf_get,
1145         .mac_addr_set           = cxgbe_mac_addr_set,
1146 };
1147
1148 /*
1149  * Initialize driver
1150  * It returns 0 on success.
1151  */
1152 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1153 {
1154         struct rte_pci_device *pci_dev;
1155         struct port_info *pi = eth_dev->data->dev_private;
1156         struct adapter *adapter = NULL;
1157         char name[RTE_ETH_NAME_MAX_LEN];
1158         int err = 0;
1159
1160         CXGBE_FUNC_TRACE();
1161
1162         eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1163         eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1164         eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1165         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1166
1167         /* for secondary processes, we attach to ethdevs allocated by primary
1168          * and do minimal initialization.
1169          */
1170         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1171                 int i;
1172
1173                 for (i = 1; i < MAX_NPORTS; i++) {
1174                         struct rte_eth_dev *rest_eth_dev;
1175                         char namei[RTE_ETH_NAME_MAX_LEN];
1176
1177                         snprintf(namei, sizeof(namei), "%s_%d",
1178                                  pci_dev->device.name, i);
1179                         rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1180                         if (rest_eth_dev) {
1181                                 rest_eth_dev->device = &pci_dev->device;
1182                                 rest_eth_dev->dev_ops =
1183                                         eth_dev->dev_ops;
1184                                 rest_eth_dev->rx_pkt_burst =
1185                                         eth_dev->rx_pkt_burst;
1186                                 rest_eth_dev->tx_pkt_burst =
1187                                         eth_dev->tx_pkt_burst;
1188                                 rte_eth_dev_probing_finish(rest_eth_dev);
1189                         }
1190                 }
1191                 return 0;
1192         }
1193
1194         snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1195         adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1196         if (!adapter)
1197                 return -1;
1198
1199         adapter->use_unpacked_mode = 1;
1200         adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1201         if (!adapter->regs) {
1202                 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1203                 err = -ENOMEM;
1204                 goto out_free_adapter;
1205         }
1206         adapter->pdev = pci_dev;
1207         adapter->eth_dev = eth_dev;
1208         pi->adapter = adapter;
1209
1210         cxgbe_process_devargs(adapter);
1211
1212         err = cxgbe_probe(adapter);
1213         if (err) {
1214                 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1215                         __func__, err);
1216                 goto out_free_adapter;
1217         }
1218
1219         return 0;
1220
1221 out_free_adapter:
1222         rte_free(adapter);
1223         return err;
1224 }
1225
1226 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1227 {
1228         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1229         uint16_t port_id;
1230
1231         /* Free up other ports and all resources */
1232         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
1233                 rte_eth_dev_close(port_id);
1234
1235         return 0;
1236 }
1237
1238 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1239         struct rte_pci_device *pci_dev)
1240 {
1241         return rte_eth_dev_pci_generic_probe(pci_dev,
1242                 sizeof(struct port_info), eth_cxgbe_dev_init);
1243 }
1244
1245 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1246 {
1247         return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1248 }
1249
1250 static struct rte_pci_driver rte_cxgbe_pmd = {
1251         .id_table = cxgb4_pci_tbl,
1252         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1253         .probe = eth_cxgbe_pci_probe,
1254         .remove = eth_cxgbe_pci_remove,
1255 };
1256
1257 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1258 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1259 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1260 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1261                               CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> "
1262                               CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> "
1263                               CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> "
1264                               CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> ");
1265 RTE_LOG_REGISTER(cxgbe_logtype, pmd.net.cxgbe, NOTICE);
1266 RTE_LOG_REGISTER(cxgbe_mbox_logtype, pmd.net.cxgbe.mbox, NOTICE);