1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
38 #include "cxgbe_pfvf.h"
41 * Macros needed to support the PCI Device ID Table ...
43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
44 static const struct rte_pci_id cxgb4_pci_tbl[] = {
45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
47 #define PCI_VENDOR_ID_CHELSIO 0x1425
49 #define CH_PCI_ID_TABLE_ENTRY(devid) \
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
57 *... and the PCI ID Table itself ...
59 #include "t4_pci_id_tbl.h"
61 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
62 DEV_TX_OFFLOAD_IPV4_CKSUM |\
63 DEV_TX_OFFLOAD_UDP_CKSUM |\
64 DEV_TX_OFFLOAD_TCP_CKSUM |\
65 DEV_TX_OFFLOAD_TCP_TSO)
67 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
68 DEV_RX_OFFLOAD_CRC_STRIP |\
69 DEV_RX_OFFLOAD_IPV4_CKSUM |\
70 DEV_RX_OFFLOAD_JUMBO_FRAME |\
71 DEV_RX_OFFLOAD_UDP_CKSUM |\
72 DEV_RX_OFFLOAD_TCP_CKSUM)
74 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
77 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
78 uint16_t pkts_sent, pkts_remain;
79 uint16_t total_sent = 0;
82 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
83 __func__, txq, tx_pkts, nb_pkts);
85 t4_os_lock(&txq->txq_lock);
86 /* free up desc from already completed tx */
87 reclaim_completed_tx(&txq->q);
88 while (total_sent < nb_pkts) {
89 pkts_remain = nb_pkts - total_sent;
91 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
92 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
99 total_sent += pkts_sent;
100 /* reclaim as much as possible */
101 reclaim_completed_tx(&txq->q);
104 t4_os_unlock(&txq->txq_lock);
108 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
111 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
112 unsigned int work_done;
114 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
115 __func__, rxq->rspq.cntxt_id, nb_pkts);
117 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
118 dev_err(adapter, "error in cxgbe poll\n");
120 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
124 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
125 struct rte_eth_dev_info *device_info)
127 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
128 struct adapter *adapter = pi->adapter;
129 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
131 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
132 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
133 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
137 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
138 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
139 device_info->max_rx_queues = max_queues;
140 device_info->max_tx_queues = max_queues;
141 device_info->max_mac_addrs = 1;
142 /* XXX: For now we support one MAC/port */
143 device_info->max_vfs = adapter->params.arch.vfcount;
144 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
146 device_info->rx_queue_offload_capa = 0UL;
147 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
149 device_info->tx_queue_offload_capa = 0UL;
150 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
152 device_info->reta_size = pi->rss_size;
153 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
154 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
156 device_info->rx_desc_lim = cxgbe_desc_lim;
157 device_info->tx_desc_lim = cxgbe_desc_lim;
158 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
161 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
163 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
164 struct adapter *adapter = pi->adapter;
166 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
167 1, -1, 1, -1, false);
170 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
172 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
173 struct adapter *adapter = pi->adapter;
175 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
176 0, -1, 1, -1, false);
179 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
181 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
182 struct adapter *adapter = pi->adapter;
184 /* TODO: address filters ?? */
186 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
187 -1, 1, 1, -1, false);
190 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
192 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
193 struct adapter *adapter = pi->adapter;
195 /* TODO: address filters ?? */
197 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
198 -1, 0, 1, -1, false);
201 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
202 __rte_unused int wait_to_complete)
204 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
205 struct adapter *adapter = pi->adapter;
206 struct sge *s = &adapter->sge;
207 struct rte_eth_link *old_link = ð_dev->data->dev_link;
208 unsigned int work_done, budget = 4;
210 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
211 if (old_link->link_status == pi->link_cfg.link_ok)
212 return -1; /* link not changed */
214 eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok;
215 eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX;
216 eth_dev->data->dev_link.link_speed = pi->link_cfg.speed;
218 /* link has changed */
222 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
224 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
225 struct adapter *adapter = pi->adapter;
226 struct rte_eth_dev_info dev_info;
228 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
230 cxgbe_dev_info_get(eth_dev, &dev_info);
232 /* Must accommodate at least ETHER_MIN_MTU */
233 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
236 /* set to jumbo mode if needed */
237 if (new_mtu > ETHER_MAX_LEN)
238 eth_dev->data->dev_conf.rxmode.offloads |=
239 DEV_RX_OFFLOAD_JUMBO_FRAME;
241 eth_dev->data->dev_conf.rxmode.offloads &=
242 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
244 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
247 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
255 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
257 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
258 struct adapter *adapter = pi->adapter;
263 if (!(adapter->flags & FULL_INIT_DONE))
269 * We clear queues only if both tx and rx path of the port
272 t4_sge_eth_clear_queues(pi);
274 /* See if all ports are down */
275 for_each_port(adapter, i) {
276 pi = adap2pinfo(adapter, i);
278 * Skip first port of the adapter since it will be closed
283 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0;
286 /* If rest of the ports are stopped, then free up resources */
287 if (dev_down == (adapter->params.nports - 1))
288 cxgbe_close(adapter);
292 * It returns 0 on success.
294 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
296 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
297 struct adapter *adapter = pi->adapter;
303 * If we don't have a connection to the firmware there's nothing we
306 if (!(adapter->flags & FW_OK)) {
311 if (!(adapter->flags & FULL_INIT_DONE)) {
312 err = cxgbe_up(adapter);
317 cxgbe_enable_rx_queues(pi);
323 for (i = 0; i < pi->n_tx_qsets; i++) {
324 err = cxgbe_dev_tx_queue_start(eth_dev, i);
329 for (i = 0; i < pi->n_rx_qsets; i++) {
330 err = cxgbe_dev_rx_queue_start(eth_dev, i);
335 err = link_start(pi);
344 * Stop device: disable rx and tx functions to allow for reconfiguring.
346 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
348 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
349 struct adapter *adapter = pi->adapter;
353 if (!(adapter->flags & FULL_INIT_DONE))
359 * We clear queues only if both tx and rx path of the port
362 t4_sge_eth_clear_queues(pi);
365 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
367 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
368 struct adapter *adapter = pi->adapter;
369 uint64_t configured_offloads;
373 configured_offloads = eth_dev->data->dev_conf.rxmode.offloads;
374 if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
375 dev_info(adapter, "can't disable hw crc strip\n");
376 eth_dev->data->dev_conf.rxmode.offloads |=
377 DEV_RX_OFFLOAD_CRC_STRIP;
380 if (!(adapter->flags & FW_QUEUE_BOUND)) {
381 err = setup_sge_fwevtq(adapter);
384 adapter->flags |= FW_QUEUE_BOUND;
387 err = cfg_queue_count(eth_dev);
394 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
397 struct sge_eth_txq *txq = (struct sge_eth_txq *)
398 (eth_dev->data->tx_queues[tx_queue_id]);
400 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
402 ret = t4_sge_eth_txq_start(txq);
404 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
409 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
412 struct sge_eth_txq *txq = (struct sge_eth_txq *)
413 (eth_dev->data->tx_queues[tx_queue_id]);
415 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
417 ret = t4_sge_eth_txq_stop(txq);
419 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
424 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
425 uint16_t queue_idx, uint16_t nb_desc,
426 unsigned int socket_id,
427 const struct rte_eth_txconf *tx_conf __rte_unused)
429 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
430 struct adapter *adapter = pi->adapter;
431 struct sge *s = &adapter->sge;
432 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
434 unsigned int temp_nb_desc;
436 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
437 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
438 socket_id, pi->first_qset);
440 /* Free up the existing queue */
441 if (eth_dev->data->tx_queues[queue_idx]) {
442 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
443 eth_dev->data->tx_queues[queue_idx] = NULL;
446 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
450 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
452 temp_nb_desc = nb_desc;
453 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
454 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
455 __func__, CXGBE_MIN_RING_DESC_SIZE,
456 CXGBE_DEFAULT_TX_DESC_SIZE);
457 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
458 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
459 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
460 __func__, CXGBE_MIN_RING_DESC_SIZE,
461 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
465 txq->q.size = temp_nb_desc;
467 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
468 s->fw_evtq.cntxt_id, socket_id);
470 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
471 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
475 void cxgbe_dev_tx_queue_release(void *q)
477 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
480 struct port_info *pi = (struct port_info *)
481 (txq->eth_dev->data->dev_private);
482 struct adapter *adap = pi->adapter;
484 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
485 __func__, pi->port_id, txq->q.cntxt_id);
487 t4_sge_eth_txq_release(adap, txq);
491 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
494 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
495 struct adapter *adap = pi->adapter;
498 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
499 __func__, pi->port_id, rx_queue_id);
501 q = eth_dev->data->rx_queues[rx_queue_id];
503 ret = t4_sge_eth_rxq_start(adap, q);
505 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
510 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
513 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
514 struct adapter *adap = pi->adapter;
517 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
518 __func__, pi->port_id, rx_queue_id);
520 q = eth_dev->data->rx_queues[rx_queue_id];
521 ret = t4_sge_eth_rxq_stop(adap, q);
523 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
528 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
529 uint16_t queue_idx, uint16_t nb_desc,
530 unsigned int socket_id,
531 const struct rte_eth_rxconf *rx_conf __rte_unused,
532 struct rte_mempool *mp)
534 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
535 struct adapter *adapter = pi->adapter;
536 struct sge *s = &adapter->sge;
537 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
540 unsigned int temp_nb_desc;
541 struct rte_eth_dev_info dev_info;
542 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
544 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
545 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
548 cxgbe_dev_info_get(eth_dev, &dev_info);
550 /* Must accommodate at least ETHER_MIN_MTU */
551 if ((pkt_len < dev_info.min_rx_bufsize) ||
552 (pkt_len > dev_info.max_rx_pktlen)) {
553 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
554 __func__, dev_info.min_rx_bufsize,
555 dev_info.max_rx_pktlen);
559 /* Free up the existing queue */
560 if (eth_dev->data->rx_queues[queue_idx]) {
561 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
562 eth_dev->data->rx_queues[queue_idx] = NULL;
565 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
569 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
571 temp_nb_desc = nb_desc;
572 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
573 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
574 __func__, CXGBE_MIN_RING_DESC_SIZE,
575 CXGBE_DEFAULT_RX_DESC_SIZE);
576 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
577 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
578 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
579 __func__, CXGBE_MIN_RING_DESC_SIZE,
580 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
584 rxq->rspq.size = temp_nb_desc;
585 if ((&rxq->fl) != NULL)
586 rxq->fl.size = temp_nb_desc;
588 /* Set to jumbo mode if necessary */
589 if (pkt_len > ETHER_MAX_LEN)
590 eth_dev->data->dev_conf.rxmode.offloads |=
591 DEV_RX_OFFLOAD_JUMBO_FRAME;
593 eth_dev->data->dev_conf.rxmode.offloads &=
594 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
596 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
597 &rxq->fl, t4_ethrx_handler,
599 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
600 queue_idx, socket_id);
602 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
603 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
608 void cxgbe_dev_rx_queue_release(void *q)
610 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
611 struct sge_rspq *rq = &rxq->rspq;
614 struct port_info *pi = (struct port_info *)
615 (rq->eth_dev->data->dev_private);
616 struct adapter *adap = pi->adapter;
618 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
619 __func__, pi->port_id, rxq->rspq.cntxt_id);
621 t4_sge_eth_rxq_release(adap, rxq);
626 * Get port statistics.
628 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
629 struct rte_eth_stats *eth_stats)
631 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
632 struct adapter *adapter = pi->adapter;
633 struct sge *s = &adapter->sge;
634 struct port_stats ps;
637 cxgbe_stats_get(pi, &ps);
640 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
641 ps.rx_ovflow2 + ps.rx_ovflow3 +
642 ps.rx_trunc0 + ps.rx_trunc1 +
643 ps.rx_trunc2 + ps.rx_trunc3;
644 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
645 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
649 eth_stats->opackets = ps.tx_frames;
650 eth_stats->obytes = ps.tx_octets;
651 eth_stats->oerrors = ps.tx_error_frames;
653 for (i = 0; i < pi->n_rx_qsets; i++) {
654 struct sge_eth_rxq *rxq =
655 &s->ethrxq[pi->first_qset + i];
657 eth_stats->q_ipackets[i] = rxq->stats.pkts;
658 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
659 eth_stats->ipackets += eth_stats->q_ipackets[i];
660 eth_stats->ibytes += eth_stats->q_ibytes[i];
663 for (i = 0; i < pi->n_tx_qsets; i++) {
664 struct sge_eth_txq *txq =
665 &s->ethtxq[pi->first_qset + i];
667 eth_stats->q_opackets[i] = txq->stats.pkts;
668 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
669 eth_stats->q_errors[i] = txq->stats.mapping_err;
675 * Reset port statistics.
677 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
679 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
680 struct adapter *adapter = pi->adapter;
681 struct sge *s = &adapter->sge;
684 cxgbe_stats_reset(pi);
685 for (i = 0; i < pi->n_rx_qsets; i++) {
686 struct sge_eth_rxq *rxq =
687 &s->ethrxq[pi->first_qset + i];
690 rxq->stats.rx_bytes = 0;
692 for (i = 0; i < pi->n_tx_qsets; i++) {
693 struct sge_eth_txq *txq =
694 &s->ethtxq[pi->first_qset + i];
697 txq->stats.tx_bytes = 0;
698 txq->stats.mapping_err = 0;
702 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
703 struct rte_eth_fc_conf *fc_conf)
705 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
706 struct link_config *lc = &pi->link_cfg;
707 int rx_pause, tx_pause;
709 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
710 rx_pause = lc->fc & PAUSE_RX;
711 tx_pause = lc->fc & PAUSE_TX;
713 if (rx_pause && tx_pause)
714 fc_conf->mode = RTE_FC_FULL;
716 fc_conf->mode = RTE_FC_RX_PAUSE;
718 fc_conf->mode = RTE_FC_TX_PAUSE;
720 fc_conf->mode = RTE_FC_NONE;
724 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
725 struct rte_eth_fc_conf *fc_conf)
727 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
728 struct adapter *adapter = pi->adapter;
729 struct link_config *lc = &pi->link_cfg;
731 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
732 if (fc_conf->autoneg)
733 lc->requested_fc |= PAUSE_AUTONEG;
735 lc->requested_fc &= ~PAUSE_AUTONEG;
738 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
739 (fc_conf->mode & RTE_FC_RX_PAUSE))
740 lc->requested_fc |= PAUSE_RX;
742 lc->requested_fc &= ~PAUSE_RX;
744 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
745 (fc_conf->mode & RTE_FC_TX_PAUSE))
746 lc->requested_fc |= PAUSE_TX;
748 lc->requested_fc &= ~PAUSE_TX;
750 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
755 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
757 static const uint32_t ptypes[] = {
763 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
768 /* Update RSS hash configuration
770 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
771 struct rte_eth_rss_conf *rss_conf)
773 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
774 struct adapter *adapter = pi->adapter;
777 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
781 pi->rss_hf = rss_conf->rss_hf;
783 if (rss_conf->rss_key) {
784 u32 key[10], mod_key[10];
787 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
789 for (i = 9, j = 0; i >= 0; i--, j++)
790 mod_key[j] = cpu_to_be32(key[i]);
792 t4_write_rss_key(adapter, mod_key, -1);
798 /* Get RSS hash configuration
800 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
801 struct rte_eth_rss_conf *rss_conf)
803 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
804 struct adapter *adapter = pi->adapter;
809 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
815 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
816 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
817 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
818 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
821 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
822 rss_hf |= ETH_RSS_IPV6;
824 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
825 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
826 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
827 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
830 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
831 rss_hf |= ETH_RSS_IPV4;
833 rss_conf->rss_hf = rss_hf;
835 if (rss_conf->rss_key) {
836 u32 key[10], mod_key[10];
839 t4_read_rss_key(adapter, key);
841 for (i = 9, j = 0; i >= 0; i--, j++)
842 mod_key[j] = be32_to_cpu(key[i]);
844 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
850 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
857 * eeprom_ptov - translate a physical EEPROM address to virtual
858 * @phys_addr: the physical EEPROM address
859 * @fn: the PCI function number
860 * @sz: size of function-specific area
862 * Translate a physical EEPROM address to virtual. The first 1K is
863 * accessed through virtual addresses starting at 31K, the rest is
864 * accessed through virtual addresses starting at 0.
866 * The mapping is as follows:
867 * [0..1K) -> [31K..32K)
868 * [1K..1K+A) -> [31K-A..31K)
869 * [1K+A..ES) -> [0..ES-A-1K)
871 * where A = @fn * @sz, and ES = EEPROM size.
873 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
876 if (phys_addr < 1024)
877 return phys_addr + (31 << 10);
878 if (phys_addr < 1024 + fn)
879 return fn + phys_addr - 1024;
880 if (phys_addr < EEPROMSIZE)
881 return phys_addr - 1024 - fn;
882 if (phys_addr < EEPROMVSIZE)
883 return phys_addr - 1024;
887 /* The next two routines implement eeprom read/write from physical addresses.
889 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
891 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
894 vaddr = t4_seeprom_read(adap, vaddr, v);
895 return vaddr < 0 ? vaddr : 0;
898 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
900 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
903 vaddr = t4_seeprom_write(adap, vaddr, v);
904 return vaddr < 0 ? vaddr : 0;
907 #define EEPROM_MAGIC 0x38E2F10C
909 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
910 struct rte_dev_eeprom_info *e)
912 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
913 struct adapter *adapter = pi->adapter;
915 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
920 e->magic = EEPROM_MAGIC;
921 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
922 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
925 rte_memcpy(e->data, buf + e->offset, e->length);
930 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
931 struct rte_dev_eeprom_info *eeprom)
933 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
934 struct adapter *adapter = pi->adapter;
937 u32 aligned_offset, aligned_len, *p;
939 if (eeprom->magic != EEPROM_MAGIC)
942 aligned_offset = eeprom->offset & ~3;
943 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
945 if (adapter->pf > 0) {
946 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
948 if (aligned_offset < start ||
949 aligned_offset + aligned_len > start + EEPROMPFSIZE)
953 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
954 /* RMW possibly needed for first or last words.
956 buf = rte_zmalloc(NULL, aligned_len, 0);
959 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
960 if (!err && aligned_len > 4)
961 err = eeprom_rd_phys(adapter,
962 aligned_offset + aligned_len - 4,
963 (u32 *)&buf[aligned_len - 4]);
966 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
972 err = t4_seeprom_wp(adapter, false);
976 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
977 err = eeprom_wr_phys(adapter, aligned_offset, *p);
982 err = t4_seeprom_wp(adapter, true);
984 if (buf != eeprom->data)
989 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
991 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
992 struct adapter *adapter = pi->adapter;
994 return t4_get_regs_len(adapter) / sizeof(uint32_t);
997 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
998 struct rte_dev_reg_info *regs)
1000 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1001 struct adapter *adapter = pi->adapter;
1003 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
1004 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
1007 if (regs->data == NULL) {
1008 regs->length = cxgbe_get_regs_len(eth_dev);
1009 regs->width = sizeof(uint32_t);
1014 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1019 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1021 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1022 struct adapter *adapter = pi->adapter;
1025 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1026 pi->xact_addr_filt, (u8 *)addr, true, true);
1028 dev_err(adapter, "failed to set mac addr; err = %d\n",
1032 pi->xact_addr_filt = ret;
1036 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1037 .dev_start = cxgbe_dev_start,
1038 .dev_stop = cxgbe_dev_stop,
1039 .dev_close = cxgbe_dev_close,
1040 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1041 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1042 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1043 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1044 .dev_configure = cxgbe_dev_configure,
1045 .dev_infos_get = cxgbe_dev_info_get,
1046 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1047 .link_update = cxgbe_dev_link_update,
1048 .mtu_set = cxgbe_dev_mtu_set,
1049 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1050 .tx_queue_start = cxgbe_dev_tx_queue_start,
1051 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1052 .tx_queue_release = cxgbe_dev_tx_queue_release,
1053 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1054 .rx_queue_start = cxgbe_dev_rx_queue_start,
1055 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1056 .rx_queue_release = cxgbe_dev_rx_queue_release,
1057 .stats_get = cxgbe_dev_stats_get,
1058 .stats_reset = cxgbe_dev_stats_reset,
1059 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1060 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1061 .get_eeprom_length = cxgbe_get_eeprom_length,
1062 .get_eeprom = cxgbe_get_eeprom,
1063 .set_eeprom = cxgbe_set_eeprom,
1064 .get_reg = cxgbe_get_regs,
1065 .rss_hash_update = cxgbe_dev_rss_hash_update,
1066 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1067 .mac_addr_set = cxgbe_mac_addr_set,
1072 * It returns 0 on success.
1074 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1076 struct rte_pci_device *pci_dev;
1077 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1078 struct adapter *adapter = NULL;
1079 char name[RTE_ETH_NAME_MAX_LEN];
1084 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1085 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1086 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1087 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1089 /* for secondary processes, we attach to ethdevs allocated by primary
1090 * and do minimal initialization.
1092 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1095 for (i = 1; i < MAX_NPORTS; i++) {
1096 struct rte_eth_dev *rest_eth_dev;
1097 char namei[RTE_ETH_NAME_MAX_LEN];
1099 snprintf(namei, sizeof(namei), "%s_%d",
1100 pci_dev->device.name, i);
1101 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1103 rest_eth_dev->device = &pci_dev->device;
1104 rest_eth_dev->dev_ops =
1106 rest_eth_dev->rx_pkt_burst =
1107 eth_dev->rx_pkt_burst;
1108 rest_eth_dev->tx_pkt_burst =
1109 eth_dev->tx_pkt_burst;
1115 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1116 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1120 adapter->use_unpacked_mode = 1;
1121 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1122 if (!adapter->regs) {
1123 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1125 goto out_free_adapter;
1127 adapter->pdev = pci_dev;
1128 adapter->eth_dev = eth_dev;
1129 pi->adapter = adapter;
1131 err = cxgbe_probe(adapter);
1133 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1135 goto out_free_adapter;
1145 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1146 struct rte_pci_device *pci_dev)
1148 return rte_eth_dev_pci_generic_probe(pci_dev,
1149 sizeof(struct port_info), eth_cxgbe_dev_init);
1152 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1154 return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
1157 static struct rte_pci_driver rte_cxgbe_pmd = {
1158 .id_table = cxgb4_pci_tbl,
1159 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1160 .probe = eth_cxgbe_pci_probe,
1161 .remove = eth_cxgbe_pci_remove,
1164 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1165 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1166 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");