1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_bus_pci.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_ethdev_pci.h>
33 #include <rte_malloc.h>
34 #include <rte_random.h>
38 #include "cxgbe_pfvf.h"
41 * Macros needed to support the PCI Device ID Table ...
43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
44 static const struct rte_pci_id cxgb4_pci_tbl[] = {
45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
47 #define PCI_VENDOR_ID_CHELSIO 0x1425
49 #define CH_PCI_ID_TABLE_ENTRY(devid) \
50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) }
52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
57 *... and the PCI ID Table itself ...
59 #include "t4_pci_id_tbl.h"
61 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\
62 DEV_TX_OFFLOAD_IPV4_CKSUM |\
63 DEV_TX_OFFLOAD_UDP_CKSUM |\
64 DEV_TX_OFFLOAD_TCP_CKSUM |\
65 DEV_TX_OFFLOAD_TCP_TSO)
67 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\
68 DEV_RX_OFFLOAD_CRC_STRIP |\
69 DEV_RX_OFFLOAD_IPV4_CKSUM |\
70 DEV_RX_OFFLOAD_JUMBO_FRAME |\
71 DEV_RX_OFFLOAD_UDP_CKSUM |\
72 DEV_RX_OFFLOAD_TCP_CKSUM)
74 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
77 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue;
78 uint16_t pkts_sent, pkts_remain;
79 uint16_t total_sent = 0;
82 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n",
83 __func__, txq, tx_pkts, nb_pkts);
85 t4_os_lock(&txq->txq_lock);
86 /* free up desc from already completed tx */
87 reclaim_completed_tx(&txq->q);
88 while (total_sent < nb_pkts) {
89 pkts_remain = nb_pkts - total_sent;
91 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) {
92 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent],
99 total_sent += pkts_sent;
100 /* reclaim as much as possible */
101 reclaim_completed_tx(&txq->q);
104 t4_os_unlock(&txq->txq_lock);
108 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
111 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue;
112 unsigned int work_done;
114 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n",
115 __func__, rxq->rspq.cntxt_id, nb_pkts);
117 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done))
118 dev_err(adapter, "error in cxgbe poll\n");
120 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done);
124 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev,
125 struct rte_eth_dev_info *device_info)
127 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
128 struct adapter *adapter = pi->adapter;
129 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports;
131 static const struct rte_eth_desc_lim cxgbe_desc_lim = {
132 .nb_max = CXGBE_MAX_RING_DESC_SIZE,
133 .nb_min = CXGBE_MIN_RING_DESC_SIZE,
137 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE;
138 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN;
139 device_info->max_rx_queues = max_queues;
140 device_info->max_tx_queues = max_queues;
141 device_info->max_mac_addrs = 1;
142 /* XXX: For now we support one MAC/port */
143 device_info->max_vfs = adapter->params.arch.vfcount;
144 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */
146 device_info->rx_queue_offload_capa = 0UL;
147 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS;
149 device_info->tx_queue_offload_capa = 0UL;
150 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS;
152 device_info->reta_size = pi->rss_size;
153 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN;
154 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL;
156 device_info->rx_desc_lim = cxgbe_desc_lim;
157 device_info->tx_desc_lim = cxgbe_desc_lim;
158 cxgbe_get_speed_caps(pi, &device_info->speed_capa);
161 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev)
163 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
164 struct adapter *adapter = pi->adapter;
166 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
167 1, -1, 1, -1, false);
170 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev)
172 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
173 struct adapter *adapter = pi->adapter;
175 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
176 0, -1, 1, -1, false);
179 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev)
181 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
182 struct adapter *adapter = pi->adapter;
184 /* TODO: address filters ?? */
186 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
187 -1, 1, 1, -1, false);
190 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev)
192 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
193 struct adapter *adapter = pi->adapter;
195 /* TODO: address filters ?? */
197 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1,
198 -1, 0, 1, -1, false);
201 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev,
202 __rte_unused int wait_to_complete)
204 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
205 struct adapter *adapter = pi->adapter;
206 struct sge *s = &adapter->sge;
207 struct rte_eth_link new_link = { 0 };
208 unsigned int work_done, budget = 4;
210 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done);
212 new_link.link_status = force_linkup(adapter) ?
213 ETH_LINK_UP : pi->link_cfg.link_ok;
214 new_link.link_autoneg = pi->link_cfg.autoneg;
215 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
216 new_link.link_speed = pi->link_cfg.speed;
218 return rte_eth_linkstatus_set(eth_dev, &new_link);
221 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
223 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
224 struct adapter *adapter = pi->adapter;
225 struct rte_eth_dev_info dev_info;
227 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
229 cxgbe_dev_info_get(eth_dev, &dev_info);
231 /* Must accommodate at least ETHER_MIN_MTU */
232 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen))
235 /* set to jumbo mode if needed */
236 if (new_mtu > ETHER_MAX_LEN)
237 eth_dev->data->dev_conf.rxmode.offloads |=
238 DEV_RX_OFFLOAD_JUMBO_FRAME;
240 eth_dev->data->dev_conf.rxmode.offloads &=
241 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
243 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1,
246 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu;
254 void cxgbe_dev_close(struct rte_eth_dev *eth_dev)
256 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
257 struct adapter *adapter = pi->adapter;
261 if (!(adapter->flags & FULL_INIT_DONE))
267 * We clear queues only if both tx and rx path of the port
270 t4_sge_eth_clear_queues(pi);
274 * It returns 0 on success.
276 int cxgbe_dev_start(struct rte_eth_dev *eth_dev)
278 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
279 struct adapter *adapter = pi->adapter;
285 * If we don't have a connection to the firmware there's nothing we
288 if (!(adapter->flags & FW_OK)) {
293 if (!(adapter->flags & FULL_INIT_DONE)) {
294 err = cxgbe_up(adapter);
299 cxgbe_enable_rx_queues(pi);
305 for (i = 0; i < pi->n_tx_qsets; i++) {
306 err = cxgbe_dev_tx_queue_start(eth_dev, i);
311 for (i = 0; i < pi->n_rx_qsets; i++) {
312 err = cxgbe_dev_rx_queue_start(eth_dev, i);
317 err = link_start(pi);
326 * Stop device: disable rx and tx functions to allow for reconfiguring.
328 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev)
330 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
331 struct adapter *adapter = pi->adapter;
335 if (!(adapter->flags & FULL_INIT_DONE))
341 * We clear queues only if both tx and rx path of the port
344 t4_sge_eth_clear_queues(pi);
347 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev)
349 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
350 struct adapter *adapter = pi->adapter;
351 uint64_t configured_offloads;
355 configured_offloads = eth_dev->data->dev_conf.rxmode.offloads;
356 if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) {
357 dev_info(adapter, "can't disable hw crc strip\n");
358 eth_dev->data->dev_conf.rxmode.offloads |=
359 DEV_RX_OFFLOAD_CRC_STRIP;
362 if (!(adapter->flags & FW_QUEUE_BOUND)) {
363 err = setup_sge_fwevtq(adapter);
366 adapter->flags |= FW_QUEUE_BOUND;
369 err = cfg_queue_count(eth_dev);
376 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
379 struct sge_eth_txq *txq = (struct sge_eth_txq *)
380 (eth_dev->data->tx_queues[tx_queue_id]);
382 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
384 ret = t4_sge_eth_txq_start(txq);
386 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
391 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
394 struct sge_eth_txq *txq = (struct sge_eth_txq *)
395 (eth_dev->data->tx_queues[tx_queue_id]);
397 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id);
399 ret = t4_sge_eth_txq_stop(txq);
401 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
406 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev,
407 uint16_t queue_idx, uint16_t nb_desc,
408 unsigned int socket_id,
409 const struct rte_eth_txconf *tx_conf __rte_unused)
411 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
412 struct adapter *adapter = pi->adapter;
413 struct sge *s = &adapter->sge;
414 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx];
416 unsigned int temp_nb_desc;
418 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n",
419 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc,
420 socket_id, pi->first_qset);
422 /* Free up the existing queue */
423 if (eth_dev->data->tx_queues[queue_idx]) {
424 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]);
425 eth_dev->data->tx_queues[queue_idx] = NULL;
428 eth_dev->data->tx_queues[queue_idx] = (void *)txq;
432 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE
434 temp_nb_desc = nb_desc;
435 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
436 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
437 __func__, CXGBE_MIN_RING_DESC_SIZE,
438 CXGBE_DEFAULT_TX_DESC_SIZE);
439 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE;
440 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
441 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
442 __func__, CXGBE_MIN_RING_DESC_SIZE,
443 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE);
447 txq->q.size = temp_nb_desc;
449 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx,
450 s->fw_evtq.cntxt_id, socket_id);
452 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n",
453 __func__, txq->q.cntxt_id, txq->q.abs_id, err);
457 void cxgbe_dev_tx_queue_release(void *q)
459 struct sge_eth_txq *txq = (struct sge_eth_txq *)q;
462 struct port_info *pi = (struct port_info *)
463 (txq->eth_dev->data->dev_private);
464 struct adapter *adap = pi->adapter;
466 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n",
467 __func__, pi->port_id, txq->q.cntxt_id);
469 t4_sge_eth_txq_release(adap, txq);
473 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
476 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
477 struct adapter *adap = pi->adapter;
480 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
481 __func__, pi->port_id, rx_queue_id);
483 q = eth_dev->data->rx_queues[rx_queue_id];
485 ret = t4_sge_eth_rxq_start(adap, q);
487 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
492 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
495 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
496 struct adapter *adap = pi->adapter;
499 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
500 __func__, pi->port_id, rx_queue_id);
502 q = eth_dev->data->rx_queues[rx_queue_id];
503 ret = t4_sge_eth_rxq_stop(adap, q);
505 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
510 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
511 uint16_t queue_idx, uint16_t nb_desc,
512 unsigned int socket_id,
513 const struct rte_eth_rxconf *rx_conf __rte_unused,
514 struct rte_mempool *mp)
516 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
517 struct adapter *adapter = pi->adapter;
518 struct sge *s = &adapter->sge;
519 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx];
522 unsigned int temp_nb_desc;
523 struct rte_eth_dev_info dev_info;
524 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
526 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n",
527 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc,
530 cxgbe_dev_info_get(eth_dev, &dev_info);
532 /* Must accommodate at least ETHER_MIN_MTU */
533 if ((pkt_len < dev_info.min_rx_bufsize) ||
534 (pkt_len > dev_info.max_rx_pktlen)) {
535 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n",
536 __func__, dev_info.min_rx_bufsize,
537 dev_info.max_rx_pktlen);
541 /* Free up the existing queue */
542 if (eth_dev->data->rx_queues[queue_idx]) {
543 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]);
544 eth_dev->data->rx_queues[queue_idx] = NULL;
547 eth_dev->data->rx_queues[queue_idx] = (void *)rxq;
551 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE
553 temp_nb_desc = nb_desc;
554 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) {
555 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n",
556 __func__, CXGBE_MIN_RING_DESC_SIZE,
557 CXGBE_DEFAULT_RX_DESC_SIZE);
558 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE;
559 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) {
560 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n",
561 __func__, CXGBE_MIN_RING_DESC_SIZE,
562 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE);
566 rxq->rspq.size = temp_nb_desc;
567 if ((&rxq->fl) != NULL)
568 rxq->fl.size = temp_nb_desc;
570 /* Set to jumbo mode if necessary */
571 if (pkt_len > ETHER_MAX_LEN)
572 eth_dev->data->dev_conf.rxmode.offloads |=
573 DEV_RX_OFFLOAD_JUMBO_FRAME;
575 eth_dev->data->dev_conf.rxmode.offloads &=
576 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
578 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx,
579 &rxq->fl, t4_ethrx_handler,
581 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp,
582 queue_idx, socket_id);
584 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n",
585 __func__, err, pi->port_id, rxq->rspq.cntxt_id,
590 void cxgbe_dev_rx_queue_release(void *q)
592 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q;
593 struct sge_rspq *rq = &rxq->rspq;
596 struct port_info *pi = (struct port_info *)
597 (rq->eth_dev->data->dev_private);
598 struct adapter *adap = pi->adapter;
600 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n",
601 __func__, pi->port_id, rxq->rspq.cntxt_id);
603 t4_sge_eth_rxq_release(adap, rxq);
608 * Get port statistics.
610 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev,
611 struct rte_eth_stats *eth_stats)
613 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
614 struct adapter *adapter = pi->adapter;
615 struct sge *s = &adapter->sge;
616 struct port_stats ps;
619 cxgbe_stats_get(pi, &ps);
622 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 +
623 ps.rx_ovflow2 + ps.rx_ovflow3 +
624 ps.rx_trunc0 + ps.rx_trunc1 +
625 ps.rx_trunc2 + ps.rx_trunc3;
626 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err +
627 ps.rx_jabber + ps.rx_too_long + ps.rx_runt +
631 eth_stats->opackets = ps.tx_frames;
632 eth_stats->obytes = ps.tx_octets;
633 eth_stats->oerrors = ps.tx_error_frames;
635 for (i = 0; i < pi->n_rx_qsets; i++) {
636 struct sge_eth_rxq *rxq =
637 &s->ethrxq[pi->first_qset + i];
639 eth_stats->q_ipackets[i] = rxq->stats.pkts;
640 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes;
641 eth_stats->ipackets += eth_stats->q_ipackets[i];
642 eth_stats->ibytes += eth_stats->q_ibytes[i];
645 for (i = 0; i < pi->n_tx_qsets; i++) {
646 struct sge_eth_txq *txq =
647 &s->ethtxq[pi->first_qset + i];
649 eth_stats->q_opackets[i] = txq->stats.pkts;
650 eth_stats->q_obytes[i] = txq->stats.tx_bytes;
651 eth_stats->q_errors[i] = txq->stats.mapping_err;
657 * Reset port statistics.
659 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev)
661 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
662 struct adapter *adapter = pi->adapter;
663 struct sge *s = &adapter->sge;
666 cxgbe_stats_reset(pi);
667 for (i = 0; i < pi->n_rx_qsets; i++) {
668 struct sge_eth_rxq *rxq =
669 &s->ethrxq[pi->first_qset + i];
672 rxq->stats.rx_bytes = 0;
674 for (i = 0; i < pi->n_tx_qsets; i++) {
675 struct sge_eth_txq *txq =
676 &s->ethtxq[pi->first_qset + i];
679 txq->stats.tx_bytes = 0;
680 txq->stats.mapping_err = 0;
684 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev,
685 struct rte_eth_fc_conf *fc_conf)
687 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
688 struct link_config *lc = &pi->link_cfg;
689 int rx_pause, tx_pause;
691 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG;
692 rx_pause = lc->fc & PAUSE_RX;
693 tx_pause = lc->fc & PAUSE_TX;
695 if (rx_pause && tx_pause)
696 fc_conf->mode = RTE_FC_FULL;
698 fc_conf->mode = RTE_FC_RX_PAUSE;
700 fc_conf->mode = RTE_FC_TX_PAUSE;
702 fc_conf->mode = RTE_FC_NONE;
706 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev,
707 struct rte_eth_fc_conf *fc_conf)
709 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
710 struct adapter *adapter = pi->adapter;
711 struct link_config *lc = &pi->link_cfg;
713 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
714 if (fc_conf->autoneg)
715 lc->requested_fc |= PAUSE_AUTONEG;
717 lc->requested_fc &= ~PAUSE_AUTONEG;
720 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
721 (fc_conf->mode & RTE_FC_RX_PAUSE))
722 lc->requested_fc |= PAUSE_RX;
724 lc->requested_fc &= ~PAUSE_RX;
726 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
727 (fc_conf->mode & RTE_FC_TX_PAUSE))
728 lc->requested_fc |= PAUSE_TX;
730 lc->requested_fc &= ~PAUSE_TX;
732 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
737 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
739 static const uint32_t ptypes[] = {
745 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts)
750 /* Update RSS hash configuration
752 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
753 struct rte_eth_rss_conf *rss_conf)
755 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
756 struct adapter *adapter = pi->adapter;
759 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf);
763 pi->rss_hf = rss_conf->rss_hf;
765 if (rss_conf->rss_key) {
766 u32 key[10], mod_key[10];
769 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN);
771 for (i = 9, j = 0; i >= 0; i--, j++)
772 mod_key[j] = cpu_to_be32(key[i]);
774 t4_write_rss_key(adapter, mod_key, -1);
780 /* Get RSS hash configuration
782 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
783 struct rte_eth_rss_conf *rss_conf)
785 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
786 struct adapter *adapter = pi->adapter;
791 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid,
797 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) {
798 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
799 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
800 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
803 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
804 rss_hf |= ETH_RSS_IPV6;
806 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) {
807 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
808 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN)
809 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
812 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
813 rss_hf |= ETH_RSS_IPV4;
815 rss_conf->rss_hf = rss_hf;
817 if (rss_conf->rss_key) {
818 u32 key[10], mod_key[10];
821 t4_read_rss_key(adapter, key);
823 for (i = 9, j = 0; i >= 0; i--, j++)
824 mod_key[j] = be32_to_cpu(key[i]);
826 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN);
832 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev)
839 * eeprom_ptov - translate a physical EEPROM address to virtual
840 * @phys_addr: the physical EEPROM address
841 * @fn: the PCI function number
842 * @sz: size of function-specific area
844 * Translate a physical EEPROM address to virtual. The first 1K is
845 * accessed through virtual addresses starting at 31K, the rest is
846 * accessed through virtual addresses starting at 0.
848 * The mapping is as follows:
849 * [0..1K) -> [31K..32K)
850 * [1K..1K+A) -> [31K-A..31K)
851 * [1K+A..ES) -> [0..ES-A-1K)
853 * where A = @fn * @sz, and ES = EEPROM size.
855 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
858 if (phys_addr < 1024)
859 return phys_addr + (31 << 10);
860 if (phys_addr < 1024 + fn)
861 return fn + phys_addr - 1024;
862 if (phys_addr < EEPROMSIZE)
863 return phys_addr - 1024 - fn;
864 if (phys_addr < EEPROMVSIZE)
865 return phys_addr - 1024;
869 /* The next two routines implement eeprom read/write from physical addresses.
871 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
873 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
876 vaddr = t4_seeprom_read(adap, vaddr, v);
877 return vaddr < 0 ? vaddr : 0;
880 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
882 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE);
885 vaddr = t4_seeprom_write(adap, vaddr, v);
886 return vaddr < 0 ? vaddr : 0;
889 #define EEPROM_MAGIC 0x38E2F10C
891 static int cxgbe_get_eeprom(struct rte_eth_dev *dev,
892 struct rte_dev_eeprom_info *e)
894 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
895 struct adapter *adapter = pi->adapter;
897 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0);
902 e->magic = EEPROM_MAGIC;
903 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4)
904 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
907 rte_memcpy(e->data, buf + e->offset, e->length);
912 static int cxgbe_set_eeprom(struct rte_eth_dev *dev,
913 struct rte_dev_eeprom_info *eeprom)
915 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
916 struct adapter *adapter = pi->adapter;
919 u32 aligned_offset, aligned_len, *p;
921 if (eeprom->magic != EEPROM_MAGIC)
924 aligned_offset = eeprom->offset & ~3;
925 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3;
927 if (adapter->pf > 0) {
928 u32 start = 1024 + adapter->pf * EEPROMPFSIZE;
930 if (aligned_offset < start ||
931 aligned_offset + aligned_len > start + EEPROMPFSIZE)
935 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) {
936 /* RMW possibly needed for first or last words.
938 buf = rte_zmalloc(NULL, aligned_len, 0);
941 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
942 if (!err && aligned_len > 4)
943 err = eeprom_rd_phys(adapter,
944 aligned_offset + aligned_len - 4,
945 (u32 *)&buf[aligned_len - 4]);
948 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data,
954 err = t4_seeprom_wp(adapter, false);
958 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
959 err = eeprom_wr_phys(adapter, aligned_offset, *p);
964 err = t4_seeprom_wp(adapter, true);
966 if (buf != eeprom->data)
971 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev)
973 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
974 struct adapter *adapter = pi->adapter;
976 return t4_get_regs_len(adapter) / sizeof(uint32_t);
979 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev,
980 struct rte_dev_reg_info *regs)
982 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
983 struct adapter *adapter = pi->adapter;
985 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) |
986 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) |
989 if (regs->data == NULL) {
990 regs->length = cxgbe_get_regs_len(eth_dev);
991 regs->width = sizeof(uint32_t);
996 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t)));
1001 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr)
1003 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
1004 struct adapter *adapter = pi->adapter;
1007 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1008 pi->xact_addr_filt, (u8 *)addr, true, true);
1010 dev_err(adapter, "failed to set mac addr; err = %d\n",
1014 pi->xact_addr_filt = ret;
1018 static const struct eth_dev_ops cxgbe_eth_dev_ops = {
1019 .dev_start = cxgbe_dev_start,
1020 .dev_stop = cxgbe_dev_stop,
1021 .dev_close = cxgbe_dev_close,
1022 .promiscuous_enable = cxgbe_dev_promiscuous_enable,
1023 .promiscuous_disable = cxgbe_dev_promiscuous_disable,
1024 .allmulticast_enable = cxgbe_dev_allmulticast_enable,
1025 .allmulticast_disable = cxgbe_dev_allmulticast_disable,
1026 .dev_configure = cxgbe_dev_configure,
1027 .dev_infos_get = cxgbe_dev_info_get,
1028 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get,
1029 .link_update = cxgbe_dev_link_update,
1030 .mtu_set = cxgbe_dev_mtu_set,
1031 .tx_queue_setup = cxgbe_dev_tx_queue_setup,
1032 .tx_queue_start = cxgbe_dev_tx_queue_start,
1033 .tx_queue_stop = cxgbe_dev_tx_queue_stop,
1034 .tx_queue_release = cxgbe_dev_tx_queue_release,
1035 .rx_queue_setup = cxgbe_dev_rx_queue_setup,
1036 .rx_queue_start = cxgbe_dev_rx_queue_start,
1037 .rx_queue_stop = cxgbe_dev_rx_queue_stop,
1038 .rx_queue_release = cxgbe_dev_rx_queue_release,
1039 .stats_get = cxgbe_dev_stats_get,
1040 .stats_reset = cxgbe_dev_stats_reset,
1041 .flow_ctrl_get = cxgbe_flow_ctrl_get,
1042 .flow_ctrl_set = cxgbe_flow_ctrl_set,
1043 .get_eeprom_length = cxgbe_get_eeprom_length,
1044 .get_eeprom = cxgbe_get_eeprom,
1045 .set_eeprom = cxgbe_set_eeprom,
1046 .get_reg = cxgbe_get_regs,
1047 .rss_hash_update = cxgbe_dev_rss_hash_update,
1048 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get,
1049 .mac_addr_set = cxgbe_mac_addr_set,
1054 * It returns 0 on success.
1056 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev)
1058 struct rte_pci_device *pci_dev;
1059 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1060 struct adapter *adapter = NULL;
1061 char name[RTE_ETH_NAME_MAX_LEN];
1066 eth_dev->dev_ops = &cxgbe_eth_dev_ops;
1067 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts;
1068 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts;
1069 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1071 /* for secondary processes, we attach to ethdevs allocated by primary
1072 * and do minimal initialization.
1074 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1077 for (i = 1; i < MAX_NPORTS; i++) {
1078 struct rte_eth_dev *rest_eth_dev;
1079 char namei[RTE_ETH_NAME_MAX_LEN];
1081 snprintf(namei, sizeof(namei), "%s_%d",
1082 pci_dev->device.name, i);
1083 rest_eth_dev = rte_eth_dev_attach_secondary(namei);
1085 rest_eth_dev->device = &pci_dev->device;
1086 rest_eth_dev->dev_ops =
1088 rest_eth_dev->rx_pkt_burst =
1089 eth_dev->rx_pkt_burst;
1090 rest_eth_dev->tx_pkt_burst =
1091 eth_dev->tx_pkt_burst;
1092 rte_eth_dev_probing_finish(rest_eth_dev);
1098 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id);
1099 adapter = rte_zmalloc(name, sizeof(*adapter), 0);
1103 adapter->use_unpacked_mode = 1;
1104 adapter->regs = (void *)pci_dev->mem_resource[0].addr;
1105 if (!adapter->regs) {
1106 dev_err(adapter, "%s: cannot map device registers\n", __func__);
1108 goto out_free_adapter;
1110 adapter->pdev = pci_dev;
1111 adapter->eth_dev = eth_dev;
1112 pi->adapter = adapter;
1114 err = cxgbe_probe(adapter);
1116 dev_err(adapter, "%s: cxgbe probe failed with err %d\n",
1118 goto out_free_adapter;
1128 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev)
1130 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1131 struct adapter *adap = pi->adapter;
1133 /* Free up other ports and all resources */
1138 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1139 struct rte_pci_device *pci_dev)
1141 return rte_eth_dev_pci_generic_probe(pci_dev,
1142 sizeof(struct port_info), eth_cxgbe_dev_init);
1145 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev)
1147 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit);
1150 static struct rte_pci_driver rte_cxgbe_pmd = {
1151 .id_table = cxgb4_pci_tbl,
1152 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1153 .probe = eth_cxgbe_pci_probe,
1154 .remove = eth_cxgbe_pci_remove,
1157 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd);
1158 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl);
1159 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci");
1160 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe,
1161 CXGBE_DEVARG_KEEP_OVLAN "=<0|1> "
1162 CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> ");