1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Chelsio Communications.
7 #include "base/common.h"
8 #include "base/t4_tcb.h"
9 #include "base/t4_regs.h"
10 #include "cxgbe_filter.h"
15 * Initialize Hash Filters
17 int cxgbe_init_hash_filter(struct adapter *adap)
19 unsigned int n_user_filters;
20 unsigned int user_filter_perc;
22 u32 params[7], val[7];
24 #define FW_PARAM_DEV(param) \
25 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
26 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
28 #define FW_PARAM_PFVF(param) \
29 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
30 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
31 V_FW_PARAMS_PARAM_Y(0) | \
32 V_FW_PARAMS_PARAM_Z(0))
34 params[0] = FW_PARAM_DEV(NTID);
35 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
39 adap->tids.ntids = val[0];
40 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
42 user_filter_perc = 100;
43 n_user_filters = mult_frac(adap->tids.nftids,
47 adap->tids.nftids = n_user_filters;
48 adap->params.hash_filter = 1;
53 * Validate if the requested filter specification can be set by checking
54 * if the requested features have been enabled
56 int cxgbe_validate_filter(struct adapter *adapter,
57 struct ch_filter_specification *fs)
62 * Check for unconfigured fields being used.
64 fconf = adapter->params.tp.vlan_pri_map;
66 iconf = adapter->params.tp.ingress_config;
69 (fs->val._field || fs->mask._field)
70 #define U(_mask, _field) \
71 (!(fconf & (_mask)) && S(_field))
73 if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) ||
74 U(F_PROTOCOL, proto) || U(F_MACMATCH, macidx) ||
75 U(F_VLAN, ivlan_vld) || U(F_VNIC_ID, ovlan_vld) ||
79 /* Ensure OVLAN match is enabled in hardware */
80 if (S(ovlan_vld) && (iconf & F_VNIC))
83 /* To use OVLAN, L4 encapsulation match must not be enabled */
84 if (S(ovlan_vld) && (iconf & F_USE_ENC_IDX))
91 * If the user is requesting that the filter action loop
92 * matching packets back out one of our ports, make sure that
93 * the egress port is in range.
95 if (fs->action == FILTER_SWITCH &&
96 fs->eport >= adapter->params.nports)
100 * Don't allow various trivially obvious bogus out-of-range
103 if (fs->val.iport >= adapter->params.nports)
106 if (!fs->cap && fs->nat_mode && !adapter->params.filter2_wr_support)
109 if (!fs->cap && fs->swapmac && !adapter->params.filter2_wr_support)
116 * Get the queue to which the traffic must be steered to.
118 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
119 struct ch_filter_specification *fs)
121 struct port_info *pi = ethdev2pinfo(dev);
122 struct adapter *adapter = pi->adapter;
126 * If the user has requested steering matching Ingress Packets
127 * to a specific Queue Set, we need to make sure it's in range
128 * for the port and map that into the Absolute Queue ID of the
129 * Queue Set's Response Queue.
135 * If the iq id is greater than the number of qsets,
136 * then assume it is an absolute qid.
138 if (fs->iq < pi->n_rx_qsets)
139 iq = adapter->sge.ethrxq[pi->first_qset +
148 /* Return an error number if the indicated filter isn't writable ... */
149 static int writable_filter(struct filter_entry *f)
160 * Send CPL_SET_TCB_FIELD message
162 static void set_tcb_field(struct adapter *adapter, unsigned int ftid,
163 u16 word, u64 mask, u64 val, int no_reply)
165 struct rte_mbuf *mbuf;
166 struct cpl_set_tcb_field *req;
167 struct sge_ctrl_txq *ctrlq;
169 ctrlq = &adapter->sge.ctrlq[0];
170 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
173 mbuf->data_len = sizeof(*req);
174 mbuf->pkt_len = mbuf->data_len;
176 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
177 memset(req, 0, sizeof(*req));
178 INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, ftid);
179 req->reply_ctrl = cpu_to_be16(V_REPLY_CHAN(0) |
180 V_QUEUENO(adapter->sge.fw_evtq.abs_id) |
181 V_NO_REPLY(no_reply));
182 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(ftid));
183 req->mask = cpu_to_be64(mask);
184 req->val = cpu_to_be64(val);
186 t4_mgmt_tx(ctrlq, mbuf);
190 * Set one of the t_flags bits in the TCB.
192 static void set_tcb_tflag(struct adapter *adap, unsigned int ftid,
193 unsigned int bit_pos, unsigned int val, int no_reply)
195 set_tcb_field(adap, ftid, W_TCB_T_FLAGS, 1ULL << bit_pos,
196 (unsigned long long)val << bit_pos, no_reply);
200 * Build a CPL_SET_TCB_FIELD message as payload of a ULP_TX_PKT command.
202 static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
203 struct cpl_set_tcb_field *req,
205 u64 mask, u64 val, u8 cookie,
208 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
209 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
211 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
212 V_ULP_TXPKT_DEST(0));
213 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
214 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
215 sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
216 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
217 req->reply_ctrl = cpu_to_be16(V_NO_REPLY(no_reply) | V_REPLY_CHAN(0) |
219 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(cookie));
220 req->mask = cpu_to_be64(mask);
221 req->val = cpu_to_be64(val);
222 sc = (struct ulptx_idata *)(req + 1);
223 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
224 sc->len = cpu_to_be32(0);
228 * IPv6 requires 2 slots on T6 and 4 slots for cards below T6.
229 * IPv4 requires only 1 slot on all cards.
231 u8 cxgbe_filter_slots(struct adapter *adap, u8 family)
233 if (family == FILTER_TYPE_IPV6) {
234 if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T6)
244 * Check if entries are already filled.
246 bool cxgbe_is_filter_set(struct tid_info *t, u32 fidx, u8 nentries)
251 /* Ensure there's enough slots available. */
252 t4_os_lock(&t->ftid_lock);
253 for (i = fidx; i < fidx + nentries; i++) {
254 if (rte_bitmap_get(t->ftid_bmap, i)) {
259 t4_os_unlock(&t->ftid_lock);
264 * Allocate available free entries.
266 int cxgbe_alloc_ftid(struct adapter *adap, u8 nentries)
268 struct tid_info *t = &adap->tids;
270 int size = t->nftids;
272 t4_os_lock(&t->ftid_lock);
274 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size,
277 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
278 t4_os_unlock(&t->ftid_lock);
280 return pos < size ? pos : -1;
284 * Construct hash filter ntuple.
286 static u64 hash_filter_ntuple(const struct filter_entry *f)
288 struct adapter *adap = ethdev2adap(f->dev);
289 struct tp_params *tp = &adap->params.tp;
291 u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
293 if (tp->port_shift >= 0 && f->fs.mask.iport)
294 ntuple |= (u64)f->fs.val.iport << tp->port_shift;
296 if (tp->protocol_shift >= 0) {
297 if (!f->fs.val.proto)
298 ntuple |= (u64)tcp_proto << tp->protocol_shift;
300 ntuple |= (u64)f->fs.val.proto << tp->protocol_shift;
303 if (tp->ethertype_shift >= 0 && f->fs.mask.ethtype)
304 ntuple |= (u64)(f->fs.val.ethtype) << tp->ethertype_shift;
305 if (tp->macmatch_shift >= 0 && f->fs.mask.macidx)
306 ntuple |= (u64)(f->fs.val.macidx) << tp->macmatch_shift;
307 if (tp->vlan_shift >= 0 && f->fs.mask.ivlan)
308 ntuple |= (u64)(F_FT_VLAN_VLD | f->fs.val.ivlan) <<
310 if (tp->vnic_shift >= 0) {
311 if (!(adap->params.tp.ingress_config & F_VNIC) &&
312 f->fs.mask.ovlan_vld)
313 ntuple |= (u64)(f->fs.val.ovlan_vld << 16 |
314 f->fs.val.ovlan) << tp->vnic_shift;
316 if (tp->tos_shift >= 0 && f->fs.mask.tos)
317 ntuple |= (u64)f->fs.val.tos << tp->tos_shift;
323 * Build a CPL_ABORT_REQ message as payload of a ULP_TX_PKT command.
325 static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
328 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_req;
329 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
331 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
332 V_ULP_TXPKT_DEST(0));
333 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
334 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
335 sc->len = cpu_to_be32(sizeof(*abort_req) -
336 sizeof(struct work_request_hdr));
337 OPCODE_TID(abort_req) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_REQ, tid));
338 abort_req->rsvd0 = cpu_to_be32(0);
339 abort_req->rsvd1 = 0;
340 abort_req->cmd = CPL_ABORT_NO_RST;
341 sc = (struct ulptx_idata *)(abort_req + 1);
342 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
343 sc->len = cpu_to_be32(0);
347 * Build a CPL_ABORT_RPL message as payload of a ULP_TX_PKT command.
349 static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
352 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_rpl;
353 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
355 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
356 V_ULP_TXPKT_DEST(0));
357 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
358 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
359 sc->len = cpu_to_be32(sizeof(*abort_rpl) -
360 sizeof(struct work_request_hdr));
361 OPCODE_TID(abort_rpl) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_RPL, tid));
362 abort_rpl->rsvd0 = cpu_to_be32(0);
363 abort_rpl->rsvd1 = 0;
364 abort_rpl->cmd = CPL_ABORT_NO_RST;
365 sc = (struct ulptx_idata *)(abort_rpl + 1);
366 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
367 sc->len = cpu_to_be32(0);
371 * Delete the specified hash filter.
373 static int cxgbe_del_hash_filter(struct rte_eth_dev *dev,
374 unsigned int filter_id,
375 struct filter_ctx *ctx)
377 struct adapter *adapter = ethdev2adap(dev);
378 struct tid_info *t = &adapter->tids;
379 struct filter_entry *f;
380 struct sge_ctrl_txq *ctrlq;
381 unsigned int port_id = ethdev2pinfo(dev)->port_id;
384 if (filter_id > adapter->tids.ntids)
387 f = lookup_tid(t, filter_id);
389 dev_err(adapter, "%s: no filter entry for filter_id = %d\n",
390 __func__, filter_id);
394 ret = writable_filter(f);
400 struct rte_mbuf *mbuf;
401 struct work_request_hdr *wr;
402 struct ulptx_idata *aligner;
403 struct cpl_set_tcb_field *req;
404 struct cpl_abort_req *abort_req;
405 struct cpl_abort_rpl *abort_rpl;
410 wrlen = cxgbe_roundup(sizeof(*wr) +
411 (sizeof(*req) + sizeof(*aligner)) +
412 sizeof(*abort_req) + sizeof(*abort_rpl),
415 ctrlq = &adapter->sge.ctrlq[port_id];
416 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
418 dev_err(adapter, "%s: could not allocate skb ..\n",
423 mbuf->data_len = wrlen;
424 mbuf->pkt_len = mbuf->data_len;
426 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
427 INIT_ULPTX_WR(req, wrlen, 0, 0);
428 wr = (struct work_request_hdr *)req;
430 req = (struct cpl_set_tcb_field *)wr;
431 mk_set_tcb_field_ulp(f, req, W_TCB_RSS_INFO,
432 V_TCB_RSS_INFO(M_TCB_RSS_INFO),
433 V_TCB_RSS_INFO(adapter->sge.fw_evtq.abs_id),
435 aligner = (struct ulptx_idata *)(req + 1);
436 abort_req = (struct cpl_abort_req *)(aligner + 1);
437 mk_abort_req_ulp(abort_req, f->tid);
438 abort_rpl = (struct cpl_abort_rpl *)(abort_req + 1);
439 mk_abort_rpl_ulp(abort_rpl, f->tid);
440 t4_mgmt_tx(ctrlq, mbuf);
449 * Build a ACT_OPEN_REQ6 message for setting IPv6 hash filter.
451 static void mk_act_open_req6(struct filter_entry *f, struct rte_mbuf *mbuf,
452 unsigned int qid_filterid, struct adapter *adap)
454 struct cpl_t6_act_open_req6 *req = NULL;
455 u64 local_lo, local_hi, peer_lo, peer_hi;
456 u32 *lip = (u32 *)f->fs.val.lip;
457 u32 *fip = (u32 *)f->fs.val.fip;
459 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
461 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req6 *);
466 dev_err(adap, "%s: unsupported chip type!\n", __func__);
470 local_hi = ((u64)lip[1]) << 32 | lip[0];
471 local_lo = ((u64)lip[3]) << 32 | lip[2];
472 peer_hi = ((u64)fip[1]) << 32 | fip[0];
473 peer_lo = ((u64)fip[3]) << 32 | fip[2];
475 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
477 req->local_port = cpu_to_be16(f->fs.val.lport);
478 req->peer_port = cpu_to_be16(f->fs.val.fport);
479 req->local_ip_hi = local_hi;
480 req->local_ip_lo = local_lo;
481 req->peer_ip_hi = peer_hi;
482 req->peer_ip_lo = peer_lo;
483 req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
484 f->fs.newvlan == VLAN_REWRITE) |
485 V_DELACK(f->fs.hitcnts) |
486 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
487 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
489 V_TX_CHAN(f->fs.eport) |
490 V_ULP_MODE(ULP_MODE_NONE) |
491 F_TCAM_BYPASS | F_NON_OFFLOAD);
492 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
493 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
494 V_RSS_QUEUE(f->fs.iq) |
497 V_SACK_EN(f->fs.swapmac) |
498 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
499 (f->fs.dirsteer << 1)) |
500 V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
504 * Build a ACT_OPEN_REQ message for setting IPv4 hash filter.
506 static void mk_act_open_req(struct filter_entry *f, struct rte_mbuf *mbuf,
507 unsigned int qid_filterid, struct adapter *adap)
509 struct cpl_t6_act_open_req *req = NULL;
511 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
513 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req *);
518 dev_err(adap, "%s: unsupported chip type!\n", __func__);
522 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
524 req->local_port = cpu_to_be16(f->fs.val.lport);
525 req->peer_port = cpu_to_be16(f->fs.val.fport);
526 req->local_ip = f->fs.val.lip[0] | f->fs.val.lip[1] << 8 |
527 f->fs.val.lip[2] << 16 | f->fs.val.lip[3] << 24;
528 req->peer_ip = f->fs.val.fip[0] | f->fs.val.fip[1] << 8 |
529 f->fs.val.fip[2] << 16 | f->fs.val.fip[3] << 24;
530 req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
531 f->fs.newvlan == VLAN_REWRITE) |
532 V_DELACK(f->fs.hitcnts) |
533 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
534 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
536 V_TX_CHAN(f->fs.eport) |
537 V_ULP_MODE(ULP_MODE_NONE) |
538 F_TCAM_BYPASS | F_NON_OFFLOAD);
539 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
540 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
541 V_RSS_QUEUE(f->fs.iq) |
544 V_SACK_EN(f->fs.swapmac) |
545 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
546 (f->fs.dirsteer << 1)) |
547 V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
551 * Set the specified hash filter.
553 static int cxgbe_set_hash_filter(struct rte_eth_dev *dev,
554 struct ch_filter_specification *fs,
555 struct filter_ctx *ctx)
557 struct port_info *pi = ethdev2pinfo(dev);
558 struct adapter *adapter = pi->adapter;
559 struct tid_info *t = &adapter->tids;
560 struct filter_entry *f;
561 struct rte_mbuf *mbuf;
562 struct sge_ctrl_txq *ctrlq;
567 ret = cxgbe_validate_filter(adapter, fs);
571 iq = get_filter_steerq(dev, fs);
573 ctrlq = &adapter->sge.ctrlq[pi->port_id];
575 f = t4_os_alloc(sizeof(*f));
585 * If the new filter requires loopback Destination MAC and/or VLAN
586 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
589 if (f->fs.newvlan == VLAN_INSERT ||
590 f->fs.newvlan == VLAN_REWRITE) {
591 /* allocate L2T entry for new filter */
592 f->l2t = cxgbe_l2t_alloc_switching(dev, f->fs.vlan,
593 f->fs.eport, f->fs.dmac);
600 atid = cxgbe_alloc_atid(t, f);
604 if (f->fs.type == FILTER_TYPE_IPV6) {
605 /* IPv6 hash filter */
606 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
610 size = sizeof(struct cpl_t6_act_open_req6);
611 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
617 mbuf->data_len = size;
618 mbuf->pkt_len = mbuf->data_len;
620 mk_act_open_req6(f, mbuf,
621 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
624 /* IPv4 hash filter */
625 size = sizeof(struct cpl_t6_act_open_req);
626 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
632 mbuf->data_len = size;
633 mbuf->pkt_len = mbuf->data_len;
635 mk_act_open_req(f, mbuf,
636 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
641 t4_mgmt_tx(ctrlq, mbuf);
645 cxgbe_clip_release(f->dev, f->clipt);
647 cxgbe_free_atid(t, atid);
655 * Clear a filter and release any of its resources that we own. This also
656 * clears the filter's "pending" status.
658 static void clear_filter(struct filter_entry *f)
661 cxgbe_clip_release(f->dev, f->clipt);
664 * The zeroing of the filter rule below clears the filter valid,
665 * pending, locked flags etc. so it's all we need for
668 memset(f, 0, sizeof(*f));
672 * t4_mk_filtdelwr - create a delete filter WR
673 * @adap: adapter context
674 * @ftid: the filter ID
675 * @wr: the filter work request to populate
676 * @qid: ingress queue to receive the delete notification
678 * Creates a filter work request to delete the supplied filter. If @qid is
679 * negative the delete notification is suppressed.
681 static void t4_mk_filtdelwr(struct adapter *adap, unsigned int ftid,
682 struct fw_filter2_wr *wr, int qid)
684 memset(wr, 0, sizeof(*wr));
685 if (adap->params.filter2_wr_support)
686 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
688 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
689 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
690 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
691 V_FW_FILTER_WR_NOREPLY(qid < 0));
692 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
694 wr->rx_chan_rx_rpl_iq =
695 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
699 * Create FW work request to delete the filter at a specified index
701 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
703 struct adapter *adapter = ethdev2adap(dev);
704 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
705 struct rte_mbuf *mbuf;
706 struct fw_filter2_wr *fwr;
707 struct sge_ctrl_txq *ctrlq;
708 unsigned int port_id = ethdev2pinfo(dev)->port_id;
710 ctrlq = &adapter->sge.ctrlq[port_id];
711 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
715 mbuf->data_len = sizeof(*fwr);
716 mbuf->pkt_len = mbuf->data_len;
718 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
719 t4_mk_filtdelwr(adapter, f->tid, fwr, adapter->sge.fw_evtq.abs_id);
722 * Mark the filter as "pending" and ship off the Filter Work Request.
723 * When we get the Work Request Reply we'll clear the pending status.
726 t4_mgmt_tx(ctrlq, mbuf);
730 static int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
732 struct adapter *adapter = ethdev2adap(dev);
733 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
734 struct rte_mbuf *mbuf;
735 struct fw_filter2_wr *fwr;
736 struct sge_ctrl_txq *ctrlq;
737 unsigned int port_id = ethdev2pinfo(dev)->port_id;
741 * If the new filter requires loopback Destination MAC and/or VLAN
742 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
746 /* allocate L2T entry for new filter */
747 f->l2t = cxgbe_l2t_alloc_switching(f->dev, f->fs.vlan,
748 f->fs.eport, f->fs.dmac);
753 ctrlq = &adapter->sge.ctrlq[port_id];
754 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
760 mbuf->data_len = sizeof(*fwr);
761 mbuf->pkt_len = mbuf->data_len;
763 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
764 memset(fwr, 0, sizeof(*fwr));
767 * Construct the work request to set the filter.
769 if (adapter->params.filter2_wr_support)
770 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
772 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
773 fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
775 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
776 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
777 V_FW_FILTER_WR_NOREPLY(0) |
778 V_FW_FILTER_WR_IQ(f->fs.iq));
779 fwr->del_filter_to_l2tix =
780 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
781 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
782 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
783 V_FW_FILTER_WR_INSVLAN
784 (f->fs.newvlan == VLAN_INSERT ||
785 f->fs.newvlan == VLAN_REWRITE) |
786 V_FW_FILTER_WR_RMVLAN
787 (f->fs.newvlan == VLAN_REMOVE ||
788 f->fs.newvlan == VLAN_REWRITE) |
789 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
790 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
791 V_FW_FILTER_WR_PRIO(f->fs.prio) |
792 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
793 fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
794 fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
795 fwr->frag_to_ovlan_vldm =
796 (V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
797 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
798 V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
799 V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
801 fwr->rx_chan_rx_rpl_iq =
802 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
803 V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
805 fwr->maci_to_matchtypem =
806 cpu_to_be32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
807 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
808 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
809 V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
810 fwr->ptcl = f->fs.val.proto;
811 fwr->ptclm = f->fs.mask.proto;
812 fwr->ttyp = f->fs.val.tos;
813 fwr->ttypm = f->fs.mask.tos;
814 fwr->ivlan = cpu_to_be16(f->fs.val.ivlan);
815 fwr->ivlanm = cpu_to_be16(f->fs.mask.ivlan);
816 fwr->ovlan = cpu_to_be16(f->fs.val.ovlan);
817 fwr->ovlanm = cpu_to_be16(f->fs.mask.ovlan);
818 rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
819 rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
820 rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
821 rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
822 fwr->lp = cpu_to_be16(f->fs.val.lport);
823 fwr->lpm = cpu_to_be16(f->fs.mask.lport);
824 fwr->fp = cpu_to_be16(f->fs.val.fport);
825 fwr->fpm = cpu_to_be16(f->fs.mask.fport);
827 if (adapter->params.filter2_wr_support) {
828 fwr->filter_type_swapmac =
829 V_FW_FILTER2_WR_SWAPMAC(f->fs.swapmac);
830 fwr->natmode_to_ulp_type =
831 V_FW_FILTER2_WR_ULP_TYPE(f->fs.nat_mode ?
834 V_FW_FILTER2_WR_NATMODE(f->fs.nat_mode);
835 memcpy(fwr->newlip, f->fs.nat_lip, sizeof(fwr->newlip));
836 memcpy(fwr->newfip, f->fs.nat_fip, sizeof(fwr->newfip));
837 fwr->newlport = cpu_to_be16(f->fs.nat_lport);
838 fwr->newfport = cpu_to_be16(f->fs.nat_fport);
842 * Mark the filter as "pending" and ship off the Filter Work Request.
843 * When we get the Work Request Reply we'll clear the pending status.
846 t4_mgmt_tx(ctrlq, mbuf);
854 * Set the corresponding entries in the bitmap.
856 static int cxgbe_set_ftid(struct tid_info *t, u32 fidx, u8 nentries)
860 t4_os_lock(&t->ftid_lock);
861 if (rte_bitmap_get(t->ftid_bmap, fidx)) {
862 t4_os_unlock(&t->ftid_lock);
866 for (i = fidx; i < fidx + nentries; i++)
867 rte_bitmap_set(t->ftid_bmap, i);
868 t4_os_unlock(&t->ftid_lock);
873 * Clear the corresponding entries in the bitmap.
875 static void cxgbe_clear_ftid(struct tid_info *t, u32 fidx, u8 nentries)
879 t4_os_lock(&t->ftid_lock);
880 for (i = fidx; i < fidx + nentries; i++)
881 rte_bitmap_clear(t->ftid_bmap, i);
882 t4_os_unlock(&t->ftid_lock);
886 * Check a delete filter request for validity and send it to the hardware.
887 * Return 0 on success, an error number otherwise. We attach any provided
888 * filter operation context to the internal filter specification in order to
889 * facilitate signaling completion of the operation.
891 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
892 struct ch_filter_specification *fs,
893 struct filter_ctx *ctx)
895 struct port_info *pi = dev->data->dev_private;
896 struct adapter *adapter = pi->adapter;
897 struct filter_entry *f;
898 unsigned int chip_ver;
902 if (is_hashfilter(adapter) && fs->cap)
903 return cxgbe_del_hash_filter(dev, filter_id, ctx);
905 if (filter_id >= adapter->tids.nftids)
908 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
911 * Ensure IPv6 filter id is aligned on the 2 slot boundary for T6,
912 * and 4 slot boundary for cards below T6.
914 if (fs->type == FILTER_TYPE_IPV6) {
915 if (chip_ver < CHELSIO_T6)
921 nentries = cxgbe_filter_slots(adapter, fs->type);
922 ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
924 dev_warn(adap, "%s: could not find filter entry: %u\n",
925 __func__, filter_id);
929 f = &adapter->tids.ftid_tab[filter_id];
930 ret = writable_filter(f);
936 cxgbe_clear_ftid(&adapter->tids,
937 f->tid - adapter->tids.ftid_base,
939 return del_filter_wr(dev, filter_id);
943 * If the caller has passed in a Completion Context then we need to
944 * mark it as a successful completion so they don't stall waiting
949 t4_complete(&ctx->completion);
956 * Check a Chelsio Filter Request for validity, convert it into our internal
957 * format and send it to the hardware. Return 0 on success, an error number
958 * otherwise. We attach any provided filter operation context to the internal
959 * filter specification in order to facilitate signaling completion of the
962 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
963 struct ch_filter_specification *fs,
964 struct filter_ctx *ctx)
966 struct port_info *pi = ethdev2pinfo(dev);
967 struct adapter *adapter = pi->adapter;
968 unsigned int fidx, iq;
969 struct filter_entry *f;
970 unsigned int chip_ver;
971 u8 nentries, bitoff[16] = {0};
974 if (is_hashfilter(adapter) && fs->cap)
975 return cxgbe_set_hash_filter(dev, fs, ctx);
977 if (filter_id >= adapter->tids.nftids)
980 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
982 ret = cxgbe_validate_filter(adapter, fs);
987 * IPv6 filters occupy four slots and must be aligned on four-slot
988 * boundaries for T5. On T6, IPv6 filters occupy two-slots and
989 * must be aligned on two-slot boundaries.
991 * IPv4 filters only occupy a single slot and have no alignment
995 if (fs->type == FILTER_TYPE_IPV6) {
996 if (chip_ver < CHELSIO_T6)
1002 if (fidx != filter_id)
1005 nentries = cxgbe_filter_slots(adapter, fs->type);
1006 ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
1010 iq = get_filter_steerq(dev, fs);
1013 * Check to make sure that provided filter index is not
1014 * already in use by someone else
1016 f = &adapter->tids.ftid_tab[filter_id];
1020 fidx = adapter->tids.ftid_base + filter_id;
1021 ret = cxgbe_set_ftid(&adapter->tids, filter_id, nentries);
1026 * Check to make sure the filter requested is writable ...
1028 ret = writable_filter(f);
1030 /* Clear the bits we have set above */
1031 cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1036 * Allocate a clip table entry only if we have non-zero IPv6 address
1038 if (chip_ver > CHELSIO_T5 && fs->type &&
1039 memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
1040 f->clipt = cxgbe_clip_alloc(dev, (u32 *)&fs->val.lip);
1046 * Convert the filter specification into our internal format.
1047 * We copy the PF/VF specification into the Outer VLAN field
1048 * here so the rest of the code -- including the interface to
1049 * the firmware -- doesn't have to constantly do these checks.
1056 * Attempt to set the filter. If we don't succeed, we clear
1057 * it and return the failure.
1060 f->tid = fidx; /* Save the actual tid */
1061 ret = set_filter_wr(dev, filter_id);
1068 cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1074 * Handle a Hash filter write reply.
1076 void cxgbe_hash_filter_rpl(struct adapter *adap,
1077 const struct cpl_act_open_rpl *rpl)
1079 struct tid_info *t = &adap->tids;
1080 struct filter_entry *f;
1081 struct filter_ctx *ctx = NULL;
1082 unsigned int tid = GET_TID(rpl);
1083 unsigned int ftid = G_TID_TID(G_AOPEN_ATID
1084 (be32_to_cpu(rpl->atid_status)));
1085 unsigned int status = G_AOPEN_STATUS(be32_to_cpu(rpl->atid_status));
1087 f = lookup_atid(t, ftid);
1089 dev_warn(adap, "%s: could not find filter entry: %d\n",
1098 case CPL_ERR_NONE: {
1100 f->pending = 0; /* asynchronous setup completed */
1103 cxgbe_insert_tid(t, f, f->tid, 0);
1104 cxgbe_free_atid(t, ftid);
1110 set_tcb_field(adap, tid,
1112 V_TCB_TIMESTAMP(M_TCB_TIMESTAMP) |
1113 V_TCB_T_RTT_TS_RECENT_AGE
1114 (M_TCB_T_RTT_TS_RECENT_AGE),
1115 V_TCB_TIMESTAMP(0ULL) |
1116 V_TCB_T_RTT_TS_RECENT_AGE(0ULL),
1118 if (f->fs.newvlan == VLAN_INSERT ||
1119 f->fs.newvlan == VLAN_REWRITE)
1120 set_tcb_tflag(adap, tid, S_TF_CCTRL_RFR, 1, 1);
1124 dev_warn(adap, "%s: filter creation failed with status = %u\n",
1128 if (status == CPL_ERR_TCAM_FULL)
1129 ctx->result = -EAGAIN;
1131 ctx->result = -EINVAL;
1134 cxgbe_free_atid(t, ftid);
1139 t4_complete(&ctx->completion);
1143 * Handle a LE-TCAM filter write/deletion reply.
1145 void cxgbe_filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
1147 struct filter_entry *f = NULL;
1148 unsigned int tid = GET_TID(rpl);
1149 int idx, max_fidx = adap->tids.nftids;
1151 /* Get the corresponding filter entry for this tid */
1152 if (adap->tids.ftid_tab) {
1153 /* Check this in normal filter region */
1154 idx = tid - adap->tids.ftid_base;
1155 if (idx >= max_fidx)
1158 f = &adap->tids.ftid_tab[idx];
1163 /* We found the filter entry for this tid */
1165 unsigned int ret = G_COOKIE(rpl->cookie);
1166 struct filter_ctx *ctx;
1169 * Pull off any filter operation context attached to the
1175 if (ret == FW_FILTER_WR_FLT_ADDED) {
1176 f->pending = 0; /* asynchronous setup completed */
1182 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
1184 * Clear the filter when we get confirmation from the
1185 * hardware that the filter has been deleted.
1192 * Something went wrong. Issue a warning about the
1193 * problem and clear everything out.
1195 dev_warn(adap, "filter %u setup failed with error %u\n",
1199 ctx->result = -EINVAL;
1203 t4_complete(&ctx->completion);
1208 * Retrieve the packet count for the specified filter.
1210 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
1211 u64 *c, int hash, bool get_byte)
1213 struct filter_entry *f;
1214 unsigned int tcb_base, tcbaddr;
1217 tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
1218 if (is_hashfilter(adapter) && hash) {
1219 if (fidx < adapter->tids.ntids) {
1220 f = adapter->tids.tid_tab[fidx];
1224 if (is_t5(adapter->params.chip)) {
1228 tcbaddr = tcb_base + (fidx * TCB_SIZE);
1234 if (fidx >= adapter->tids.nftids)
1237 f = &adapter->tids.ftid_tab[fidx];
1241 tcbaddr = tcb_base + f->tid * TCB_SIZE;
1244 f = &adapter->tids.ftid_tab[fidx];
1249 if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
1251 * For T5, the Filter Packet Hit Count is maintained as a
1252 * 32-bit Big Endian value in the TCB field {timestamp}.
1253 * Similar to the craziness above, instead of the filter hit
1254 * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
1255 * sizeof(u32)), it actually shows up at offset 24. Whacky.
1258 unsigned int word_offset = 4;
1259 __be64 be64_byte_count;
1261 t4_os_lock(&adapter->win0_lock);
1262 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1264 (word_offset * sizeof(__be32)),
1265 sizeof(be64_byte_count),
1268 t4_os_unlock(&adapter->win0_lock);
1271 *c = be64_to_cpu(be64_byte_count);
1273 unsigned int word_offset = 6;
1276 t4_os_lock(&adapter->win0_lock);
1277 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1279 (word_offset * sizeof(__be32)),
1280 sizeof(be32_count), &be32_count,
1282 t4_os_unlock(&adapter->win0_lock);
1285 *c = (u64)be32_to_cpu(be32_count);
1292 * Clear the packet count for the specified filter.
1294 int cxgbe_clear_filter_count(struct adapter *adapter, unsigned int fidx,
1295 int hash, bool clear_byte)
1297 u64 tcb_mask = 0, tcb_val = 0;
1298 struct filter_entry *f = NULL;
1301 if (is_hashfilter(adapter) && hash) {
1302 if (fidx >= adapter->tids.ntids)
1305 /* No hitcounts supported for T5 hashfilters */
1306 if (is_t5(adapter->params.chip))
1309 f = adapter->tids.tid_tab[fidx];
1311 if (fidx >= adapter->tids.nftids)
1314 f = &adapter->tids.ftid_tab[fidx];
1317 if (!f || !f->valid)
1320 tcb_word = W_TCB_TIMESTAMP;
1321 tcb_mask = V_TCB_TIMESTAMP(M_TCB_TIMESTAMP);
1322 tcb_val = V_TCB_TIMESTAMP(0ULL);
1324 set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1327 tcb_word = W_TCB_T_RTT_TS_RECENT_AGE;
1329 V_TCB_T_RTT_TS_RECENT_AGE(M_TCB_T_RTT_TS_RECENT_AGE) |
1330 V_TCB_T_RTSEQ_RECENT(M_TCB_T_RTSEQ_RECENT);
1331 tcb_val = V_TCB_T_RTT_TS_RECENT_AGE(0ULL) |
1332 V_TCB_T_RTSEQ_RECENT(0ULL);
1334 set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1341 * Handle a Hash filter delete reply.
1343 void cxgbe_hash_del_filter_rpl(struct adapter *adap,
1344 const struct cpl_abort_rpl_rss *rpl)
1346 struct tid_info *t = &adap->tids;
1347 struct filter_entry *f;
1348 struct filter_ctx *ctx = NULL;
1349 unsigned int tid = GET_TID(rpl);
1351 f = lookup_tid(t, tid);
1353 dev_warn(adap, "%s: could not find filter entry: %u\n",
1364 cxgbe_clip_release(f->dev, f->clipt);
1366 cxgbe_remove_tid(t, 0, tid, 0);
1371 t4_complete(&ctx->completion);