1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Chelsio Communications.
9 #include "cxgbe_filter.h"
14 * Initialize Hash Filters
16 int init_hash_filter(struct adapter *adap)
18 unsigned int n_user_filters;
19 unsigned int user_filter_perc;
21 u32 params[7], val[7];
23 #define FW_PARAM_DEV(param) \
24 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
25 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
27 #define FW_PARAM_PFVF(param) \
28 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
29 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
30 V_FW_PARAMS_PARAM_Y(0) | \
31 V_FW_PARAMS_PARAM_Z(0))
33 params[0] = FW_PARAM_DEV(NTID);
34 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
38 adap->tids.ntids = val[0];
39 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
41 user_filter_perc = 100;
42 n_user_filters = mult_frac(adap->tids.nftids,
46 adap->tids.nftids = n_user_filters;
47 adap->params.hash_filter = 1;
52 * Validate if the requested filter specification can be set by checking
53 * if the requested features have been enabled
55 int validate_filter(struct adapter *adapter, struct ch_filter_specification *fs)
60 * Check for unconfigured fields being used.
62 fconf = adapter->params.tp.vlan_pri_map;
65 (fs->val._field || fs->mask._field)
66 #define U(_mask, _field) \
67 (!(fconf & (_mask)) && S(_field))
69 if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) ||
70 U(F_PROTOCOL, proto) || U(F_MACMATCH, macidx))
77 * If the user is requesting that the filter action loop
78 * matching packets back out one of our ports, make sure that
79 * the egress port is in range.
81 if (fs->action == FILTER_SWITCH &&
82 fs->eport >= adapter->params.nports)
86 * Don't allow various trivially obvious bogus out-of-range
89 if (fs->val.iport >= adapter->params.nports)
92 if (!fs->cap && fs->nat_mode && !adapter->params.filter2_wr_support)
95 if (!fs->cap && fs->swapmac && !adapter->params.filter2_wr_support)
102 * Get the queue to which the traffic must be steered to.
104 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
105 struct ch_filter_specification *fs)
107 struct port_info *pi = ethdev2pinfo(dev);
108 struct adapter *adapter = pi->adapter;
112 * If the user has requested steering matching Ingress Packets
113 * to a specific Queue Set, we need to make sure it's in range
114 * for the port and map that into the Absolute Queue ID of the
115 * Queue Set's Response Queue.
121 * If the iq id is greater than the number of qsets,
122 * then assume it is an absolute qid.
124 if (fs->iq < pi->n_rx_qsets)
125 iq = adapter->sge.ethrxq[pi->first_qset +
134 /* Return an error number if the indicated filter isn't writable ... */
135 int writable_filter(struct filter_entry *f)
146 * Send CPL_SET_TCB_FIELD message
148 static void set_tcb_field(struct adapter *adapter, unsigned int ftid,
149 u16 word, u64 mask, u64 val, int no_reply)
151 struct rte_mbuf *mbuf;
152 struct cpl_set_tcb_field *req;
153 struct sge_ctrl_txq *ctrlq;
155 ctrlq = &adapter->sge.ctrlq[0];
156 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
159 mbuf->data_len = sizeof(*req);
160 mbuf->pkt_len = mbuf->data_len;
162 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
163 memset(req, 0, sizeof(*req));
164 INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, ftid);
165 req->reply_ctrl = cpu_to_be16(V_REPLY_CHAN(0) |
166 V_QUEUENO(adapter->sge.fw_evtq.abs_id) |
167 V_NO_REPLY(no_reply));
168 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(ftid));
169 req->mask = cpu_to_be64(mask);
170 req->val = cpu_to_be64(val);
172 t4_mgmt_tx(ctrlq, mbuf);
176 * Set one of the t_flags bits in the TCB.
178 static void set_tcb_tflag(struct adapter *adap, unsigned int ftid,
179 unsigned int bit_pos, unsigned int val, int no_reply)
181 set_tcb_field(adap, ftid, W_TCB_T_FLAGS, 1ULL << bit_pos,
182 (unsigned long long)val << bit_pos, no_reply);
186 * Build a CPL_SET_TCB_FIELD message as payload of a ULP_TX_PKT command.
188 static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
189 struct cpl_set_tcb_field *req,
191 u64 mask, u64 val, u8 cookie,
194 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
195 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
197 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
198 V_ULP_TXPKT_DEST(0));
199 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
200 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
201 sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
202 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
203 req->reply_ctrl = cpu_to_be16(V_NO_REPLY(no_reply) | V_REPLY_CHAN(0) |
205 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(cookie));
206 req->mask = cpu_to_be64(mask);
207 req->val = cpu_to_be64(val);
208 sc = (struct ulptx_idata *)(req + 1);
209 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
210 sc->len = cpu_to_be32(0);
214 * Check if entry already filled.
216 bool is_filter_set(struct tid_info *t, int fidx, int family)
221 /* IPv6 requires four slots and IPv4 requires only 1 slot.
222 * Ensure, there's enough slots available.
224 max = family == FILTER_TYPE_IPV6 ? fidx + 3 : fidx;
226 t4_os_lock(&t->ftid_lock);
227 for (i = fidx; i <= max; i++) {
228 if (rte_bitmap_get(t->ftid_bmap, i)) {
233 t4_os_unlock(&t->ftid_lock);
238 * Allocate a available free entry
240 int cxgbe_alloc_ftid(struct adapter *adap, unsigned int family)
242 struct tid_info *t = &adap->tids;
244 int size = t->nftids;
246 t4_os_lock(&t->ftid_lock);
247 if (family == FILTER_TYPE_IPV6)
248 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size, 4);
250 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
251 t4_os_unlock(&t->ftid_lock);
253 return pos < size ? pos : -1;
257 * Construct hash filter ntuple.
259 static u64 hash_filter_ntuple(const struct filter_entry *f)
261 struct adapter *adap = ethdev2adap(f->dev);
262 struct tp_params *tp = &adap->params.tp;
264 u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
266 if (tp->port_shift >= 0 && f->fs.mask.iport)
267 ntuple |= (u64)f->fs.val.iport << tp->port_shift;
269 if (tp->protocol_shift >= 0) {
270 if (!f->fs.val.proto)
271 ntuple |= (u64)tcp_proto << tp->protocol_shift;
273 ntuple |= (u64)f->fs.val.proto << tp->protocol_shift;
276 if (tp->ethertype_shift >= 0 && f->fs.mask.ethtype)
277 ntuple |= (u64)(f->fs.val.ethtype) << tp->ethertype_shift;
278 if (tp->macmatch_shift >= 0 && f->fs.mask.macidx)
279 ntuple |= (u64)(f->fs.val.macidx) << tp->macmatch_shift;
285 * Build a CPL_ABORT_REQ message as payload of a ULP_TX_PKT command.
287 static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
290 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_req;
291 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
293 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
294 V_ULP_TXPKT_DEST(0));
295 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
296 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
297 sc->len = cpu_to_be32(sizeof(*abort_req) -
298 sizeof(struct work_request_hdr));
299 OPCODE_TID(abort_req) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_REQ, tid));
300 abort_req->rsvd0 = cpu_to_be32(0);
301 abort_req->rsvd1 = 0;
302 abort_req->cmd = CPL_ABORT_NO_RST;
303 sc = (struct ulptx_idata *)(abort_req + 1);
304 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
305 sc->len = cpu_to_be32(0);
309 * Build a CPL_ABORT_RPL message as payload of a ULP_TX_PKT command.
311 static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
314 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_rpl;
315 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
317 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
318 V_ULP_TXPKT_DEST(0));
319 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
320 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
321 sc->len = cpu_to_be32(sizeof(*abort_rpl) -
322 sizeof(struct work_request_hdr));
323 OPCODE_TID(abort_rpl) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_RPL, tid));
324 abort_rpl->rsvd0 = cpu_to_be32(0);
325 abort_rpl->rsvd1 = 0;
326 abort_rpl->cmd = CPL_ABORT_NO_RST;
327 sc = (struct ulptx_idata *)(abort_rpl + 1);
328 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
329 sc->len = cpu_to_be32(0);
333 * Delete the specified hash filter.
335 static int cxgbe_del_hash_filter(struct rte_eth_dev *dev,
336 unsigned int filter_id,
337 struct filter_ctx *ctx)
339 struct adapter *adapter = ethdev2adap(dev);
340 struct tid_info *t = &adapter->tids;
341 struct filter_entry *f;
342 struct sge_ctrl_txq *ctrlq;
343 unsigned int port_id = ethdev2pinfo(dev)->port_id;
346 if (filter_id > adapter->tids.ntids)
349 f = lookup_tid(t, filter_id);
351 dev_err(adapter, "%s: no filter entry for filter_id = %d\n",
352 __func__, filter_id);
356 ret = writable_filter(f);
362 struct rte_mbuf *mbuf;
363 struct work_request_hdr *wr;
364 struct ulptx_idata *aligner;
365 struct cpl_set_tcb_field *req;
366 struct cpl_abort_req *abort_req;
367 struct cpl_abort_rpl *abort_rpl;
372 wrlen = cxgbe_roundup(sizeof(*wr) +
373 (sizeof(*req) + sizeof(*aligner)) +
374 sizeof(*abort_req) + sizeof(*abort_rpl),
377 ctrlq = &adapter->sge.ctrlq[port_id];
378 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
380 dev_err(adapter, "%s: could not allocate skb ..\n",
385 mbuf->data_len = wrlen;
386 mbuf->pkt_len = mbuf->data_len;
388 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
389 INIT_ULPTX_WR(req, wrlen, 0, 0);
390 wr = (struct work_request_hdr *)req;
392 req = (struct cpl_set_tcb_field *)wr;
393 mk_set_tcb_field_ulp(f, req, W_TCB_RSS_INFO,
394 V_TCB_RSS_INFO(M_TCB_RSS_INFO),
395 V_TCB_RSS_INFO(adapter->sge.fw_evtq.abs_id),
397 aligner = (struct ulptx_idata *)(req + 1);
398 abort_req = (struct cpl_abort_req *)(aligner + 1);
399 mk_abort_req_ulp(abort_req, f->tid);
400 abort_rpl = (struct cpl_abort_rpl *)(abort_req + 1);
401 mk_abort_rpl_ulp(abort_rpl, f->tid);
402 t4_mgmt_tx(ctrlq, mbuf);
411 * Build a ACT_OPEN_REQ6 message for setting IPv6 hash filter.
413 static void mk_act_open_req6(struct filter_entry *f, struct rte_mbuf *mbuf,
414 unsigned int qid_filterid, struct adapter *adap)
416 struct cpl_t6_act_open_req6 *req = NULL;
417 u64 local_lo, local_hi, peer_lo, peer_hi;
418 u32 *lip = (u32 *)f->fs.val.lip;
419 u32 *fip = (u32 *)f->fs.val.fip;
421 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
423 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req6 *);
428 dev_err(adap, "%s: unsupported chip type!\n", __func__);
432 local_hi = ((u64)lip[1]) << 32 | lip[0];
433 local_lo = ((u64)lip[3]) << 32 | lip[2];
434 peer_hi = ((u64)fip[1]) << 32 | fip[0];
435 peer_lo = ((u64)fip[3]) << 32 | fip[2];
437 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
439 req->local_port = cpu_to_be16(f->fs.val.lport);
440 req->peer_port = cpu_to_be16(f->fs.val.fport);
441 req->local_ip_hi = local_hi;
442 req->local_ip_lo = local_lo;
443 req->peer_ip_hi = peer_hi;
444 req->peer_ip_lo = peer_lo;
445 req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
446 f->fs.newvlan == VLAN_REWRITE) |
447 V_DELACK(f->fs.hitcnts) |
448 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
449 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
451 V_TX_CHAN(f->fs.eport) |
452 V_ULP_MODE(ULP_MODE_NONE) |
453 F_TCAM_BYPASS | F_NON_OFFLOAD);
454 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
455 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
456 V_RSS_QUEUE(f->fs.iq) |
459 V_SACK_EN(f->fs.swapmac) |
460 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
461 (f->fs.dirsteer << 1)) |
462 V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
466 * Build a ACT_OPEN_REQ message for setting IPv4 hash filter.
468 static void mk_act_open_req(struct filter_entry *f, struct rte_mbuf *mbuf,
469 unsigned int qid_filterid, struct adapter *adap)
471 struct cpl_t6_act_open_req *req = NULL;
473 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
475 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req *);
480 dev_err(adap, "%s: unsupported chip type!\n", __func__);
484 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
486 req->local_port = cpu_to_be16(f->fs.val.lport);
487 req->peer_port = cpu_to_be16(f->fs.val.fport);
488 req->local_ip = f->fs.val.lip[0] | f->fs.val.lip[1] << 8 |
489 f->fs.val.lip[2] << 16 | f->fs.val.lip[3] << 24;
490 req->peer_ip = f->fs.val.fip[0] | f->fs.val.fip[1] << 8 |
491 f->fs.val.fip[2] << 16 | f->fs.val.fip[3] << 24;
492 req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
493 f->fs.newvlan == VLAN_REWRITE) |
494 V_DELACK(f->fs.hitcnts) |
495 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
496 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
498 V_TX_CHAN(f->fs.eport) |
499 V_ULP_MODE(ULP_MODE_NONE) |
500 F_TCAM_BYPASS | F_NON_OFFLOAD);
501 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
502 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
503 V_RSS_QUEUE(f->fs.iq) |
506 V_SACK_EN(f->fs.swapmac) |
507 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
508 (f->fs.dirsteer << 1)) |
509 V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
513 * Set the specified hash filter.
515 static int cxgbe_set_hash_filter(struct rte_eth_dev *dev,
516 struct ch_filter_specification *fs,
517 struct filter_ctx *ctx)
519 struct port_info *pi = ethdev2pinfo(dev);
520 struct adapter *adapter = pi->adapter;
521 struct tid_info *t = &adapter->tids;
522 struct filter_entry *f;
523 struct rte_mbuf *mbuf;
524 struct sge_ctrl_txq *ctrlq;
529 ret = validate_filter(adapter, fs);
533 iq = get_filter_steerq(dev, fs);
535 ctrlq = &adapter->sge.ctrlq[pi->port_id];
537 f = t4_os_alloc(sizeof(*f));
547 * If the new filter requires loopback Destination MAC and/or VLAN
548 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
551 if (f->fs.newvlan == VLAN_INSERT ||
552 f->fs.newvlan == VLAN_REWRITE) {
553 /* allocate L2T entry for new filter */
554 f->l2t = cxgbe_l2t_alloc_switching(dev, f->fs.vlan,
555 f->fs.eport, f->fs.dmac);
562 atid = cxgbe_alloc_atid(t, f);
567 /* IPv6 hash filter */
568 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
572 size = sizeof(struct cpl_t6_act_open_req6);
573 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
579 mbuf->data_len = size;
580 mbuf->pkt_len = mbuf->data_len;
582 mk_act_open_req6(f, mbuf,
583 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
586 /* IPv4 hash filter */
587 size = sizeof(struct cpl_t6_act_open_req);
588 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
594 mbuf->data_len = size;
595 mbuf->pkt_len = mbuf->data_len;
597 mk_act_open_req(f, mbuf,
598 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
603 t4_mgmt_tx(ctrlq, mbuf);
607 cxgbe_clip_release(f->dev, f->clipt);
609 cxgbe_free_atid(t, atid);
617 * Clear a filter and release any of its resources that we own. This also
618 * clears the filter's "pending" status.
620 void clear_filter(struct filter_entry *f)
623 cxgbe_clip_release(f->dev, f->clipt);
626 * The zeroing of the filter rule below clears the filter valid,
627 * pending, locked flags etc. so it's all we need for
630 memset(f, 0, sizeof(*f));
634 * t4_mk_filtdelwr - create a delete filter WR
635 * @adap: adapter context
636 * @ftid: the filter ID
637 * @wr: the filter work request to populate
638 * @qid: ingress queue to receive the delete notification
640 * Creates a filter work request to delete the supplied filter. If @qid is
641 * negative the delete notification is suppressed.
643 static void t4_mk_filtdelwr(struct adapter *adap, unsigned int ftid,
644 struct fw_filter2_wr *wr, int qid)
646 memset(wr, 0, sizeof(*wr));
647 if (adap->params.filter2_wr_support)
648 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
650 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
651 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
652 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
653 V_FW_FILTER_WR_NOREPLY(qid < 0));
654 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
656 wr->rx_chan_rx_rpl_iq =
657 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
661 * Create FW work request to delete the filter at a specified index
663 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
665 struct adapter *adapter = ethdev2adap(dev);
666 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
667 struct rte_mbuf *mbuf;
668 struct fw_filter2_wr *fwr;
669 struct sge_ctrl_txq *ctrlq;
670 unsigned int port_id = ethdev2pinfo(dev)->port_id;
672 ctrlq = &adapter->sge.ctrlq[port_id];
673 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
677 mbuf->data_len = sizeof(*fwr);
678 mbuf->pkt_len = mbuf->data_len;
680 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
681 t4_mk_filtdelwr(adapter, f->tid, fwr, adapter->sge.fw_evtq.abs_id);
684 * Mark the filter as "pending" and ship off the Filter Work Request.
685 * When we get the Work Request Reply we'll clear the pending status.
688 t4_mgmt_tx(ctrlq, mbuf);
692 int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
694 struct adapter *adapter = ethdev2adap(dev);
695 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
696 struct rte_mbuf *mbuf;
697 struct fw_filter2_wr *fwr;
698 struct sge_ctrl_txq *ctrlq;
699 unsigned int port_id = ethdev2pinfo(dev)->port_id;
703 * If the new filter requires loopback Destination MAC and/or VLAN
704 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
708 /* allocate L2T entry for new filter */
709 f->l2t = cxgbe_l2t_alloc_switching(f->dev, f->fs.vlan,
710 f->fs.eport, f->fs.dmac);
715 ctrlq = &adapter->sge.ctrlq[port_id];
716 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
722 mbuf->data_len = sizeof(*fwr);
723 mbuf->pkt_len = mbuf->data_len;
725 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
726 memset(fwr, 0, sizeof(*fwr));
729 * Construct the work request to set the filter.
731 if (adapter->params.filter2_wr_support)
732 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
734 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
735 fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
737 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
738 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
739 V_FW_FILTER_WR_NOREPLY(0) |
740 V_FW_FILTER_WR_IQ(f->fs.iq));
741 fwr->del_filter_to_l2tix =
742 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
743 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
744 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
745 V_FW_FILTER_WR_INSVLAN
746 (f->fs.newvlan == VLAN_INSERT ||
747 f->fs.newvlan == VLAN_REWRITE) |
748 V_FW_FILTER_WR_RMVLAN
749 (f->fs.newvlan == VLAN_REMOVE ||
750 f->fs.newvlan == VLAN_REWRITE) |
751 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
752 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
753 V_FW_FILTER_WR_PRIO(f->fs.prio) |
754 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
755 fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
756 fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
758 fwr->rx_chan_rx_rpl_iq =
759 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
760 V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
762 fwr->maci_to_matchtypem =
763 cpu_to_be32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
764 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
765 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
766 V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
767 fwr->ptcl = f->fs.val.proto;
768 fwr->ptclm = f->fs.mask.proto;
769 rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
770 rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
771 rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
772 rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
773 fwr->lp = cpu_to_be16(f->fs.val.lport);
774 fwr->lpm = cpu_to_be16(f->fs.mask.lport);
775 fwr->fp = cpu_to_be16(f->fs.val.fport);
776 fwr->fpm = cpu_to_be16(f->fs.mask.fport);
778 if (adapter->params.filter2_wr_support) {
779 fwr->filter_type_swapmac =
780 V_FW_FILTER2_WR_SWAPMAC(f->fs.swapmac);
781 fwr->natmode_to_ulp_type =
782 V_FW_FILTER2_WR_ULP_TYPE(f->fs.nat_mode ?
785 V_FW_FILTER2_WR_NATMODE(f->fs.nat_mode);
786 memcpy(fwr->newlip, f->fs.nat_lip, sizeof(fwr->newlip));
787 memcpy(fwr->newfip, f->fs.nat_fip, sizeof(fwr->newfip));
788 fwr->newlport = cpu_to_be16(f->fs.nat_lport);
789 fwr->newfport = cpu_to_be16(f->fs.nat_fport);
793 * Mark the filter as "pending" and ship off the Filter Work Request.
794 * When we get the Work Request Reply we'll clear the pending status.
797 t4_mgmt_tx(ctrlq, mbuf);
805 * Set the corresponding entry in the bitmap. 4 slots are
806 * marked for IPv6, whereas only 1 slot is marked for IPv4.
808 static int cxgbe_set_ftid(struct tid_info *t, int fidx, int family)
810 t4_os_lock(&t->ftid_lock);
811 if (rte_bitmap_get(t->ftid_bmap, fidx)) {
812 t4_os_unlock(&t->ftid_lock);
816 if (family == FILTER_TYPE_IPV4) {
817 rte_bitmap_set(t->ftid_bmap, fidx);
819 rte_bitmap_set(t->ftid_bmap, fidx);
820 rte_bitmap_set(t->ftid_bmap, fidx + 1);
821 rte_bitmap_set(t->ftid_bmap, fidx + 2);
822 rte_bitmap_set(t->ftid_bmap, fidx + 3);
824 t4_os_unlock(&t->ftid_lock);
829 * Clear the corresponding entry in the bitmap. 4 slots are
830 * cleared for IPv6, whereas only 1 slot is cleared for IPv4.
832 static void cxgbe_clear_ftid(struct tid_info *t, int fidx, int family)
834 t4_os_lock(&t->ftid_lock);
835 if (family == FILTER_TYPE_IPV4) {
836 rte_bitmap_clear(t->ftid_bmap, fidx);
838 rte_bitmap_clear(t->ftid_bmap, fidx);
839 rte_bitmap_clear(t->ftid_bmap, fidx + 1);
840 rte_bitmap_clear(t->ftid_bmap, fidx + 2);
841 rte_bitmap_clear(t->ftid_bmap, fidx + 3);
843 t4_os_unlock(&t->ftid_lock);
847 * Check a delete filter request for validity and send it to the hardware.
848 * Return 0 on success, an error number otherwise. We attach any provided
849 * filter operation context to the internal filter specification in order to
850 * facilitate signaling completion of the operation.
852 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
853 struct ch_filter_specification *fs,
854 struct filter_ctx *ctx)
856 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
857 struct adapter *adapter = pi->adapter;
858 struct filter_entry *f;
859 unsigned int chip_ver;
862 if (is_hashfilter(adapter) && fs->cap)
863 return cxgbe_del_hash_filter(dev, filter_id, ctx);
865 if (filter_id >= adapter->tids.nftids)
868 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
870 ret = is_filter_set(&adapter->tids, filter_id, fs->type);
872 dev_warn(adap, "%s: could not find filter entry: %u\n",
873 __func__, filter_id);
878 * Ensure filter id is aligned on the 2 slot boundary for T6,
879 * and 4 slot boundary for cards below T6.
882 if (chip_ver < CHELSIO_T6)
888 f = &adapter->tids.ftid_tab[filter_id];
889 ret = writable_filter(f);
895 cxgbe_clear_ftid(&adapter->tids,
896 f->tid - adapter->tids.ftid_base,
897 f->fs.type ? FILTER_TYPE_IPV6 :
899 return del_filter_wr(dev, filter_id);
903 * If the caller has passed in a Completion Context then we need to
904 * mark it as a successful completion so they don't stall waiting
909 t4_complete(&ctx->completion);
916 * Check a Chelsio Filter Request for validity, convert it into our internal
917 * format and send it to the hardware. Return 0 on success, an error number
918 * otherwise. We attach any provided filter operation context to the internal
919 * filter specification in order to facilitate signaling completion of the
922 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
923 struct ch_filter_specification *fs,
924 struct filter_ctx *ctx)
926 struct port_info *pi = ethdev2pinfo(dev);
927 struct adapter *adapter = pi->adapter;
928 unsigned int fidx, iq, fid_bit = 0;
929 struct filter_entry *f;
930 unsigned int chip_ver;
931 uint8_t bitoff[16] = {0};
934 if (is_hashfilter(adapter) && fs->cap)
935 return cxgbe_set_hash_filter(dev, fs, ctx);
937 if (filter_id >= adapter->tids.nftids)
940 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
942 ret = validate_filter(adapter, fs);
947 * Ensure filter id is aligned on the 4 slot boundary for IPv6
953 ret = is_filter_set(&adapter->tids, filter_id, fs->type);
957 iq = get_filter_steerq(dev, fs);
960 * IPv6 filters occupy four slots and must be aligned on four-slot
961 * boundaries for T5. On T6, IPv6 filters occupy two-slots and
962 * must be aligned on two-slot boundaries.
964 * IPv4 filters only occupy a single slot and have no alignment
965 * requirements but writing a new IPv4 filter into the middle
966 * of an existing IPv6 filter requires clearing the old IPv6
969 if (fs->type == FILTER_TYPE_IPV4) { /* IPv4 */
971 * For T6, If our IPv4 filter isn't being written to a
972 * multiple of two filter index and there's an IPv6
973 * filter at the multiple of 2 base slot, then we need
974 * to delete that IPv6 filter ...
975 * For adapters below T6, IPv6 filter occupies 4 entries.
977 if (chip_ver < CHELSIO_T6)
978 fidx = filter_id & ~0x3;
980 fidx = filter_id & ~0x1;
982 if (fidx != filter_id && adapter->tids.ftid_tab[fidx].fs.type) {
983 f = &adapter->tids.ftid_tab[fidx];
988 unsigned int max_filter_id;
990 if (chip_ver < CHELSIO_T6) {
992 * Ensure that the IPv6 filter is aligned on a
993 * multiple of 4 boundary.
998 max_filter_id = filter_id + 4;
1001 * For T6, CLIP being enabled, IPv6 filter would occupy
1004 if (filter_id & 0x1)
1007 max_filter_id = filter_id + 2;
1011 * Check all except the base overlapping IPv4 filter
1014 for (fidx = filter_id + 1; fidx < max_filter_id; fidx++) {
1015 f = &adapter->tids.ftid_tab[fidx];
1022 * Check to make sure that provided filter index is not
1023 * already in use by someone else
1025 f = &adapter->tids.ftid_tab[filter_id];
1029 fidx = adapter->tids.ftid_base + filter_id;
1030 fid_bit = filter_id;
1031 ret = cxgbe_set_ftid(&adapter->tids, fid_bit,
1032 fs->type ? FILTER_TYPE_IPV6 : FILTER_TYPE_IPV4);
1037 * Check to make sure the filter requested is writable ...
1039 ret = writable_filter(f);
1041 /* Clear the bits we have set above */
1042 cxgbe_clear_ftid(&adapter->tids, fid_bit,
1043 fs->type ? FILTER_TYPE_IPV6 :
1049 * Allocate a clip table entry only if we have non-zero IPv6 address
1051 if (chip_ver > CHELSIO_T5 && fs->type &&
1052 memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
1053 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
1059 * Convert the filter specification into our internal format.
1060 * We copy the PF/VF specification into the Outer VLAN field
1061 * here so the rest of the code -- including the interface to
1062 * the firmware -- doesn't have to constantly do these checks.
1069 * Attempt to set the filter. If we don't succeed, we clear
1070 * it and return the failure.
1073 f->tid = fidx; /* Save the actual tid */
1074 ret = set_filter_wr(dev, filter_id);
1076 fid_bit = f->tid - adapter->tids.ftid_base;
1083 cxgbe_clear_ftid(&adapter->tids, fid_bit,
1084 fs->type ? FILTER_TYPE_IPV6 :
1091 * Handle a Hash filter write reply.
1093 void hash_filter_rpl(struct adapter *adap, const struct cpl_act_open_rpl *rpl)
1095 struct tid_info *t = &adap->tids;
1096 struct filter_entry *f;
1097 struct filter_ctx *ctx = NULL;
1098 unsigned int tid = GET_TID(rpl);
1099 unsigned int ftid = G_TID_TID(G_AOPEN_ATID
1100 (be32_to_cpu(rpl->atid_status)));
1101 unsigned int status = G_AOPEN_STATUS(be32_to_cpu(rpl->atid_status));
1103 f = lookup_atid(t, ftid);
1105 dev_warn(adap, "%s: could not find filter entry: %d\n",
1114 case CPL_ERR_NONE: {
1116 f->pending = 0; /* asynchronous setup completed */
1119 cxgbe_insert_tid(t, f, f->tid, 0);
1120 cxgbe_free_atid(t, ftid);
1126 set_tcb_field(adap, tid,
1128 V_TCB_TIMESTAMP(M_TCB_TIMESTAMP) |
1129 V_TCB_T_RTT_TS_RECENT_AGE
1130 (M_TCB_T_RTT_TS_RECENT_AGE),
1131 V_TCB_TIMESTAMP(0ULL) |
1132 V_TCB_T_RTT_TS_RECENT_AGE(0ULL),
1134 if (f->fs.newvlan == VLAN_INSERT ||
1135 f->fs.newvlan == VLAN_REWRITE)
1136 set_tcb_tflag(adap, tid, S_TF_CCTRL_RFR, 1, 1);
1140 dev_warn(adap, "%s: filter creation failed with status = %u\n",
1144 if (status == CPL_ERR_TCAM_FULL)
1145 ctx->result = -EAGAIN;
1147 ctx->result = -EINVAL;
1150 cxgbe_free_atid(t, ftid);
1155 t4_complete(&ctx->completion);
1159 * Handle a LE-TCAM filter write/deletion reply.
1161 void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
1163 struct filter_entry *f = NULL;
1164 unsigned int tid = GET_TID(rpl);
1165 int idx, max_fidx = adap->tids.nftids;
1167 /* Get the corresponding filter entry for this tid */
1168 if (adap->tids.ftid_tab) {
1169 /* Check this in normal filter region */
1170 idx = tid - adap->tids.ftid_base;
1171 if (idx >= max_fidx)
1174 f = &adap->tids.ftid_tab[idx];
1179 /* We found the filter entry for this tid */
1181 unsigned int ret = G_COOKIE(rpl->cookie);
1182 struct filter_ctx *ctx;
1185 * Pull off any filter operation context attached to the
1191 if (ret == FW_FILTER_WR_FLT_ADDED) {
1192 f->pending = 0; /* asynchronous setup completed */
1198 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
1200 * Clear the filter when we get confirmation from the
1201 * hardware that the filter has been deleted.
1208 * Something went wrong. Issue a warning about the
1209 * problem and clear everything out.
1211 dev_warn(adap, "filter %u setup failed with error %u\n",
1215 ctx->result = -EINVAL;
1219 t4_complete(&ctx->completion);
1224 * Retrieve the packet count for the specified filter.
1226 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
1227 u64 *c, int hash, bool get_byte)
1229 struct filter_entry *f;
1230 unsigned int tcb_base, tcbaddr;
1233 tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
1234 if (is_hashfilter(adapter) && hash) {
1235 if (fidx < adapter->tids.ntids) {
1236 f = adapter->tids.tid_tab[fidx];
1240 if (is_t5(adapter->params.chip)) {
1244 tcbaddr = tcb_base + (fidx * TCB_SIZE);
1250 if (fidx >= adapter->tids.nftids)
1253 f = &adapter->tids.ftid_tab[fidx];
1257 tcbaddr = tcb_base + f->tid * TCB_SIZE;
1260 f = &adapter->tids.ftid_tab[fidx];
1265 if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
1267 * For T5, the Filter Packet Hit Count is maintained as a
1268 * 32-bit Big Endian value in the TCB field {timestamp}.
1269 * Similar to the craziness above, instead of the filter hit
1270 * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
1271 * sizeof(u32)), it actually shows up at offset 24. Whacky.
1274 unsigned int word_offset = 4;
1275 __be64 be64_byte_count;
1277 t4_os_lock(&adapter->win0_lock);
1278 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1280 (word_offset * sizeof(__be32)),
1281 sizeof(be64_byte_count),
1284 t4_os_unlock(&adapter->win0_lock);
1287 *c = be64_to_cpu(be64_byte_count);
1289 unsigned int word_offset = 6;
1292 t4_os_lock(&adapter->win0_lock);
1293 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1295 (word_offset * sizeof(__be32)),
1296 sizeof(be32_count), &be32_count,
1298 t4_os_unlock(&adapter->win0_lock);
1301 *c = (u64)be32_to_cpu(be32_count);
1308 * Handle a Hash filter delete reply.
1310 void hash_del_filter_rpl(struct adapter *adap,
1311 const struct cpl_abort_rpl_rss *rpl)
1313 struct tid_info *t = &adap->tids;
1314 struct filter_entry *f;
1315 struct filter_ctx *ctx = NULL;
1316 unsigned int tid = GET_TID(rpl);
1318 f = lookup_tid(t, tid);
1320 dev_warn(adap, "%s: could not find filter entry: %u\n",
1331 cxgbe_clip_release(f->dev, f->clipt);
1333 cxgbe_remove_tid(t, 0, tid, 0);
1338 t4_complete(&ctx->completion);