1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Chelsio Communications.
7 #include "base/common.h"
8 #include "base/t4_tcb.h"
9 #include "base/t4_regs.h"
10 #include "cxgbe_filter.h"
15 * Initialize Hash Filters
17 int cxgbe_init_hash_filter(struct adapter *adap)
19 unsigned int n_user_filters;
20 unsigned int user_filter_perc;
22 u32 params[7], val[7];
24 #define FW_PARAM_DEV(param) \
25 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
26 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
28 #define FW_PARAM_PFVF(param) \
29 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
30 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
31 V_FW_PARAMS_PARAM_Y(0) | \
32 V_FW_PARAMS_PARAM_Z(0))
34 params[0] = FW_PARAM_DEV(NTID);
35 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
39 adap->tids.ntids = val[0];
40 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
42 user_filter_perc = 100;
43 n_user_filters = mult_frac(adap->tids.nftids,
47 adap->tids.nftids = n_user_filters;
48 adap->params.hash_filter = 1;
53 * Validate if the requested filter specification can be set by checking
54 * if the requested features have been enabled
56 int cxgbe_validate_filter(struct adapter *adapter,
57 struct ch_filter_specification *fs)
62 * Check for unconfigured fields being used.
64 fconf = adapter->params.tp.vlan_pri_map;
66 iconf = adapter->params.tp.ingress_config;
69 (fs->val._field || fs->mask._field)
70 #define U(_mask, _field) \
71 (!(fconf & (_mask)) && S(_field))
73 if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) ||
74 U(F_PROTOCOL, proto) || U(F_MACMATCH, macidx) ||
75 U(F_VLAN, ivlan_vld) || U(F_VNIC_ID, ovlan_vld) ||
76 U(F_TOS, tos) || U(F_VNIC_ID, pfvf_vld))
79 /* Either OVLAN or PFVF match is enabled in hardware, but not both */
80 if ((S(pfvf_vld) && !(iconf & F_VNIC)) ||
81 (S(ovlan_vld) && (iconf & F_VNIC)))
84 /* To use OVLAN or PFVF, L4 encapsulation match must not be enabled */
85 if ((S(ovlan_vld) && (iconf & F_USE_ENC_IDX)) ||
86 (S(pfvf_vld) && (iconf & F_USE_ENC_IDX)))
93 * If the user is requesting that the filter action loop
94 * matching packets back out one of our ports, make sure that
95 * the egress port is in range.
97 if (fs->action == FILTER_SWITCH &&
98 fs->eport >= adapter->params.nports)
102 * Don't allow various trivially obvious bogus out-of-range
105 if (fs->val.iport >= adapter->params.nports)
108 if (!fs->cap && fs->nat_mode && !adapter->params.filter2_wr_support)
111 if (!fs->cap && fs->swapmac && !adapter->params.filter2_wr_support)
118 * Get the queue to which the traffic must be steered to.
120 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
121 struct ch_filter_specification *fs)
123 struct port_info *pi = ethdev2pinfo(dev);
124 struct adapter *adapter = pi->adapter;
128 * If the user has requested steering matching Ingress Packets
129 * to a specific Queue Set, we need to make sure it's in range
130 * for the port and map that into the Absolute Queue ID of the
131 * Queue Set's Response Queue.
137 * If the iq id is greater than the number of qsets,
138 * then assume it is an absolute qid.
140 if (fs->iq < pi->n_rx_qsets)
141 iq = adapter->sge.ethrxq[pi->first_qset +
150 /* Return an error number if the indicated filter isn't writable ... */
151 static int writable_filter(struct filter_entry *f)
162 * Send CPL_SET_TCB_FIELD message
164 static void set_tcb_field(struct adapter *adapter, unsigned int ftid,
165 u16 word, u64 mask, u64 val, int no_reply)
167 struct rte_mbuf *mbuf;
168 struct cpl_set_tcb_field *req;
169 struct sge_ctrl_txq *ctrlq;
171 ctrlq = &adapter->sge.ctrlq[0];
172 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
175 mbuf->data_len = sizeof(*req);
176 mbuf->pkt_len = mbuf->data_len;
178 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
179 memset(req, 0, sizeof(*req));
180 INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, ftid);
181 req->reply_ctrl = cpu_to_be16(V_REPLY_CHAN(0) |
182 V_QUEUENO(adapter->sge.fw_evtq.abs_id) |
183 V_NO_REPLY(no_reply));
184 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(ftid));
185 req->mask = cpu_to_be64(mask);
186 req->val = cpu_to_be64(val);
188 t4_mgmt_tx(ctrlq, mbuf);
192 * Set one of the t_flags bits in the TCB.
194 static void set_tcb_tflag(struct adapter *adap, unsigned int ftid,
195 unsigned int bit_pos, unsigned int val, int no_reply)
197 set_tcb_field(adap, ftid, W_TCB_T_FLAGS, 1ULL << bit_pos,
198 (unsigned long long)val << bit_pos, no_reply);
202 * Build a CPL_SET_TCB_FIELD message as payload of a ULP_TX_PKT command.
204 static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
205 struct cpl_set_tcb_field *req,
207 u64 mask, u64 val, u8 cookie,
210 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
211 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
213 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
214 V_ULP_TXPKT_DEST(0));
215 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
216 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
217 sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
218 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
219 req->reply_ctrl = cpu_to_be16(V_NO_REPLY(no_reply) | V_REPLY_CHAN(0) |
221 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(cookie));
222 req->mask = cpu_to_be64(mask);
223 req->val = cpu_to_be64(val);
224 sc = (struct ulptx_idata *)(req + 1);
225 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
226 sc->len = cpu_to_be32(0);
230 * IPv6 requires 2 slots on T6 and 4 slots for cards below T6.
231 * IPv4 requires only 1 slot on all cards.
233 u8 cxgbe_filter_slots(struct adapter *adap, u8 family)
235 if (family == FILTER_TYPE_IPV6) {
236 if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T6)
246 * Check if entries are already filled.
248 bool cxgbe_is_filter_set(struct tid_info *t, u32 fidx, u8 nentries)
253 /* Ensure there's enough slots available. */
254 t4_os_lock(&t->ftid_lock);
255 for (i = fidx; i < fidx + nentries; i++) {
256 if (rte_bitmap_get(t->ftid_bmap, i)) {
261 t4_os_unlock(&t->ftid_lock);
266 * Allocate available free entries.
268 int cxgbe_alloc_ftid(struct adapter *adap, u8 nentries)
270 struct tid_info *t = &adap->tids;
272 int size = t->nftids;
274 t4_os_lock(&t->ftid_lock);
276 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size,
279 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
280 t4_os_unlock(&t->ftid_lock);
282 return pos < size ? pos : -1;
286 * Construct hash filter ntuple.
288 static u64 hash_filter_ntuple(const struct filter_entry *f)
290 struct adapter *adap = ethdev2adap(f->dev);
291 struct tp_params *tp = &adap->params.tp;
293 u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
295 if (tp->port_shift >= 0 && f->fs.mask.iport)
296 ntuple |= (u64)f->fs.val.iport << tp->port_shift;
298 if (tp->protocol_shift >= 0) {
299 if (!f->fs.val.proto)
300 ntuple |= (u64)tcp_proto << tp->protocol_shift;
302 ntuple |= (u64)f->fs.val.proto << tp->protocol_shift;
305 if (tp->ethertype_shift >= 0 && f->fs.mask.ethtype)
306 ntuple |= (u64)(f->fs.val.ethtype) << tp->ethertype_shift;
307 if (tp->macmatch_shift >= 0 && f->fs.mask.macidx)
308 ntuple |= (u64)(f->fs.val.macidx) << tp->macmatch_shift;
309 if (tp->vlan_shift >= 0 && f->fs.mask.ivlan)
310 ntuple |= (u64)(F_FT_VLAN_VLD | f->fs.val.ivlan) <<
312 if (tp->vnic_shift >= 0) {
313 if ((adap->params.tp.ingress_config & F_VNIC) &&
315 ntuple |= (u64)((f->fs.val.pfvf_vld << 16) |
316 (f->fs.val.pf << 13)) << tp->vnic_shift;
317 else if (!(adap->params.tp.ingress_config & F_VNIC) &&
318 f->fs.mask.ovlan_vld)
319 ntuple |= (u64)(f->fs.val.ovlan_vld << 16 |
320 f->fs.val.ovlan) << tp->vnic_shift;
322 if (tp->tos_shift >= 0 && f->fs.mask.tos)
323 ntuple |= (u64)f->fs.val.tos << tp->tos_shift;
329 * Build a CPL_ABORT_REQ message as payload of a ULP_TX_PKT command.
331 static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
334 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_req;
335 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
337 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
338 V_ULP_TXPKT_DEST(0));
339 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
340 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
341 sc->len = cpu_to_be32(sizeof(*abort_req) -
342 sizeof(struct work_request_hdr));
343 OPCODE_TID(abort_req) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_REQ, tid));
344 abort_req->rsvd0 = cpu_to_be32(0);
345 abort_req->rsvd1 = 0;
346 abort_req->cmd = CPL_ABORT_NO_RST;
347 sc = (struct ulptx_idata *)(abort_req + 1);
348 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
349 sc->len = cpu_to_be32(0);
353 * Build a CPL_ABORT_RPL message as payload of a ULP_TX_PKT command.
355 static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
358 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_rpl;
359 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
361 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
362 V_ULP_TXPKT_DEST(0));
363 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
364 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
365 sc->len = cpu_to_be32(sizeof(*abort_rpl) -
366 sizeof(struct work_request_hdr));
367 OPCODE_TID(abort_rpl) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_RPL, tid));
368 abort_rpl->rsvd0 = cpu_to_be32(0);
369 abort_rpl->rsvd1 = 0;
370 abort_rpl->cmd = CPL_ABORT_NO_RST;
371 sc = (struct ulptx_idata *)(abort_rpl + 1);
372 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
373 sc->len = cpu_to_be32(0);
377 * Delete the specified hash filter.
379 static int cxgbe_del_hash_filter(struct rte_eth_dev *dev,
380 unsigned int filter_id,
381 struct filter_ctx *ctx)
383 struct adapter *adapter = ethdev2adap(dev);
384 struct tid_info *t = &adapter->tids;
385 struct filter_entry *f;
386 struct sge_ctrl_txq *ctrlq;
387 unsigned int port_id = ethdev2pinfo(dev)->port_id;
390 if (filter_id > adapter->tids.ntids)
393 f = lookup_tid(t, filter_id);
395 dev_err(adapter, "%s: no filter entry for filter_id = %d\n",
396 __func__, filter_id);
400 ret = writable_filter(f);
406 struct rte_mbuf *mbuf;
407 struct work_request_hdr *wr;
408 struct ulptx_idata *aligner;
409 struct cpl_set_tcb_field *req;
410 struct cpl_abort_req *abort_req;
411 struct cpl_abort_rpl *abort_rpl;
416 wrlen = cxgbe_roundup(sizeof(*wr) +
417 (sizeof(*req) + sizeof(*aligner)) +
418 sizeof(*abort_req) + sizeof(*abort_rpl),
421 ctrlq = &adapter->sge.ctrlq[port_id];
422 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
424 dev_err(adapter, "%s: could not allocate skb ..\n",
429 mbuf->data_len = wrlen;
430 mbuf->pkt_len = mbuf->data_len;
432 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
433 INIT_ULPTX_WR(req, wrlen, 0, 0);
434 wr = (struct work_request_hdr *)req;
436 req = (struct cpl_set_tcb_field *)wr;
437 mk_set_tcb_field_ulp(f, req, W_TCB_RSS_INFO,
438 V_TCB_RSS_INFO(M_TCB_RSS_INFO),
439 V_TCB_RSS_INFO(adapter->sge.fw_evtq.abs_id),
441 aligner = (struct ulptx_idata *)(req + 1);
442 abort_req = (struct cpl_abort_req *)(aligner + 1);
443 mk_abort_req_ulp(abort_req, f->tid);
444 abort_rpl = (struct cpl_abort_rpl *)(abort_req + 1);
445 mk_abort_rpl_ulp(abort_rpl, f->tid);
446 t4_mgmt_tx(ctrlq, mbuf);
455 * Build a ACT_OPEN_REQ6 message for setting IPv6 hash filter.
457 static void mk_act_open_req6(struct filter_entry *f, struct rte_mbuf *mbuf,
458 unsigned int qid_filterid, struct adapter *adap)
460 struct cpl_t6_act_open_req6 *req = NULL;
461 u64 local_lo, local_hi, peer_lo, peer_hi;
462 u32 *lip = (u32 *)f->fs.val.lip;
463 u32 *fip = (u32 *)f->fs.val.fip;
465 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
467 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req6 *);
472 dev_err(adap, "%s: unsupported chip type!\n", __func__);
476 local_hi = ((u64)lip[1]) << 32 | lip[0];
477 local_lo = ((u64)lip[3]) << 32 | lip[2];
478 peer_hi = ((u64)fip[1]) << 32 | fip[0];
479 peer_lo = ((u64)fip[3]) << 32 | fip[2];
481 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
483 req->local_port = cpu_to_be16(f->fs.val.lport);
484 req->peer_port = cpu_to_be16(f->fs.val.fport);
485 req->local_ip_hi = local_hi;
486 req->local_ip_lo = local_lo;
487 req->peer_ip_hi = peer_hi;
488 req->peer_ip_lo = peer_lo;
489 req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
490 f->fs.newvlan == VLAN_REWRITE) |
491 V_DELACK(f->fs.hitcnts) |
492 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
493 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
495 V_TX_CHAN(f->fs.eport) |
496 V_ULP_MODE(ULP_MODE_NONE) |
497 F_TCAM_BYPASS | F_NON_OFFLOAD);
498 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
499 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
500 V_RSS_QUEUE(f->fs.iq) |
503 V_SACK_EN(f->fs.swapmac) |
504 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
505 (f->fs.dirsteer << 1)) |
506 V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
510 * Build a ACT_OPEN_REQ message for setting IPv4 hash filter.
512 static void mk_act_open_req(struct filter_entry *f, struct rte_mbuf *mbuf,
513 unsigned int qid_filterid, struct adapter *adap)
515 struct cpl_t6_act_open_req *req = NULL;
517 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
519 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req *);
524 dev_err(adap, "%s: unsupported chip type!\n", __func__);
528 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
530 req->local_port = cpu_to_be16(f->fs.val.lport);
531 req->peer_port = cpu_to_be16(f->fs.val.fport);
532 req->local_ip = f->fs.val.lip[0] | f->fs.val.lip[1] << 8 |
533 f->fs.val.lip[2] << 16 | f->fs.val.lip[3] << 24;
534 req->peer_ip = f->fs.val.fip[0] | f->fs.val.fip[1] << 8 |
535 f->fs.val.fip[2] << 16 | f->fs.val.fip[3] << 24;
536 req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
537 f->fs.newvlan == VLAN_REWRITE) |
538 V_DELACK(f->fs.hitcnts) |
539 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
540 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
542 V_TX_CHAN(f->fs.eport) |
543 V_ULP_MODE(ULP_MODE_NONE) |
544 F_TCAM_BYPASS | F_NON_OFFLOAD);
545 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
546 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
547 V_RSS_QUEUE(f->fs.iq) |
550 V_SACK_EN(f->fs.swapmac) |
551 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
552 (f->fs.dirsteer << 1)) |
553 V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
557 * Set the specified hash filter.
559 static int cxgbe_set_hash_filter(struct rte_eth_dev *dev,
560 struct ch_filter_specification *fs,
561 struct filter_ctx *ctx)
563 struct port_info *pi = ethdev2pinfo(dev);
564 struct adapter *adapter = pi->adapter;
565 struct tid_info *t = &adapter->tids;
566 struct filter_entry *f;
567 struct rte_mbuf *mbuf;
568 struct sge_ctrl_txq *ctrlq;
573 ret = cxgbe_validate_filter(adapter, fs);
577 iq = get_filter_steerq(dev, fs);
579 ctrlq = &adapter->sge.ctrlq[pi->port_id];
581 f = t4_os_alloc(sizeof(*f));
591 * If the new filter requires loopback Destination MAC and/or VLAN
592 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
595 if (f->fs.newvlan == VLAN_INSERT ||
596 f->fs.newvlan == VLAN_REWRITE) {
597 /* allocate L2T entry for new filter */
598 f->l2t = cxgbe_l2t_alloc_switching(dev, f->fs.vlan,
599 f->fs.eport, f->fs.dmac);
606 atid = cxgbe_alloc_atid(t, f);
610 if (f->fs.type == FILTER_TYPE_IPV6) {
611 /* IPv6 hash filter */
612 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
616 size = sizeof(struct cpl_t6_act_open_req6);
617 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
623 mbuf->data_len = size;
624 mbuf->pkt_len = mbuf->data_len;
626 mk_act_open_req6(f, mbuf,
627 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
630 /* IPv4 hash filter */
631 size = sizeof(struct cpl_t6_act_open_req);
632 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
638 mbuf->data_len = size;
639 mbuf->pkt_len = mbuf->data_len;
641 mk_act_open_req(f, mbuf,
642 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
647 t4_mgmt_tx(ctrlq, mbuf);
651 cxgbe_clip_release(f->dev, f->clipt);
653 cxgbe_free_atid(t, atid);
661 * Clear a filter and release any of its resources that we own. This also
662 * clears the filter's "pending" status.
664 static void clear_filter(struct filter_entry *f)
667 cxgbe_clip_release(f->dev, f->clipt);
670 * The zeroing of the filter rule below clears the filter valid,
671 * pending, locked flags etc. so it's all we need for
674 memset(f, 0, sizeof(*f));
678 * t4_mk_filtdelwr - create a delete filter WR
679 * @adap: adapter context
680 * @ftid: the filter ID
681 * @wr: the filter work request to populate
682 * @qid: ingress queue to receive the delete notification
684 * Creates a filter work request to delete the supplied filter. If @qid is
685 * negative the delete notification is suppressed.
687 static void t4_mk_filtdelwr(struct adapter *adap, unsigned int ftid,
688 struct fw_filter2_wr *wr, int qid)
690 memset(wr, 0, sizeof(*wr));
691 if (adap->params.filter2_wr_support)
692 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
694 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
695 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
696 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
697 V_FW_FILTER_WR_NOREPLY(qid < 0));
698 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
700 wr->rx_chan_rx_rpl_iq =
701 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
705 * Create FW work request to delete the filter at a specified index
707 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
709 struct adapter *adapter = ethdev2adap(dev);
710 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
711 struct rte_mbuf *mbuf;
712 struct fw_filter2_wr *fwr;
713 struct sge_ctrl_txq *ctrlq;
714 unsigned int port_id = ethdev2pinfo(dev)->port_id;
716 ctrlq = &adapter->sge.ctrlq[port_id];
717 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
721 mbuf->data_len = sizeof(*fwr);
722 mbuf->pkt_len = mbuf->data_len;
724 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
725 t4_mk_filtdelwr(adapter, f->tid, fwr, adapter->sge.fw_evtq.abs_id);
728 * Mark the filter as "pending" and ship off the Filter Work Request.
729 * When we get the Work Request Reply we'll clear the pending status.
732 t4_mgmt_tx(ctrlq, mbuf);
736 static int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
738 struct adapter *adapter = ethdev2adap(dev);
739 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
740 struct rte_mbuf *mbuf;
741 struct fw_filter2_wr *fwr;
742 struct sge_ctrl_txq *ctrlq;
743 unsigned int port_id = ethdev2pinfo(dev)->port_id;
747 * If the new filter requires loopback Destination MAC and/or VLAN
748 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
752 /* allocate L2T entry for new filter */
753 f->l2t = cxgbe_l2t_alloc_switching(f->dev, f->fs.vlan,
754 f->fs.eport, f->fs.dmac);
759 ctrlq = &adapter->sge.ctrlq[port_id];
760 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
766 mbuf->data_len = sizeof(*fwr);
767 mbuf->pkt_len = mbuf->data_len;
769 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
770 memset(fwr, 0, sizeof(*fwr));
773 * Construct the work request to set the filter.
775 if (adapter->params.filter2_wr_support)
776 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
778 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
779 fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
781 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
782 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
783 V_FW_FILTER_WR_NOREPLY(0) |
784 V_FW_FILTER_WR_IQ(f->fs.iq));
785 fwr->del_filter_to_l2tix =
786 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
787 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
788 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
789 V_FW_FILTER_WR_INSVLAN
790 (f->fs.newvlan == VLAN_INSERT ||
791 f->fs.newvlan == VLAN_REWRITE) |
792 V_FW_FILTER_WR_RMVLAN
793 (f->fs.newvlan == VLAN_REMOVE ||
794 f->fs.newvlan == VLAN_REWRITE) |
795 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
796 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
797 V_FW_FILTER_WR_PRIO(f->fs.prio) |
798 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
799 fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
800 fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
801 fwr->frag_to_ovlan_vldm =
802 (V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
803 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
804 V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
805 V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
807 fwr->rx_chan_rx_rpl_iq =
808 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
809 V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
811 fwr->maci_to_matchtypem =
812 cpu_to_be32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
813 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
814 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
815 V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
816 fwr->ptcl = f->fs.val.proto;
817 fwr->ptclm = f->fs.mask.proto;
818 fwr->ttyp = f->fs.val.tos;
819 fwr->ttypm = f->fs.mask.tos;
820 fwr->ivlan = cpu_to_be16(f->fs.val.ivlan);
821 fwr->ivlanm = cpu_to_be16(f->fs.mask.ivlan);
822 fwr->ovlan = cpu_to_be16(f->fs.val.ovlan);
823 fwr->ovlanm = cpu_to_be16(f->fs.mask.ovlan);
824 rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
825 rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
826 rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
827 rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
828 fwr->lp = cpu_to_be16(f->fs.val.lport);
829 fwr->lpm = cpu_to_be16(f->fs.mask.lport);
830 fwr->fp = cpu_to_be16(f->fs.val.fport);
831 fwr->fpm = cpu_to_be16(f->fs.mask.fport);
833 if (adapter->params.filter2_wr_support) {
834 fwr->filter_type_swapmac =
835 V_FW_FILTER2_WR_SWAPMAC(f->fs.swapmac);
836 fwr->natmode_to_ulp_type =
837 V_FW_FILTER2_WR_ULP_TYPE(f->fs.nat_mode ?
840 V_FW_FILTER2_WR_NATMODE(f->fs.nat_mode);
841 memcpy(fwr->newlip, f->fs.nat_lip, sizeof(fwr->newlip));
842 memcpy(fwr->newfip, f->fs.nat_fip, sizeof(fwr->newfip));
843 fwr->newlport = cpu_to_be16(f->fs.nat_lport);
844 fwr->newfport = cpu_to_be16(f->fs.nat_fport);
848 * Mark the filter as "pending" and ship off the Filter Work Request.
849 * When we get the Work Request Reply we'll clear the pending status.
852 t4_mgmt_tx(ctrlq, mbuf);
860 * Set the corresponding entries in the bitmap.
862 static int cxgbe_set_ftid(struct tid_info *t, u32 fidx, u8 nentries)
866 t4_os_lock(&t->ftid_lock);
867 if (rte_bitmap_get(t->ftid_bmap, fidx)) {
868 t4_os_unlock(&t->ftid_lock);
872 for (i = fidx; i < fidx + nentries; i++)
873 rte_bitmap_set(t->ftid_bmap, i);
874 t4_os_unlock(&t->ftid_lock);
879 * Clear the corresponding entries in the bitmap.
881 static void cxgbe_clear_ftid(struct tid_info *t, u32 fidx, u8 nentries)
885 t4_os_lock(&t->ftid_lock);
886 for (i = fidx; i < fidx + nentries; i++)
887 rte_bitmap_clear(t->ftid_bmap, i);
888 t4_os_unlock(&t->ftid_lock);
892 * Check a delete filter request for validity and send it to the hardware.
893 * Return 0 on success, an error number otherwise. We attach any provided
894 * filter operation context to the internal filter specification in order to
895 * facilitate signaling completion of the operation.
897 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
898 struct ch_filter_specification *fs,
899 struct filter_ctx *ctx)
901 struct port_info *pi = dev->data->dev_private;
902 struct adapter *adapter = pi->adapter;
903 struct filter_entry *f;
904 unsigned int chip_ver;
908 if (is_hashfilter(adapter) && fs->cap)
909 return cxgbe_del_hash_filter(dev, filter_id, ctx);
911 if (filter_id >= adapter->tids.nftids)
914 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
917 * Ensure IPv6 filter id is aligned on the 2 slot boundary for T6,
918 * and 4 slot boundary for cards below T6.
920 if (fs->type == FILTER_TYPE_IPV6) {
921 if (chip_ver < CHELSIO_T6)
927 nentries = cxgbe_filter_slots(adapter, fs->type);
928 ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
930 dev_warn(adap, "%s: could not find filter entry: %u\n",
931 __func__, filter_id);
935 f = &adapter->tids.ftid_tab[filter_id];
936 ret = writable_filter(f);
942 cxgbe_clear_ftid(&adapter->tids,
943 f->tid - adapter->tids.ftid_base,
945 return del_filter_wr(dev, filter_id);
949 * If the caller has passed in a Completion Context then we need to
950 * mark it as a successful completion so they don't stall waiting
955 t4_complete(&ctx->completion);
962 * Check a Chelsio Filter Request for validity, convert it into our internal
963 * format and send it to the hardware. Return 0 on success, an error number
964 * otherwise. We attach any provided filter operation context to the internal
965 * filter specification in order to facilitate signaling completion of the
968 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
969 struct ch_filter_specification *fs,
970 struct filter_ctx *ctx)
972 struct port_info *pi = ethdev2pinfo(dev);
973 struct adapter *adapter = pi->adapter;
974 u8 nentries, bitoff[16] = {0};
975 struct filter_entry *f;
976 unsigned int chip_ver;
977 unsigned int fidx, iq;
981 if (is_hashfilter(adapter) && fs->cap)
982 return cxgbe_set_hash_filter(dev, fs, ctx);
984 if (filter_id >= adapter->tids.nftids)
987 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
989 ret = cxgbe_validate_filter(adapter, fs);
994 * IPv6 filters occupy four slots and must be aligned on four-slot
995 * boundaries for T5. On T6, IPv6 filters occupy two-slots and
996 * must be aligned on two-slot boundaries.
998 * IPv4 filters only occupy a single slot and have no alignment
1002 if (fs->type == FILTER_TYPE_IPV6) {
1003 if (chip_ver < CHELSIO_T6)
1009 if (fidx != filter_id)
1012 nentries = cxgbe_filter_slots(adapter, fs->type);
1013 ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
1017 iq = get_filter_steerq(dev, fs);
1020 * Check to make sure that provided filter index is not
1021 * already in use by someone else
1023 f = &adapter->tids.ftid_tab[filter_id];
1027 fidx = adapter->tids.ftid_base + filter_id;
1028 ret = cxgbe_set_ftid(&adapter->tids, filter_id, nentries);
1033 * Check to make sure the filter requested is writable ...
1035 ret = writable_filter(f);
1037 /* Clear the bits we have set above */
1038 cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1043 * Allocate a clip table entry only if we have non-zero IPv6 address
1045 if (chip_ver > CHELSIO_T5 && fs->type &&
1046 memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
1047 f->clipt = cxgbe_clip_alloc(dev, (u32 *)&fs->val.lip);
1053 * Convert the filter specification into our internal format.
1054 * We copy the PF/VF specification into the Outer VLAN field
1055 * here so the rest of the code -- including the interface to
1056 * the firmware -- doesn't have to constantly do these checks.
1062 iconf = adapter->params.tp.ingress_config;
1064 /* Either PFVF or OVLAN can be active, but not both
1065 * So, if PFVF is enabled, then overwrite the OVLAN
1066 * fields with PFVF fields before writing the spec
1069 if (iconf & F_VNIC) {
1070 f->fs.val.ovlan = fs->val.pf << 13;
1071 f->fs.mask.ovlan = fs->mask.pf << 13;
1072 f->fs.val.ovlan_vld = fs->val.pfvf_vld;
1073 f->fs.mask.ovlan_vld = fs->mask.pfvf_vld;
1077 * Attempt to set the filter. If we don't succeed, we clear
1078 * it and return the failure.
1081 f->tid = fidx; /* Save the actual tid */
1082 ret = set_filter_wr(dev, filter_id);
1089 cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1095 * Handle a Hash filter write reply.
1097 void cxgbe_hash_filter_rpl(struct adapter *adap,
1098 const struct cpl_act_open_rpl *rpl)
1100 struct tid_info *t = &adap->tids;
1101 struct filter_entry *f;
1102 struct filter_ctx *ctx = NULL;
1103 unsigned int tid = GET_TID(rpl);
1104 unsigned int ftid = G_TID_TID(G_AOPEN_ATID
1105 (be32_to_cpu(rpl->atid_status)));
1106 unsigned int status = G_AOPEN_STATUS(be32_to_cpu(rpl->atid_status));
1108 f = lookup_atid(t, ftid);
1110 dev_warn(adap, "%s: could not find filter entry: %d\n",
1119 case CPL_ERR_NONE: {
1121 f->pending = 0; /* asynchronous setup completed */
1124 cxgbe_insert_tid(t, f, f->tid, 0);
1125 cxgbe_free_atid(t, ftid);
1131 set_tcb_field(adap, tid,
1133 V_TCB_TIMESTAMP(M_TCB_TIMESTAMP) |
1134 V_TCB_T_RTT_TS_RECENT_AGE
1135 (M_TCB_T_RTT_TS_RECENT_AGE),
1136 V_TCB_TIMESTAMP(0ULL) |
1137 V_TCB_T_RTT_TS_RECENT_AGE(0ULL),
1139 if (f->fs.newvlan == VLAN_INSERT ||
1140 f->fs.newvlan == VLAN_REWRITE)
1141 set_tcb_tflag(adap, tid, S_TF_CCTRL_RFR, 1, 1);
1145 dev_warn(adap, "%s: filter creation failed with status = %u\n",
1149 if (status == CPL_ERR_TCAM_FULL)
1150 ctx->result = -EAGAIN;
1152 ctx->result = -EINVAL;
1155 cxgbe_free_atid(t, ftid);
1160 t4_complete(&ctx->completion);
1164 * Handle a LE-TCAM filter write/deletion reply.
1166 void cxgbe_filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
1168 struct filter_entry *f = NULL;
1169 unsigned int tid = GET_TID(rpl);
1170 int idx, max_fidx = adap->tids.nftids;
1172 /* Get the corresponding filter entry for this tid */
1173 if (adap->tids.ftid_tab) {
1174 /* Check this in normal filter region */
1175 idx = tid - adap->tids.ftid_base;
1176 if (idx >= max_fidx)
1179 f = &adap->tids.ftid_tab[idx];
1184 /* We found the filter entry for this tid */
1186 unsigned int ret = G_COOKIE(rpl->cookie);
1187 struct filter_ctx *ctx;
1190 * Pull off any filter operation context attached to the
1196 if (ret == FW_FILTER_WR_FLT_ADDED) {
1197 f->pending = 0; /* asynchronous setup completed */
1203 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
1205 * Clear the filter when we get confirmation from the
1206 * hardware that the filter has been deleted.
1213 * Something went wrong. Issue a warning about the
1214 * problem and clear everything out.
1216 dev_warn(adap, "filter %u setup failed with error %u\n",
1220 ctx->result = -EINVAL;
1224 t4_complete(&ctx->completion);
1229 * Retrieve the packet count for the specified filter.
1231 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
1232 u64 *c, int hash, bool get_byte)
1234 struct filter_entry *f;
1235 unsigned int tcb_base, tcbaddr;
1238 tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
1239 if (is_hashfilter(adapter) && hash) {
1240 if (fidx < adapter->tids.ntids) {
1241 f = adapter->tids.tid_tab[fidx];
1245 if (is_t5(adapter->params.chip)) {
1249 tcbaddr = tcb_base + (fidx * TCB_SIZE);
1255 if (fidx >= adapter->tids.nftids)
1258 f = &adapter->tids.ftid_tab[fidx];
1262 tcbaddr = tcb_base + f->tid * TCB_SIZE;
1265 f = &adapter->tids.ftid_tab[fidx];
1270 if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
1272 * For T5, the Filter Packet Hit Count is maintained as a
1273 * 32-bit Big Endian value in the TCB field {timestamp}.
1274 * Similar to the craziness above, instead of the filter hit
1275 * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
1276 * sizeof(u32)), it actually shows up at offset 24. Whacky.
1279 unsigned int word_offset = 4;
1280 __be64 be64_byte_count;
1282 t4_os_lock(&adapter->win0_lock);
1283 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1285 (word_offset * sizeof(__be32)),
1286 sizeof(be64_byte_count),
1289 t4_os_unlock(&adapter->win0_lock);
1292 *c = be64_to_cpu(be64_byte_count);
1294 unsigned int word_offset = 6;
1297 t4_os_lock(&adapter->win0_lock);
1298 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1300 (word_offset * sizeof(__be32)),
1301 sizeof(be32_count), &be32_count,
1303 t4_os_unlock(&adapter->win0_lock);
1306 *c = (u64)be32_to_cpu(be32_count);
1313 * Clear the packet count for the specified filter.
1315 int cxgbe_clear_filter_count(struct adapter *adapter, unsigned int fidx,
1316 int hash, bool clear_byte)
1318 u64 tcb_mask = 0, tcb_val = 0;
1319 struct filter_entry *f = NULL;
1322 if (is_hashfilter(adapter) && hash) {
1323 if (fidx >= adapter->tids.ntids)
1326 /* No hitcounts supported for T5 hashfilters */
1327 if (is_t5(adapter->params.chip))
1330 f = adapter->tids.tid_tab[fidx];
1332 if (fidx >= adapter->tids.nftids)
1335 f = &adapter->tids.ftid_tab[fidx];
1338 if (!f || !f->valid)
1341 tcb_word = W_TCB_TIMESTAMP;
1342 tcb_mask = V_TCB_TIMESTAMP(M_TCB_TIMESTAMP);
1343 tcb_val = V_TCB_TIMESTAMP(0ULL);
1345 set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1348 tcb_word = W_TCB_T_RTT_TS_RECENT_AGE;
1350 V_TCB_T_RTT_TS_RECENT_AGE(M_TCB_T_RTT_TS_RECENT_AGE) |
1351 V_TCB_T_RTSEQ_RECENT(M_TCB_T_RTSEQ_RECENT);
1352 tcb_val = V_TCB_T_RTT_TS_RECENT_AGE(0ULL) |
1353 V_TCB_T_RTSEQ_RECENT(0ULL);
1355 set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1362 * Handle a Hash filter delete reply.
1364 void cxgbe_hash_del_filter_rpl(struct adapter *adap,
1365 const struct cpl_abort_rpl_rss *rpl)
1367 struct tid_info *t = &adap->tids;
1368 struct filter_entry *f;
1369 struct filter_ctx *ctx = NULL;
1370 unsigned int tid = GET_TID(rpl);
1372 f = lookup_tid(t, tid);
1374 dev_warn(adap, "%s: could not find filter entry: %u\n",
1385 cxgbe_clip_release(f->dev, f->clipt);
1387 cxgbe_remove_tid(t, 0, tid, 0);
1392 t4_complete(&ctx->completion);