1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Chelsio Communications.
9 #include "cxgbe_filter.h"
13 * Initialize Hash Filters
15 int init_hash_filter(struct adapter *adap)
17 unsigned int n_user_filters;
18 unsigned int user_filter_perc;
20 u32 params[7], val[7];
22 #define FW_PARAM_DEV(param) \
23 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
24 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
26 #define FW_PARAM_PFVF(param) \
27 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
28 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
29 V_FW_PARAMS_PARAM_Y(0) | \
30 V_FW_PARAMS_PARAM_Z(0))
32 params[0] = FW_PARAM_DEV(NTID);
33 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
37 adap->tids.ntids = val[0];
38 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
40 user_filter_perc = 100;
41 n_user_filters = mult_frac(adap->tids.nftids,
45 adap->tids.nftids = n_user_filters;
46 adap->params.hash_filter = 1;
51 * Validate if the requested filter specification can be set by checking
52 * if the requested features have been enabled
54 int validate_filter(struct adapter *adapter, struct ch_filter_specification *fs)
59 * Check for unconfigured fields being used.
61 fconf = adapter->params.tp.vlan_pri_map;
64 (fs->val._field || fs->mask._field)
65 #define U(_mask, _field) \
66 (!(fconf & (_mask)) && S(_field))
68 if (U(F_ETHERTYPE, ethtype) || U(F_PROTOCOL, proto))
77 * Get the queue to which the traffic must be steered to.
79 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
80 struct ch_filter_specification *fs)
82 struct port_info *pi = ethdev2pinfo(dev);
83 struct adapter *adapter = pi->adapter;
87 * If the user has requested steering matching Ingress Packets
88 * to a specific Queue Set, we need to make sure it's in range
89 * for the port and map that into the Absolute Queue ID of the
90 * Queue Set's Response Queue.
96 * If the iq id is greater than the number of qsets,
97 * then assume it is an absolute qid.
99 if (fs->iq < pi->n_rx_qsets)
100 iq = adapter->sge.ethrxq[pi->first_qset +
109 /* Return an error number if the indicated filter isn't writable ... */
110 int writable_filter(struct filter_entry *f)
121 * Build a CPL_SET_TCB_FIELD message as payload of a ULP_TX_PKT command.
123 static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
124 struct cpl_set_tcb_field *req,
126 u64 mask, u64 val, u8 cookie,
129 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
130 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
132 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
133 V_ULP_TXPKT_DEST(0));
134 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
135 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
136 sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
137 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
138 req->reply_ctrl = cpu_to_be16(V_NO_REPLY(no_reply) | V_REPLY_CHAN(0) |
140 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(cookie));
141 req->mask = cpu_to_be64(mask);
142 req->val = cpu_to_be64(val);
143 sc = (struct ulptx_idata *)(req + 1);
144 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
145 sc->len = cpu_to_be32(0);
149 * Check if entry already filled.
151 bool is_filter_set(struct tid_info *t, int fidx, int family)
156 /* IPv6 requires four slots and IPv4 requires only 1 slot.
157 * Ensure, there's enough slots available.
159 max = family == FILTER_TYPE_IPV6 ? fidx + 3 : fidx;
161 t4_os_lock(&t->ftid_lock);
162 for (i = fidx; i <= max; i++) {
163 if (rte_bitmap_get(t->ftid_bmap, i)) {
168 t4_os_unlock(&t->ftid_lock);
173 * Allocate a available free entry
175 int cxgbe_alloc_ftid(struct adapter *adap, unsigned int family)
177 struct tid_info *t = &adap->tids;
179 int size = t->nftids;
181 t4_os_lock(&t->ftid_lock);
182 if (family == FILTER_TYPE_IPV6)
183 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size, 4);
185 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
186 t4_os_unlock(&t->ftid_lock);
188 return pos < size ? pos : -1;
192 * Construct hash filter ntuple.
194 static u64 hash_filter_ntuple(const struct filter_entry *f)
196 struct adapter *adap = ethdev2adap(f->dev);
197 struct tp_params *tp = &adap->params.tp;
199 u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
201 if (tp->protocol_shift >= 0) {
202 if (!f->fs.val.proto)
203 ntuple |= (u64)tcp_proto << tp->protocol_shift;
205 ntuple |= (u64)f->fs.val.proto << tp->protocol_shift;
208 if (tp->ethertype_shift >= 0 && f->fs.mask.ethtype)
209 ntuple |= (u64)(f->fs.val.ethtype) << tp->ethertype_shift;
211 if (ntuple != tp->hash_filter_mask)
218 * Build a CPL_ABORT_REQ message as payload of a ULP_TX_PKT command.
220 static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
223 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_req;
224 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
226 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
227 V_ULP_TXPKT_DEST(0));
228 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
229 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
230 sc->len = cpu_to_be32(sizeof(*abort_req) -
231 sizeof(struct work_request_hdr));
232 OPCODE_TID(abort_req) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_REQ, tid));
233 abort_req->rsvd0 = cpu_to_be32(0);
234 abort_req->rsvd1 = 0;
235 abort_req->cmd = CPL_ABORT_NO_RST;
236 sc = (struct ulptx_idata *)(abort_req + 1);
237 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
238 sc->len = cpu_to_be32(0);
242 * Build a CPL_ABORT_RPL message as payload of a ULP_TX_PKT command.
244 static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
247 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_rpl;
248 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
250 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
251 V_ULP_TXPKT_DEST(0));
252 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
253 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
254 sc->len = cpu_to_be32(sizeof(*abort_rpl) -
255 sizeof(struct work_request_hdr));
256 OPCODE_TID(abort_rpl) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_RPL, tid));
257 abort_rpl->rsvd0 = cpu_to_be32(0);
258 abort_rpl->rsvd1 = 0;
259 abort_rpl->cmd = CPL_ABORT_NO_RST;
260 sc = (struct ulptx_idata *)(abort_rpl + 1);
261 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
262 sc->len = cpu_to_be32(0);
266 * Delete the specified hash filter.
268 static int cxgbe_del_hash_filter(struct rte_eth_dev *dev,
269 unsigned int filter_id,
270 struct filter_ctx *ctx)
272 struct adapter *adapter = ethdev2adap(dev);
273 struct tid_info *t = &adapter->tids;
274 struct filter_entry *f;
275 struct sge_ctrl_txq *ctrlq;
276 unsigned int port_id = ethdev2pinfo(dev)->port_id;
279 if (filter_id > adapter->tids.ntids)
282 f = lookup_tid(t, filter_id);
284 dev_err(adapter, "%s: no filter entry for filter_id = %d\n",
285 __func__, filter_id);
289 ret = writable_filter(f);
295 struct rte_mbuf *mbuf;
296 struct work_request_hdr *wr;
297 struct ulptx_idata *aligner;
298 struct cpl_set_tcb_field *req;
299 struct cpl_abort_req *abort_req;
300 struct cpl_abort_rpl *abort_rpl;
305 wrlen = cxgbe_roundup(sizeof(*wr) +
306 (sizeof(*req) + sizeof(*aligner)) +
307 sizeof(*abort_req) + sizeof(*abort_rpl),
310 ctrlq = &adapter->sge.ctrlq[port_id];
311 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
313 dev_err(adapter, "%s: could not allocate skb ..\n",
318 mbuf->data_len = wrlen;
319 mbuf->pkt_len = mbuf->data_len;
321 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
322 INIT_ULPTX_WR(req, wrlen, 0, 0);
323 wr = (struct work_request_hdr *)req;
325 req = (struct cpl_set_tcb_field *)wr;
326 mk_set_tcb_field_ulp(f, req, W_TCB_RSS_INFO,
327 V_TCB_RSS_INFO(M_TCB_RSS_INFO),
328 V_TCB_RSS_INFO(adapter->sge.fw_evtq.abs_id),
330 aligner = (struct ulptx_idata *)(req + 1);
331 abort_req = (struct cpl_abort_req *)(aligner + 1);
332 mk_abort_req_ulp(abort_req, f->tid);
333 abort_rpl = (struct cpl_abort_rpl *)(abort_req + 1);
334 mk_abort_rpl_ulp(abort_rpl, f->tid);
335 t4_mgmt_tx(ctrlq, mbuf);
344 * Build a ACT_OPEN_REQ6 message for setting IPv6 hash filter.
346 static void mk_act_open_req6(struct filter_entry *f, struct rte_mbuf *mbuf,
347 unsigned int qid_filterid, struct adapter *adap)
349 struct cpl_t6_act_open_req6 *req = NULL;
350 u64 local_lo, local_hi, peer_lo, peer_hi;
351 u32 *lip = (u32 *)f->fs.val.lip;
352 u32 *fip = (u32 *)f->fs.val.fip;
354 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
356 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req6 *);
361 dev_err(adap, "%s: unsupported chip type!\n", __func__);
365 local_hi = ((u64)lip[1]) << 32 | lip[0];
366 local_lo = ((u64)lip[3]) << 32 | lip[2];
367 peer_hi = ((u64)fip[1]) << 32 | fip[0];
368 peer_lo = ((u64)fip[3]) << 32 | fip[2];
370 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
372 req->local_port = cpu_to_be16(f->fs.val.lport);
373 req->peer_port = cpu_to_be16(f->fs.val.fport);
374 req->local_ip_hi = local_hi;
375 req->local_ip_lo = local_lo;
376 req->peer_ip_hi = peer_hi;
377 req->peer_ip_lo = peer_lo;
378 req->opt0 = cpu_to_be64(V_DELACK(f->fs.hitcnts) |
379 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
381 V_ULP_MODE(ULP_MODE_NONE) |
382 F_TCAM_BYPASS | F_NON_OFFLOAD);
383 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
384 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
385 V_RSS_QUEUE(f->fs.iq) |
388 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
389 (f->fs.dirsteer << 1)));
393 * Build a ACT_OPEN_REQ message for setting IPv4 hash filter.
395 static void mk_act_open_req(struct filter_entry *f, struct rte_mbuf *mbuf,
396 unsigned int qid_filterid, struct adapter *adap)
398 struct cpl_t6_act_open_req *req = NULL;
400 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
402 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req *);
407 dev_err(adap, "%s: unsupported chip type!\n", __func__);
411 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
413 req->local_port = cpu_to_be16(f->fs.val.lport);
414 req->peer_port = cpu_to_be16(f->fs.val.fport);
415 req->local_ip = f->fs.val.lip[0] | f->fs.val.lip[1] << 8 |
416 f->fs.val.lip[2] << 16 | f->fs.val.lip[3] << 24;
417 req->peer_ip = f->fs.val.fip[0] | f->fs.val.fip[1] << 8 |
418 f->fs.val.fip[2] << 16 | f->fs.val.fip[3] << 24;
419 req->opt0 = cpu_to_be64(V_DELACK(f->fs.hitcnts) |
420 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
422 V_ULP_MODE(ULP_MODE_NONE) |
423 F_TCAM_BYPASS | F_NON_OFFLOAD);
424 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
425 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
426 V_RSS_QUEUE(f->fs.iq) |
429 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
430 (f->fs.dirsteer << 1)));
434 * Set the specified hash filter.
436 static int cxgbe_set_hash_filter(struct rte_eth_dev *dev,
437 struct ch_filter_specification *fs,
438 struct filter_ctx *ctx)
440 struct port_info *pi = ethdev2pinfo(dev);
441 struct adapter *adapter = pi->adapter;
442 struct tid_info *t = &adapter->tids;
443 struct filter_entry *f;
444 struct rte_mbuf *mbuf;
445 struct sge_ctrl_txq *ctrlq;
450 ret = validate_filter(adapter, fs);
454 iq = get_filter_steerq(dev, fs);
456 ctrlq = &adapter->sge.ctrlq[pi->port_id];
458 f = t4_os_alloc(sizeof(*f));
467 atid = cxgbe_alloc_atid(t, f);
472 /* IPv6 hash filter */
473 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
477 size = sizeof(struct cpl_t6_act_open_req6);
478 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
484 mbuf->data_len = size;
485 mbuf->pkt_len = mbuf->data_len;
487 mk_act_open_req6(f, mbuf,
488 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
491 /* IPv4 hash filter */
492 size = sizeof(struct cpl_t6_act_open_req);
493 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
499 mbuf->data_len = size;
500 mbuf->pkt_len = mbuf->data_len;
502 mk_act_open_req(f, mbuf,
503 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
508 t4_mgmt_tx(ctrlq, mbuf);
512 cxgbe_clip_release(f->dev, f->clipt);
514 cxgbe_free_atid(t, atid);
522 * Clear a filter and release any of its resources that we own. This also
523 * clears the filter's "pending" status.
525 void clear_filter(struct filter_entry *f)
528 cxgbe_clip_release(f->dev, f->clipt);
531 * The zeroing of the filter rule below clears the filter valid,
532 * pending, locked flags etc. so it's all we need for
535 memset(f, 0, sizeof(*f));
539 * t4_mk_filtdelwr - create a delete filter WR
540 * @ftid: the filter ID
541 * @wr: the filter work request to populate
542 * @qid: ingress queue to receive the delete notification
544 * Creates a filter work request to delete the supplied filter. If @qid is
545 * negative the delete notification is suppressed.
547 static void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
549 memset(wr, 0, sizeof(*wr));
550 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
551 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
552 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
553 V_FW_FILTER_WR_NOREPLY(qid < 0));
554 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
556 wr->rx_chan_rx_rpl_iq =
557 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
561 * Create FW work request to delete the filter at a specified index
563 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
565 struct adapter *adapter = ethdev2adap(dev);
566 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
567 struct rte_mbuf *mbuf;
568 struct fw_filter_wr *fwr;
569 struct sge_ctrl_txq *ctrlq;
570 unsigned int port_id = ethdev2pinfo(dev)->port_id;
572 ctrlq = &adapter->sge.ctrlq[port_id];
573 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
577 mbuf->data_len = sizeof(*fwr);
578 mbuf->pkt_len = mbuf->data_len;
580 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter_wr *);
581 t4_mk_filtdelwr(f->tid, fwr, adapter->sge.fw_evtq.abs_id);
584 * Mark the filter as "pending" and ship off the Filter Work Request.
585 * When we get the Work Request Reply we'll clear the pending status.
588 t4_mgmt_tx(ctrlq, mbuf);
592 int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
594 struct adapter *adapter = ethdev2adap(dev);
595 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
596 struct rte_mbuf *mbuf;
597 struct fw_filter_wr *fwr;
598 struct sge_ctrl_txq *ctrlq;
599 unsigned int port_id = ethdev2pinfo(dev)->port_id;
602 ctrlq = &adapter->sge.ctrlq[port_id];
603 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
609 mbuf->data_len = sizeof(*fwr);
610 mbuf->pkt_len = mbuf->data_len;
612 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter_wr *);
613 memset(fwr, 0, sizeof(*fwr));
616 * Construct the work request to set the filter.
618 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
619 fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
621 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
622 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
623 V_FW_FILTER_WR_NOREPLY(0) |
624 V_FW_FILTER_WR_IQ(f->fs.iq));
625 fwr->del_filter_to_l2tix =
626 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
627 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
628 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
629 V_FW_FILTER_WR_PRIO(f->fs.prio));
630 fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
631 fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
633 fwr->rx_chan_rx_rpl_iq =
634 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
635 V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
637 fwr->ptcl = f->fs.val.proto;
638 fwr->ptclm = f->fs.mask.proto;
639 rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
640 rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
641 rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
642 rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
643 fwr->lp = cpu_to_be16(f->fs.val.lport);
644 fwr->lpm = cpu_to_be16(f->fs.mask.lport);
645 fwr->fp = cpu_to_be16(f->fs.val.fport);
646 fwr->fpm = cpu_to_be16(f->fs.mask.fport);
649 * Mark the filter as "pending" and ship off the Filter Work Request.
650 * When we get the Work Request Reply we'll clear the pending status.
653 t4_mgmt_tx(ctrlq, mbuf);
661 * Set the corresponding entry in the bitmap. 4 slots are
662 * marked for IPv6, whereas only 1 slot is marked for IPv4.
664 static int cxgbe_set_ftid(struct tid_info *t, int fidx, int family)
666 t4_os_lock(&t->ftid_lock);
667 if (rte_bitmap_get(t->ftid_bmap, fidx)) {
668 t4_os_unlock(&t->ftid_lock);
672 if (family == FILTER_TYPE_IPV4) {
673 rte_bitmap_set(t->ftid_bmap, fidx);
675 rte_bitmap_set(t->ftid_bmap, fidx);
676 rte_bitmap_set(t->ftid_bmap, fidx + 1);
677 rte_bitmap_set(t->ftid_bmap, fidx + 2);
678 rte_bitmap_set(t->ftid_bmap, fidx + 3);
680 t4_os_unlock(&t->ftid_lock);
685 * Clear the corresponding entry in the bitmap. 4 slots are
686 * cleared for IPv6, whereas only 1 slot is cleared for IPv4.
688 static void cxgbe_clear_ftid(struct tid_info *t, int fidx, int family)
690 t4_os_lock(&t->ftid_lock);
691 if (family == FILTER_TYPE_IPV4) {
692 rte_bitmap_clear(t->ftid_bmap, fidx);
694 rte_bitmap_clear(t->ftid_bmap, fidx);
695 rte_bitmap_clear(t->ftid_bmap, fidx + 1);
696 rte_bitmap_clear(t->ftid_bmap, fidx + 2);
697 rte_bitmap_clear(t->ftid_bmap, fidx + 3);
699 t4_os_unlock(&t->ftid_lock);
703 * Check a delete filter request for validity and send it to the hardware.
704 * Return 0 on success, an error number otherwise. We attach any provided
705 * filter operation context to the internal filter specification in order to
706 * facilitate signaling completion of the operation.
708 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
709 struct ch_filter_specification *fs,
710 struct filter_ctx *ctx)
712 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
713 struct adapter *adapter = pi->adapter;
714 struct filter_entry *f;
715 unsigned int chip_ver;
718 if (is_hashfilter(adapter) && fs->cap)
719 return cxgbe_del_hash_filter(dev, filter_id, ctx);
721 if (filter_id >= adapter->tids.nftids)
724 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
726 ret = is_filter_set(&adapter->tids, filter_id, fs->type);
728 dev_warn(adap, "%s: could not find filter entry: %u\n",
729 __func__, filter_id);
734 * Ensure filter id is aligned on the 2 slot boundary for T6,
735 * and 4 slot boundary for cards below T6.
738 if (chip_ver < CHELSIO_T6)
744 f = &adapter->tids.ftid_tab[filter_id];
745 ret = writable_filter(f);
751 cxgbe_clear_ftid(&adapter->tids,
752 f->tid - adapter->tids.ftid_base,
753 f->fs.type ? FILTER_TYPE_IPV6 :
755 return del_filter_wr(dev, filter_id);
759 * If the caller has passed in a Completion Context then we need to
760 * mark it as a successful completion so they don't stall waiting
765 t4_complete(&ctx->completion);
772 * Check a Chelsio Filter Request for validity, convert it into our internal
773 * format and send it to the hardware. Return 0 on success, an error number
774 * otherwise. We attach any provided filter operation context to the internal
775 * filter specification in order to facilitate signaling completion of the
778 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
779 struct ch_filter_specification *fs,
780 struct filter_ctx *ctx)
782 struct port_info *pi = ethdev2pinfo(dev);
783 struct adapter *adapter = pi->adapter;
784 unsigned int fidx, iq, fid_bit = 0;
785 struct filter_entry *f;
786 unsigned int chip_ver;
787 uint8_t bitoff[16] = {0};
790 if (is_hashfilter(adapter) && fs->cap)
791 return cxgbe_set_hash_filter(dev, fs, ctx);
793 if (filter_id >= adapter->tids.nftids)
796 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
798 ret = validate_filter(adapter, fs);
803 * Ensure filter id is aligned on the 4 slot boundary for IPv6
809 ret = is_filter_set(&adapter->tids, filter_id, fs->type);
813 iq = get_filter_steerq(dev, fs);
816 * IPv6 filters occupy four slots and must be aligned on four-slot
817 * boundaries for T5. On T6, IPv6 filters occupy two-slots and
818 * must be aligned on two-slot boundaries.
820 * IPv4 filters only occupy a single slot and have no alignment
821 * requirements but writing a new IPv4 filter into the middle
822 * of an existing IPv6 filter requires clearing the old IPv6
825 if (fs->type == FILTER_TYPE_IPV4) { /* IPv4 */
827 * For T6, If our IPv4 filter isn't being written to a
828 * multiple of two filter index and there's an IPv6
829 * filter at the multiple of 2 base slot, then we need
830 * to delete that IPv6 filter ...
831 * For adapters below T6, IPv6 filter occupies 4 entries.
833 if (chip_ver < CHELSIO_T6)
834 fidx = filter_id & ~0x3;
836 fidx = filter_id & ~0x1;
838 if (fidx != filter_id && adapter->tids.ftid_tab[fidx].fs.type) {
839 f = &adapter->tids.ftid_tab[fidx];
844 unsigned int max_filter_id;
846 if (chip_ver < CHELSIO_T6) {
848 * Ensure that the IPv6 filter is aligned on a
849 * multiple of 4 boundary.
854 max_filter_id = filter_id + 4;
857 * For T6, CLIP being enabled, IPv6 filter would occupy
863 max_filter_id = filter_id + 2;
867 * Check all except the base overlapping IPv4 filter
870 for (fidx = filter_id + 1; fidx < max_filter_id; fidx++) {
871 f = &adapter->tids.ftid_tab[fidx];
878 * Check to make sure that provided filter index is not
879 * already in use by someone else
881 f = &adapter->tids.ftid_tab[filter_id];
885 fidx = adapter->tids.ftid_base + filter_id;
887 ret = cxgbe_set_ftid(&adapter->tids, fid_bit,
888 fs->type ? FILTER_TYPE_IPV6 : FILTER_TYPE_IPV4);
893 * Check to make sure the filter requested is writable ...
895 ret = writable_filter(f);
897 /* Clear the bits we have set above */
898 cxgbe_clear_ftid(&adapter->tids, fid_bit,
899 fs->type ? FILTER_TYPE_IPV6 :
905 * Allocate a clip table entry only if we have non-zero IPv6 address
907 if (chip_ver > CHELSIO_T5 && fs->type &&
908 memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
909 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
915 * Convert the filter specification into our internal format.
916 * We copy the PF/VF specification into the Outer VLAN field
917 * here so the rest of the code -- including the interface to
918 * the firmware -- doesn't have to constantly do these checks.
925 * Attempt to set the filter. If we don't succeed, we clear
926 * it and return the failure.
929 f->tid = fidx; /* Save the actual tid */
930 ret = set_filter_wr(dev, filter_id);
932 fid_bit = f->tid - adapter->tids.ftid_base;
939 cxgbe_clear_ftid(&adapter->tids, fid_bit,
940 fs->type ? FILTER_TYPE_IPV6 :
947 * Handle a Hash filter write reply.
949 void hash_filter_rpl(struct adapter *adap, const struct cpl_act_open_rpl *rpl)
951 struct tid_info *t = &adap->tids;
952 struct filter_entry *f;
953 struct filter_ctx *ctx = NULL;
954 unsigned int tid = GET_TID(rpl);
955 unsigned int ftid = G_TID_TID(G_AOPEN_ATID
956 (be32_to_cpu(rpl->atid_status)));
957 unsigned int status = G_AOPEN_STATUS(be32_to_cpu(rpl->atid_status));
959 f = lookup_atid(t, ftid);
961 dev_warn(adap, "%s: could not find filter entry: %d\n",
972 f->pending = 0; /* asynchronous setup completed */
975 cxgbe_insert_tid(t, f, f->tid, 0);
976 cxgbe_free_atid(t, ftid);
984 dev_warn(adap, "%s: filter creation failed with status = %u\n",
988 if (status == CPL_ERR_TCAM_FULL)
989 ctx->result = -EAGAIN;
991 ctx->result = -EINVAL;
994 cxgbe_free_atid(t, ftid);
999 t4_complete(&ctx->completion);
1003 * Handle a LE-TCAM filter write/deletion reply.
1005 void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
1007 struct filter_entry *f = NULL;
1008 unsigned int tid = GET_TID(rpl);
1009 int idx, max_fidx = adap->tids.nftids;
1011 /* Get the corresponding filter entry for this tid */
1012 if (adap->tids.ftid_tab) {
1013 /* Check this in normal filter region */
1014 idx = tid - adap->tids.ftid_base;
1015 if (idx >= max_fidx)
1018 f = &adap->tids.ftid_tab[idx];
1023 /* We found the filter entry for this tid */
1025 unsigned int ret = G_COOKIE(rpl->cookie);
1026 struct filter_ctx *ctx;
1029 * Pull off any filter operation context attached to the
1035 if (ret == FW_FILTER_WR_FLT_ADDED) {
1036 f->pending = 0; /* asynchronous setup completed */
1042 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
1044 * Clear the filter when we get confirmation from the
1045 * hardware that the filter has been deleted.
1052 * Something went wrong. Issue a warning about the
1053 * problem and clear everything out.
1055 dev_warn(adap, "filter %u setup failed with error %u\n",
1059 ctx->result = -EINVAL;
1063 t4_complete(&ctx->completion);
1068 * Retrieve the packet count for the specified filter.
1070 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
1071 u64 *c, bool get_byte)
1073 struct filter_entry *f;
1074 unsigned int tcb_base, tcbaddr;
1077 tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
1078 if (fidx >= adapter->tids.nftids)
1081 f = &adapter->tids.ftid_tab[fidx];
1085 tcbaddr = tcb_base + f->tid * TCB_SIZE;
1087 if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
1089 * For T5, the Filter Packet Hit Count is maintained as a
1090 * 32-bit Big Endian value in the TCB field {timestamp}.
1091 * Similar to the craziness above, instead of the filter hit
1092 * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
1093 * sizeof(u32)), it actually shows up at offset 24. Whacky.
1096 unsigned int word_offset = 4;
1097 __be64 be64_byte_count;
1099 t4_os_lock(&adapter->win0_lock);
1100 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1102 (word_offset * sizeof(__be32)),
1103 sizeof(be64_byte_count),
1106 t4_os_unlock(&adapter->win0_lock);
1109 *c = be64_to_cpu(be64_byte_count);
1111 unsigned int word_offset = 6;
1114 t4_os_lock(&adapter->win0_lock);
1115 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1117 (word_offset * sizeof(__be32)),
1118 sizeof(be32_count), &be32_count,
1120 t4_os_unlock(&adapter->win0_lock);
1123 *c = (u64)be32_to_cpu(be32_count);
1130 * Handle a Hash filter delete reply.
1132 void hash_del_filter_rpl(struct adapter *adap,
1133 const struct cpl_abort_rpl_rss *rpl)
1135 struct tid_info *t = &adap->tids;
1136 struct filter_entry *f;
1137 struct filter_ctx *ctx = NULL;
1138 unsigned int tid = GET_TID(rpl);
1140 f = lookup_tid(t, tid);
1142 dev_warn(adap, "%s: could not find filter entry: %u\n",
1153 cxgbe_clip_release(f->dev, f->clipt);
1155 cxgbe_remove_tid(t, 0, tid, 0);
1160 t4_complete(&ctx->completion);