1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Chelsio Communications.
9 #include "cxgbe_filter.h"
14 * Initialize Hash Filters
16 int init_hash_filter(struct adapter *adap)
18 unsigned int n_user_filters;
19 unsigned int user_filter_perc;
21 u32 params[7], val[7];
23 #define FW_PARAM_DEV(param) \
24 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
25 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
27 #define FW_PARAM_PFVF(param) \
28 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
29 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
30 V_FW_PARAMS_PARAM_Y(0) | \
31 V_FW_PARAMS_PARAM_Z(0))
33 params[0] = FW_PARAM_DEV(NTID);
34 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
38 adap->tids.ntids = val[0];
39 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
41 user_filter_perc = 100;
42 n_user_filters = mult_frac(adap->tids.nftids,
46 adap->tids.nftids = n_user_filters;
47 adap->params.hash_filter = 1;
52 * Validate if the requested filter specification can be set by checking
53 * if the requested features have been enabled
55 int validate_filter(struct adapter *adapter, struct ch_filter_specification *fs)
60 * Check for unconfigured fields being used.
62 fconf = adapter->params.tp.vlan_pri_map;
65 (fs->val._field || fs->mask._field)
66 #define U(_mask, _field) \
67 (!(fconf & (_mask)) && S(_field))
69 if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) ||
70 U(F_PROTOCOL, proto) || U(F_MACMATCH, macidx))
77 * If the user is requesting that the filter action loop
78 * matching packets back out one of our ports, make sure that
79 * the egress port is in range.
81 if (fs->action == FILTER_SWITCH &&
82 fs->eport >= adapter->params.nports)
86 * Don't allow various trivially obvious bogus out-of-range
89 if (fs->val.iport >= adapter->params.nports)
92 if (!fs->cap && fs->nat_mode && !adapter->params.filter2_wr_support)
99 * Get the queue to which the traffic must be steered to.
101 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
102 struct ch_filter_specification *fs)
104 struct port_info *pi = ethdev2pinfo(dev);
105 struct adapter *adapter = pi->adapter;
109 * If the user has requested steering matching Ingress Packets
110 * to a specific Queue Set, we need to make sure it's in range
111 * for the port and map that into the Absolute Queue ID of the
112 * Queue Set's Response Queue.
118 * If the iq id is greater than the number of qsets,
119 * then assume it is an absolute qid.
121 if (fs->iq < pi->n_rx_qsets)
122 iq = adapter->sge.ethrxq[pi->first_qset +
131 /* Return an error number if the indicated filter isn't writable ... */
132 int writable_filter(struct filter_entry *f)
143 * Send CPL_SET_TCB_FIELD message
145 static void set_tcb_field(struct adapter *adapter, unsigned int ftid,
146 u16 word, u64 mask, u64 val, int no_reply)
148 struct rte_mbuf *mbuf;
149 struct cpl_set_tcb_field *req;
150 struct sge_ctrl_txq *ctrlq;
152 ctrlq = &adapter->sge.ctrlq[0];
153 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
156 mbuf->data_len = sizeof(*req);
157 mbuf->pkt_len = mbuf->data_len;
159 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
160 memset(req, 0, sizeof(*req));
161 INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, ftid);
162 req->reply_ctrl = cpu_to_be16(V_REPLY_CHAN(0) |
163 V_QUEUENO(adapter->sge.fw_evtq.abs_id) |
164 V_NO_REPLY(no_reply));
165 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(ftid));
166 req->mask = cpu_to_be64(mask);
167 req->val = cpu_to_be64(val);
169 t4_mgmt_tx(ctrlq, mbuf);
173 * Set one of the t_flags bits in the TCB.
175 static void set_tcb_tflag(struct adapter *adap, unsigned int ftid,
176 unsigned int bit_pos, unsigned int val, int no_reply)
178 set_tcb_field(adap, ftid, W_TCB_T_FLAGS, 1ULL << bit_pos,
179 (unsigned long long)val << bit_pos, no_reply);
183 * Build a CPL_SET_TCB_FIELD message as payload of a ULP_TX_PKT command.
185 static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
186 struct cpl_set_tcb_field *req,
188 u64 mask, u64 val, u8 cookie,
191 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
192 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
194 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
195 V_ULP_TXPKT_DEST(0));
196 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
197 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
198 sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
199 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
200 req->reply_ctrl = cpu_to_be16(V_NO_REPLY(no_reply) | V_REPLY_CHAN(0) |
202 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(cookie));
203 req->mask = cpu_to_be64(mask);
204 req->val = cpu_to_be64(val);
205 sc = (struct ulptx_idata *)(req + 1);
206 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
207 sc->len = cpu_to_be32(0);
211 * Check if entry already filled.
213 bool is_filter_set(struct tid_info *t, int fidx, int family)
218 /* IPv6 requires four slots and IPv4 requires only 1 slot.
219 * Ensure, there's enough slots available.
221 max = family == FILTER_TYPE_IPV6 ? fidx + 3 : fidx;
223 t4_os_lock(&t->ftid_lock);
224 for (i = fidx; i <= max; i++) {
225 if (rte_bitmap_get(t->ftid_bmap, i)) {
230 t4_os_unlock(&t->ftid_lock);
235 * Allocate a available free entry
237 int cxgbe_alloc_ftid(struct adapter *adap, unsigned int family)
239 struct tid_info *t = &adap->tids;
241 int size = t->nftids;
243 t4_os_lock(&t->ftid_lock);
244 if (family == FILTER_TYPE_IPV6)
245 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size, 4);
247 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
248 t4_os_unlock(&t->ftid_lock);
250 return pos < size ? pos : -1;
254 * Construct hash filter ntuple.
256 static u64 hash_filter_ntuple(const struct filter_entry *f)
258 struct adapter *adap = ethdev2adap(f->dev);
259 struct tp_params *tp = &adap->params.tp;
261 u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
263 if (tp->port_shift >= 0)
264 ntuple |= (u64)f->fs.mask.iport << tp->port_shift;
266 if (tp->protocol_shift >= 0) {
267 if (!f->fs.val.proto)
268 ntuple |= (u64)tcp_proto << tp->protocol_shift;
270 ntuple |= (u64)f->fs.val.proto << tp->protocol_shift;
273 if (tp->ethertype_shift >= 0 && f->fs.mask.ethtype)
274 ntuple |= (u64)(f->fs.val.ethtype) << tp->ethertype_shift;
275 if (tp->macmatch_shift >= 0 && f->fs.mask.macidx)
276 ntuple |= (u64)(f->fs.val.macidx) << tp->macmatch_shift;
278 if (ntuple != tp->hash_filter_mask)
285 * Build a CPL_ABORT_REQ message as payload of a ULP_TX_PKT command.
287 static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
290 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_req;
291 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
293 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
294 V_ULP_TXPKT_DEST(0));
295 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
296 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
297 sc->len = cpu_to_be32(sizeof(*abort_req) -
298 sizeof(struct work_request_hdr));
299 OPCODE_TID(abort_req) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_REQ, tid));
300 abort_req->rsvd0 = cpu_to_be32(0);
301 abort_req->rsvd1 = 0;
302 abort_req->cmd = CPL_ABORT_NO_RST;
303 sc = (struct ulptx_idata *)(abort_req + 1);
304 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
305 sc->len = cpu_to_be32(0);
309 * Build a CPL_ABORT_RPL message as payload of a ULP_TX_PKT command.
311 static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
314 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_rpl;
315 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
317 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
318 V_ULP_TXPKT_DEST(0));
319 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
320 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
321 sc->len = cpu_to_be32(sizeof(*abort_rpl) -
322 sizeof(struct work_request_hdr));
323 OPCODE_TID(abort_rpl) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_RPL, tid));
324 abort_rpl->rsvd0 = cpu_to_be32(0);
325 abort_rpl->rsvd1 = 0;
326 abort_rpl->cmd = CPL_ABORT_NO_RST;
327 sc = (struct ulptx_idata *)(abort_rpl + 1);
328 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
329 sc->len = cpu_to_be32(0);
333 * Delete the specified hash filter.
335 static int cxgbe_del_hash_filter(struct rte_eth_dev *dev,
336 unsigned int filter_id,
337 struct filter_ctx *ctx)
339 struct adapter *adapter = ethdev2adap(dev);
340 struct tid_info *t = &adapter->tids;
341 struct filter_entry *f;
342 struct sge_ctrl_txq *ctrlq;
343 unsigned int port_id = ethdev2pinfo(dev)->port_id;
346 if (filter_id > adapter->tids.ntids)
349 f = lookup_tid(t, filter_id);
351 dev_err(adapter, "%s: no filter entry for filter_id = %d\n",
352 __func__, filter_id);
356 ret = writable_filter(f);
362 struct rte_mbuf *mbuf;
363 struct work_request_hdr *wr;
364 struct ulptx_idata *aligner;
365 struct cpl_set_tcb_field *req;
366 struct cpl_abort_req *abort_req;
367 struct cpl_abort_rpl *abort_rpl;
372 wrlen = cxgbe_roundup(sizeof(*wr) +
373 (sizeof(*req) + sizeof(*aligner)) +
374 sizeof(*abort_req) + sizeof(*abort_rpl),
377 ctrlq = &adapter->sge.ctrlq[port_id];
378 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
380 dev_err(adapter, "%s: could not allocate skb ..\n",
385 mbuf->data_len = wrlen;
386 mbuf->pkt_len = mbuf->data_len;
388 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
389 INIT_ULPTX_WR(req, wrlen, 0, 0);
390 wr = (struct work_request_hdr *)req;
392 req = (struct cpl_set_tcb_field *)wr;
393 mk_set_tcb_field_ulp(f, req, W_TCB_RSS_INFO,
394 V_TCB_RSS_INFO(M_TCB_RSS_INFO),
395 V_TCB_RSS_INFO(adapter->sge.fw_evtq.abs_id),
397 aligner = (struct ulptx_idata *)(req + 1);
398 abort_req = (struct cpl_abort_req *)(aligner + 1);
399 mk_abort_req_ulp(abort_req, f->tid);
400 abort_rpl = (struct cpl_abort_rpl *)(abort_req + 1);
401 mk_abort_rpl_ulp(abort_rpl, f->tid);
402 t4_mgmt_tx(ctrlq, mbuf);
411 * Build a ACT_OPEN_REQ6 message for setting IPv6 hash filter.
413 static void mk_act_open_req6(struct filter_entry *f, struct rte_mbuf *mbuf,
414 unsigned int qid_filterid, struct adapter *adap)
416 struct cpl_t6_act_open_req6 *req = NULL;
417 u64 local_lo, local_hi, peer_lo, peer_hi;
418 u32 *lip = (u32 *)f->fs.val.lip;
419 u32 *fip = (u32 *)f->fs.val.fip;
421 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
423 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req6 *);
428 dev_err(adap, "%s: unsupported chip type!\n", __func__);
432 local_hi = ((u64)lip[1]) << 32 | lip[0];
433 local_lo = ((u64)lip[3]) << 32 | lip[2];
434 peer_hi = ((u64)fip[1]) << 32 | fip[0];
435 peer_lo = ((u64)fip[3]) << 32 | fip[2];
437 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
439 req->local_port = cpu_to_be16(f->fs.val.lport);
440 req->peer_port = cpu_to_be16(f->fs.val.fport);
441 req->local_ip_hi = local_hi;
442 req->local_ip_lo = local_lo;
443 req->peer_ip_hi = peer_hi;
444 req->peer_ip_lo = peer_lo;
445 req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
446 f->fs.newvlan == VLAN_REWRITE) |
447 V_DELACK(f->fs.hitcnts) |
448 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
449 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
451 V_TX_CHAN(f->fs.eport) |
452 V_ULP_MODE(ULP_MODE_NONE) |
453 F_TCAM_BYPASS | F_NON_OFFLOAD);
454 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
455 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
456 V_RSS_QUEUE(f->fs.iq) |
459 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
460 (f->fs.dirsteer << 1)) |
461 V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
465 * Build a ACT_OPEN_REQ message for setting IPv4 hash filter.
467 static void mk_act_open_req(struct filter_entry *f, struct rte_mbuf *mbuf,
468 unsigned int qid_filterid, struct adapter *adap)
470 struct cpl_t6_act_open_req *req = NULL;
472 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
474 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req *);
479 dev_err(adap, "%s: unsupported chip type!\n", __func__);
483 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
485 req->local_port = cpu_to_be16(f->fs.val.lport);
486 req->peer_port = cpu_to_be16(f->fs.val.fport);
487 req->local_ip = f->fs.val.lip[0] | f->fs.val.lip[1] << 8 |
488 f->fs.val.lip[2] << 16 | f->fs.val.lip[3] << 24;
489 req->peer_ip = f->fs.val.fip[0] | f->fs.val.fip[1] << 8 |
490 f->fs.val.fip[2] << 16 | f->fs.val.fip[3] << 24;
491 req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
492 f->fs.newvlan == VLAN_REWRITE) |
493 V_DELACK(f->fs.hitcnts) |
494 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
495 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
497 V_TX_CHAN(f->fs.eport) |
498 V_ULP_MODE(ULP_MODE_NONE) |
499 F_TCAM_BYPASS | F_NON_OFFLOAD);
500 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
501 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
502 V_RSS_QUEUE(f->fs.iq) |
505 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
506 (f->fs.dirsteer << 1)) |
507 V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
511 * Set the specified hash filter.
513 static int cxgbe_set_hash_filter(struct rte_eth_dev *dev,
514 struct ch_filter_specification *fs,
515 struct filter_ctx *ctx)
517 struct port_info *pi = ethdev2pinfo(dev);
518 struct adapter *adapter = pi->adapter;
519 struct tid_info *t = &adapter->tids;
520 struct filter_entry *f;
521 struct rte_mbuf *mbuf;
522 struct sge_ctrl_txq *ctrlq;
527 ret = validate_filter(adapter, fs);
531 iq = get_filter_steerq(dev, fs);
533 ctrlq = &adapter->sge.ctrlq[pi->port_id];
535 f = t4_os_alloc(sizeof(*f));
545 * If the new filter requires loopback Destination MAC and/or VLAN
546 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
549 if (f->fs.newvlan == VLAN_INSERT ||
550 f->fs.newvlan == VLAN_REWRITE) {
551 /* allocate L2T entry for new filter */
552 f->l2t = cxgbe_l2t_alloc_switching(dev, f->fs.vlan,
553 f->fs.eport, f->fs.dmac);
560 atid = cxgbe_alloc_atid(t, f);
565 /* IPv6 hash filter */
566 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
570 size = sizeof(struct cpl_t6_act_open_req6);
571 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
577 mbuf->data_len = size;
578 mbuf->pkt_len = mbuf->data_len;
580 mk_act_open_req6(f, mbuf,
581 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
584 /* IPv4 hash filter */
585 size = sizeof(struct cpl_t6_act_open_req);
586 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
592 mbuf->data_len = size;
593 mbuf->pkt_len = mbuf->data_len;
595 mk_act_open_req(f, mbuf,
596 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
601 t4_mgmt_tx(ctrlq, mbuf);
605 cxgbe_clip_release(f->dev, f->clipt);
607 cxgbe_free_atid(t, atid);
615 * Clear a filter and release any of its resources that we own. This also
616 * clears the filter's "pending" status.
618 void clear_filter(struct filter_entry *f)
621 cxgbe_clip_release(f->dev, f->clipt);
624 * The zeroing of the filter rule below clears the filter valid,
625 * pending, locked flags etc. so it's all we need for
628 memset(f, 0, sizeof(*f));
632 * t4_mk_filtdelwr - create a delete filter WR
633 * @adap: adapter context
634 * @ftid: the filter ID
635 * @wr: the filter work request to populate
636 * @qid: ingress queue to receive the delete notification
638 * Creates a filter work request to delete the supplied filter. If @qid is
639 * negative the delete notification is suppressed.
641 static void t4_mk_filtdelwr(struct adapter *adap, unsigned int ftid,
642 struct fw_filter2_wr *wr, int qid)
644 memset(wr, 0, sizeof(*wr));
645 if (adap->params.filter2_wr_support)
646 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
648 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
649 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
650 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
651 V_FW_FILTER_WR_NOREPLY(qid < 0));
652 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
654 wr->rx_chan_rx_rpl_iq =
655 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
659 * Create FW work request to delete the filter at a specified index
661 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
663 struct adapter *adapter = ethdev2adap(dev);
664 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
665 struct rte_mbuf *mbuf;
666 struct fw_filter2_wr *fwr;
667 struct sge_ctrl_txq *ctrlq;
668 unsigned int port_id = ethdev2pinfo(dev)->port_id;
670 ctrlq = &adapter->sge.ctrlq[port_id];
671 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
675 mbuf->data_len = sizeof(*fwr);
676 mbuf->pkt_len = mbuf->data_len;
678 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
679 t4_mk_filtdelwr(adapter, f->tid, fwr, adapter->sge.fw_evtq.abs_id);
682 * Mark the filter as "pending" and ship off the Filter Work Request.
683 * When we get the Work Request Reply we'll clear the pending status.
686 t4_mgmt_tx(ctrlq, mbuf);
690 int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
692 struct adapter *adapter = ethdev2adap(dev);
693 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
694 struct rte_mbuf *mbuf;
695 struct fw_filter2_wr *fwr;
696 struct sge_ctrl_txq *ctrlq;
697 unsigned int port_id = ethdev2pinfo(dev)->port_id;
701 * If the new filter requires loopback Destination MAC and/or VLAN
702 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
706 /* allocate L2T entry for new filter */
707 f->l2t = cxgbe_l2t_alloc_switching(f->dev, f->fs.vlan,
708 f->fs.eport, f->fs.dmac);
713 ctrlq = &adapter->sge.ctrlq[port_id];
714 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
720 mbuf->data_len = sizeof(*fwr);
721 mbuf->pkt_len = mbuf->data_len;
723 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
724 memset(fwr, 0, sizeof(*fwr));
727 * Construct the work request to set the filter.
729 if (adapter->params.filter2_wr_support)
730 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
732 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
733 fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
735 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
736 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
737 V_FW_FILTER_WR_NOREPLY(0) |
738 V_FW_FILTER_WR_IQ(f->fs.iq));
739 fwr->del_filter_to_l2tix =
740 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
741 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
742 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
743 V_FW_FILTER_WR_INSVLAN
744 (f->fs.newvlan == VLAN_INSERT ||
745 f->fs.newvlan == VLAN_REWRITE) |
746 V_FW_FILTER_WR_RMVLAN
747 (f->fs.newvlan == VLAN_REMOVE ||
748 f->fs.newvlan == VLAN_REWRITE) |
749 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
750 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
751 V_FW_FILTER_WR_PRIO(f->fs.prio) |
752 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
753 fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
754 fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
756 fwr->rx_chan_rx_rpl_iq =
757 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
758 V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
760 fwr->maci_to_matchtypem =
761 cpu_to_be32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
762 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
763 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
764 V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
765 fwr->ptcl = f->fs.val.proto;
766 fwr->ptclm = f->fs.mask.proto;
767 rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
768 rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
769 rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
770 rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
771 fwr->lp = cpu_to_be16(f->fs.val.lport);
772 fwr->lpm = cpu_to_be16(f->fs.mask.lport);
773 fwr->fp = cpu_to_be16(f->fs.val.fport);
774 fwr->fpm = cpu_to_be16(f->fs.mask.fport);
776 if (adapter->params.filter2_wr_support && f->fs.nat_mode) {
777 fwr->natmode_to_ulp_type =
778 V_FW_FILTER2_WR_ULP_TYPE(ULP_MODE_TCPDDP) |
779 V_FW_FILTER2_WR_NATMODE(f->fs.nat_mode);
780 memcpy(fwr->newlip, f->fs.nat_lip, sizeof(fwr->newlip));
781 memcpy(fwr->newfip, f->fs.nat_fip, sizeof(fwr->newfip));
782 fwr->newlport = cpu_to_be16(f->fs.nat_lport);
783 fwr->newfport = cpu_to_be16(f->fs.nat_fport);
787 * Mark the filter as "pending" and ship off the Filter Work Request.
788 * When we get the Work Request Reply we'll clear the pending status.
791 t4_mgmt_tx(ctrlq, mbuf);
799 * Set the corresponding entry in the bitmap. 4 slots are
800 * marked for IPv6, whereas only 1 slot is marked for IPv4.
802 static int cxgbe_set_ftid(struct tid_info *t, int fidx, int family)
804 t4_os_lock(&t->ftid_lock);
805 if (rte_bitmap_get(t->ftid_bmap, fidx)) {
806 t4_os_unlock(&t->ftid_lock);
810 if (family == FILTER_TYPE_IPV4) {
811 rte_bitmap_set(t->ftid_bmap, fidx);
813 rte_bitmap_set(t->ftid_bmap, fidx);
814 rte_bitmap_set(t->ftid_bmap, fidx + 1);
815 rte_bitmap_set(t->ftid_bmap, fidx + 2);
816 rte_bitmap_set(t->ftid_bmap, fidx + 3);
818 t4_os_unlock(&t->ftid_lock);
823 * Clear the corresponding entry in the bitmap. 4 slots are
824 * cleared for IPv6, whereas only 1 slot is cleared for IPv4.
826 static void cxgbe_clear_ftid(struct tid_info *t, int fidx, int family)
828 t4_os_lock(&t->ftid_lock);
829 if (family == FILTER_TYPE_IPV4) {
830 rte_bitmap_clear(t->ftid_bmap, fidx);
832 rte_bitmap_clear(t->ftid_bmap, fidx);
833 rte_bitmap_clear(t->ftid_bmap, fidx + 1);
834 rte_bitmap_clear(t->ftid_bmap, fidx + 2);
835 rte_bitmap_clear(t->ftid_bmap, fidx + 3);
837 t4_os_unlock(&t->ftid_lock);
841 * Check a delete filter request for validity and send it to the hardware.
842 * Return 0 on success, an error number otherwise. We attach any provided
843 * filter operation context to the internal filter specification in order to
844 * facilitate signaling completion of the operation.
846 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
847 struct ch_filter_specification *fs,
848 struct filter_ctx *ctx)
850 struct port_info *pi = (struct port_info *)(dev->data->dev_private);
851 struct adapter *adapter = pi->adapter;
852 struct filter_entry *f;
853 unsigned int chip_ver;
856 if (is_hashfilter(adapter) && fs->cap)
857 return cxgbe_del_hash_filter(dev, filter_id, ctx);
859 if (filter_id >= adapter->tids.nftids)
862 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
864 ret = is_filter_set(&adapter->tids, filter_id, fs->type);
866 dev_warn(adap, "%s: could not find filter entry: %u\n",
867 __func__, filter_id);
872 * Ensure filter id is aligned on the 2 slot boundary for T6,
873 * and 4 slot boundary for cards below T6.
876 if (chip_ver < CHELSIO_T6)
882 f = &adapter->tids.ftid_tab[filter_id];
883 ret = writable_filter(f);
889 cxgbe_clear_ftid(&adapter->tids,
890 f->tid - adapter->tids.ftid_base,
891 f->fs.type ? FILTER_TYPE_IPV6 :
893 return del_filter_wr(dev, filter_id);
897 * If the caller has passed in a Completion Context then we need to
898 * mark it as a successful completion so they don't stall waiting
903 t4_complete(&ctx->completion);
910 * Check a Chelsio Filter Request for validity, convert it into our internal
911 * format and send it to the hardware. Return 0 on success, an error number
912 * otherwise. We attach any provided filter operation context to the internal
913 * filter specification in order to facilitate signaling completion of the
916 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
917 struct ch_filter_specification *fs,
918 struct filter_ctx *ctx)
920 struct port_info *pi = ethdev2pinfo(dev);
921 struct adapter *adapter = pi->adapter;
922 unsigned int fidx, iq, fid_bit = 0;
923 struct filter_entry *f;
924 unsigned int chip_ver;
925 uint8_t bitoff[16] = {0};
928 if (is_hashfilter(adapter) && fs->cap)
929 return cxgbe_set_hash_filter(dev, fs, ctx);
931 if (filter_id >= adapter->tids.nftids)
934 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
936 ret = validate_filter(adapter, fs);
941 * Ensure filter id is aligned on the 4 slot boundary for IPv6
947 ret = is_filter_set(&adapter->tids, filter_id, fs->type);
951 iq = get_filter_steerq(dev, fs);
954 * IPv6 filters occupy four slots and must be aligned on four-slot
955 * boundaries for T5. On T6, IPv6 filters occupy two-slots and
956 * must be aligned on two-slot boundaries.
958 * IPv4 filters only occupy a single slot and have no alignment
959 * requirements but writing a new IPv4 filter into the middle
960 * of an existing IPv6 filter requires clearing the old IPv6
963 if (fs->type == FILTER_TYPE_IPV4) { /* IPv4 */
965 * For T6, If our IPv4 filter isn't being written to a
966 * multiple of two filter index and there's an IPv6
967 * filter at the multiple of 2 base slot, then we need
968 * to delete that IPv6 filter ...
969 * For adapters below T6, IPv6 filter occupies 4 entries.
971 if (chip_ver < CHELSIO_T6)
972 fidx = filter_id & ~0x3;
974 fidx = filter_id & ~0x1;
976 if (fidx != filter_id && adapter->tids.ftid_tab[fidx].fs.type) {
977 f = &adapter->tids.ftid_tab[fidx];
982 unsigned int max_filter_id;
984 if (chip_ver < CHELSIO_T6) {
986 * Ensure that the IPv6 filter is aligned on a
987 * multiple of 4 boundary.
992 max_filter_id = filter_id + 4;
995 * For T6, CLIP being enabled, IPv6 filter would occupy
1001 max_filter_id = filter_id + 2;
1005 * Check all except the base overlapping IPv4 filter
1008 for (fidx = filter_id + 1; fidx < max_filter_id; fidx++) {
1009 f = &adapter->tids.ftid_tab[fidx];
1016 * Check to make sure that provided filter index is not
1017 * already in use by someone else
1019 f = &adapter->tids.ftid_tab[filter_id];
1023 fidx = adapter->tids.ftid_base + filter_id;
1024 fid_bit = filter_id;
1025 ret = cxgbe_set_ftid(&adapter->tids, fid_bit,
1026 fs->type ? FILTER_TYPE_IPV6 : FILTER_TYPE_IPV4);
1031 * Check to make sure the filter requested is writable ...
1033 ret = writable_filter(f);
1035 /* Clear the bits we have set above */
1036 cxgbe_clear_ftid(&adapter->tids, fid_bit,
1037 fs->type ? FILTER_TYPE_IPV6 :
1043 * Allocate a clip table entry only if we have non-zero IPv6 address
1045 if (chip_ver > CHELSIO_T5 && fs->type &&
1046 memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
1047 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
1053 * Convert the filter specification into our internal format.
1054 * We copy the PF/VF specification into the Outer VLAN field
1055 * here so the rest of the code -- including the interface to
1056 * the firmware -- doesn't have to constantly do these checks.
1063 * Attempt to set the filter. If we don't succeed, we clear
1064 * it and return the failure.
1067 f->tid = fidx; /* Save the actual tid */
1068 ret = set_filter_wr(dev, filter_id);
1070 fid_bit = f->tid - adapter->tids.ftid_base;
1077 cxgbe_clear_ftid(&adapter->tids, fid_bit,
1078 fs->type ? FILTER_TYPE_IPV6 :
1085 * Handle a Hash filter write reply.
1087 void hash_filter_rpl(struct adapter *adap, const struct cpl_act_open_rpl *rpl)
1089 struct tid_info *t = &adap->tids;
1090 struct filter_entry *f;
1091 struct filter_ctx *ctx = NULL;
1092 unsigned int tid = GET_TID(rpl);
1093 unsigned int ftid = G_TID_TID(G_AOPEN_ATID
1094 (be32_to_cpu(rpl->atid_status)));
1095 unsigned int status = G_AOPEN_STATUS(be32_to_cpu(rpl->atid_status));
1097 f = lookup_atid(t, ftid);
1099 dev_warn(adap, "%s: could not find filter entry: %d\n",
1108 case CPL_ERR_NONE: {
1110 f->pending = 0; /* asynchronous setup completed */
1113 cxgbe_insert_tid(t, f, f->tid, 0);
1114 cxgbe_free_atid(t, ftid);
1120 set_tcb_field(adap, tid,
1122 V_TCB_TIMESTAMP(M_TCB_TIMESTAMP) |
1123 V_TCB_T_RTT_TS_RECENT_AGE
1124 (M_TCB_T_RTT_TS_RECENT_AGE),
1125 V_TCB_TIMESTAMP(0ULL) |
1126 V_TCB_T_RTT_TS_RECENT_AGE(0ULL),
1128 if (f->fs.newvlan == VLAN_INSERT ||
1129 f->fs.newvlan == VLAN_REWRITE)
1130 set_tcb_tflag(adap, tid, S_TF_CCTRL_RFR, 1, 1);
1134 dev_warn(adap, "%s: filter creation failed with status = %u\n",
1138 if (status == CPL_ERR_TCAM_FULL)
1139 ctx->result = -EAGAIN;
1141 ctx->result = -EINVAL;
1144 cxgbe_free_atid(t, ftid);
1149 t4_complete(&ctx->completion);
1153 * Handle a LE-TCAM filter write/deletion reply.
1155 void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
1157 struct filter_entry *f = NULL;
1158 unsigned int tid = GET_TID(rpl);
1159 int idx, max_fidx = adap->tids.nftids;
1161 /* Get the corresponding filter entry for this tid */
1162 if (adap->tids.ftid_tab) {
1163 /* Check this in normal filter region */
1164 idx = tid - adap->tids.ftid_base;
1165 if (idx >= max_fidx)
1168 f = &adap->tids.ftid_tab[idx];
1173 /* We found the filter entry for this tid */
1175 unsigned int ret = G_COOKIE(rpl->cookie);
1176 struct filter_ctx *ctx;
1179 * Pull off any filter operation context attached to the
1185 if (ret == FW_FILTER_WR_FLT_ADDED) {
1186 f->pending = 0; /* asynchronous setup completed */
1192 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
1194 * Clear the filter when we get confirmation from the
1195 * hardware that the filter has been deleted.
1202 * Something went wrong. Issue a warning about the
1203 * problem and clear everything out.
1205 dev_warn(adap, "filter %u setup failed with error %u\n",
1209 ctx->result = -EINVAL;
1213 t4_complete(&ctx->completion);
1218 * Retrieve the packet count for the specified filter.
1220 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
1221 u64 *c, int hash, bool get_byte)
1223 struct filter_entry *f;
1224 unsigned int tcb_base, tcbaddr;
1227 tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
1228 if (is_hashfilter(adapter) && hash) {
1229 if (fidx < adapter->tids.ntids) {
1230 f = adapter->tids.tid_tab[fidx];
1234 if (is_t5(adapter->params.chip)) {
1238 tcbaddr = tcb_base + (fidx * TCB_SIZE);
1244 if (fidx >= adapter->tids.nftids)
1247 f = &adapter->tids.ftid_tab[fidx];
1251 tcbaddr = tcb_base + f->tid * TCB_SIZE;
1254 f = &adapter->tids.ftid_tab[fidx];
1259 if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
1261 * For T5, the Filter Packet Hit Count is maintained as a
1262 * 32-bit Big Endian value in the TCB field {timestamp}.
1263 * Similar to the craziness above, instead of the filter hit
1264 * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
1265 * sizeof(u32)), it actually shows up at offset 24. Whacky.
1268 unsigned int word_offset = 4;
1269 __be64 be64_byte_count;
1271 t4_os_lock(&adapter->win0_lock);
1272 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1274 (word_offset * sizeof(__be32)),
1275 sizeof(be64_byte_count),
1278 t4_os_unlock(&adapter->win0_lock);
1281 *c = be64_to_cpu(be64_byte_count);
1283 unsigned int word_offset = 6;
1286 t4_os_lock(&adapter->win0_lock);
1287 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1289 (word_offset * sizeof(__be32)),
1290 sizeof(be32_count), &be32_count,
1292 t4_os_unlock(&adapter->win0_lock);
1295 *c = (u64)be32_to_cpu(be32_count);
1302 * Handle a Hash filter delete reply.
1304 void hash_del_filter_rpl(struct adapter *adap,
1305 const struct cpl_abort_rpl_rss *rpl)
1307 struct tid_info *t = &adap->tids;
1308 struct filter_entry *f;
1309 struct filter_ctx *ctx = NULL;
1310 unsigned int tid = GET_TID(rpl);
1312 f = lookup_tid(t, tid);
1314 dev_warn(adap, "%s: could not find filter entry: %u\n",
1325 cxgbe_clip_release(f->dev, f->clipt);
1327 cxgbe_remove_tid(t, 0, tid, 0);
1332 t4_complete(&ctx->completion);