1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Chelsio Communications.
7 #include "base/common.h"
8 #include "base/t4_tcb.h"
9 #include "base/t4_regs.h"
10 #include "cxgbe_filter.h"
15 * Initialize Hash Filters
17 int cxgbe_init_hash_filter(struct adapter *adap)
19 unsigned int n_user_filters;
20 unsigned int user_filter_perc;
22 u32 params[7], val[7];
24 #define FW_PARAM_DEV(param) \
25 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
26 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
28 #define FW_PARAM_PFVF(param) \
29 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
30 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
31 V_FW_PARAMS_PARAM_Y(0) | \
32 V_FW_PARAMS_PARAM_Z(0))
34 params[0] = FW_PARAM_DEV(NTID);
35 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
39 adap->tids.ntids = val[0];
40 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
42 user_filter_perc = 100;
43 n_user_filters = mult_frac(adap->tids.nftids,
47 adap->tids.nftids = n_user_filters;
48 adap->params.hash_filter = 1;
53 * Validate if the requested filter specification can be set by checking
54 * if the requested features have been enabled
56 int cxgbe_validate_filter(struct adapter *adapter,
57 struct ch_filter_specification *fs)
62 * Check for unconfigured fields being used.
64 fconf = adapter->params.tp.vlan_pri_map;
66 iconf = adapter->params.tp.ingress_config;
69 (fs->val._field || fs->mask._field)
70 #define U(_mask, _field) \
71 (!(fconf & (_mask)) && S(_field))
73 if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) ||
74 U(F_PROTOCOL, proto) || U(F_MACMATCH, macidx) ||
75 U(F_VLAN, ivlan_vld) || U(F_VNIC_ID, ovlan_vld) ||
76 U(F_TOS, tos) || U(F_VNIC_ID, pfvf_vld))
79 /* Either OVLAN or PFVF match is enabled in hardware, but not both */
80 if ((S(pfvf_vld) && !(iconf & F_VNIC)) ||
81 (S(ovlan_vld) && (iconf & F_VNIC)))
84 /* To use OVLAN or PFVF, L4 encapsulation match must not be enabled */
85 if ((S(ovlan_vld) && (iconf & F_USE_ENC_IDX)) ||
86 (S(pfvf_vld) && (iconf & F_USE_ENC_IDX)))
93 * If the user is requesting that the filter action loop
94 * matching packets back out one of our ports, make sure that
95 * the egress port is in range.
97 if (fs->action == FILTER_SWITCH &&
98 fs->eport >= adapter->params.nports)
102 * Don't allow various trivially obvious bogus out-of-range
105 if (fs->val.iport >= adapter->params.nports)
108 if (!fs->cap && fs->nat_mode && !adapter->params.filter2_wr_support)
111 if (!fs->cap && fs->swapmac && !adapter->params.filter2_wr_support)
118 * Get the queue to which the traffic must be steered to.
120 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
121 struct ch_filter_specification *fs)
123 struct port_info *pi = ethdev2pinfo(dev);
124 struct adapter *adapter = pi->adapter;
128 * If the user has requested steering matching Ingress Packets
129 * to a specific Queue Set, we need to make sure it's in range
130 * for the port and map that into the Absolute Queue ID of the
131 * Queue Set's Response Queue.
137 * If the iq id is greater than the number of qsets,
138 * then assume it is an absolute qid.
140 if (fs->iq < pi->n_rx_qsets)
141 iq = adapter->sge.ethrxq[pi->first_qset +
150 /* Return an error number if the indicated filter isn't writable ... */
151 static int writable_filter(struct filter_entry *f)
162 * Send CPL_SET_TCB_FIELD message
164 static void set_tcb_field(struct adapter *adapter, unsigned int ftid,
165 u16 word, u64 mask, u64 val, int no_reply)
167 struct rte_mbuf *mbuf;
168 struct cpl_set_tcb_field *req;
169 struct sge_ctrl_txq *ctrlq;
171 ctrlq = &adapter->sge.ctrlq[0];
172 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
175 mbuf->data_len = sizeof(*req);
176 mbuf->pkt_len = mbuf->data_len;
178 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
179 memset(req, 0, sizeof(*req));
180 INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, ftid);
181 req->reply_ctrl = cpu_to_be16(V_REPLY_CHAN(0) |
182 V_QUEUENO(adapter->sge.fw_evtq.abs_id) |
183 V_NO_REPLY(no_reply));
184 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(ftid));
185 req->mask = cpu_to_be64(mask);
186 req->val = cpu_to_be64(val);
188 t4_mgmt_tx(ctrlq, mbuf);
192 * Set one of the t_flags bits in the TCB.
194 static void set_tcb_tflag(struct adapter *adap, unsigned int ftid,
195 unsigned int bit_pos, unsigned int val, int no_reply)
197 set_tcb_field(adap, ftid, W_TCB_T_FLAGS, 1ULL << bit_pos,
198 (unsigned long long)val << bit_pos, no_reply);
202 * Build a CPL_SET_TCB_FIELD message as payload of a ULP_TX_PKT command.
204 static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
205 struct cpl_set_tcb_field *req,
207 u64 mask, u64 val, u8 cookie,
210 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
211 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
213 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
214 V_ULP_TXPKT_DEST(0));
215 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
216 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
217 sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
218 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
219 req->reply_ctrl = cpu_to_be16(V_NO_REPLY(no_reply) | V_REPLY_CHAN(0) |
221 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(cookie));
222 req->mask = cpu_to_be64(mask);
223 req->val = cpu_to_be64(val);
224 sc = (struct ulptx_idata *)(req + 1);
225 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
226 sc->len = cpu_to_be32(0);
230 * IPv6 requires 2 slots on T6 and 4 slots for cards below T6.
231 * IPv4 requires only 1 slot on all cards.
233 u8 cxgbe_filter_slots(struct adapter *adap, u8 family)
235 if (family == FILTER_TYPE_IPV6) {
236 if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T6)
246 * Check if entries are already filled.
248 bool cxgbe_is_filter_set(struct tid_info *t, u32 fidx, u8 nentries)
253 /* Ensure there's enough slots available. */
254 t4_os_lock(&t->ftid_lock);
255 for (i = fidx; i < fidx + nentries; i++) {
256 if (rte_bitmap_get(t->ftid_bmap, i)) {
261 t4_os_unlock(&t->ftid_lock);
266 * Allocate available free entries.
268 int cxgbe_alloc_ftid(struct adapter *adap, u8 nentries)
270 struct tid_info *t = &adap->tids;
272 int size = t->nftids;
274 t4_os_lock(&t->ftid_lock);
276 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size,
279 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
280 t4_os_unlock(&t->ftid_lock);
282 return pos < size ? pos : -1;
286 * Construct hash filter ntuple.
288 static u64 hash_filter_ntuple(const struct filter_entry *f)
290 struct adapter *adap = ethdev2adap(f->dev);
291 struct tp_params *tp = &adap->params.tp;
293 u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
295 if (tp->port_shift >= 0 && f->fs.mask.iport)
296 ntuple |= (u64)f->fs.val.iport << tp->port_shift;
298 if (tp->protocol_shift >= 0) {
299 if (!f->fs.val.proto)
300 ntuple |= (u64)tcp_proto << tp->protocol_shift;
302 ntuple |= (u64)f->fs.val.proto << tp->protocol_shift;
305 if (tp->ethertype_shift >= 0 && f->fs.mask.ethtype)
306 ntuple |= (u64)(f->fs.val.ethtype) << tp->ethertype_shift;
307 if (tp->macmatch_shift >= 0 && f->fs.mask.macidx)
308 ntuple |= (u64)(f->fs.val.macidx) << tp->macmatch_shift;
309 if (tp->vlan_shift >= 0 && f->fs.mask.ivlan)
310 ntuple |= (u64)(F_FT_VLAN_VLD | f->fs.val.ivlan) <<
312 if (tp->vnic_shift >= 0) {
313 if ((adap->params.tp.ingress_config & F_VNIC) &&
315 ntuple |= (u64)(f->fs.val.pfvf_vld << 16 |
316 f->fs.val.pf << 13 | f->fs.val.vf) <<
318 else if (!(adap->params.tp.ingress_config & F_VNIC) &&
319 f->fs.mask.ovlan_vld)
320 ntuple |= (u64)(f->fs.val.ovlan_vld << 16 |
321 f->fs.val.ovlan) << tp->vnic_shift;
323 if (tp->tos_shift >= 0 && f->fs.mask.tos)
324 ntuple |= (u64)f->fs.val.tos << tp->tos_shift;
330 * Build a CPL_ABORT_REQ message as payload of a ULP_TX_PKT command.
332 static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
335 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_req;
336 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
338 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
339 V_ULP_TXPKT_DEST(0));
340 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
341 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
342 sc->len = cpu_to_be32(sizeof(*abort_req) -
343 sizeof(struct work_request_hdr));
344 OPCODE_TID(abort_req) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_REQ, tid));
345 abort_req->rsvd0 = cpu_to_be32(0);
346 abort_req->rsvd1 = 0;
347 abort_req->cmd = CPL_ABORT_NO_RST;
348 sc = (struct ulptx_idata *)(abort_req + 1);
349 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
350 sc->len = cpu_to_be32(0);
354 * Build a CPL_ABORT_RPL message as payload of a ULP_TX_PKT command.
356 static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
359 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_rpl;
360 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
362 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
363 V_ULP_TXPKT_DEST(0));
364 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
365 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
366 sc->len = cpu_to_be32(sizeof(*abort_rpl) -
367 sizeof(struct work_request_hdr));
368 OPCODE_TID(abort_rpl) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_RPL, tid));
369 abort_rpl->rsvd0 = cpu_to_be32(0);
370 abort_rpl->rsvd1 = 0;
371 abort_rpl->cmd = CPL_ABORT_NO_RST;
372 sc = (struct ulptx_idata *)(abort_rpl + 1);
373 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
374 sc->len = cpu_to_be32(0);
378 * Delete the specified hash filter.
380 static int cxgbe_del_hash_filter(struct rte_eth_dev *dev,
381 unsigned int filter_id,
382 struct filter_ctx *ctx)
384 struct adapter *adapter = ethdev2adap(dev);
385 struct tid_info *t = &adapter->tids;
386 struct filter_entry *f;
387 struct sge_ctrl_txq *ctrlq;
388 unsigned int port_id = ethdev2pinfo(dev)->port_id;
391 if (filter_id > adapter->tids.ntids)
394 f = lookup_tid(t, filter_id);
396 dev_err(adapter, "%s: no filter entry for filter_id = %d\n",
397 __func__, filter_id);
401 ret = writable_filter(f);
407 struct rte_mbuf *mbuf;
408 struct work_request_hdr *wr;
409 struct ulptx_idata *aligner;
410 struct cpl_set_tcb_field *req;
411 struct cpl_abort_req *abort_req;
412 struct cpl_abort_rpl *abort_rpl;
417 wrlen = cxgbe_roundup(sizeof(*wr) +
418 (sizeof(*req) + sizeof(*aligner)) +
419 sizeof(*abort_req) + sizeof(*abort_rpl),
422 ctrlq = &adapter->sge.ctrlq[port_id];
423 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
425 dev_err(adapter, "%s: could not allocate skb ..\n",
430 mbuf->data_len = wrlen;
431 mbuf->pkt_len = mbuf->data_len;
433 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
434 INIT_ULPTX_WR(req, wrlen, 0, 0);
435 wr = (struct work_request_hdr *)req;
437 req = (struct cpl_set_tcb_field *)wr;
438 mk_set_tcb_field_ulp(f, req, W_TCB_RSS_INFO,
439 V_TCB_RSS_INFO(M_TCB_RSS_INFO),
440 V_TCB_RSS_INFO(adapter->sge.fw_evtq.abs_id),
442 aligner = (struct ulptx_idata *)(req + 1);
443 abort_req = (struct cpl_abort_req *)(aligner + 1);
444 mk_abort_req_ulp(abort_req, f->tid);
445 abort_rpl = (struct cpl_abort_rpl *)(abort_req + 1);
446 mk_abort_rpl_ulp(abort_rpl, f->tid);
447 t4_mgmt_tx(ctrlq, mbuf);
456 * Build a ACT_OPEN_REQ6 message for setting IPv6 hash filter.
458 static void mk_act_open_req6(struct filter_entry *f, struct rte_mbuf *mbuf,
459 unsigned int qid_filterid, struct adapter *adap)
461 struct cpl_t6_act_open_req6 *req = NULL;
462 u64 local_lo, local_hi, peer_lo, peer_hi;
463 u32 *lip = (u32 *)f->fs.val.lip;
464 u32 *fip = (u32 *)f->fs.val.fip;
466 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
468 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req6 *);
473 dev_err(adap, "%s: unsupported chip type!\n", __func__);
477 local_hi = ((u64)lip[1]) << 32 | lip[0];
478 local_lo = ((u64)lip[3]) << 32 | lip[2];
479 peer_hi = ((u64)fip[1]) << 32 | fip[0];
480 peer_lo = ((u64)fip[3]) << 32 | fip[2];
482 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
484 req->local_port = cpu_to_be16(f->fs.val.lport);
485 req->peer_port = cpu_to_be16(f->fs.val.fport);
486 req->local_ip_hi = local_hi;
487 req->local_ip_lo = local_lo;
488 req->peer_ip_hi = peer_hi;
489 req->peer_ip_lo = peer_lo;
490 req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
491 f->fs.newvlan == VLAN_REWRITE) |
492 V_DELACK(f->fs.hitcnts) |
493 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
494 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
496 V_TX_CHAN(f->fs.eport) |
497 V_ULP_MODE(ULP_MODE_NONE) |
498 F_TCAM_BYPASS | F_NON_OFFLOAD);
499 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
500 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
501 V_RSS_QUEUE(f->fs.iq) |
504 V_SACK_EN(f->fs.swapmac) |
505 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
506 (f->fs.dirsteer << 1)) |
507 V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
511 * Build a ACT_OPEN_REQ message for setting IPv4 hash filter.
513 static void mk_act_open_req(struct filter_entry *f, struct rte_mbuf *mbuf,
514 unsigned int qid_filterid, struct adapter *adap)
516 struct cpl_t6_act_open_req *req = NULL;
518 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
520 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req *);
525 dev_err(adap, "%s: unsupported chip type!\n", __func__);
529 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
531 req->local_port = cpu_to_be16(f->fs.val.lport);
532 req->peer_port = cpu_to_be16(f->fs.val.fport);
533 req->local_ip = f->fs.val.lip[0] | f->fs.val.lip[1] << 8 |
534 f->fs.val.lip[2] << 16 | f->fs.val.lip[3] << 24;
535 req->peer_ip = f->fs.val.fip[0] | f->fs.val.fip[1] << 8 |
536 f->fs.val.fip[2] << 16 | f->fs.val.fip[3] << 24;
537 req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
538 f->fs.newvlan == VLAN_REWRITE) |
539 V_DELACK(f->fs.hitcnts) |
540 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
541 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
543 V_TX_CHAN(f->fs.eport) |
544 V_ULP_MODE(ULP_MODE_NONE) |
545 F_TCAM_BYPASS | F_NON_OFFLOAD);
546 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
547 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
548 V_RSS_QUEUE(f->fs.iq) |
551 V_SACK_EN(f->fs.swapmac) |
552 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
553 (f->fs.dirsteer << 1)) |
554 V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
558 * Set the specified hash filter.
560 static int cxgbe_set_hash_filter(struct rte_eth_dev *dev,
561 struct ch_filter_specification *fs,
562 struct filter_ctx *ctx)
564 struct port_info *pi = ethdev2pinfo(dev);
565 struct adapter *adapter = pi->adapter;
566 struct tid_info *t = &adapter->tids;
567 struct filter_entry *f;
568 struct rte_mbuf *mbuf;
569 struct sge_ctrl_txq *ctrlq;
574 ret = cxgbe_validate_filter(adapter, fs);
578 iq = get_filter_steerq(dev, fs);
580 ctrlq = &adapter->sge.ctrlq[pi->port_id];
582 f = t4_os_alloc(sizeof(*f));
592 * If the new filter requires loopback Destination MAC and/or VLAN
593 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
596 if (f->fs.newvlan == VLAN_INSERT ||
597 f->fs.newvlan == VLAN_REWRITE) {
598 /* allocate L2T entry for new filter */
599 f->l2t = cxgbe_l2t_alloc_switching(dev, f->fs.vlan,
600 f->fs.eport, f->fs.dmac);
607 atid = cxgbe_alloc_atid(t, f);
611 if (f->fs.type == FILTER_TYPE_IPV6) {
612 /* IPv6 hash filter */
613 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
617 size = sizeof(struct cpl_t6_act_open_req6);
618 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
624 mbuf->data_len = size;
625 mbuf->pkt_len = mbuf->data_len;
627 mk_act_open_req6(f, mbuf,
628 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
631 /* IPv4 hash filter */
632 size = sizeof(struct cpl_t6_act_open_req);
633 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
639 mbuf->data_len = size;
640 mbuf->pkt_len = mbuf->data_len;
642 mk_act_open_req(f, mbuf,
643 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
648 t4_mgmt_tx(ctrlq, mbuf);
652 cxgbe_clip_release(f->dev, f->clipt);
654 cxgbe_free_atid(t, atid);
662 * Clear a filter and release any of its resources that we own. This also
663 * clears the filter's "pending" status.
665 static void clear_filter(struct filter_entry *f)
668 cxgbe_clip_release(f->dev, f->clipt);
671 * The zeroing of the filter rule below clears the filter valid,
672 * pending, locked flags etc. so it's all we need for
675 memset(f, 0, sizeof(*f));
679 * t4_mk_filtdelwr - create a delete filter WR
680 * @adap: adapter context
681 * @ftid: the filter ID
682 * @wr: the filter work request to populate
683 * @qid: ingress queue to receive the delete notification
685 * Creates a filter work request to delete the supplied filter. If @qid is
686 * negative the delete notification is suppressed.
688 static void t4_mk_filtdelwr(struct adapter *adap, unsigned int ftid,
689 struct fw_filter2_wr *wr, int qid)
691 memset(wr, 0, sizeof(*wr));
692 if (adap->params.filter2_wr_support)
693 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
695 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
696 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
697 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
698 V_FW_FILTER_WR_NOREPLY(qid < 0));
699 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
701 wr->rx_chan_rx_rpl_iq =
702 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
706 * Create FW work request to delete the filter at a specified index
708 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
710 struct adapter *adapter = ethdev2adap(dev);
711 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
712 struct rte_mbuf *mbuf;
713 struct fw_filter2_wr *fwr;
714 struct sge_ctrl_txq *ctrlq;
715 unsigned int port_id = ethdev2pinfo(dev)->port_id;
717 ctrlq = &adapter->sge.ctrlq[port_id];
718 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
722 mbuf->data_len = sizeof(*fwr);
723 mbuf->pkt_len = mbuf->data_len;
725 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
726 t4_mk_filtdelwr(adapter, f->tid, fwr, adapter->sge.fw_evtq.abs_id);
729 * Mark the filter as "pending" and ship off the Filter Work Request.
730 * When we get the Work Request Reply we'll clear the pending status.
733 t4_mgmt_tx(ctrlq, mbuf);
737 static int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
739 struct adapter *adapter = ethdev2adap(dev);
740 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
741 struct rte_mbuf *mbuf;
742 struct fw_filter2_wr *fwr;
743 struct sge_ctrl_txq *ctrlq;
744 unsigned int port_id = ethdev2pinfo(dev)->port_id;
748 * If the new filter requires loopback Destination MAC and/or VLAN
749 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
753 /* allocate L2T entry for new filter */
754 f->l2t = cxgbe_l2t_alloc_switching(f->dev, f->fs.vlan,
755 f->fs.eport, f->fs.dmac);
760 ctrlq = &adapter->sge.ctrlq[port_id];
761 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
767 mbuf->data_len = sizeof(*fwr);
768 mbuf->pkt_len = mbuf->data_len;
770 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
771 memset(fwr, 0, sizeof(*fwr));
774 * Construct the work request to set the filter.
776 if (adapter->params.filter2_wr_support)
777 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
779 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
780 fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
782 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
783 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
784 V_FW_FILTER_WR_NOREPLY(0) |
785 V_FW_FILTER_WR_IQ(f->fs.iq));
786 fwr->del_filter_to_l2tix =
787 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
788 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
789 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
790 V_FW_FILTER_WR_INSVLAN
791 (f->fs.newvlan == VLAN_INSERT ||
792 f->fs.newvlan == VLAN_REWRITE) |
793 V_FW_FILTER_WR_RMVLAN
794 (f->fs.newvlan == VLAN_REMOVE ||
795 f->fs.newvlan == VLAN_REWRITE) |
796 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
797 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
798 V_FW_FILTER_WR_PRIO(f->fs.prio) |
799 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
800 fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
801 fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
802 fwr->frag_to_ovlan_vldm =
803 (V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
804 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
805 V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
806 V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
808 fwr->rx_chan_rx_rpl_iq =
809 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
810 V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
812 fwr->maci_to_matchtypem =
813 cpu_to_be32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
814 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
815 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
816 V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
817 fwr->ptcl = f->fs.val.proto;
818 fwr->ptclm = f->fs.mask.proto;
819 fwr->ttyp = f->fs.val.tos;
820 fwr->ttypm = f->fs.mask.tos;
821 fwr->ivlan = cpu_to_be16(f->fs.val.ivlan);
822 fwr->ivlanm = cpu_to_be16(f->fs.mask.ivlan);
823 fwr->ovlan = cpu_to_be16(f->fs.val.ovlan);
824 fwr->ovlanm = cpu_to_be16(f->fs.mask.ovlan);
825 rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
826 rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
827 rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
828 rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
829 fwr->lp = cpu_to_be16(f->fs.val.lport);
830 fwr->lpm = cpu_to_be16(f->fs.mask.lport);
831 fwr->fp = cpu_to_be16(f->fs.val.fport);
832 fwr->fpm = cpu_to_be16(f->fs.mask.fport);
834 if (adapter->params.filter2_wr_support) {
835 fwr->filter_type_swapmac =
836 V_FW_FILTER2_WR_SWAPMAC(f->fs.swapmac);
837 fwr->natmode_to_ulp_type =
838 V_FW_FILTER2_WR_ULP_TYPE(f->fs.nat_mode ?
841 V_FW_FILTER2_WR_NATMODE(f->fs.nat_mode);
842 memcpy(fwr->newlip, f->fs.nat_lip, sizeof(fwr->newlip));
843 memcpy(fwr->newfip, f->fs.nat_fip, sizeof(fwr->newfip));
844 fwr->newlport = cpu_to_be16(f->fs.nat_lport);
845 fwr->newfport = cpu_to_be16(f->fs.nat_fport);
849 * Mark the filter as "pending" and ship off the Filter Work Request.
850 * When we get the Work Request Reply we'll clear the pending status.
853 t4_mgmt_tx(ctrlq, mbuf);
861 * Set the corresponding entries in the bitmap.
863 static int cxgbe_set_ftid(struct tid_info *t, u32 fidx, u8 nentries)
867 t4_os_lock(&t->ftid_lock);
868 if (rte_bitmap_get(t->ftid_bmap, fidx)) {
869 t4_os_unlock(&t->ftid_lock);
873 for (i = fidx; i < fidx + nentries; i++)
874 rte_bitmap_set(t->ftid_bmap, i);
875 t4_os_unlock(&t->ftid_lock);
880 * Clear the corresponding entries in the bitmap.
882 static void cxgbe_clear_ftid(struct tid_info *t, u32 fidx, u8 nentries)
886 t4_os_lock(&t->ftid_lock);
887 for (i = fidx; i < fidx + nentries; i++)
888 rte_bitmap_clear(t->ftid_bmap, i);
889 t4_os_unlock(&t->ftid_lock);
893 * Check a delete filter request for validity and send it to the hardware.
894 * Return 0 on success, an error number otherwise. We attach any provided
895 * filter operation context to the internal filter specification in order to
896 * facilitate signaling completion of the operation.
898 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
899 struct ch_filter_specification *fs,
900 struct filter_ctx *ctx)
902 struct port_info *pi = dev->data->dev_private;
903 struct adapter *adapter = pi->adapter;
904 struct filter_entry *f;
905 unsigned int chip_ver;
909 if (is_hashfilter(adapter) && fs->cap)
910 return cxgbe_del_hash_filter(dev, filter_id, ctx);
912 if (filter_id >= adapter->tids.nftids)
915 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
918 * Ensure IPv6 filter id is aligned on the 2 slot boundary for T6,
919 * and 4 slot boundary for cards below T6.
921 if (fs->type == FILTER_TYPE_IPV6) {
922 if (chip_ver < CHELSIO_T6)
928 nentries = cxgbe_filter_slots(adapter, fs->type);
929 ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
931 dev_warn(adap, "%s: could not find filter entry: %u\n",
932 __func__, filter_id);
936 f = &adapter->tids.ftid_tab[filter_id];
937 ret = writable_filter(f);
943 cxgbe_clear_ftid(&adapter->tids,
944 f->tid - adapter->tids.ftid_base,
946 return del_filter_wr(dev, filter_id);
950 * If the caller has passed in a Completion Context then we need to
951 * mark it as a successful completion so they don't stall waiting
956 t4_complete(&ctx->completion);
963 * Check a Chelsio Filter Request for validity, convert it into our internal
964 * format and send it to the hardware. Return 0 on success, an error number
965 * otherwise. We attach any provided filter operation context to the internal
966 * filter specification in order to facilitate signaling completion of the
969 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
970 struct ch_filter_specification *fs,
971 struct filter_ctx *ctx)
973 struct port_info *pi = ethdev2pinfo(dev);
974 struct adapter *adapter = pi->adapter;
975 u8 nentries, bitoff[16] = {0};
976 struct filter_entry *f;
977 unsigned int chip_ver;
978 unsigned int fidx, iq;
982 if (is_hashfilter(adapter) && fs->cap)
983 return cxgbe_set_hash_filter(dev, fs, ctx);
985 if (filter_id >= adapter->tids.nftids)
988 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
990 ret = cxgbe_validate_filter(adapter, fs);
995 * IPv6 filters occupy four slots and must be aligned on four-slot
996 * boundaries for T5. On T6, IPv6 filters occupy two-slots and
997 * must be aligned on two-slot boundaries.
999 * IPv4 filters only occupy a single slot and have no alignment
1003 if (fs->type == FILTER_TYPE_IPV6) {
1004 if (chip_ver < CHELSIO_T6)
1010 if (fidx != filter_id)
1013 nentries = cxgbe_filter_slots(adapter, fs->type);
1014 ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
1018 iq = get_filter_steerq(dev, fs);
1021 * Check to make sure that provided filter index is not
1022 * already in use by someone else
1024 f = &adapter->tids.ftid_tab[filter_id];
1028 fidx = adapter->tids.ftid_base + filter_id;
1029 ret = cxgbe_set_ftid(&adapter->tids, filter_id, nentries);
1034 * Check to make sure the filter requested is writable ...
1036 ret = writable_filter(f);
1038 /* Clear the bits we have set above */
1039 cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1044 * Allocate a clip table entry only if we have non-zero IPv6 address
1046 if (chip_ver > CHELSIO_T5 && fs->type &&
1047 memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
1048 f->clipt = cxgbe_clip_alloc(dev, (u32 *)&fs->val.lip);
1054 * Convert the filter specification into our internal format.
1055 * We copy the PF/VF specification into the Outer VLAN field
1056 * here so the rest of the code -- including the interface to
1057 * the firmware -- doesn't have to constantly do these checks.
1063 iconf = adapter->params.tp.ingress_config;
1065 /* Either PFVF or OVLAN can be active, but not both
1066 * So, if PFVF is enabled, then overwrite the OVLAN
1067 * fields with PFVF fields before writing the spec
1070 if (iconf & F_VNIC) {
1071 f->fs.val.ovlan = fs->val.pf << 13 | fs->val.vf;
1072 f->fs.mask.ovlan = fs->mask.pf << 13 | fs->mask.vf;
1073 f->fs.val.ovlan_vld = fs->val.pfvf_vld;
1074 f->fs.mask.ovlan_vld = fs->mask.pfvf_vld;
1078 * Attempt to set the filter. If we don't succeed, we clear
1079 * it and return the failure.
1082 f->tid = fidx; /* Save the actual tid */
1083 ret = set_filter_wr(dev, filter_id);
1090 cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1096 * Handle a Hash filter write reply.
1098 void cxgbe_hash_filter_rpl(struct adapter *adap,
1099 const struct cpl_act_open_rpl *rpl)
1101 struct tid_info *t = &adap->tids;
1102 struct filter_entry *f;
1103 struct filter_ctx *ctx = NULL;
1104 unsigned int tid = GET_TID(rpl);
1105 unsigned int ftid = G_TID_TID(G_AOPEN_ATID
1106 (be32_to_cpu(rpl->atid_status)));
1107 unsigned int status = G_AOPEN_STATUS(be32_to_cpu(rpl->atid_status));
1109 f = lookup_atid(t, ftid);
1111 dev_warn(adap, "%s: could not find filter entry: %d\n",
1120 case CPL_ERR_NONE: {
1122 f->pending = 0; /* asynchronous setup completed */
1125 cxgbe_insert_tid(t, f, f->tid, 0);
1126 cxgbe_free_atid(t, ftid);
1132 set_tcb_field(adap, tid,
1134 V_TCB_TIMESTAMP(M_TCB_TIMESTAMP) |
1135 V_TCB_T_RTT_TS_RECENT_AGE
1136 (M_TCB_T_RTT_TS_RECENT_AGE),
1137 V_TCB_TIMESTAMP(0ULL) |
1138 V_TCB_T_RTT_TS_RECENT_AGE(0ULL),
1140 if (f->fs.newvlan == VLAN_INSERT ||
1141 f->fs.newvlan == VLAN_REWRITE)
1142 set_tcb_tflag(adap, tid, S_TF_CCTRL_RFR, 1, 1);
1146 dev_warn(adap, "%s: filter creation failed with status = %u\n",
1150 if (status == CPL_ERR_TCAM_FULL)
1151 ctx->result = -EAGAIN;
1153 ctx->result = -EINVAL;
1156 cxgbe_free_atid(t, ftid);
1161 t4_complete(&ctx->completion);
1165 * Handle a LE-TCAM filter write/deletion reply.
1167 void cxgbe_filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
1169 struct filter_entry *f = NULL;
1170 unsigned int tid = GET_TID(rpl);
1171 int idx, max_fidx = adap->tids.nftids;
1173 /* Get the corresponding filter entry for this tid */
1174 if (adap->tids.ftid_tab) {
1175 /* Check this in normal filter region */
1176 idx = tid - adap->tids.ftid_base;
1177 if (idx >= max_fidx)
1180 f = &adap->tids.ftid_tab[idx];
1185 /* We found the filter entry for this tid */
1187 unsigned int ret = G_COOKIE(rpl->cookie);
1188 struct filter_ctx *ctx;
1191 * Pull off any filter operation context attached to the
1197 if (ret == FW_FILTER_WR_FLT_ADDED) {
1198 f->pending = 0; /* asynchronous setup completed */
1204 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
1206 * Clear the filter when we get confirmation from the
1207 * hardware that the filter has been deleted.
1214 * Something went wrong. Issue a warning about the
1215 * problem and clear everything out.
1217 dev_warn(adap, "filter %u setup failed with error %u\n",
1221 ctx->result = -EINVAL;
1225 t4_complete(&ctx->completion);
1230 * Retrieve the packet count for the specified filter.
1232 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
1233 u64 *c, int hash, bool get_byte)
1235 struct filter_entry *f;
1236 unsigned int tcb_base, tcbaddr;
1239 tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
1240 if (is_hashfilter(adapter) && hash) {
1241 if (fidx < adapter->tids.ntids) {
1242 f = adapter->tids.tid_tab[fidx];
1246 if (is_t5(adapter->params.chip)) {
1250 tcbaddr = tcb_base + (fidx * TCB_SIZE);
1256 if (fidx >= adapter->tids.nftids)
1259 f = &adapter->tids.ftid_tab[fidx];
1263 tcbaddr = tcb_base + f->tid * TCB_SIZE;
1266 f = &adapter->tids.ftid_tab[fidx];
1271 if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
1273 * For T5, the Filter Packet Hit Count is maintained as a
1274 * 32-bit Big Endian value in the TCB field {timestamp}.
1275 * Similar to the craziness above, instead of the filter hit
1276 * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
1277 * sizeof(u32)), it actually shows up at offset 24. Whacky.
1280 unsigned int word_offset = 4;
1281 __be64 be64_byte_count;
1283 t4_os_lock(&adapter->win0_lock);
1284 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1286 (word_offset * sizeof(__be32)),
1287 sizeof(be64_byte_count),
1290 t4_os_unlock(&adapter->win0_lock);
1293 *c = be64_to_cpu(be64_byte_count);
1295 unsigned int word_offset = 6;
1298 t4_os_lock(&adapter->win0_lock);
1299 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1301 (word_offset * sizeof(__be32)),
1302 sizeof(be32_count), &be32_count,
1304 t4_os_unlock(&adapter->win0_lock);
1307 *c = (u64)be32_to_cpu(be32_count);
1314 * Clear the packet count for the specified filter.
1316 int cxgbe_clear_filter_count(struct adapter *adapter, unsigned int fidx,
1317 int hash, bool clear_byte)
1319 u64 tcb_mask = 0, tcb_val = 0;
1320 struct filter_entry *f = NULL;
1323 if (is_hashfilter(adapter) && hash) {
1324 if (fidx >= adapter->tids.ntids)
1327 /* No hitcounts supported for T5 hashfilters */
1328 if (is_t5(adapter->params.chip))
1331 f = adapter->tids.tid_tab[fidx];
1333 if (fidx >= adapter->tids.nftids)
1336 f = &adapter->tids.ftid_tab[fidx];
1339 if (!f || !f->valid)
1342 tcb_word = W_TCB_TIMESTAMP;
1343 tcb_mask = V_TCB_TIMESTAMP(M_TCB_TIMESTAMP);
1344 tcb_val = V_TCB_TIMESTAMP(0ULL);
1346 set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1349 tcb_word = W_TCB_T_RTT_TS_RECENT_AGE;
1351 V_TCB_T_RTT_TS_RECENT_AGE(M_TCB_T_RTT_TS_RECENT_AGE) |
1352 V_TCB_T_RTSEQ_RECENT(M_TCB_T_RTSEQ_RECENT);
1353 tcb_val = V_TCB_T_RTT_TS_RECENT_AGE(0ULL) |
1354 V_TCB_T_RTSEQ_RECENT(0ULL);
1356 set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1363 * Handle a Hash filter delete reply.
1365 void cxgbe_hash_del_filter_rpl(struct adapter *adap,
1366 const struct cpl_abort_rpl_rss *rpl)
1368 struct tid_info *t = &adap->tids;
1369 struct filter_entry *f;
1370 struct filter_ctx *ctx = NULL;
1371 unsigned int tid = GET_TID(rpl);
1373 f = lookup_tid(t, tid);
1375 dev_warn(adap, "%s: could not find filter entry: %u\n",
1386 cxgbe_clip_release(f->dev, f->clipt);
1388 cxgbe_remove_tid(t, 0, tid, 0);
1393 t4_complete(&ctx->completion);