1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Chelsio Communications.
7 #include "base/common.h"
8 #include "base/t4_tcb.h"
9 #include "base/t4_regs.h"
10 #include "cxgbe_filter.h"
16 * Initialize Hash Filters
18 int cxgbe_init_hash_filter(struct adapter *adap)
20 unsigned int n_user_filters;
21 unsigned int user_filter_perc;
23 u32 params[7], val[7];
25 #define FW_PARAM_DEV(param) \
26 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
27 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
29 #define FW_PARAM_PFVF(param) \
30 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
31 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
32 V_FW_PARAMS_PARAM_Y(0) | \
33 V_FW_PARAMS_PARAM_Z(0))
35 params[0] = FW_PARAM_DEV(NTID);
36 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
40 adap->tids.ntids = val[0];
41 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
43 user_filter_perc = 100;
44 n_user_filters = mult_frac(adap->tids.nftids,
48 adap->tids.nftids = n_user_filters;
49 adap->params.hash_filter = 1;
54 * Validate if the requested filter specification can be set by checking
55 * if the requested features have been enabled
57 int cxgbe_validate_filter(struct adapter *adapter,
58 struct ch_filter_specification *fs)
63 * Check for unconfigured fields being used.
65 fconf = fs->cap ? adapter->params.tp.filter_mask :
66 adapter->params.tp.vlan_pri_map;
68 iconf = adapter->params.tp.ingress_config;
71 (fs->val._field || fs->mask._field)
72 #define U(_mask, _field) \
73 (!(fconf & (_mask)) && S(_field))
75 if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) ||
76 U(F_PROTOCOL, proto) || U(F_MACMATCH, macidx) ||
77 U(F_VLAN, ivlan_vld) || U(F_VNIC_ID, ovlan_vld) ||
78 U(F_TOS, tos) || U(F_VNIC_ID, pfvf_vld))
81 /* Either OVLAN or PFVF match is enabled in hardware, but not both */
82 if ((S(pfvf_vld) && !(iconf & F_VNIC)) ||
83 (S(ovlan_vld) && (iconf & F_VNIC)))
86 /* To use OVLAN or PFVF, L4 encapsulation match must not be enabled */
87 if ((S(ovlan_vld) && (iconf & F_USE_ENC_IDX)) ||
88 (S(pfvf_vld) && (iconf & F_USE_ENC_IDX)))
95 * If the user is requesting that the filter action loop
96 * matching packets back out one of our ports, make sure that
97 * the egress port is in range.
99 if (fs->action == FILTER_SWITCH &&
100 fs->eport >= adapter->params.nports)
104 * Don't allow various trivially obvious bogus out-of-range
107 if (fs->val.iport >= adapter->params.nports)
110 if (!fs->cap && fs->nat_mode && !adapter->params.filter2_wr_support)
113 if (!fs->cap && fs->swapmac && !adapter->params.filter2_wr_support)
120 * Get the queue to which the traffic must be steered to.
122 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
123 struct ch_filter_specification *fs)
125 struct port_info *pi = ethdev2pinfo(dev);
126 struct adapter *adapter = pi->adapter;
130 * If the user has requested steering matching Ingress Packets
131 * to a specific Queue Set, we need to make sure it's in range
132 * for the port and map that into the Absolute Queue ID of the
133 * Queue Set's Response Queue.
139 * If the iq id is greater than the number of qsets,
140 * then assume it is an absolute qid.
142 if (fs->iq < pi->n_rx_qsets)
143 iq = adapter->sge.ethrxq[pi->first_qset +
152 /* Return an error number if the indicated filter isn't writable ... */
153 static int writable_filter(struct filter_entry *f)
164 * Send CPL_SET_TCB_FIELD message
166 static void set_tcb_field(struct adapter *adapter, unsigned int ftid,
167 u16 word, u64 mask, u64 val, int no_reply)
169 struct rte_mbuf *mbuf;
170 struct cpl_set_tcb_field *req;
171 struct sge_ctrl_txq *ctrlq;
173 ctrlq = &adapter->sge.ctrlq[0];
174 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
177 mbuf->data_len = sizeof(*req);
178 mbuf->pkt_len = mbuf->data_len;
180 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
181 memset(req, 0, sizeof(*req));
182 INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, ftid);
183 req->reply_ctrl = cpu_to_be16(V_REPLY_CHAN(0) |
184 V_QUEUENO(adapter->sge.fw_evtq.abs_id) |
185 V_NO_REPLY(no_reply));
186 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(ftid));
187 req->mask = cpu_to_be64(mask);
188 req->val = cpu_to_be64(val);
190 t4_mgmt_tx(ctrlq, mbuf);
194 * Set one of the t_flags bits in the TCB.
196 static void set_tcb_tflag(struct adapter *adap, unsigned int ftid,
197 unsigned int bit_pos, unsigned int val, int no_reply)
199 set_tcb_field(adap, ftid, W_TCB_T_FLAGS, 1ULL << bit_pos,
200 (unsigned long long)val << bit_pos, no_reply);
204 * Build a CPL_SET_TCB_FIELD message as payload of a ULP_TX_PKT command.
206 static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
207 struct cpl_set_tcb_field *req,
209 u64 mask, u64 val, u8 cookie,
212 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
213 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
215 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
216 V_ULP_TXPKT_DEST(0));
217 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
218 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
219 sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
220 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
221 req->reply_ctrl = cpu_to_be16(V_NO_REPLY(no_reply) | V_REPLY_CHAN(0) |
223 req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(cookie));
224 req->mask = cpu_to_be64(mask);
225 req->val = cpu_to_be64(val);
226 sc = (struct ulptx_idata *)(req + 1);
227 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
228 sc->len = cpu_to_be32(0);
232 * IPv6 requires 2 slots on T6 and 4 slots for cards below T6.
233 * IPv4 requires only 1 slot on all cards.
235 u8 cxgbe_filter_slots(struct adapter *adap, u8 family)
237 if (family == FILTER_TYPE_IPV6) {
238 if (CHELSIO_CHIP_VERSION(adap->params.chip) < CHELSIO_T6)
248 * Check if entries are already filled.
250 bool cxgbe_is_filter_set(struct tid_info *t, u32 fidx, u8 nentries)
255 /* Ensure there's enough slots available. */
256 t4_os_lock(&t->ftid_lock);
257 for (i = fidx; i < fidx + nentries; i++) {
258 if (rte_bitmap_get(t->ftid_bmap, i)) {
263 t4_os_unlock(&t->ftid_lock);
268 * Allocate available free entries.
270 int cxgbe_alloc_ftid(struct adapter *adap, u8 nentries)
272 struct tid_info *t = &adap->tids;
274 int size = t->nftids;
276 t4_os_lock(&t->ftid_lock);
278 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size,
281 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
282 t4_os_unlock(&t->ftid_lock);
284 return pos < size ? pos : -1;
288 * Construct hash filter ntuple.
290 static u64 hash_filter_ntuple(const struct filter_entry *f)
292 struct adapter *adap = ethdev2adap(f->dev);
293 struct tp_params *tp = &adap->params.tp;
295 u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
297 if (tp->port_shift >= 0 && f->fs.mask.iport)
298 ntuple |= (u64)f->fs.val.iport << tp->port_shift;
300 if (tp->protocol_shift >= 0) {
301 if (!f->fs.val.proto)
302 ntuple |= (u64)tcp_proto << tp->protocol_shift;
304 ntuple |= (u64)f->fs.val.proto << tp->protocol_shift;
307 if (tp->ethertype_shift >= 0 && f->fs.mask.ethtype)
308 ntuple |= (u64)(f->fs.val.ethtype) << tp->ethertype_shift;
309 if (tp->macmatch_shift >= 0 && f->fs.mask.macidx)
310 ntuple |= (u64)(f->fs.val.macidx) << tp->macmatch_shift;
311 if (tp->vlan_shift >= 0 && f->fs.mask.ivlan)
312 ntuple |= (u64)(F_FT_VLAN_VLD | f->fs.val.ivlan) <<
314 if (tp->vnic_shift >= 0) {
315 if ((adap->params.tp.ingress_config & F_VNIC) &&
317 ntuple |= (u64)(f->fs.val.pfvf_vld << 16 |
318 f->fs.val.pf << 13 | f->fs.val.vf) <<
320 else if (!(adap->params.tp.ingress_config & F_VNIC) &&
321 f->fs.mask.ovlan_vld)
322 ntuple |= (u64)(f->fs.val.ovlan_vld << 16 |
323 f->fs.val.ovlan) << tp->vnic_shift;
325 if (tp->tos_shift >= 0 && f->fs.mask.tos)
326 ntuple |= (u64)f->fs.val.tos << tp->tos_shift;
332 * Build a CPL_ABORT_REQ message as payload of a ULP_TX_PKT command.
334 static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
337 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_req;
338 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
340 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
341 V_ULP_TXPKT_DEST(0));
342 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
343 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
344 sc->len = cpu_to_be32(sizeof(*abort_req) -
345 sizeof(struct work_request_hdr));
346 OPCODE_TID(abort_req) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_REQ, tid));
347 abort_req->rsvd0 = cpu_to_be32(0);
348 abort_req->rsvd1 = 0;
349 abort_req->cmd = CPL_ABORT_NO_RST;
350 sc = (struct ulptx_idata *)(abort_req + 1);
351 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
352 sc->len = cpu_to_be32(0);
356 * Build a CPL_ABORT_RPL message as payload of a ULP_TX_PKT command.
358 static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
361 struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_rpl;
362 struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
364 txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
365 V_ULP_TXPKT_DEST(0));
366 txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
367 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
368 sc->len = cpu_to_be32(sizeof(*abort_rpl) -
369 sizeof(struct work_request_hdr));
370 OPCODE_TID(abort_rpl) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_RPL, tid));
371 abort_rpl->rsvd0 = cpu_to_be32(0);
372 abort_rpl->rsvd1 = 0;
373 abort_rpl->cmd = CPL_ABORT_NO_RST;
374 sc = (struct ulptx_idata *)(abort_rpl + 1);
375 sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
376 sc->len = cpu_to_be32(0);
380 * Delete the specified hash filter.
382 static int cxgbe_del_hash_filter(struct rte_eth_dev *dev,
383 unsigned int filter_id,
384 struct filter_ctx *ctx)
386 struct adapter *adapter = ethdev2adap(dev);
387 struct tid_info *t = &adapter->tids;
388 struct filter_entry *f;
389 struct sge_ctrl_txq *ctrlq;
390 unsigned int port_id = ethdev2pinfo(dev)->port_id;
393 if (filter_id > adapter->tids.ntids)
396 f = lookup_tid(t, filter_id);
398 dev_err(adapter, "%s: no filter entry for filter_id = %d\n",
399 __func__, filter_id);
403 ret = writable_filter(f);
409 struct rte_mbuf *mbuf;
410 struct work_request_hdr *wr;
411 struct ulptx_idata *aligner;
412 struct cpl_set_tcb_field *req;
413 struct cpl_abort_req *abort_req;
414 struct cpl_abort_rpl *abort_rpl;
419 wrlen = cxgbe_roundup(sizeof(*wr) +
420 (sizeof(*req) + sizeof(*aligner)) +
421 sizeof(*abort_req) + sizeof(*abort_rpl),
424 ctrlq = &adapter->sge.ctrlq[port_id];
425 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
427 dev_err(adapter, "%s: could not allocate skb ..\n",
432 mbuf->data_len = wrlen;
433 mbuf->pkt_len = mbuf->data_len;
435 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
436 INIT_ULPTX_WR(req, wrlen, 0, 0);
437 wr = (struct work_request_hdr *)req;
439 req = (struct cpl_set_tcb_field *)wr;
440 mk_set_tcb_field_ulp(f, req, W_TCB_RSS_INFO,
441 V_TCB_RSS_INFO(M_TCB_RSS_INFO),
442 V_TCB_RSS_INFO(adapter->sge.fw_evtq.abs_id),
444 aligner = (struct ulptx_idata *)(req + 1);
445 abort_req = (struct cpl_abort_req *)(aligner + 1);
446 mk_abort_req_ulp(abort_req, f->tid);
447 abort_rpl = (struct cpl_abort_rpl *)(abort_req + 1);
448 mk_abort_rpl_ulp(abort_rpl, f->tid);
449 t4_mgmt_tx(ctrlq, mbuf);
458 * Build a ACT_OPEN_REQ6 message for setting IPv6 hash filter.
460 static void mk_act_open_req6(struct filter_entry *f, struct rte_mbuf *mbuf,
461 unsigned int qid_filterid, struct adapter *adap)
463 struct cpl_t6_act_open_req6 *req = NULL;
464 u64 local_lo, local_hi, peer_lo, peer_hi;
465 u32 *lip = (u32 *)f->fs.val.lip;
466 u32 *fip = (u32 *)f->fs.val.fip;
468 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
470 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req6 *);
475 dev_err(adap, "%s: unsupported chip type!\n", __func__);
479 local_hi = ((u64)lip[1]) << 32 | lip[0];
480 local_lo = ((u64)lip[3]) << 32 | lip[2];
481 peer_hi = ((u64)fip[1]) << 32 | fip[0];
482 peer_lo = ((u64)fip[3]) << 32 | fip[2];
484 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
486 req->local_port = cpu_to_be16(f->fs.val.lport);
487 req->peer_port = cpu_to_be16(f->fs.val.fport);
488 req->local_ip_hi = local_hi;
489 req->local_ip_lo = local_lo;
490 req->peer_ip_hi = peer_hi;
491 req->peer_ip_lo = peer_lo;
492 req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
493 f->fs.newvlan == VLAN_REWRITE) |
494 V_DELACK(f->fs.hitcnts) |
495 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
496 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
498 V_TX_CHAN(f->fs.eport) |
499 V_ULP_MODE(ULP_MODE_NONE) |
500 F_TCAM_BYPASS | F_NON_OFFLOAD);
501 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
502 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
503 V_RSS_QUEUE(f->fs.iq) |
506 V_SACK_EN(f->fs.swapmac) |
507 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
508 (f->fs.dirsteer << 1)) |
509 V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
513 * Build a ACT_OPEN_REQ message for setting IPv4 hash filter.
515 static void mk_act_open_req(struct filter_entry *f, struct rte_mbuf *mbuf,
516 unsigned int qid_filterid, struct adapter *adap)
518 struct cpl_t6_act_open_req *req = NULL;
520 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
522 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req *);
527 dev_err(adap, "%s: unsupported chip type!\n", __func__);
531 OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
533 req->local_port = cpu_to_be16(f->fs.val.lport);
534 req->peer_port = cpu_to_be16(f->fs.val.fport);
535 req->local_ip = f->fs.val.lip[0] | f->fs.val.lip[1] << 8 |
536 f->fs.val.lip[2] << 16 | f->fs.val.lip[3] << 24;
537 req->peer_ip = f->fs.val.fip[0] | f->fs.val.fip[1] << 8 |
538 f->fs.val.fip[2] << 16 | f->fs.val.fip[3] << 24;
539 req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
540 f->fs.newvlan == VLAN_REWRITE) |
541 V_DELACK(f->fs.hitcnts) |
542 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
543 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
545 V_TX_CHAN(f->fs.eport) |
546 V_ULP_MODE(ULP_MODE_NONE) |
547 F_TCAM_BYPASS | F_NON_OFFLOAD);
548 req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
549 req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
550 V_RSS_QUEUE(f->fs.iq) |
553 V_SACK_EN(f->fs.swapmac) |
554 V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
555 (f->fs.dirsteer << 1)) |
556 V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
560 * Set the specified hash filter.
562 static int cxgbe_set_hash_filter(struct rte_eth_dev *dev,
563 struct ch_filter_specification *fs,
564 struct filter_ctx *ctx)
566 struct port_info *pi = ethdev2pinfo(dev);
567 struct adapter *adapter = pi->adapter;
568 struct tid_info *t = &adapter->tids;
569 struct filter_entry *f;
570 struct rte_mbuf *mbuf;
571 struct sge_ctrl_txq *ctrlq;
576 ret = cxgbe_validate_filter(adapter, fs);
580 iq = get_filter_steerq(dev, fs);
582 ctrlq = &adapter->sge.ctrlq[pi->port_id];
584 f = t4_os_alloc(sizeof(*f));
594 * If the new filter requires loopback Destination MAC and/or VLAN
595 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
598 if (f->fs.newdmac || f->fs.newvlan == VLAN_INSERT ||
599 f->fs.newvlan == VLAN_REWRITE) {
600 /* allocate L2T entry for new filter */
601 f->l2t = cxgbe_l2t_alloc_switching(dev, f->fs.vlan,
602 f->fs.eport, f->fs.dmac);
609 /* If the new filter requires Source MAC rewriting then we need to
610 * allocate a SMT entry for the filter
613 f->smt = cxgbe_smt_alloc_switching(f->dev, f->fs.smac);
620 atid = cxgbe_alloc_atid(t, f);
624 if (f->fs.type == FILTER_TYPE_IPV6) {
625 /* IPv6 hash filter */
626 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
630 size = sizeof(struct cpl_t6_act_open_req6);
631 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
637 mbuf->data_len = size;
638 mbuf->pkt_len = mbuf->data_len;
640 mk_act_open_req6(f, mbuf,
641 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
644 /* IPv4 hash filter */
645 size = sizeof(struct cpl_t6_act_open_req);
646 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
652 mbuf->data_len = size;
653 mbuf->pkt_len = mbuf->data_len;
655 mk_act_open_req(f, mbuf,
656 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
661 t4_mgmt_tx(ctrlq, mbuf);
665 cxgbe_clip_release(f->dev, f->clipt);
667 cxgbe_free_atid(t, atid);
675 * Clear a filter and release any of its resources that we own. This also
676 * clears the filter's "pending" status.
678 static void clear_filter(struct filter_entry *f)
681 cxgbe_clip_release(f->dev, f->clipt);
684 * The zeroing of the filter rule below clears the filter valid,
685 * pending, locked flags etc. so it's all we need for
688 memset(f, 0, sizeof(*f));
692 * t4_mk_filtdelwr - create a delete filter WR
693 * @adap: adapter context
694 * @ftid: the filter ID
695 * @wr: the filter work request to populate
696 * @qid: ingress queue to receive the delete notification
698 * Creates a filter work request to delete the supplied filter. If @qid is
699 * negative the delete notification is suppressed.
701 static void t4_mk_filtdelwr(struct adapter *adap, unsigned int ftid,
702 struct fw_filter2_wr *wr, int qid)
704 memset(wr, 0, sizeof(*wr));
705 if (adap->params.filter2_wr_support)
706 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
708 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
709 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
710 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
711 V_FW_FILTER_WR_NOREPLY(qid < 0));
712 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
714 wr->rx_chan_rx_rpl_iq =
715 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
719 * Create FW work request to delete the filter at a specified index
721 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
723 struct adapter *adapter = ethdev2adap(dev);
724 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
725 struct rte_mbuf *mbuf;
726 struct fw_filter2_wr *fwr;
727 struct sge_ctrl_txq *ctrlq;
728 unsigned int port_id = ethdev2pinfo(dev)->port_id;
730 ctrlq = &adapter->sge.ctrlq[port_id];
731 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
735 mbuf->data_len = sizeof(*fwr);
736 mbuf->pkt_len = mbuf->data_len;
738 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
739 t4_mk_filtdelwr(adapter, f->tid, fwr, adapter->sge.fw_evtq.abs_id);
742 * Mark the filter as "pending" and ship off the Filter Work Request.
743 * When we get the Work Request Reply we'll clear the pending status.
746 t4_mgmt_tx(ctrlq, mbuf);
750 static int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
752 struct adapter *adapter = ethdev2adap(dev);
753 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
754 struct rte_mbuf *mbuf;
755 struct fw_filter2_wr *fwr;
756 struct sge_ctrl_txq *ctrlq;
757 unsigned int port_id = ethdev2pinfo(dev)->port_id;
761 * If the new filter requires loopback Destination MAC and/or VLAN
762 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
765 if (f->fs.newvlan || f->fs.newdmac) {
766 /* allocate L2T entry for new filter */
767 f->l2t = cxgbe_l2t_alloc_switching(f->dev, f->fs.vlan,
768 f->fs.eport, f->fs.dmac);
774 /* If the new filter requires Source MAC rewriting then we need to
775 * allocate a SMT entry for the filter
778 f->smt = cxgbe_smt_alloc_switching(f->dev, f->fs.smac);
781 cxgbe_l2t_release(f->l2t);
788 ctrlq = &adapter->sge.ctrlq[port_id];
789 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
795 mbuf->data_len = sizeof(*fwr);
796 mbuf->pkt_len = mbuf->data_len;
798 fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
799 memset(fwr, 0, sizeof(*fwr));
802 * Construct the work request to set the filter.
804 if (adapter->params.filter2_wr_support)
805 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
807 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
808 fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
810 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
811 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
812 V_FW_FILTER_WR_NOREPLY(0) |
813 V_FW_FILTER_WR_IQ(f->fs.iq));
814 fwr->del_filter_to_l2tix =
815 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
816 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
817 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
818 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
819 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
820 V_FW_FILTER_WR_INSVLAN
821 (f->fs.newvlan == VLAN_INSERT ||
822 f->fs.newvlan == VLAN_REWRITE) |
823 V_FW_FILTER_WR_RMVLAN
824 (f->fs.newvlan == VLAN_REMOVE ||
825 f->fs.newvlan == VLAN_REWRITE) |
826 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
827 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
828 V_FW_FILTER_WR_PRIO(f->fs.prio) |
829 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
830 fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
831 fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
832 fwr->frag_to_ovlan_vldm =
833 (V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
834 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
835 V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
836 V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
837 fwr->smac_sel = f->smt ? f->smt->hw_idx : 0;
838 fwr->rx_chan_rx_rpl_iq =
839 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
840 V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
842 fwr->maci_to_matchtypem =
843 cpu_to_be32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
844 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
845 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
846 V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
847 fwr->ptcl = f->fs.val.proto;
848 fwr->ptclm = f->fs.mask.proto;
849 fwr->ttyp = f->fs.val.tos;
850 fwr->ttypm = f->fs.mask.tos;
851 fwr->ivlan = cpu_to_be16(f->fs.val.ivlan);
852 fwr->ivlanm = cpu_to_be16(f->fs.mask.ivlan);
853 fwr->ovlan = cpu_to_be16(f->fs.val.ovlan);
854 fwr->ovlanm = cpu_to_be16(f->fs.mask.ovlan);
855 rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
856 rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
857 rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
858 rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
859 fwr->lp = cpu_to_be16(f->fs.val.lport);
860 fwr->lpm = cpu_to_be16(f->fs.mask.lport);
861 fwr->fp = cpu_to_be16(f->fs.val.fport);
862 fwr->fpm = cpu_to_be16(f->fs.mask.fport);
864 if (adapter->params.filter2_wr_support) {
865 fwr->filter_type_swapmac =
866 V_FW_FILTER2_WR_SWAPMAC(f->fs.swapmac);
867 fwr->natmode_to_ulp_type =
868 V_FW_FILTER2_WR_ULP_TYPE(f->fs.nat_mode ?
871 V_FW_FILTER2_WR_NATMODE(f->fs.nat_mode);
872 memcpy(fwr->newlip, f->fs.nat_lip, sizeof(fwr->newlip));
873 memcpy(fwr->newfip, f->fs.nat_fip, sizeof(fwr->newfip));
874 fwr->newlport = cpu_to_be16(f->fs.nat_lport);
875 fwr->newfport = cpu_to_be16(f->fs.nat_fport);
879 * Mark the filter as "pending" and ship off the Filter Work Request.
880 * When we get the Work Request Reply we'll clear the pending status.
883 t4_mgmt_tx(ctrlq, mbuf);
891 * Set the corresponding entries in the bitmap.
893 static int cxgbe_set_ftid(struct tid_info *t, u32 fidx, u8 nentries)
897 t4_os_lock(&t->ftid_lock);
898 if (rte_bitmap_get(t->ftid_bmap, fidx)) {
899 t4_os_unlock(&t->ftid_lock);
903 for (i = fidx; i < fidx + nentries; i++)
904 rte_bitmap_set(t->ftid_bmap, i);
905 t4_os_unlock(&t->ftid_lock);
910 * Clear the corresponding entries in the bitmap.
912 static void cxgbe_clear_ftid(struct tid_info *t, u32 fidx, u8 nentries)
916 t4_os_lock(&t->ftid_lock);
917 for (i = fidx; i < fidx + nentries; i++)
918 rte_bitmap_clear(t->ftid_bmap, i);
919 t4_os_unlock(&t->ftid_lock);
923 * Check a delete filter request for validity and send it to the hardware.
924 * Return 0 on success, an error number otherwise. We attach any provided
925 * filter operation context to the internal filter specification in order to
926 * facilitate signaling completion of the operation.
928 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
929 struct ch_filter_specification *fs,
930 struct filter_ctx *ctx)
932 struct port_info *pi = dev->data->dev_private;
933 struct adapter *adapter = pi->adapter;
934 struct filter_entry *f;
935 unsigned int chip_ver;
939 if (is_hashfilter(adapter) && fs->cap)
940 return cxgbe_del_hash_filter(dev, filter_id, ctx);
942 if (filter_id >= adapter->tids.nftids)
945 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
948 * Ensure IPv6 filter id is aligned on the 2 slot boundary for T6,
949 * and 4 slot boundary for cards below T6.
951 if (fs->type == FILTER_TYPE_IPV6) {
952 if (chip_ver < CHELSIO_T6)
958 nentries = cxgbe_filter_slots(adapter, fs->type);
959 ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
961 dev_warn(adap, "%s: could not find filter entry: %u\n",
962 __func__, filter_id);
966 f = &adapter->tids.ftid_tab[filter_id];
967 ret = writable_filter(f);
973 cxgbe_clear_ftid(&adapter->tids,
974 f->tid - adapter->tids.ftid_base,
976 return del_filter_wr(dev, filter_id);
980 * If the caller has passed in a Completion Context then we need to
981 * mark it as a successful completion so they don't stall waiting
986 t4_complete(&ctx->completion);
993 * Check a Chelsio Filter Request for validity, convert it into our internal
994 * format and send it to the hardware. Return 0 on success, an error number
995 * otherwise. We attach any provided filter operation context to the internal
996 * filter specification in order to facilitate signaling completion of the
999 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
1000 struct ch_filter_specification *fs,
1001 struct filter_ctx *ctx)
1003 struct port_info *pi = ethdev2pinfo(dev);
1004 struct adapter *adapter = pi->adapter;
1005 u8 nentries, bitoff[16] = {0};
1006 struct filter_entry *f;
1007 unsigned int chip_ver;
1008 unsigned int fidx, iq;
1012 if (is_hashfilter(adapter) && fs->cap)
1013 return cxgbe_set_hash_filter(dev, fs, ctx);
1015 if (filter_id >= adapter->tids.nftids)
1018 chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
1020 ret = cxgbe_validate_filter(adapter, fs);
1025 * IPv6 filters occupy four slots and must be aligned on four-slot
1026 * boundaries for T5. On T6, IPv6 filters occupy two-slots and
1027 * must be aligned on two-slot boundaries.
1029 * IPv4 filters only occupy a single slot and have no alignment
1033 if (fs->type == FILTER_TYPE_IPV6) {
1034 if (chip_ver < CHELSIO_T6)
1040 if (fidx != filter_id)
1043 nentries = cxgbe_filter_slots(adapter, fs->type);
1044 ret = cxgbe_is_filter_set(&adapter->tids, filter_id, nentries);
1048 iq = get_filter_steerq(dev, fs);
1051 * Check to make sure that provided filter index is not
1052 * already in use by someone else
1054 f = &adapter->tids.ftid_tab[filter_id];
1058 fidx = adapter->tids.ftid_base + filter_id;
1059 ret = cxgbe_set_ftid(&adapter->tids, filter_id, nentries);
1064 * Check to make sure the filter requested is writable ...
1066 ret = writable_filter(f);
1068 /* Clear the bits we have set above */
1069 cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1074 * Allocate a clip table entry only if we have non-zero IPv6 address
1076 if (chip_ver > CHELSIO_T5 && fs->type &&
1077 memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
1078 f->clipt = cxgbe_clip_alloc(dev, (u32 *)&fs->val.lip);
1084 * Convert the filter specification into our internal format.
1085 * We copy the PF/VF specification into the Outer VLAN field
1086 * here so the rest of the code -- including the interface to
1087 * the firmware -- doesn't have to constantly do these checks.
1093 iconf = adapter->params.tp.ingress_config;
1095 /* Either PFVF or OVLAN can be active, but not both
1096 * So, if PFVF is enabled, then overwrite the OVLAN
1097 * fields with PFVF fields before writing the spec
1100 if (iconf & F_VNIC) {
1101 f->fs.val.ovlan = fs->val.pf << 13 | fs->val.vf;
1102 f->fs.mask.ovlan = fs->mask.pf << 13 | fs->mask.vf;
1103 f->fs.val.ovlan_vld = fs->val.pfvf_vld;
1104 f->fs.mask.ovlan_vld = fs->mask.pfvf_vld;
1108 * Attempt to set the filter. If we don't succeed, we clear
1109 * it and return the failure.
1112 f->tid = fidx; /* Save the actual tid */
1113 ret = set_filter_wr(dev, filter_id);
1120 cxgbe_clear_ftid(&adapter->tids, filter_id, nentries);
1126 * Handle a Hash filter write reply.
1128 void cxgbe_hash_filter_rpl(struct adapter *adap,
1129 const struct cpl_act_open_rpl *rpl)
1131 struct tid_info *t = &adap->tids;
1132 struct filter_entry *f;
1133 struct filter_ctx *ctx = NULL;
1134 unsigned int tid = GET_TID(rpl);
1135 unsigned int ftid = G_TID_TID(G_AOPEN_ATID
1136 (be32_to_cpu(rpl->atid_status)));
1137 unsigned int status = G_AOPEN_STATUS(be32_to_cpu(rpl->atid_status));
1139 f = lookup_atid(t, ftid);
1141 dev_warn(adap, "%s: could not find filter entry: %d\n",
1150 case CPL_ERR_NONE: {
1152 f->pending = 0; /* asynchronous setup completed */
1155 cxgbe_insert_tid(t, f, f->tid, 0);
1156 cxgbe_free_atid(t, ftid);
1162 set_tcb_field(adap, tid,
1164 V_TCB_TIMESTAMP(M_TCB_TIMESTAMP) |
1165 V_TCB_T_RTT_TS_RECENT_AGE
1166 (M_TCB_T_RTT_TS_RECENT_AGE),
1167 V_TCB_TIMESTAMP(0ULL) |
1168 V_TCB_T_RTT_TS_RECENT_AGE(0ULL),
1171 set_tcb_tflag(adap, tid, S_TF_CCTRL_ECE, 1, 1);
1172 if (f->fs.newvlan == VLAN_INSERT ||
1173 f->fs.newvlan == VLAN_REWRITE)
1174 set_tcb_tflag(adap, tid, S_TF_CCTRL_RFR, 1, 1);
1175 if (f->fs.newsmac) {
1176 set_tcb_tflag(adap, tid, S_TF_CCTRL_CWR, 1, 1);
1177 set_tcb_field(adap, tid, W_TCB_SMAC_SEL,
1178 V_TCB_SMAC_SEL(M_TCB_SMAC_SEL),
1179 V_TCB_SMAC_SEL(f->smt->hw_idx), 1);
1184 dev_warn(adap, "%s: filter creation failed with status = %u\n",
1188 if (status == CPL_ERR_TCAM_FULL)
1189 ctx->result = -EAGAIN;
1191 ctx->result = -EINVAL;
1194 cxgbe_free_atid(t, ftid);
1199 t4_complete(&ctx->completion);
1203 * Handle a LE-TCAM filter write/deletion reply.
1205 void cxgbe_filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
1207 struct filter_entry *f = NULL;
1208 unsigned int tid = GET_TID(rpl);
1209 int idx, max_fidx = adap->tids.nftids;
1211 /* Get the corresponding filter entry for this tid */
1212 if (adap->tids.ftid_tab) {
1213 /* Check this in normal filter region */
1214 idx = tid - adap->tids.ftid_base;
1215 if (idx >= max_fidx)
1218 f = &adap->tids.ftid_tab[idx];
1223 /* We found the filter entry for this tid */
1225 unsigned int ret = G_COOKIE(rpl->cookie);
1226 struct filter_ctx *ctx;
1229 * Pull off any filter operation context attached to the
1235 if (ret == FW_FILTER_WR_FLT_ADDED) {
1236 f->pending = 0; /* asynchronous setup completed */
1242 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
1244 * Clear the filter when we get confirmation from the
1245 * hardware that the filter has been deleted.
1252 * Something went wrong. Issue a warning about the
1253 * problem and clear everything out.
1255 dev_warn(adap, "filter %u setup failed with error %u\n",
1259 ctx->result = -EINVAL;
1263 t4_complete(&ctx->completion);
1268 * Retrieve the packet count for the specified filter.
1270 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
1271 u64 *c, int hash, bool get_byte)
1273 struct filter_entry *f;
1274 unsigned int tcb_base, tcbaddr;
1277 tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
1278 if (is_hashfilter(adapter) && hash) {
1279 if (fidx < adapter->tids.ntids) {
1280 f = adapter->tids.tid_tab[fidx];
1284 if (is_t5(adapter->params.chip)) {
1288 tcbaddr = tcb_base + (fidx * TCB_SIZE);
1294 if (fidx >= adapter->tids.nftids)
1297 f = &adapter->tids.ftid_tab[fidx];
1301 tcbaddr = tcb_base + f->tid * TCB_SIZE;
1304 f = &adapter->tids.ftid_tab[fidx];
1309 if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
1311 * For T5, the Filter Packet Hit Count is maintained as a
1312 * 32-bit Big Endian value in the TCB field {timestamp}.
1313 * Similar to the craziness above, instead of the filter hit
1314 * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
1315 * sizeof(u32)), it actually shows up at offset 24. Whacky.
1318 unsigned int word_offset = 4;
1319 __be64 be64_byte_count;
1321 t4_os_lock(&adapter->win0_lock);
1322 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1324 (word_offset * sizeof(__be32)),
1325 sizeof(be64_byte_count),
1328 t4_os_unlock(&adapter->win0_lock);
1331 *c = be64_to_cpu(be64_byte_count);
1333 unsigned int word_offset = 6;
1336 t4_os_lock(&adapter->win0_lock);
1337 ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1339 (word_offset * sizeof(__be32)),
1340 sizeof(be32_count), &be32_count,
1342 t4_os_unlock(&adapter->win0_lock);
1345 *c = (u64)be32_to_cpu(be32_count);
1352 * Clear the packet count for the specified filter.
1354 int cxgbe_clear_filter_count(struct adapter *adapter, unsigned int fidx,
1355 int hash, bool clear_byte)
1357 u64 tcb_mask = 0, tcb_val = 0;
1358 struct filter_entry *f = NULL;
1361 if (is_hashfilter(adapter) && hash) {
1362 if (fidx >= adapter->tids.ntids)
1365 /* No hitcounts supported for T5 hashfilters */
1366 if (is_t5(adapter->params.chip))
1369 f = adapter->tids.tid_tab[fidx];
1371 if (fidx >= adapter->tids.nftids)
1374 f = &adapter->tids.ftid_tab[fidx];
1377 if (!f || !f->valid)
1380 tcb_word = W_TCB_TIMESTAMP;
1381 tcb_mask = V_TCB_TIMESTAMP(M_TCB_TIMESTAMP);
1382 tcb_val = V_TCB_TIMESTAMP(0ULL);
1384 set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1387 tcb_word = W_TCB_T_RTT_TS_RECENT_AGE;
1389 V_TCB_T_RTT_TS_RECENT_AGE(M_TCB_T_RTT_TS_RECENT_AGE) |
1390 V_TCB_T_RTSEQ_RECENT(M_TCB_T_RTSEQ_RECENT);
1391 tcb_val = V_TCB_T_RTT_TS_RECENT_AGE(0ULL) |
1392 V_TCB_T_RTSEQ_RECENT(0ULL);
1394 set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1401 * Handle a Hash filter delete reply.
1403 void cxgbe_hash_del_filter_rpl(struct adapter *adap,
1404 const struct cpl_abort_rpl_rss *rpl)
1406 struct tid_info *t = &adap->tids;
1407 struct filter_entry *f;
1408 struct filter_ctx *ctx = NULL;
1409 unsigned int tid = GET_TID(rpl);
1411 f = lookup_tid(t, tid);
1413 dev_warn(adap, "%s: could not find filter entry: %u\n",
1424 cxgbe_clip_release(f->dev, f->clipt);
1426 cxgbe_remove_tid(t, 0, tid, 0);
1431 t4_complete(&ctx->completion);