drivers/net/cxgbe/cxgbe_filter.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5 #include <rte_net.h>
   6
   7 #include "base/common.h"
   8 #include "base/t4_tcb.h"
   9 #include "base/t4_regs.h"
  10 #include "cxgbe_filter.h"
  11 #include "clip_tbl.h"
  12 #include "l2t.h"
  13
  14 /**
  15  * Initialize Hash Filters
  16  */
  17 int cxgbe_init_hash_filter(struct adapter *adap)
  18 {
  19         unsigned int n_user_filters;
  20         unsigned int user_filter_perc;
  21         int ret;
  22         u32 params[7], val[7];
  23
  24 #define FW_PARAM_DEV(param) \
  25         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
  26         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
  27
  28 #define FW_PARAM_PFVF(param) \
  29         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
  30         V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
  31         V_FW_PARAMS_PARAM_Y(0) | \
  32         V_FW_PARAMS_PARAM_Z(0))
  33
  34         params[0] = FW_PARAM_DEV(NTID);
  35         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
  36                               params, val);
  37         if (ret < 0)
  38                 return ret;
  39         adap->tids.ntids = val[0];
  40         adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
  41
  42         user_filter_perc = 100;
  43         n_user_filters = mult_frac(adap->tids.nftids,
  44                                    user_filter_perc,
  45                                    100);
  46
  47         adap->tids.nftids = n_user_filters;
  48         adap->params.hash_filter = 1;
  49         return 0;
  50 }
  51
  52 /**
  53  * Validate if the requested filter specification can be set by checking
  54  * if the requested features have been enabled
  55  */
  56 int cxgbe_validate_filter(struct adapter *adapter,
  57                           struct ch_filter_specification *fs)
  58 {
  59         u32 fconf;
  60
  61         /*
  62          * Check for unconfigured fields being used.
  63          */
  64         fconf = adapter->params.tp.vlan_pri_map;
  65
  66 #define S(_field) \
  67         (fs->val._field || fs->mask._field)
  68 #define U(_mask, _field) \
  69         (!(fconf & (_mask)) && S(_field))
  70
  71         if (U(F_PORT, iport) || U(F_ETHERTYPE, ethtype) ||
  72             U(F_PROTOCOL, proto) || U(F_MACMATCH, macidx))
  73                 return -EOPNOTSUPP;
  74
  75 #undef S
  76 #undef U
  77
  78         /*
  79          * If the user is requesting that the filter action loop
  80          * matching packets back out one of our ports, make sure that
  81          * the egress port is in range.
  82          */
  83         if (fs->action == FILTER_SWITCH &&
  84             fs->eport >= adapter->params.nports)
  85                 return -ERANGE;
  86
  87         /*
  88          * Don't allow various trivially obvious bogus out-of-range
  89          * values ...
  90          */
  91         if (fs->val.iport >= adapter->params.nports)
  92                 return -ERANGE;
  93
  94         if (!fs->cap && fs->nat_mode && !adapter->params.filter2_wr_support)
  95                 return -EOPNOTSUPP;
  96
  97         if (!fs->cap && fs->swapmac && !adapter->params.filter2_wr_support)
  98                 return -EOPNOTSUPP;
  99
 100         return 0;
 101 }
 102
 103 /**
 104  * Get the queue to which the traffic must be steered to.
 105  */
 106 static unsigned int get_filter_steerq(struct rte_eth_dev *dev,
 107                                       struct ch_filter_specification *fs)
 108 {
 109         struct port_info *pi = ethdev2pinfo(dev);
 110         struct adapter *adapter = pi->adapter;
 111         unsigned int iq;
 112
 113         /*
 114          * If the user has requested steering matching Ingress Packets
 115          * to a specific Queue Set, we need to make sure it's in range
 116          * for the port and map that into the Absolute Queue ID of the
 117          * Queue Set's Response Queue.
 118          */
 119         if (!fs->dirsteer) {
 120                 iq = 0;
 121         } else {
 122                 /*
 123                  * If the iq id is greater than the number of qsets,
 124                  * then assume it is an absolute qid.
 125                  */
 126                 if (fs->iq < pi->n_rx_qsets)
 127                         iq = adapter->sge.ethrxq[pi->first_qset +
 128                                                  fs->iq].rspq.abs_id;
 129                 else
 130                         iq = fs->iq;
 131         }
 132
 133         return iq;
 134 }
 135
 136 /* Return an error number if the indicated filter isn't writable ... */
 137 static int writable_filter(struct filter_entry *f)
 138 {
 139         if (f->locked)
 140                 return -EPERM;
 141         if (f->pending)
 142                 return -EBUSY;
 143
 144         return 0;
 145 }
 146
 147 /**
 148  * Send CPL_SET_TCB_FIELD message
 149  */
 150 static void set_tcb_field(struct adapter *adapter, unsigned int ftid,
 151                           u16 word, u64 mask, u64 val, int no_reply)
 152 {
 153         struct rte_mbuf *mbuf;
 154         struct cpl_set_tcb_field *req;
 155         struct sge_ctrl_txq *ctrlq;
 156
 157         ctrlq = &adapter->sge.ctrlq[0];
 158         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 159         WARN_ON(!mbuf);
 160
 161         mbuf->data_len = sizeof(*req);
 162         mbuf->pkt_len = mbuf->data_len;
 163
 164         req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
 165         memset(req, 0, sizeof(*req));
 166         INIT_TP_WR_MIT_CPL(req, CPL_SET_TCB_FIELD, ftid);
 167         req->reply_ctrl = cpu_to_be16(V_REPLY_CHAN(0) |
 168                                       V_QUEUENO(adapter->sge.fw_evtq.abs_id) |
 169                                       V_NO_REPLY(no_reply));
 170         req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(ftid));
 171         req->mask = cpu_to_be64(mask);
 172         req->val = cpu_to_be64(val);
 173
 174         t4_mgmt_tx(ctrlq, mbuf);
 175 }
 176
 177 /**
 178  * Set one of the t_flags bits in the TCB.
 179  */
 180 static void set_tcb_tflag(struct adapter *adap, unsigned int ftid,
 181                           unsigned int bit_pos, unsigned int val, int no_reply)
 182 {
 183         set_tcb_field(adap, ftid,  W_TCB_T_FLAGS, 1ULL << bit_pos,
 184                       (unsigned long long)val << bit_pos, no_reply);
 185 }
 186
 187 /**
 188  * Build a CPL_SET_TCB_FIELD message as payload of a ULP_TX_PKT command.
 189  */
 190 static inline void mk_set_tcb_field_ulp(struct filter_entry *f,
 191                                         struct cpl_set_tcb_field *req,
 192                                         unsigned int word,
 193                                         u64 mask, u64 val, u8 cookie,
 194                                         int no_reply)
 195 {
 196         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
 197         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 198
 199         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 200                                       V_ULP_TXPKT_DEST(0));
 201         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*req), 16));
 202         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 203         sc->len = cpu_to_be32(sizeof(*req) - sizeof(struct work_request_hdr));
 204         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_SET_TCB_FIELD, f->tid));
 205         req->reply_ctrl = cpu_to_be16(V_NO_REPLY(no_reply) | V_REPLY_CHAN(0) |
 206                                       V_QUEUENO(0));
 207         req->word_cookie = cpu_to_be16(V_WORD(word) | V_COOKIE(cookie));
 208         req->mask = cpu_to_be64(mask);
 209         req->val = cpu_to_be64(val);
 210         sc = (struct ulptx_idata *)(req + 1);
 211         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 212         sc->len = cpu_to_be32(0);
 213 }
 214
 215 /**
 216  * Check if entry already filled.
 217  */
 218 bool cxgbe_is_filter_set(struct tid_info *t, int fidx, int family)
 219 {
 220         bool result = FALSE;
 221         int i, max;
 222
 223         /* IPv6 requires four slots and IPv4 requires only 1 slot.
 224          * Ensure, there's enough slots available.
 225          */
 226         max = family == FILTER_TYPE_IPV6 ? fidx + 3 : fidx;
 227
 228         t4_os_lock(&t->ftid_lock);
 229         for (i = fidx; i <= max; i++) {
 230                 if (rte_bitmap_get(t->ftid_bmap, i)) {
 231                         result = TRUE;
 232                         break;
 233                 }
 234         }
 235         t4_os_unlock(&t->ftid_lock);
 236         return result;
 237 }
 238
 239 /**
 240  * Allocate a available free entry
 241  */
 242 int cxgbe_alloc_ftid(struct adapter *adap, unsigned int family)
 243 {
 244         struct tid_info *t = &adap->tids;
 245         int pos;
 246         int size = t->nftids;
 247
 248         t4_os_lock(&t->ftid_lock);
 249         if (family == FILTER_TYPE_IPV6)
 250                 pos = cxgbe_bitmap_find_free_region(t->ftid_bmap, size, 4);
 251         else
 252                 pos = cxgbe_find_first_zero_bit(t->ftid_bmap, size);
 253         t4_os_unlock(&t->ftid_lock);
 254
 255         return pos < size ? pos : -1;
 256 }
 257
 258 /**
 259  * Construct hash filter ntuple.
 260  */
 261 static u64 hash_filter_ntuple(const struct filter_entry *f)
 262 {
 263         struct adapter *adap = ethdev2adap(f->dev);
 264         struct tp_params *tp = &adap->params.tp;
 265         u64 ntuple = 0;
 266         u16 tcp_proto = IPPROTO_TCP; /* TCP Protocol Number */
 267
 268         if (tp->port_shift >= 0 && f->fs.mask.iport)
 269                 ntuple |= (u64)f->fs.val.iport << tp->port_shift;
 270
 271         if (tp->protocol_shift >= 0) {
 272                 if (!f->fs.val.proto)
 273                         ntuple |= (u64)tcp_proto << tp->protocol_shift;
 274                 else
 275                         ntuple |= (u64)f->fs.val.proto << tp->protocol_shift;
 276         }
 277
 278         if (tp->ethertype_shift >= 0 && f->fs.mask.ethtype)
 279                 ntuple |= (u64)(f->fs.val.ethtype) << tp->ethertype_shift;
 280         if (tp->macmatch_shift >= 0 && f->fs.mask.macidx)
 281                 ntuple |= (u64)(f->fs.val.macidx) << tp->macmatch_shift;
 282
 283         return ntuple;
 284 }
 285
 286 /**
 287  * Build a CPL_ABORT_REQ message as payload of a ULP_TX_PKT command.
 288  */
 289 static void mk_abort_req_ulp(struct cpl_abort_req *abort_req,
 290                              unsigned int tid)
 291 {
 292         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_req;
 293         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 294
 295         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 296                                       V_ULP_TXPKT_DEST(0));
 297         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_req), 16));
 298         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 299         sc->len = cpu_to_be32(sizeof(*abort_req) -
 300                               sizeof(struct work_request_hdr));
 301         OPCODE_TID(abort_req) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_REQ, tid));
 302         abort_req->rsvd0 = cpu_to_be32(0);
 303         abort_req->rsvd1 = 0;
 304         abort_req->cmd = CPL_ABORT_NO_RST;
 305         sc = (struct ulptx_idata *)(abort_req + 1);
 306         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 307         sc->len = cpu_to_be32(0);
 308 }
 309
 310 /**
 311  * Build a CPL_ABORT_RPL message as payload of a ULP_TX_PKT command.
 312  */
 313 static void mk_abort_rpl_ulp(struct cpl_abort_rpl *abort_rpl,
 314                              unsigned int tid)
 315 {
 316         struct ulp_txpkt *txpkt = (struct ulp_txpkt *)abort_rpl;
 317         struct ulptx_idata *sc = (struct ulptx_idata *)(txpkt + 1);
 318
 319         txpkt->cmd_dest = cpu_to_be32(V_ULPTX_CMD(ULP_TX_PKT) |
 320                                       V_ULP_TXPKT_DEST(0));
 321         txpkt->len = cpu_to_be32(DIV_ROUND_UP(sizeof(*abort_rpl), 16));
 322         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_IMM));
 323         sc->len = cpu_to_be32(sizeof(*abort_rpl) -
 324                               sizeof(struct work_request_hdr));
 325         OPCODE_TID(abort_rpl) = cpu_to_be32(MK_OPCODE_TID(CPL_ABORT_RPL, tid));
 326         abort_rpl->rsvd0 = cpu_to_be32(0);
 327         abort_rpl->rsvd1 = 0;
 328         abort_rpl->cmd = CPL_ABORT_NO_RST;
 329         sc = (struct ulptx_idata *)(abort_rpl + 1);
 330         sc->cmd_more = cpu_to_be32(V_ULPTX_CMD(ULP_TX_SC_NOOP));
 331         sc->len = cpu_to_be32(0);
 332 }
 333
 334 /**
 335  * Delete the specified hash filter.
 336  */
 337 static int cxgbe_del_hash_filter(struct rte_eth_dev *dev,
 338                                  unsigned int filter_id,
 339                                  struct filter_ctx *ctx)
 340 {
 341         struct adapter *adapter = ethdev2adap(dev);
 342         struct tid_info *t = &adapter->tids;
 343         struct filter_entry *f;
 344         struct sge_ctrl_txq *ctrlq;
 345         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 346         int ret;
 347
 348         if (filter_id > adapter->tids.ntids)
 349                 return -E2BIG;
 350
 351         f = lookup_tid(t, filter_id);
 352         if (!f) {
 353                 dev_err(adapter, "%s: no filter entry for filter_id = %d\n",
 354                         __func__, filter_id);
 355                 return -EINVAL;
 356         }
 357
 358         ret = writable_filter(f);
 359         if (ret)
 360                 return ret;
 361
 362         if (f->valid) {
 363                 unsigned int wrlen;
 364                 struct rte_mbuf *mbuf;
 365                 struct work_request_hdr *wr;
 366                 struct ulptx_idata *aligner;
 367                 struct cpl_set_tcb_field *req;
 368                 struct cpl_abort_req *abort_req;
 369                 struct cpl_abort_rpl *abort_rpl;
 370
 371                 f->ctx = ctx;
 372                 f->pending = 1;
 373
 374                 wrlen = cxgbe_roundup(sizeof(*wr) +
 375                                       (sizeof(*req) + sizeof(*aligner)) +
 376                                       sizeof(*abort_req) + sizeof(*abort_rpl),
 377                                       16);
 378
 379                 ctrlq = &adapter->sge.ctrlq[port_id];
 380                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 381                 if (!mbuf) {
 382                         dev_err(adapter, "%s: could not allocate skb ..\n",
 383                                 __func__);
 384                         goto out_err;
 385                 }
 386
 387                 mbuf->data_len = wrlen;
 388                 mbuf->pkt_len = mbuf->data_len;
 389
 390                 req = rte_pktmbuf_mtod(mbuf, struct cpl_set_tcb_field *);
 391                 INIT_ULPTX_WR(req, wrlen, 0, 0);
 392                 wr = (struct work_request_hdr *)req;
 393                 wr++;
 394                 req = (struct cpl_set_tcb_field *)wr;
 395                 mk_set_tcb_field_ulp(f, req, W_TCB_RSS_INFO,
 396                                 V_TCB_RSS_INFO(M_TCB_RSS_INFO),
 397                                 V_TCB_RSS_INFO(adapter->sge.fw_evtq.abs_id),
 398                                 0, 1);
 399                 aligner = (struct ulptx_idata *)(req + 1);
 400                 abort_req = (struct cpl_abort_req *)(aligner + 1);
 401                 mk_abort_req_ulp(abort_req, f->tid);
 402                 abort_rpl = (struct cpl_abort_rpl *)(abort_req + 1);
 403                 mk_abort_rpl_ulp(abort_rpl, f->tid);
 404                 t4_mgmt_tx(ctrlq, mbuf);
 405         }
 406         return 0;
 407
 408 out_err:
 409         return -ENOMEM;
 410 }
 411
 412 /**
 413  * Build a ACT_OPEN_REQ6 message for setting IPv6 hash filter.
 414  */
 415 static void mk_act_open_req6(struct filter_entry *f, struct rte_mbuf *mbuf,
 416                              unsigned int qid_filterid, struct adapter *adap)
 417 {
 418         struct cpl_t6_act_open_req6 *req = NULL;
 419         u64 local_lo, local_hi, peer_lo, peer_hi;
 420         u32 *lip = (u32 *)f->fs.val.lip;
 421         u32 *fip = (u32 *)f->fs.val.fip;
 422
 423         switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
 424         case CHELSIO_T6:
 425                 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req6 *);
 426
 427                 INIT_TP_WR(req, 0);
 428                 break;
 429         default:
 430                 dev_err(adap, "%s: unsupported chip type!\n", __func__);
 431                 return;
 432         }
 433
 434         local_hi = ((u64)lip[1]) << 32 | lip[0];
 435         local_lo = ((u64)lip[3]) << 32 | lip[2];
 436         peer_hi = ((u64)fip[1]) << 32 | fip[0];
 437         peer_lo = ((u64)fip[3]) << 32 | fip[2];
 438
 439         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ6,
 440                                                     qid_filterid));
 441         req->local_port = cpu_to_be16(f->fs.val.lport);
 442         req->peer_port = cpu_to_be16(f->fs.val.fport);
 443         req->local_ip_hi = local_hi;
 444         req->local_ip_lo = local_lo;
 445         req->peer_ip_hi = peer_hi;
 446         req->peer_ip_lo = peer_lo;
 447         req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
 448                                         f->fs.newvlan == VLAN_REWRITE) |
 449                                 V_DELACK(f->fs.hitcnts) |
 450                                 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
 451                                 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
 452                                            << 1) |
 453                                 V_TX_CHAN(f->fs.eport) |
 454                                 V_ULP_MODE(ULP_MODE_NONE) |
 455                                 F_TCAM_BYPASS | F_NON_OFFLOAD);
 456         req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
 457         req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
 458                             V_RSS_QUEUE(f->fs.iq) |
 459                             F_T5_OPT_2_VALID |
 460                             F_RX_CHANNEL |
 461                             V_SACK_EN(f->fs.swapmac) |
 462                             V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
 463                                          (f->fs.dirsteer << 1)) |
 464                             V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
 465 }
 466
 467 /**
 468  * Build a ACT_OPEN_REQ message for setting IPv4 hash filter.
 469  */
 470 static void mk_act_open_req(struct filter_entry *f, struct rte_mbuf *mbuf,
 471                             unsigned int qid_filterid, struct adapter *adap)
 472 {
 473         struct cpl_t6_act_open_req *req = NULL;
 474
 475         switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
 476         case CHELSIO_T6:
 477                 req = rte_pktmbuf_mtod(mbuf, struct cpl_t6_act_open_req *);
 478
 479                 INIT_TP_WR(req, 0);
 480                 break;
 481         default:
 482                 dev_err(adap, "%s: unsupported chip type!\n", __func__);
 483                 return;
 484         }
 485
 486         OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
 487                                                     qid_filterid));
 488         req->local_port = cpu_to_be16(f->fs.val.lport);
 489         req->peer_port = cpu_to_be16(f->fs.val.fport);
 490         req->local_ip = f->fs.val.lip[0] | f->fs.val.lip[1] << 8 |
 491                         f->fs.val.lip[2] << 16 | f->fs.val.lip[3] << 24;
 492         req->peer_ip = f->fs.val.fip[0] | f->fs.val.fip[1] << 8 |
 493                         f->fs.val.fip[2] << 16 | f->fs.val.fip[3] << 24;
 494         req->opt0 = cpu_to_be64(V_NAGLE(f->fs.newvlan == VLAN_REMOVE ||
 495                                         f->fs.newvlan == VLAN_REWRITE) |
 496                                 V_DELACK(f->fs.hitcnts) |
 497                                 V_L2T_IDX(f->l2t ? f->l2t->idx : 0) |
 498                                 V_SMAC_SEL((cxgbe_port_viid(f->dev) & 0x7F)
 499                                            << 1) |
 500                                 V_TX_CHAN(f->fs.eport) |
 501                                 V_ULP_MODE(ULP_MODE_NONE) |
 502                                 F_TCAM_BYPASS | F_NON_OFFLOAD);
 503         req->params = cpu_to_be64(V_FILTER_TUPLE(hash_filter_ntuple(f)));
 504         req->opt2 = cpu_to_be32(F_RSS_QUEUE_VALID |
 505                             V_RSS_QUEUE(f->fs.iq) |
 506                             F_T5_OPT_2_VALID |
 507                             F_RX_CHANNEL |
 508                             V_SACK_EN(f->fs.swapmac) |
 509                             V_CONG_CNTRL((f->fs.action == FILTER_DROP) |
 510                                          (f->fs.dirsteer << 1)) |
 511                             V_CCTRL_ECN(f->fs.action == FILTER_SWITCH));
 512 }
 513
 514 /**
 515  * Set the specified hash filter.
 516  */
 517 static int cxgbe_set_hash_filter(struct rte_eth_dev *dev,
 518                                  struct ch_filter_specification *fs,
 519                                  struct filter_ctx *ctx)
 520 {
 521         struct port_info *pi = ethdev2pinfo(dev);
 522         struct adapter *adapter = pi->adapter;
 523         struct tid_info *t = &adapter->tids;
 524         struct filter_entry *f;
 525         struct rte_mbuf *mbuf;
 526         struct sge_ctrl_txq *ctrlq;
 527         unsigned int iq;
 528         int atid, size;
 529         int ret = 0;
 530
 531         ret = cxgbe_validate_filter(adapter, fs);
 532         if (ret)
 533                 return ret;
 534
 535         iq = get_filter_steerq(dev, fs);
 536
 537         ctrlq = &adapter->sge.ctrlq[pi->port_id];
 538
 539         f = t4_os_alloc(sizeof(*f));
 540         if (!f)
 541                 goto out_err;
 542
 543         f->fs = *fs;
 544         f->ctx = ctx;
 545         f->dev = dev;
 546         f->fs.iq = iq;
 547
 548         /*
 549          * If the new filter requires loopback Destination MAC and/or VLAN
 550          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
 551          * the filter.
 552          */
 553         if (f->fs.newvlan == VLAN_INSERT ||
 554             f->fs.newvlan == VLAN_REWRITE) {
 555                 /* allocate L2T entry for new filter */
 556                 f->l2t = cxgbe_l2t_alloc_switching(dev, f->fs.vlan,
 557                                                    f->fs.eport, f->fs.dmac);
 558                 if (!f->l2t) {
 559                         ret = -ENOMEM;
 560                         goto out_err;
 561                 }
 562         }
 563
 564         atid = cxgbe_alloc_atid(t, f);
 565         if (atid < 0)
 566                 goto out_err;
 567
 568         if (f->fs.type) {
 569                 /* IPv6 hash filter */
 570                 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
 571                 if (!f->clipt)
 572                         goto free_atid;
 573
 574                 size = sizeof(struct cpl_t6_act_open_req6);
 575                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 576                 if (!mbuf) {
 577                         ret = -ENOMEM;
 578                         goto free_clip;
 579                 }
 580
 581                 mbuf->data_len = size;
 582                 mbuf->pkt_len = mbuf->data_len;
 583
 584                 mk_act_open_req6(f, mbuf,
 585                                  ((adapter->sge.fw_evtq.abs_id << 14) | atid),
 586                                  adapter);
 587         } else {
 588                 /* IPv4 hash filter */
 589                 size = sizeof(struct cpl_t6_act_open_req);
 590                 mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 591                 if (!mbuf) {
 592                         ret = -ENOMEM;
 593                         goto free_atid;
 594                 }
 595
 596                 mbuf->data_len = size;
 597                 mbuf->pkt_len = mbuf->data_len;
 598
 599                 mk_act_open_req(f, mbuf,
 600                                 ((adapter->sge.fw_evtq.abs_id << 14) | atid),
 601                                 adapter);
 602         }
 603
 604         f->pending = 1;
 605         t4_mgmt_tx(ctrlq, mbuf);
 606         return 0;
 607
 608 free_clip:
 609         cxgbe_clip_release(f->dev, f->clipt);
 610 free_atid:
 611         cxgbe_free_atid(t, atid);
 612
 613 out_err:
 614         t4_os_free(f);
 615         return ret;
 616 }
 617
 618 /**
 619  * Clear a filter and release any of its resources that we own.  This also
 620  * clears the filter's "pending" status.
 621  */
 622 static void clear_filter(struct filter_entry *f)
 623 {
 624         if (f->clipt)
 625                 cxgbe_clip_release(f->dev, f->clipt);
 626
 627         /*
 628          * The zeroing of the filter rule below clears the filter valid,
 629          * pending, locked flags etc. so it's all we need for
 630          * this operation.
 631          */
 632         memset(f, 0, sizeof(*f));
 633 }
 634
 635 /**
 636  * t4_mk_filtdelwr - create a delete filter WR
 637  * @adap: adapter context
 638  * @ftid: the filter ID
 639  * @wr: the filter work request to populate
 640  * @qid: ingress queue to receive the delete notification
 641  *
 642  * Creates a filter work request to delete the supplied filter.  If @qid is
 643  * negative the delete notification is suppressed.
 644  */
 645 static void t4_mk_filtdelwr(struct adapter *adap, unsigned int ftid,
 646                             struct fw_filter2_wr *wr, int qid)
 647 {
 648         memset(wr, 0, sizeof(*wr));
 649         if (adap->params.filter2_wr_support)
 650                 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
 651         else
 652                 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
 653         wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
 654         wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
 655                                     V_FW_FILTER_WR_NOREPLY(qid < 0));
 656         wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
 657         if (qid >= 0)
 658                 wr->rx_chan_rx_rpl_iq =
 659                                 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
 660 }
 661
 662 /**
 663  * Create FW work request to delete the filter at a specified index
 664  */
 665 static int del_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
 666 {
 667         struct adapter *adapter = ethdev2adap(dev);
 668         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
 669         struct rte_mbuf *mbuf;
 670         struct fw_filter2_wr *fwr;
 671         struct sge_ctrl_txq *ctrlq;
 672         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 673
 674         ctrlq = &adapter->sge.ctrlq[port_id];
 675         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 676         if (!mbuf)
 677                 return -ENOMEM;
 678
 679         mbuf->data_len = sizeof(*fwr);
 680         mbuf->pkt_len = mbuf->data_len;
 681
 682         fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
 683         t4_mk_filtdelwr(adapter, f->tid, fwr, adapter->sge.fw_evtq.abs_id);
 684
 685         /*
 686          * Mark the filter as "pending" and ship off the Filter Work Request.
 687          * When we get the Work Request Reply we'll clear the pending status.
 688          */
 689         f->pending = 1;
 690         t4_mgmt_tx(ctrlq, mbuf);
 691         return 0;
 692 }
 693
 694 static int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx)
 695 {
 696         struct adapter *adapter = ethdev2adap(dev);
 697         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
 698         struct rte_mbuf *mbuf;
 699         struct fw_filter2_wr *fwr;
 700         struct sge_ctrl_txq *ctrlq;
 701         unsigned int port_id = ethdev2pinfo(dev)->port_id;
 702         int ret;
 703
 704         /*
 705          * If the new filter requires loopback Destination MAC and/or VLAN
 706          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
 707          * the filter.
 708          */
 709         if (f->fs.newvlan) {
 710                 /* allocate L2T entry for new filter */
 711                 f->l2t = cxgbe_l2t_alloc_switching(f->dev, f->fs.vlan,
 712                                                    f->fs.eport, f->fs.dmac);
 713                 if (!f->l2t)
 714                         return -ENOMEM;
 715         }
 716
 717         ctrlq = &adapter->sge.ctrlq[port_id];
 718         mbuf = rte_pktmbuf_alloc(ctrlq->mb_pool);
 719         if (!mbuf) {
 720                 ret = -ENOMEM;
 721                 goto out;
 722         }
 723
 724         mbuf->data_len = sizeof(*fwr);
 725         mbuf->pkt_len = mbuf->data_len;
 726
 727         fwr = rte_pktmbuf_mtod(mbuf, struct fw_filter2_wr *);
 728         memset(fwr, 0, sizeof(*fwr));
 729
 730         /*
 731          * Construct the work request to set the filter.
 732          */
 733         if (adapter->params.filter2_wr_support)
 734                 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER2_WR));
 735         else
 736                 fwr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
 737         fwr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*fwr) / 16));
 738         fwr->tid_to_iq =
 739                 cpu_to_be32(V_FW_FILTER_WR_TID(f->tid) |
 740                             V_FW_FILTER_WR_RQTYPE(f->fs.type) |
 741                             V_FW_FILTER_WR_NOREPLY(0) |
 742                             V_FW_FILTER_WR_IQ(f->fs.iq));
 743         fwr->del_filter_to_l2tix =
 744                 cpu_to_be32(V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
 745                             V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
 746                             V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
 747                             V_FW_FILTER_WR_INSVLAN
 748                                 (f->fs.newvlan == VLAN_INSERT ||
 749                                  f->fs.newvlan == VLAN_REWRITE) |
 750                             V_FW_FILTER_WR_RMVLAN
 751                                 (f->fs.newvlan == VLAN_REMOVE ||
 752                                  f->fs.newvlan == VLAN_REWRITE) |
 753                             V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
 754                             V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
 755                             V_FW_FILTER_WR_PRIO(f->fs.prio) |
 756                             V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
 757         fwr->ethtype = cpu_to_be16(f->fs.val.ethtype);
 758         fwr->ethtypem = cpu_to_be16(f->fs.mask.ethtype);
 759         fwr->smac_sel = 0;
 760         fwr->rx_chan_rx_rpl_iq =
 761                 cpu_to_be16(V_FW_FILTER_WR_RX_CHAN(0) |
 762                             V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id
 763                                                      ));
 764         fwr->maci_to_matchtypem =
 765                 cpu_to_be32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
 766                             V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
 767                             V_FW_FILTER_WR_PORT(f->fs.val.iport) |
 768                             V_FW_FILTER_WR_PORTM(f->fs.mask.iport));
 769         fwr->ptcl = f->fs.val.proto;
 770         fwr->ptclm = f->fs.mask.proto;
 771         rte_memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
 772         rte_memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
 773         rte_memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
 774         rte_memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
 775         fwr->lp = cpu_to_be16(f->fs.val.lport);
 776         fwr->lpm = cpu_to_be16(f->fs.mask.lport);
 777         fwr->fp = cpu_to_be16(f->fs.val.fport);
 778         fwr->fpm = cpu_to_be16(f->fs.mask.fport);
 779
 780         if (adapter->params.filter2_wr_support) {
 781                 fwr->filter_type_swapmac =
 782                          V_FW_FILTER2_WR_SWAPMAC(f->fs.swapmac);
 783                 fwr->natmode_to_ulp_type =
 784                         V_FW_FILTER2_WR_ULP_TYPE(f->fs.nat_mode ?
 785                                                  ULP_MODE_TCPDDP :
 786                                                  ULP_MODE_NONE) |
 787                         V_FW_FILTER2_WR_NATMODE(f->fs.nat_mode);
 788                 memcpy(fwr->newlip, f->fs.nat_lip, sizeof(fwr->newlip));
 789                 memcpy(fwr->newfip, f->fs.nat_fip, sizeof(fwr->newfip));
 790                 fwr->newlport = cpu_to_be16(f->fs.nat_lport);
 791                 fwr->newfport = cpu_to_be16(f->fs.nat_fport);
 792         }
 793
 794         /*
 795          * Mark the filter as "pending" and ship off the Filter Work Request.
 796          * When we get the Work Request Reply we'll clear the pending status.
 797          */
 798         f->pending = 1;
 799         t4_mgmt_tx(ctrlq, mbuf);
 800         return 0;
 801
 802 out:
 803         return ret;
 804 }
 805
 806 /**
 807  * Set the corresponding entry in the bitmap. 4 slots are
 808  * marked for IPv6, whereas only 1 slot is marked for IPv4.
 809  */
 810 static int cxgbe_set_ftid(struct tid_info *t, int fidx, int family)
 811 {
 812         t4_os_lock(&t->ftid_lock);
 813         if (rte_bitmap_get(t->ftid_bmap, fidx)) {
 814                 t4_os_unlock(&t->ftid_lock);
 815                 return -EBUSY;
 816         }
 817
 818         if (family == FILTER_TYPE_IPV4) {
 819                 rte_bitmap_set(t->ftid_bmap, fidx);
 820         } else {
 821                 rte_bitmap_set(t->ftid_bmap, fidx);
 822                 rte_bitmap_set(t->ftid_bmap, fidx + 1);
 823                 rte_bitmap_set(t->ftid_bmap, fidx + 2);
 824                 rte_bitmap_set(t->ftid_bmap, fidx + 3);
 825         }
 826         t4_os_unlock(&t->ftid_lock);
 827         return 0;
 828 }
 829
 830 /**
 831  * Clear the corresponding entry in the bitmap. 4 slots are
 832  * cleared for IPv6, whereas only 1 slot is cleared for IPv4.
 833  */
 834 static void cxgbe_clear_ftid(struct tid_info *t, int fidx, int family)
 835 {
 836         t4_os_lock(&t->ftid_lock);
 837         if (family == FILTER_TYPE_IPV4) {
 838                 rte_bitmap_clear(t->ftid_bmap, fidx);
 839         } else {
 840                 rte_bitmap_clear(t->ftid_bmap, fidx);
 841                 rte_bitmap_clear(t->ftid_bmap, fidx + 1);
 842                 rte_bitmap_clear(t->ftid_bmap, fidx + 2);
 843                 rte_bitmap_clear(t->ftid_bmap, fidx + 3);
 844         }
 845         t4_os_unlock(&t->ftid_lock);
 846 }
 847
 848 /**
 849  * Check a delete filter request for validity and send it to the hardware.
 850  * Return 0 on success, an error number otherwise.  We attach any provided
 851  * filter operation context to the internal filter specification in order to
 852  * facilitate signaling completion of the operation.
 853  */
 854 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 855                      struct ch_filter_specification *fs,
 856                      struct filter_ctx *ctx)
 857 {
 858         struct port_info *pi = dev->data->dev_private;
 859         struct adapter *adapter = pi->adapter;
 860         struct filter_entry *f;
 861         unsigned int chip_ver;
 862         int ret;
 863
 864         if (is_hashfilter(adapter) && fs->cap)
 865                 return cxgbe_del_hash_filter(dev, filter_id, ctx);
 866
 867         if (filter_id >= adapter->tids.nftids)
 868                 return -ERANGE;
 869
 870         chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
 871
 872         ret = cxgbe_is_filter_set(&adapter->tids, filter_id, fs->type);
 873         if (!ret) {
 874                 dev_warn(adap, "%s: could not find filter entry: %u\n",
 875                          __func__, filter_id);
 876                 return -EINVAL;
 877         }
 878
 879         /*
 880          * Ensure filter id is aligned on the 2 slot boundary for T6,
 881          * and 4 slot boundary for cards below T6.
 882          */
 883         if (fs->type) {
 884                 if (chip_ver < CHELSIO_T6)
 885                         filter_id &= ~(0x3);
 886                 else
 887                         filter_id &= ~(0x1);
 888         }
 889
 890         f = &adapter->tids.ftid_tab[filter_id];
 891         ret = writable_filter(f);
 892         if (ret)
 893                 return ret;
 894
 895         if (f->valid) {
 896                 f->ctx = ctx;
 897                 cxgbe_clear_ftid(&adapter->tids,
 898                                  f->tid - adapter->tids.ftid_base,
 899                                  f->fs.type ? FILTER_TYPE_IPV6 :
 900                                               FILTER_TYPE_IPV4);
 901                 return del_filter_wr(dev, filter_id);
 902         }
 903
 904         /*
 905          * If the caller has passed in a Completion Context then we need to
 906          * mark it as a successful completion so they don't stall waiting
 907          * for it.
 908          */
 909         if (ctx) {
 910                 ctx->result = 0;
 911                 t4_complete(&ctx->completion);
 912         }
 913
 914         return 0;
 915 }
 916
 917 /**
 918  * Check a Chelsio Filter Request for validity, convert it into our internal
 919  * format and send it to the hardware.  Return 0 on success, an error number
 920  * otherwise.  We attach any provided filter operation context to the internal
 921  * filter specification in order to facilitate signaling completion of the
 922  * operation.
 923  */
 924 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
 925                      struct ch_filter_specification *fs,
 926                      struct filter_ctx *ctx)
 927 {
 928         struct port_info *pi = ethdev2pinfo(dev);
 929         struct adapter *adapter = pi->adapter;
 930         unsigned int fidx, iq, fid_bit = 0;
 931         struct filter_entry *f;
 932         unsigned int chip_ver;
 933         uint8_t bitoff[16] = {0};
 934         int ret;
 935
 936         if (is_hashfilter(adapter) && fs->cap)
 937                 return cxgbe_set_hash_filter(dev, fs, ctx);
 938
 939         if (filter_id >= adapter->tids.nftids)
 940                 return -ERANGE;
 941
 942         chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip);
 943
 944         ret = cxgbe_validate_filter(adapter, fs);
 945         if (ret)
 946                 return ret;
 947
 948         /*
 949          * Ensure filter id is aligned on the 4 slot boundary for IPv6
 950          * maskfull filters.
 951          */
 952         if (fs->type)
 953                 filter_id &= ~(0x3);
 954
 955         ret = cxgbe_is_filter_set(&adapter->tids, filter_id, fs->type);
 956         if (ret)
 957                 return -EBUSY;
 958
 959         iq = get_filter_steerq(dev, fs);
 960
 961         /*
 962          * IPv6 filters occupy four slots and must be aligned on four-slot
 963          * boundaries for T5. On T6, IPv6 filters occupy two-slots and
 964          * must be aligned on two-slot boundaries.
 965          *
 966          * IPv4 filters only occupy a single slot and have no alignment
 967          * requirements but writing a new IPv4 filter into the middle
 968          * of an existing IPv6 filter requires clearing the old IPv6
 969          * filter.
 970          */
 971         if (fs->type == FILTER_TYPE_IPV4) { /* IPv4 */
 972                 /*
 973                  * For T6, If our IPv4 filter isn't being written to a
 974                  * multiple of two filter index and there's an IPv6
 975                  * filter at the multiple of 2 base slot, then we need
 976                  * to delete that IPv6 filter ...
 977                  * For adapters below T6, IPv6 filter occupies 4 entries.
 978                  */
 979                 if (chip_ver < CHELSIO_T6)
 980                         fidx = filter_id & ~0x3;
 981                 else
 982                         fidx = filter_id & ~0x1;
 983
 984                 if (fidx != filter_id && adapter->tids.ftid_tab[fidx].fs.type) {
 985                         f = &adapter->tids.ftid_tab[fidx];
 986                         if (f->valid)
 987                                 return -EBUSY;
 988                 }
 989         } else { /* IPv6 */
 990                 unsigned int max_filter_id;
 991
 992                 if (chip_ver < CHELSIO_T6) {
 993                         /*
 994                          * Ensure that the IPv6 filter is aligned on a
 995                          * multiple of 4 boundary.
 996                          */
 997                         if (filter_id & 0x3)
 998                                 return -EINVAL;
 999
1000                         max_filter_id = filter_id + 4;
1001                 } else {
1002                         /*
1003                          * For T6, CLIP being enabled, IPv6 filter would occupy
1004                          * 2 entries.
1005                          */
1006                         if (filter_id & 0x1)
1007                                 return -EINVAL;
1008
1009                         max_filter_id = filter_id + 2;
1010                 }
1011
1012                 /*
1013                  * Check all except the base overlapping IPv4 filter
1014                  * slots.
1015                  */
1016                 for (fidx = filter_id + 1; fidx < max_filter_id; fidx++) {
1017                         f = &adapter->tids.ftid_tab[fidx];
1018                         if (f->valid)
1019                                 return -EBUSY;
1020                 }
1021         }
1022
1023         /*
1024          * Check to make sure that provided filter index is not
1025          * already in use by someone else
1026          */
1027         f = &adapter->tids.ftid_tab[filter_id];
1028         if (f->valid)
1029                 return -EBUSY;
1030
1031         fidx = adapter->tids.ftid_base + filter_id;
1032         fid_bit = filter_id;
1033         ret = cxgbe_set_ftid(&adapter->tids, fid_bit,
1034                              fs->type ? FILTER_TYPE_IPV6 : FILTER_TYPE_IPV4);
1035         if (ret)
1036                 return ret;
1037
1038         /*
1039          * Check to make sure the filter requested is writable ...
1040          */
1041         ret = writable_filter(f);
1042         if (ret) {
1043                 /* Clear the bits we have set above */
1044                 cxgbe_clear_ftid(&adapter->tids, fid_bit,
1045                                  fs->type ? FILTER_TYPE_IPV6 :
1046                                             FILTER_TYPE_IPV4);
1047                 return ret;
1048         }
1049
1050         /*
1051          * Allocate a clip table entry only if we have non-zero IPv6 address
1052          */
1053         if (chip_ver > CHELSIO_T5 && fs->type &&
1054             memcmp(fs->val.lip, bitoff, sizeof(bitoff))) {
1055                 f->clipt = cxgbe_clip_alloc(f->dev, (u32 *)&f->fs.val.lip);
1056                 if (!f->clipt)
1057                         goto free_tid;
1058         }
1059
1060         /*
1061          * Convert the filter specification into our internal format.
1062          * We copy the PF/VF specification into the Outer VLAN field
1063          * here so the rest of the code -- including the interface to
1064          * the firmware -- doesn't have to constantly do these checks.
1065          */
1066         f->fs = *fs;
1067         f->fs.iq = iq;
1068         f->dev = dev;
1069
1070         /*
1071          * Attempt to set the filter.  If we don't succeed, we clear
1072          * it and return the failure.
1073          */
1074         f->ctx = ctx;
1075         f->tid = fidx; /* Save the actual tid */
1076         ret = set_filter_wr(dev, filter_id);
1077         if (ret) {
1078                 fid_bit = f->tid - adapter->tids.ftid_base;
1079                 goto free_tid;
1080         }
1081
1082         return ret;
1083
1084 free_tid:
1085         cxgbe_clear_ftid(&adapter->tids, fid_bit,
1086                          fs->type ? FILTER_TYPE_IPV6 :
1087                                     FILTER_TYPE_IPV4);
1088         clear_filter(f);
1089         return ret;
1090 }
1091
1092 /**
1093  * Handle a Hash filter write reply.
1094  */
1095 void cxgbe_hash_filter_rpl(struct adapter *adap,
1096                            const struct cpl_act_open_rpl *rpl)
1097 {
1098         struct tid_info *t = &adap->tids;
1099         struct filter_entry *f;
1100         struct filter_ctx *ctx = NULL;
1101         unsigned int tid = GET_TID(rpl);
1102         unsigned int ftid = G_TID_TID(G_AOPEN_ATID
1103                                       (be32_to_cpu(rpl->atid_status)));
1104         unsigned int status  = G_AOPEN_STATUS(be32_to_cpu(rpl->atid_status));
1105
1106         f = lookup_atid(t, ftid);
1107         if (!f) {
1108                 dev_warn(adap, "%s: could not find filter entry: %d\n",
1109                          __func__, ftid);
1110                 return;
1111         }
1112
1113         ctx = f->ctx;
1114         f->ctx = NULL;
1115
1116         switch (status) {
1117         case CPL_ERR_NONE: {
1118                 f->tid = tid;
1119                 f->pending = 0;  /* asynchronous setup completed */
1120                 f->valid = 1;
1121
1122                 cxgbe_insert_tid(t, f, f->tid, 0);
1123                 cxgbe_free_atid(t, ftid);
1124                 if (ctx) {
1125                         ctx->tid = f->tid;
1126                         ctx->result = 0;
1127                 }
1128                 if (f->fs.hitcnts)
1129                         set_tcb_field(adap, tid,
1130                                       W_TCB_TIMESTAMP,
1131                                       V_TCB_TIMESTAMP(M_TCB_TIMESTAMP) |
1132                                       V_TCB_T_RTT_TS_RECENT_AGE
1133                                               (M_TCB_T_RTT_TS_RECENT_AGE),
1134                                       V_TCB_TIMESTAMP(0ULL) |
1135                                       V_TCB_T_RTT_TS_RECENT_AGE(0ULL),
1136                                       1);
1137                 if (f->fs.newvlan == VLAN_INSERT ||
1138                     f->fs.newvlan == VLAN_REWRITE)
1139                         set_tcb_tflag(adap, tid, S_TF_CCTRL_RFR, 1, 1);
1140                 break;
1141         }
1142         default:
1143                 dev_warn(adap, "%s: filter creation failed with status = %u\n",
1144                          __func__, status);
1145
1146                 if (ctx) {
1147                         if (status == CPL_ERR_TCAM_FULL)
1148                                 ctx->result = -EAGAIN;
1149                         else
1150                                 ctx->result = -EINVAL;
1151                 }
1152
1153                 cxgbe_free_atid(t, ftid);
1154                 t4_os_free(f);
1155         }
1156
1157         if (ctx)
1158                 t4_complete(&ctx->completion);
1159 }
1160
1161 /**
1162  * Handle a LE-TCAM filter write/deletion reply.
1163  */
1164 void cxgbe_filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
1165 {
1166         struct filter_entry *f = NULL;
1167         unsigned int tid = GET_TID(rpl);
1168         int idx, max_fidx = adap->tids.nftids;
1169
1170         /* Get the corresponding filter entry for this tid */
1171         if (adap->tids.ftid_tab) {
1172                 /* Check this in normal filter region */
1173                 idx = tid - adap->tids.ftid_base;
1174                 if (idx >= max_fidx)
1175                         return;
1176
1177                 f = &adap->tids.ftid_tab[idx];
1178                 if (f->tid != tid)
1179                         return;
1180         }
1181
1182         /* We found the filter entry for this tid */
1183         if (f) {
1184                 unsigned int ret = G_COOKIE(rpl->cookie);
1185                 struct filter_ctx *ctx;
1186
1187                 /*
1188                  * Pull off any filter operation context attached to the
1189                  * filter.
1190                  */
1191                 ctx = f->ctx;
1192                 f->ctx = NULL;
1193
1194                 if (ret == FW_FILTER_WR_FLT_ADDED) {
1195                         f->pending = 0;  /* asynchronous setup completed */
1196                         f->valid = 1;
1197                         if (ctx) {
1198                                 ctx->tid = f->tid;
1199                                 ctx->result = 0;
1200                         }
1201                 } else if (ret == FW_FILTER_WR_FLT_DELETED) {
1202                         /*
1203                          * Clear the filter when we get confirmation from the
1204                          * hardware that the filter has been deleted.
1205                          */
1206                         clear_filter(f);
1207                         if (ctx)
1208                                 ctx->result = 0;
1209                 } else {
1210                         /*
1211                          * Something went wrong.  Issue a warning about the
1212                          * problem and clear everything out.
1213                          */
1214                         dev_warn(adap, "filter %u setup failed with error %u\n",
1215                                  idx, ret);
1216                         clear_filter(f);
1217                         if (ctx)
1218                                 ctx->result = -EINVAL;
1219                 }
1220
1221                 if (ctx)
1222                         t4_complete(&ctx->completion);
1223         }
1224 }
1225
1226 /*
1227  * Retrieve the packet count for the specified filter.
1228  */
1229 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
1230                            u64 *c, int hash, bool get_byte)
1231 {
1232         struct filter_entry *f;
1233         unsigned int tcb_base, tcbaddr;
1234         int ret;
1235
1236         tcb_base = t4_read_reg(adapter, A_TP_CMM_TCB_BASE);
1237         if (is_hashfilter(adapter) && hash) {
1238                 if (fidx < adapter->tids.ntids) {
1239                         f = adapter->tids.tid_tab[fidx];
1240                         if (!f)
1241                                 return -EINVAL;
1242
1243                         if (is_t5(adapter->params.chip)) {
1244                                 *c = 0;
1245                                 return 0;
1246                         }
1247                         tcbaddr = tcb_base + (fidx * TCB_SIZE);
1248                         goto get_count;
1249                 } else {
1250                         return -ERANGE;
1251                 }
1252         } else {
1253                 if (fidx >= adapter->tids.nftids)
1254                         return -ERANGE;
1255
1256                 f = &adapter->tids.ftid_tab[fidx];
1257                 if (!f->valid)
1258                         return -EINVAL;
1259
1260                 tcbaddr = tcb_base + f->tid * TCB_SIZE;
1261         }
1262
1263         f = &adapter->tids.ftid_tab[fidx];
1264         if (!f->valid)
1265                 return -EINVAL;
1266
1267 get_count:
1268         if (is_t5(adapter->params.chip) || is_t6(adapter->params.chip)) {
1269                 /*
1270                  * For T5, the Filter Packet Hit Count is maintained as a
1271                  * 32-bit Big Endian value in the TCB field {timestamp}.
1272                  * Similar to the craziness above, instead of the filter hit
1273                  * count showing up at offset 20 ((W_TCB_TIMESTAMP == 5) *
1274                  * sizeof(u32)), it actually shows up at offset 24.  Whacky.
1275                  */
1276                 if (get_byte) {
1277                         unsigned int word_offset = 4;
1278                         __be64 be64_byte_count;
1279
1280                         t4_os_lock(&adapter->win0_lock);
1281                         ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1282                                            tcbaddr +
1283                                            (word_offset * sizeof(__be32)),
1284                                            sizeof(be64_byte_count),
1285                                            &be64_byte_count,
1286                                            T4_MEMORY_READ);
1287                         t4_os_unlock(&adapter->win0_lock);
1288                         if (ret < 0)
1289                                 return ret;
1290                         *c = be64_to_cpu(be64_byte_count);
1291                 } else {
1292                         unsigned int word_offset = 6;
1293                         __be32 be32_count;
1294
1295                         t4_os_lock(&adapter->win0_lock);
1296                         ret = t4_memory_rw(adapter, MEMWIN_NIC, MEM_EDC0,
1297                                            tcbaddr +
1298                                            (word_offset * sizeof(__be32)),
1299                                            sizeof(be32_count), &be32_count,
1300                                            T4_MEMORY_READ);
1301                         t4_os_unlock(&adapter->win0_lock);
1302                         if (ret < 0)
1303                                 return ret;
1304                         *c = (u64)be32_to_cpu(be32_count);
1305                 }
1306         }
1307         return 0;
1308 }
1309
1310 /*
1311  * Clear the packet count for the specified filter.
1312  */
1313 int cxgbe_clear_filter_count(struct adapter *adapter, unsigned int fidx,
1314                              int hash, bool clear_byte)
1315 {
1316         u64 tcb_mask = 0, tcb_val = 0;
1317         struct filter_entry *f = NULL;
1318         u16 tcb_word = 0;
1319
1320         if (is_hashfilter(adapter) && hash) {
1321                 if (fidx >= adapter->tids.ntids)
1322                         return -ERANGE;
1323
1324                 /* No hitcounts supported for T5 hashfilters */
1325                 if (is_t5(adapter->params.chip))
1326                         return 0;
1327
1328                 f = adapter->tids.tid_tab[fidx];
1329         } else {
1330                 if (fidx >= adapter->tids.nftids)
1331                         return -ERANGE;
1332
1333                 f = &adapter->tids.ftid_tab[fidx];
1334         }
1335
1336         if (!f || !f->valid)
1337                 return -EINVAL;
1338
1339         tcb_word = W_TCB_TIMESTAMP;
1340         tcb_mask = V_TCB_TIMESTAMP(M_TCB_TIMESTAMP);
1341         tcb_val = V_TCB_TIMESTAMP(0ULL);
1342
1343         set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1344
1345         if (clear_byte) {
1346                 tcb_word = W_TCB_T_RTT_TS_RECENT_AGE;
1347                 tcb_mask =
1348                         V_TCB_T_RTT_TS_RECENT_AGE(M_TCB_T_RTT_TS_RECENT_AGE) |
1349                         V_TCB_T_RTSEQ_RECENT(M_TCB_T_RTSEQ_RECENT);
1350                 tcb_val = V_TCB_T_RTT_TS_RECENT_AGE(0ULL) |
1351                           V_TCB_T_RTSEQ_RECENT(0ULL);
1352
1353                 set_tcb_field(adapter, f->tid, tcb_word, tcb_mask, tcb_val, 1);
1354         }
1355
1356         return 0;
1357 }
1358
1359 /**
1360  * Handle a Hash filter delete reply.
1361  */
1362 void cxgbe_hash_del_filter_rpl(struct adapter *adap,
1363                                const struct cpl_abort_rpl_rss *rpl)
1364 {
1365         struct tid_info *t = &adap->tids;
1366         struct filter_entry *f;
1367         struct filter_ctx *ctx = NULL;
1368         unsigned int tid = GET_TID(rpl);
1369
1370         f = lookup_tid(t, tid);
1371         if (!f) {
1372                 dev_warn(adap, "%s: could not find filter entry: %u\n",
1373                          __func__, tid);
1374                 return;
1375         }
1376
1377         ctx = f->ctx;
1378         f->ctx = NULL;
1379
1380         f->valid = 0;
1381
1382         if (f->clipt)
1383                 cxgbe_clip_release(f->dev, f->clipt);
1384
1385         cxgbe_remove_tid(t, 0, tid, 0);
1386         t4_os_free(f);
1387
1388         if (ctx) {
1389                 ctx->result = 0;
1390                 t4_complete(&ctx->completion);
1391         }
1392 }