1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Chelsio Communications.
6 #ifndef _CXGBE_FILTER_H_
7 #define _CXGBE_FILTER_H_
11 * Defined bit width of user definable filter tuples
13 #define ETHTYPE_BITWIDTH 16
14 #define FRAG_BITWIDTH 1
15 #define MACIDX_BITWIDTH 9
16 #define FCOE_BITWIDTH 1
17 #define IPORT_BITWIDTH 3
18 #define MATCHTYPE_BITWIDTH 3
19 #define PROTO_BITWIDTH 8
20 #define TOS_BITWIDTH 8
23 #define IVLAN_BITWIDTH 16
24 #define OVLAN_BITWIDTH 16
27 * Filter matching rules. These consist of a set of ingress packet field
28 * (value, mask) tuples. The associated ingress packet field matches the
29 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
30 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
31 * matches an ingress packet when all of the individual individual field
32 * matching rules are true.
34 * Partial field masks are always valid, however, while it may be easy to
35 * understand their meanings for some fields (e.g. IP address to match a
36 * subnet), for others making sensible partial masks is less intuitive (e.g.
39 struct ch_filter_tuple {
41 * Compressed header matching field rules. The TP_VLAN_PRI_MAP
42 * register selects which of these fields will participate in the
43 * filter match rules -- up to a maximum of 36 bits. Because
44 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
47 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
48 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
49 uint32_t ivlan_vld:1; /* inner VLAN valid */
50 uint32_t ovlan_vld:1; /* outer VLAN valid */
51 uint32_t pfvf_vld:1; /* PF/VF valid */
52 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
53 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
54 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
55 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
56 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
57 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
58 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
59 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
60 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
61 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
64 * Uncompressed header matching field rules. These are always
65 * available for field rules.
67 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
68 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
69 uint16_t lport; /* local port */
70 uint16_t fport; /* foreign port */
72 /* reservations for future additions */
77 * Filter specification
79 struct ch_filter_specification {
80 /* Administrative fields for filter. */
81 uint32_t hitcnts:1; /* count filter hits in TCB */
82 uint32_t prio:1; /* filter has priority over active/server */
85 * Fundamental filter typing. This is the one element of filter
86 * matching that doesn't exist as a (value, mask) tuple.
88 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
89 uint32_t cap:1; /* 0 => LE-TCAM, 1 => Hash */
92 * Packet dispatch information. Ingress packets which match the
93 * filter rules will be dropped, passed to the host or switched back
94 * out as egress packets.
96 uint32_t action:2; /* drop, pass, switch */
98 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
99 uint32_t iq:10; /* ingress queue */
101 /* Filter rule value/mask pairs. */
102 struct ch_filter_tuple val;
103 struct ch_filter_tuple mask;
107 FILTER_PASS = 0, /* default */
112 FILTER_TYPE_IPV4 = 0,
116 struct t4_completion {
117 unsigned int done; /* completion done (0 - No, 1 - Yes) */
118 rte_spinlock_t lock; /* completion lock */
122 * Filter operation context to allow callers to wait for
123 * an asynchronous completion.
126 struct t4_completion completion; /* completion rendezvous */
127 int result; /* result of operation */
128 u32 tid; /* to store tid of hash filter */
132 * Host shadow copy of ingress filter entry. This is in host native format
133 * and doesn't match the ordering or bit order, etc. of the hardware or the
136 struct filter_entry {
138 * Administrative fields for filter.
140 u32 valid:1; /* filter allocated and valid */
141 u32 locked:1; /* filter is administratively locked */
142 u32 pending:1; /* filter action is pending FW reply */
143 struct filter_ctx *ctx; /* caller's completion hook */
144 struct rte_eth_dev *dev; /* Port's rte eth device */
145 void *private; /* For use by apps using filter_entry */
147 /* This will store the actual tid */
153 struct ch_filter_specification fs;
156 #define FILTER_ID_MAX (~0U)
162 * Find first clear bit in the bitmap.
164 static inline unsigned int cxgbe_find_first_zero_bit(struct rte_bitmap *bmap,
169 for (idx = 0; idx < size; idx++)
170 if (!rte_bitmap_get(bmap, idx))
177 * Find a free region of 'num' consecutive entries.
179 static inline unsigned int
180 cxgbe_bitmap_find_free_region(struct rte_bitmap *bmap, unsigned int size,
183 unsigned int idx, j, free = 0;
188 for (idx = 0; idx < size; idx += num) {
189 for (j = 0; j < num; j++) {
190 if (!rte_bitmap_get(bmap, idx + j)) {
198 /* Found the Region */
202 /* Reached the end and still no region found */
203 if ((idx + num) > size) {
212 bool is_filter_set(struct tid_info *, int fidx, int family);
213 void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl);
214 void clear_filter(struct filter_entry *f);
215 int set_filter_wr(struct rte_eth_dev *dev, unsigned int fidx);
216 int writable_filter(struct filter_entry *f);
217 int cxgbe_set_filter(struct rte_eth_dev *dev, unsigned int filter_id,
218 struct ch_filter_specification *fs,
219 struct filter_ctx *ctx);
220 int cxgbe_del_filter(struct rte_eth_dev *dev, unsigned int filter_id,
221 struct ch_filter_specification *fs,
222 struct filter_ctx *ctx);
223 int cxgbe_alloc_ftid(struct adapter *adap, unsigned int family);
224 int init_hash_filter(struct adapter *adap);
225 int validate_filter(struct adapter *adap, struct ch_filter_specification *fs);
226 int cxgbe_get_filter_count(struct adapter *adapter, unsigned int fidx,
227 u64 *c, bool get_byte);
228 #endif /* _CXGBE_FILTER_H_ */