1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Chelsio Communications.
6 #ifndef _CXGBE_FILTER_H_
7 #define _CXGBE_FILTER_H_
11 * Defined bit width of user definable filter tuples
13 #define ETHTYPE_BITWIDTH 16
14 #define FRAG_BITWIDTH 1
15 #define MACIDX_BITWIDTH 9
16 #define FCOE_BITWIDTH 1
17 #define IPORT_BITWIDTH 3
18 #define MATCHTYPE_BITWIDTH 3
19 #define PROTO_BITWIDTH 8
20 #define TOS_BITWIDTH 8
23 #define IVLAN_BITWIDTH 16
24 #define OVLAN_BITWIDTH 16
27 * Filter matching rules. These consist of a set of ingress packet field
28 * (value, mask) tuples. The associated ingress packet field matches the
29 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
30 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
31 * matches an ingress packet when all of the individual individual field
32 * matching rules are true.
34 * Partial field masks are always valid, however, while it may be easy to
35 * understand their meanings for some fields (e.g. IP address to match a
36 * subnet), for others making sensible partial masks is less intuitive (e.g.
39 struct ch_filter_tuple {
41 * Compressed header matching field rules. The TP_VLAN_PRI_MAP
42 * register selects which of these fields will participate in the
43 * filter match rules -- up to a maximum of 36 bits. Because
44 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
47 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
48 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
49 uint32_t ivlan_vld:1; /* inner VLAN valid */
50 uint32_t ovlan_vld:1; /* outer VLAN valid */
51 uint32_t pfvf_vld:1; /* PF/VF valid */
52 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
53 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
54 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
55 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
56 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
57 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
58 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
59 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
60 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
61 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
64 * Uncompressed header matching field rules. These are always
65 * available for field rules.
67 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
68 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
69 uint16_t lport; /* local port */
70 uint16_t fport; /* foreign port */
72 /* reservations for future additions */
77 * Filter specification
79 struct ch_filter_specification {
80 /* Filter rule value/mask pairs. */
81 struct ch_filter_tuple val;
82 struct ch_filter_tuple mask;
86 * Host shadow copy of ingress filter entry. This is in host native format
87 * and doesn't match the ordering or bit order, etc. of the hardware or the
94 struct ch_filter_specification fs;
97 #endif /* _CXGBE_FILTER_H_ */