1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Chelsio Communications.
5 #include "base/common.h"
6 #include "cxgbe_flow.h"
8 #define __CXGBE_FILL_FS(__v, __m, fs, elem, e) \
10 if ((fs)->mask.elem && ((fs)->val.elem != (__v))) \
11 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, \
12 NULL, "Redefined match item with" \
13 " different values found"); \
14 (fs)->val.elem = (__v); \
15 (fs)->mask.elem = (__m); \
18 #define __CXGBE_FILL_FS_MEMCPY(__v, __m, fs, elem) \
20 memcpy(&(fs)->val.elem, &(__v), sizeof(__v)); \
21 memcpy(&(fs)->mask.elem, &(__m), sizeof(__m)); \
24 #define CXGBE_FILL_FS(v, m, elem) \
25 __CXGBE_FILL_FS(v, m, fs, elem, e)
27 #define CXGBE_FILL_FS_MEMCPY(v, m, elem) \
28 __CXGBE_FILL_FS_MEMCPY(v, m, fs, elem)
31 cxgbe_validate_item(const struct rte_flow_item *i, struct rte_flow_error *e)
33 /* rte_flow specification does not allow it. */
34 if (!i->spec && (i->mask || i->last))
35 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
36 i, "last or mask given without spec");
38 * We don't support it.
39 * Although, we can support values in last as 0's or last == spec.
40 * But this will not provide user with any additional functionality
41 * and will only increase the complexity for us.
44 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
45 i, "last is not supported by chelsio pmd");
50 * Apart from the 4-tuple IPv4/IPv6 - TCP/UDP information,
51 * there's only 40-bits available to store match fields.
52 * So, to save space, optimize filter spec for some common
53 * known fields that hardware can parse against incoming
54 * packets automatically.
57 cxgbe_tweak_filter_spec(struct adapter *adap,
58 struct ch_filter_specification *fs)
60 /* Save 16-bit ethertype field space, by setting corresponding
61 * 1-bit flags in the filter spec for common known ethertypes.
62 * When hardware sees these flags, it automatically infers and
63 * matches incoming packets against the corresponding ethertype.
65 if (fs->mask.ethtype == 0xffff) {
66 switch (fs->val.ethtype) {
67 case RTE_ETHER_TYPE_IPV4:
68 if (adap->params.tp.ethertype_shift < 0) {
69 fs->type = FILTER_TYPE_IPV4;
74 case RTE_ETHER_TYPE_IPV6:
75 if (adap->params.tp.ethertype_shift < 0) {
76 fs->type = FILTER_TYPE_IPV6;
81 case RTE_ETHER_TYPE_VLAN:
82 if (adap->params.tp.ethertype_shift < 0 &&
83 adap->params.tp.vlan_shift >= 0) {
84 fs->val.ivlan_vld = 1;
85 fs->mask.ivlan_vld = 1;
90 case RTE_ETHER_TYPE_QINQ:
91 if (adap->params.tp.ethertype_shift < 0 &&
92 adap->params.tp.vnic_shift >= 0) {
93 fs->val.ovlan_vld = 1;
94 fs->mask.ovlan_vld = 1;
106 cxgbe_fill_filter_region(struct adapter *adap,
107 struct ch_filter_specification *fs)
109 struct tp_params *tp = &adap->params.tp;
110 u64 hash_filter_mask = tp->hash_filter_mask;
115 if (!is_hashfilter(adap))
119 uint8_t biton[16] = {0xff, 0xff, 0xff, 0xff,
120 0xff, 0xff, 0xff, 0xff,
121 0xff, 0xff, 0xff, 0xff,
122 0xff, 0xff, 0xff, 0xff};
123 uint8_t bitoff[16] = {0};
125 if (!memcmp(fs->val.lip, bitoff, sizeof(bitoff)) ||
126 !memcmp(fs->val.fip, bitoff, sizeof(bitoff)) ||
127 memcmp(fs->mask.lip, biton, sizeof(biton)) ||
128 memcmp(fs->mask.fip, biton, sizeof(biton)))
131 uint32_t biton = 0xffffffff;
132 uint32_t bitoff = 0x0U;
134 if (!memcmp(fs->val.lip, &bitoff, sizeof(bitoff)) ||
135 !memcmp(fs->val.fip, &bitoff, sizeof(bitoff)) ||
136 memcmp(fs->mask.lip, &biton, sizeof(biton)) ||
137 memcmp(fs->mask.fip, &biton, sizeof(biton)))
141 if (!fs->val.lport || fs->mask.lport != 0xffff)
143 if (!fs->val.fport || fs->mask.fport != 0xffff)
146 if (tp->protocol_shift >= 0)
147 ntuple_mask |= (u64)fs->mask.proto << tp->protocol_shift;
148 if (tp->ethertype_shift >= 0)
149 ntuple_mask |= (u64)fs->mask.ethtype << tp->ethertype_shift;
150 if (tp->port_shift >= 0)
151 ntuple_mask |= (u64)fs->mask.iport << tp->port_shift;
152 if (tp->macmatch_shift >= 0)
153 ntuple_mask |= (u64)fs->mask.macidx << tp->macmatch_shift;
154 if (tp->vlan_shift >= 0 && fs->mask.ivlan_vld)
155 ntuple_mask |= (u64)(F_FT_VLAN_VLD | fs->mask.ivlan) <<
157 if (tp->vnic_shift >= 0) {
158 if (fs->mask.ovlan_vld)
159 ntuple_mask |= (u64)(fs->val.ovlan_vld << 16 |
160 fs->mask.ovlan) << tp->vnic_shift;
161 else if (fs->mask.pfvf_vld)
162 ntuple_mask |= (u64)(fs->mask.pfvf_vld << 16 |
164 fs->mask.vf) << tp->vnic_shift;
166 if (tp->tos_shift >= 0)
167 ntuple_mask |= (u64)fs->mask.tos << tp->tos_shift;
169 if (ntuple_mask != hash_filter_mask)
172 fs->cap = 1; /* use hash region */
176 ch_rte_parsetype_eth(const void *dmask, const struct rte_flow_item *item,
177 struct ch_filter_specification *fs,
178 struct rte_flow_error *e)
180 const struct rte_flow_item_eth *spec = item->spec;
181 const struct rte_flow_item_eth *umask = item->mask;
182 const struct rte_flow_item_eth *mask;
184 /* If user has not given any mask, then use chelsio supported mask. */
185 mask = umask ? umask : (const struct rte_flow_item_eth *)dmask;
190 /* we don't support SRC_MAC filtering*/
191 if (!rte_is_zero_ether_addr(&mask->src))
192 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
194 "src mac filtering not supported");
196 if (!rte_is_zero_ether_addr(&mask->dst)) {
197 const u8 *addr = (const u8 *)&spec->dst.addr_bytes[0];
198 const u8 *m = (const u8 *)&mask->dst.addr_bytes[0];
199 struct rte_flow *flow = (struct rte_flow *)fs->private;
200 struct port_info *pi = (struct port_info *)
201 (flow->dev->data->dev_private);
204 idx = cxgbe_mpstcam_alloc(pi, addr, m);
206 return rte_flow_error_set(e, idx,
207 RTE_FLOW_ERROR_TYPE_ITEM,
208 NULL, "unable to allocate mac"
210 CXGBE_FILL_FS(idx, 0x1ff, macidx);
213 CXGBE_FILL_FS(be16_to_cpu(spec->type),
214 be16_to_cpu(mask->type), ethtype);
220 ch_rte_parsetype_port(const void *dmask, const struct rte_flow_item *item,
221 struct ch_filter_specification *fs,
222 struct rte_flow_error *e)
224 const struct rte_flow_item_phy_port *val = item->spec;
225 const struct rte_flow_item_phy_port *umask = item->mask;
226 const struct rte_flow_item_phy_port *mask;
228 mask = umask ? umask : (const struct rte_flow_item_phy_port *)dmask;
231 return 0; /* Wildcard, match all physical ports */
233 if (val->index > 0x7)
234 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
236 "port index upto 0x7 is supported");
238 CXGBE_FILL_FS(val->index, mask->index, iport);
244 ch_rte_parsetype_vlan(const void *dmask, const struct rte_flow_item *item,
245 struct ch_filter_specification *fs,
246 struct rte_flow_error *e)
248 const struct rte_flow_item_vlan *spec = item->spec;
249 const struct rte_flow_item_vlan *umask = item->mask;
250 const struct rte_flow_item_vlan *mask;
252 /* If user has not given any mask, then use chelsio supported mask. */
253 mask = umask ? umask : (const struct rte_flow_item_vlan *)dmask;
255 if (!fs->mask.ethtype)
256 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
258 "Can't parse VLAN item without knowing ethertype");
260 /* If ethertype is already set and is not VLAN (0x8100) or
261 * QINQ(0x88A8), then don't proceed further. Otherwise,
262 * reset the outer ethertype, so that it can be replaced by
263 * innermost ethertype. Note that hardware will automatically
264 * match against VLAN or QINQ packets, based on 'ivlan_vld' or
265 * 'ovlan_vld' bit set in Chelsio filter spec, respectively.
267 if (fs->mask.ethtype) {
268 if (fs->val.ethtype != RTE_ETHER_TYPE_VLAN &&
269 fs->val.ethtype != RTE_ETHER_TYPE_QINQ)
270 return rte_flow_error_set(e, EINVAL,
271 RTE_FLOW_ERROR_TYPE_ITEM,
273 "Ethertype must be 0x8100 or 0x88a8");
276 if (fs->val.ethtype == RTE_ETHER_TYPE_QINQ) {
277 CXGBE_FILL_FS(1, 1, ovlan_vld);
279 CXGBE_FILL_FS(be16_to_cpu(spec->tci),
280 be16_to_cpu(mask->tci), ovlan);
282 fs->mask.ethtype = 0;
285 } else if (fs->val.ethtype == RTE_ETHER_TYPE_VLAN) {
286 CXGBE_FILL_FS(1, 1, ivlan_vld);
288 CXGBE_FILL_FS(be16_to_cpu(spec->tci),
289 be16_to_cpu(mask->tci), ivlan);
291 fs->mask.ethtype = 0;
297 CXGBE_FILL_FS(be16_to_cpu(spec->inner_type),
298 be16_to_cpu(mask->inner_type), ethtype);
304 ch_rte_parsetype_pf(const void *dmask __rte_unused,
305 const struct rte_flow_item *item __rte_unused,
306 struct ch_filter_specification *fs,
307 struct rte_flow_error *e __rte_unused)
309 struct rte_flow *flow = (struct rte_flow *)fs->private;
310 struct rte_eth_dev *dev = flow->dev;
311 struct adapter *adap = ethdev2adap(dev);
313 CXGBE_FILL_FS(1, 1, pfvf_vld);
315 CXGBE_FILL_FS(adap->pf, 0x7, pf);
320 ch_rte_parsetype_vf(const void *dmask, const struct rte_flow_item *item,
321 struct ch_filter_specification *fs,
322 struct rte_flow_error *e)
324 const struct rte_flow_item_vf *umask = item->mask;
325 const struct rte_flow_item_vf *val = item->spec;
326 const struct rte_flow_item_vf *mask;
328 /* If user has not given any mask, then use chelsio supported mask. */
329 mask = umask ? umask : (const struct rte_flow_item_vf *)dmask;
331 CXGBE_FILL_FS(1, 1, pfvf_vld);
334 return 0; /* Wildcard, match all Vf */
336 if (val->id > UCHAR_MAX)
337 return rte_flow_error_set(e, EINVAL,
338 RTE_FLOW_ERROR_TYPE_ITEM,
342 CXGBE_FILL_FS(val->id, mask->id, vf);
348 ch_rte_parsetype_udp(const void *dmask, const struct rte_flow_item *item,
349 struct ch_filter_specification *fs,
350 struct rte_flow_error *e)
352 const struct rte_flow_item_udp *val = item->spec;
353 const struct rte_flow_item_udp *umask = item->mask;
354 const struct rte_flow_item_udp *mask;
356 mask = umask ? umask : (const struct rte_flow_item_udp *)dmask;
358 if (mask->hdr.dgram_len || mask->hdr.dgram_cksum)
359 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
361 "udp: only src/dst port supported");
363 CXGBE_FILL_FS(IPPROTO_UDP, 0xff, proto);
366 CXGBE_FILL_FS(be16_to_cpu(val->hdr.src_port),
367 be16_to_cpu(mask->hdr.src_port), fport);
368 CXGBE_FILL_FS(be16_to_cpu(val->hdr.dst_port),
369 be16_to_cpu(mask->hdr.dst_port), lport);
374 ch_rte_parsetype_tcp(const void *dmask, const struct rte_flow_item *item,
375 struct ch_filter_specification *fs,
376 struct rte_flow_error *e)
378 const struct rte_flow_item_tcp *val = item->spec;
379 const struct rte_flow_item_tcp *umask = item->mask;
380 const struct rte_flow_item_tcp *mask;
382 mask = umask ? umask : (const struct rte_flow_item_tcp *)dmask;
384 if (mask->hdr.sent_seq || mask->hdr.recv_ack || mask->hdr.data_off ||
385 mask->hdr.tcp_flags || mask->hdr.rx_win || mask->hdr.cksum ||
387 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
389 "tcp: only src/dst port supported");
391 CXGBE_FILL_FS(IPPROTO_TCP, 0xff, proto);
394 CXGBE_FILL_FS(be16_to_cpu(val->hdr.src_port),
395 be16_to_cpu(mask->hdr.src_port), fport);
396 CXGBE_FILL_FS(be16_to_cpu(val->hdr.dst_port),
397 be16_to_cpu(mask->hdr.dst_port), lport);
402 ch_rte_parsetype_ipv4(const void *dmask, const struct rte_flow_item *item,
403 struct ch_filter_specification *fs,
404 struct rte_flow_error *e)
406 const struct rte_flow_item_ipv4 *val = item->spec;
407 const struct rte_flow_item_ipv4 *umask = item->mask;
408 const struct rte_flow_item_ipv4 *mask;
410 mask = umask ? umask : (const struct rte_flow_item_ipv4 *)dmask;
412 if (mask->hdr.time_to_live)
413 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
414 item, "ttl is not supported");
416 if (fs->mask.ethtype &&
417 (fs->val.ethtype != RTE_ETHER_TYPE_IPV4))
418 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
420 "Couldn't find IPv4 ethertype");
421 fs->type = FILTER_TYPE_IPV4;
423 return 0; /* ipv4 wild card */
425 CXGBE_FILL_FS(val->hdr.next_proto_id, mask->hdr.next_proto_id, proto);
426 CXGBE_FILL_FS_MEMCPY(val->hdr.dst_addr, mask->hdr.dst_addr, lip);
427 CXGBE_FILL_FS_MEMCPY(val->hdr.src_addr, mask->hdr.src_addr, fip);
428 CXGBE_FILL_FS(val->hdr.type_of_service, mask->hdr.type_of_service, tos);
434 ch_rte_parsetype_ipv6(const void *dmask, const struct rte_flow_item *item,
435 struct ch_filter_specification *fs,
436 struct rte_flow_error *e)
438 const struct rte_flow_item_ipv6 *val = item->spec;
439 const struct rte_flow_item_ipv6 *umask = item->mask;
440 const struct rte_flow_item_ipv6 *mask;
441 u32 vtc_flow, vtc_flow_mask;
443 mask = umask ? umask : (const struct rte_flow_item_ipv6 *)dmask;
445 vtc_flow_mask = be32_to_cpu(mask->hdr.vtc_flow);
447 if (vtc_flow_mask & RTE_IPV6_HDR_FL_MASK ||
448 mask->hdr.payload_len || mask->hdr.hop_limits)
449 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
451 "flow/hop are not supported");
453 if (fs->mask.ethtype &&
454 (fs->val.ethtype != RTE_ETHER_TYPE_IPV6))
455 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM,
457 "Couldn't find IPv6 ethertype");
458 fs->type = FILTER_TYPE_IPV6;
460 return 0; /* ipv6 wild card */
462 CXGBE_FILL_FS(val->hdr.proto, mask->hdr.proto, proto);
464 vtc_flow = be32_to_cpu(val->hdr.vtc_flow);
465 CXGBE_FILL_FS((vtc_flow & RTE_IPV6_HDR_TC_MASK) >>
466 RTE_IPV6_HDR_TC_SHIFT,
467 (vtc_flow_mask & RTE_IPV6_HDR_TC_MASK) >>
468 RTE_IPV6_HDR_TC_SHIFT,
471 CXGBE_FILL_FS_MEMCPY(val->hdr.dst_addr, mask->hdr.dst_addr, lip);
472 CXGBE_FILL_FS_MEMCPY(val->hdr.src_addr, mask->hdr.src_addr, fip);
478 cxgbe_rtef_parse_attr(struct rte_flow *flow, const struct rte_flow_attr *attr,
479 struct rte_flow_error *e)
482 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ATTR,
483 attr, "attribute:<egress> is"
486 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ATTR,
487 attr, "group parameter is"
490 flow->fidx = attr->priority ? attr->priority - 1 : FILTER_ID_MAX;
495 static inline int check_rxq(struct rte_eth_dev *dev, uint16_t rxq)
497 struct port_info *pi = ethdev2pinfo(dev);
499 if (rxq > pi->n_rx_qsets)
504 static int cxgbe_validate_fidxondel(struct filter_entry *f, unsigned int fidx)
506 struct adapter *adap = ethdev2adap(f->dev);
507 struct ch_filter_specification fs = f->fs;
510 if (fidx >= adap->tids.nftids) {
511 dev_err(adap, "invalid flow index %d.\n", fidx);
515 nentries = cxgbe_filter_slots(adap, fs.type);
516 if (!cxgbe_is_filter_set(&adap->tids, fidx, nentries)) {
517 dev_err(adap, "Already free fidx:%d f:%p\n", fidx, f);
525 cxgbe_validate_fidxonadd(struct ch_filter_specification *fs,
526 struct adapter *adap, unsigned int fidx)
530 nentries = cxgbe_filter_slots(adap, fs->type);
531 if (cxgbe_is_filter_set(&adap->tids, fidx, nentries)) {
532 dev_err(adap, "filter index: %d is busy.\n", fidx);
536 if (fidx >= adap->tids.nftids) {
537 dev_err(adap, "filter index (%u) >= max(%u)\n",
538 fidx, adap->tids.nftids);
546 cxgbe_verify_fidx(struct rte_flow *flow, unsigned int fidx, uint8_t del)
549 return 0; /* Hash filters */
550 return del ? cxgbe_validate_fidxondel(flow->f, fidx) :
551 cxgbe_validate_fidxonadd(&flow->fs,
552 ethdev2adap(flow->dev), fidx);
555 static int cxgbe_get_fidx(struct rte_flow *flow, unsigned int *fidx)
557 struct ch_filter_specification *fs = &flow->fs;
558 struct adapter *adap = ethdev2adap(flow->dev);
560 /* For tcam get the next available slot, if default value specified */
561 if (flow->fidx == FILTER_ID_MAX) {
565 nentries = cxgbe_filter_slots(adap, fs->type);
566 idx = cxgbe_alloc_ftid(adap, nentries);
568 dev_err(adap, "unable to get a filter index in tcam\n");
571 *fidx = (unsigned int)idx;
580 cxgbe_get_flow_item_index(const struct rte_flow_item items[], u32 type)
582 const struct rte_flow_item *i;
583 int j, index = -ENOENT;
585 for (i = items, j = 0; i->type != RTE_FLOW_ITEM_TYPE_END; i++, j++) {
586 if (i->type == type) {
596 ch_rte_parse_nat(uint8_t nmode, struct ch_filter_specification *fs)
599 * BIT_0 = [src_ip], BIT_1 = [dst_ip]
600 * BIT_2 = [src_port], BIT_3 = [dst_port]
602 * Only below cases are supported as per our spec.
606 fs->nat_mode = NAT_MODE_NONE;
609 fs->nat_mode = NAT_MODE_DIP;
612 fs->nat_mode = NAT_MODE_SIP_SP;
615 fs->nat_mode = NAT_MODE_DIP_SIP_SP;
618 fs->nat_mode = NAT_MODE_DIP_DP;
621 fs->nat_mode = NAT_MODE_DIP_DP_SIP;
624 fs->nat_mode = NAT_MODE_DIP_DP_SP;
627 fs->nat_mode = NAT_MODE_ALL;
637 ch_rte_parse_atype_switch(const struct rte_flow_action *a,
638 const struct rte_flow_item items[],
640 struct ch_filter_specification *fs,
641 struct rte_flow_error *e)
643 const struct rte_flow_action_of_set_vlan_vid *vlanid;
644 const struct rte_flow_action_of_set_vlan_pcp *vlanpcp;
645 const struct rte_flow_action_of_push_vlan *pushvlan;
646 const struct rte_flow_action_set_ipv4 *ipv4;
647 const struct rte_flow_action_set_ipv6 *ipv6;
648 const struct rte_flow_action_set_tp *tp_port;
649 const struct rte_flow_action_phy_port *port;
654 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
655 vlanid = (const struct rte_flow_action_of_set_vlan_vid *)
657 /* If explicitly asked to push a new VLAN header,
658 * then don't set rewrite mode. Otherwise, the
659 * incoming VLAN packets will get their VLAN fields
660 * rewritten, instead of adding an additional outer
663 if (fs->newvlan != VLAN_INSERT)
664 fs->newvlan = VLAN_REWRITE;
665 tmp_vlan = fs->vlan & 0xe000;
666 fs->vlan = (be16_to_cpu(vlanid->vlan_vid) & 0xfff) | tmp_vlan;
668 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
669 vlanpcp = (const struct rte_flow_action_of_set_vlan_pcp *)
671 /* If explicitly asked to push a new VLAN header,
672 * then don't set rewrite mode. Otherwise, the
673 * incoming VLAN packets will get their VLAN fields
674 * rewritten, instead of adding an additional outer
677 if (fs->newvlan != VLAN_INSERT)
678 fs->newvlan = VLAN_REWRITE;
679 tmp_vlan = fs->vlan & 0xfff;
680 fs->vlan = (vlanpcp->vlan_pcp << 13) | tmp_vlan;
682 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
683 pushvlan = (const struct rte_flow_action_of_push_vlan *)
685 if (be16_to_cpu(pushvlan->ethertype) != RTE_ETHER_TYPE_VLAN)
686 return rte_flow_error_set(e, EINVAL,
687 RTE_FLOW_ERROR_TYPE_ACTION, a,
688 "only ethertype 0x8100 "
689 "supported for push vlan.");
690 fs->newvlan = VLAN_INSERT;
692 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
693 fs->newvlan = VLAN_REMOVE;
695 case RTE_FLOW_ACTION_TYPE_PHY_PORT:
696 port = (const struct rte_flow_action_phy_port *)a->conf;
697 fs->eport = port->index;
699 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
700 item_index = cxgbe_get_flow_item_index(items,
701 RTE_FLOW_ITEM_TYPE_IPV4);
703 return rte_flow_error_set(e, EINVAL,
704 RTE_FLOW_ERROR_TYPE_ACTION, a,
705 "No RTE_FLOW_ITEM_TYPE_IPV4 "
708 ipv4 = (const struct rte_flow_action_set_ipv4 *)a->conf;
709 memcpy(fs->nat_fip, &ipv4->ipv4_addr, sizeof(ipv4->ipv4_addr));
712 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
713 item_index = cxgbe_get_flow_item_index(items,
714 RTE_FLOW_ITEM_TYPE_IPV4);
716 return rte_flow_error_set(e, EINVAL,
717 RTE_FLOW_ERROR_TYPE_ACTION, a,
718 "No RTE_FLOW_ITEM_TYPE_IPV4 "
721 ipv4 = (const struct rte_flow_action_set_ipv4 *)a->conf;
722 memcpy(fs->nat_lip, &ipv4->ipv4_addr, sizeof(ipv4->ipv4_addr));
725 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
726 item_index = cxgbe_get_flow_item_index(items,
727 RTE_FLOW_ITEM_TYPE_IPV6);
729 return rte_flow_error_set(e, EINVAL,
730 RTE_FLOW_ERROR_TYPE_ACTION, a,
731 "No RTE_FLOW_ITEM_TYPE_IPV6 "
734 ipv6 = (const struct rte_flow_action_set_ipv6 *)a->conf;
735 memcpy(fs->nat_fip, ipv6->ipv6_addr, sizeof(ipv6->ipv6_addr));
738 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
739 item_index = cxgbe_get_flow_item_index(items,
740 RTE_FLOW_ITEM_TYPE_IPV6);
742 return rte_flow_error_set(e, EINVAL,
743 RTE_FLOW_ERROR_TYPE_ACTION, a,
744 "No RTE_FLOW_ITEM_TYPE_IPV6 "
747 ipv6 = (const struct rte_flow_action_set_ipv6 *)a->conf;
748 memcpy(fs->nat_lip, ipv6->ipv6_addr, sizeof(ipv6->ipv6_addr));
751 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
752 item_index = cxgbe_get_flow_item_index(items,
753 RTE_FLOW_ITEM_TYPE_TCP);
754 if (item_index < 0) {
756 cxgbe_get_flow_item_index(items,
757 RTE_FLOW_ITEM_TYPE_UDP);
759 return rte_flow_error_set(e, EINVAL,
760 RTE_FLOW_ERROR_TYPE_ACTION, a,
761 "No RTE_FLOW_ITEM_TYPE_TCP or "
762 "RTE_FLOW_ITEM_TYPE_UDP found");
765 tp_port = (const struct rte_flow_action_set_tp *)a->conf;
766 fs->nat_fport = be16_to_cpu(tp_port->port);
769 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
770 item_index = cxgbe_get_flow_item_index(items,
771 RTE_FLOW_ITEM_TYPE_TCP);
772 if (item_index < 0) {
774 cxgbe_get_flow_item_index(items,
775 RTE_FLOW_ITEM_TYPE_UDP);
777 return rte_flow_error_set(e, EINVAL,
778 RTE_FLOW_ERROR_TYPE_ACTION, a,
779 "No RTE_FLOW_ITEM_TYPE_TCP or "
780 "RTE_FLOW_ITEM_TYPE_UDP found");
783 tp_port = (const struct rte_flow_action_set_tp *)a->conf;
784 fs->nat_lport = be16_to_cpu(tp_port->port);
787 case RTE_FLOW_ACTION_TYPE_MAC_SWAP:
788 item_index = cxgbe_get_flow_item_index(items,
789 RTE_FLOW_ITEM_TYPE_ETH);
791 return rte_flow_error_set(e, EINVAL,
792 RTE_FLOW_ERROR_TYPE_ACTION, a,
793 "No RTE_FLOW_ITEM_TYPE_ETH "
798 /* We are not supposed to come here */
799 return rte_flow_error_set(e, EINVAL,
800 RTE_FLOW_ERROR_TYPE_ACTION, a,
801 "Action not supported");
808 cxgbe_rtef_parse_actions(struct rte_flow *flow,
809 const struct rte_flow_item items[],
810 const struct rte_flow_action action[],
811 struct rte_flow_error *e)
813 struct ch_filter_specification *fs = &flow->fs;
814 uint8_t nmode = 0, nat_ipv4 = 0, nat_ipv6 = 0;
815 uint8_t vlan_set_vid = 0, vlan_set_pcp = 0;
816 const struct rte_flow_action_queue *q;
817 const struct rte_flow_action *a;
821 for (a = action; a->type != RTE_FLOW_ACTION_TYPE_END; a++) {
823 case RTE_FLOW_ACTION_TYPE_VOID:
825 case RTE_FLOW_ACTION_TYPE_DROP:
827 return rte_flow_error_set(e, EINVAL,
828 RTE_FLOW_ERROR_TYPE_ACTION, a,
829 "specify only 1 pass/drop");
830 fs->action = FILTER_DROP;
832 case RTE_FLOW_ACTION_TYPE_QUEUE:
833 q = (const struct rte_flow_action_queue *)a->conf;
835 return rte_flow_error_set(e, EINVAL,
836 RTE_FLOW_ERROR_TYPE_ACTION, q,
837 "specify rx queue index");
838 if (check_rxq(flow->dev, q->index))
839 return rte_flow_error_set(e, EINVAL,
840 RTE_FLOW_ERROR_TYPE_ACTION, q,
843 return rte_flow_error_set(e, EINVAL,
844 RTE_FLOW_ERROR_TYPE_ACTION, a,
845 "specify only 1 pass/drop");
846 fs->action = FILTER_PASS;
850 case RTE_FLOW_ACTION_TYPE_COUNT:
853 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
856 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
859 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
860 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
861 case RTE_FLOW_ACTION_TYPE_PHY_PORT:
862 case RTE_FLOW_ACTION_TYPE_MAC_SWAP:
863 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
864 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
867 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
868 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
871 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
872 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
874 /* We allow multiple switch actions, but switch is
875 * not compatible with either queue or drop
877 if (abit++ && fs->action != FILTER_SWITCH)
878 return rte_flow_error_set(e, EINVAL,
879 RTE_FLOW_ERROR_TYPE_ACTION, a,
880 "overlapping action specified");
881 if (nat_ipv4 && nat_ipv6)
882 return rte_flow_error_set(e, EINVAL,
883 RTE_FLOW_ERROR_TYPE_ACTION, a,
884 "Can't have one address ipv4 and the"
887 ret = ch_rte_parse_atype_switch(a, items, &nmode, fs,
891 fs->action = FILTER_SWITCH;
894 /* Not supported action : return error */
895 return rte_flow_error_set(e, ENOTSUP,
896 RTE_FLOW_ERROR_TYPE_ACTION,
897 a, "Action not supported");
901 if (fs->newvlan == VLAN_REWRITE && (!vlan_set_vid || !vlan_set_pcp))
902 return rte_flow_error_set(e, EINVAL,
903 RTE_FLOW_ERROR_TYPE_ACTION, a,
904 "Both OF_SET_VLAN_VID and "
905 "OF_SET_VLAN_PCP must be specified");
907 if (ch_rte_parse_nat(nmode, fs))
908 return rte_flow_error_set(e, EINVAL,
909 RTE_FLOW_ERROR_TYPE_ACTION, a,
910 "invalid settings for swich action");
914 static struct chrte_fparse parseitem[] = {
915 [RTE_FLOW_ITEM_TYPE_ETH] = {
916 .fptr = ch_rte_parsetype_eth,
917 .dmask = &(const struct rte_flow_item_eth){
918 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
919 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00",
924 [RTE_FLOW_ITEM_TYPE_PHY_PORT] = {
925 .fptr = ch_rte_parsetype_port,
926 .dmask = &(const struct rte_flow_item_phy_port){
931 [RTE_FLOW_ITEM_TYPE_VLAN] = {
932 .fptr = ch_rte_parsetype_vlan,
933 .dmask = &(const struct rte_flow_item_vlan){
935 .inner_type = 0xffff,
939 [RTE_FLOW_ITEM_TYPE_IPV4] = {
940 .fptr = ch_rte_parsetype_ipv4,
941 .dmask = &(const struct rte_flow_item_ipv4) {
943 .src_addr = RTE_BE32(0xffffffff),
944 .dst_addr = RTE_BE32(0xffffffff),
945 .type_of_service = 0xff,
950 [RTE_FLOW_ITEM_TYPE_IPV6] = {
951 .fptr = ch_rte_parsetype_ipv6,
952 .dmask = &(const struct rte_flow_item_ipv6) {
955 "\xff\xff\xff\xff\xff\xff\xff\xff"
956 "\xff\xff\xff\xff\xff\xff\xff\xff",
958 "\xff\xff\xff\xff\xff\xff\xff\xff"
959 "\xff\xff\xff\xff\xff\xff\xff\xff",
960 .vtc_flow = RTE_BE32(0xff000000),
965 [RTE_FLOW_ITEM_TYPE_UDP] = {
966 .fptr = ch_rte_parsetype_udp,
967 .dmask = &rte_flow_item_udp_mask,
970 [RTE_FLOW_ITEM_TYPE_TCP] = {
971 .fptr = ch_rte_parsetype_tcp,
972 .dmask = &rte_flow_item_tcp_mask,
975 [RTE_FLOW_ITEM_TYPE_PF] = {
976 .fptr = ch_rte_parsetype_pf,
980 [RTE_FLOW_ITEM_TYPE_VF] = {
981 .fptr = ch_rte_parsetype_vf,
982 .dmask = &(const struct rte_flow_item_vf){
989 cxgbe_rtef_parse_items(struct rte_flow *flow,
990 const struct rte_flow_item items[],
991 struct rte_flow_error *e)
993 struct adapter *adap = ethdev2adap(flow->dev);
994 const struct rte_flow_item *i;
995 char repeat[ARRAY_SIZE(parseitem)] = {0};
997 for (i = items; i->type != RTE_FLOW_ITEM_TYPE_END; i++) {
998 struct chrte_fparse *idx;
1001 if (i->type >= ARRAY_SIZE(parseitem))
1002 return rte_flow_error_set(e, ENOTSUP,
1003 RTE_FLOW_ERROR_TYPE_ITEM,
1004 i, "Item not supported");
1007 case RTE_FLOW_ITEM_TYPE_VOID:
1010 /* check if item is repeated */
1011 if (repeat[i->type] &&
1012 i->type != RTE_FLOW_ITEM_TYPE_VLAN)
1013 return rte_flow_error_set(e, ENOTSUP,
1014 RTE_FLOW_ERROR_TYPE_ITEM, i,
1015 "parse items cannot be repeated(except void/vlan)");
1017 repeat[i->type] = 1;
1019 /* validate the item */
1020 ret = cxgbe_validate_item(i, e);
1024 idx = &flow->item_parser[i->type];
1025 if (!idx || !idx->fptr) {
1026 return rte_flow_error_set(e, ENOTSUP,
1027 RTE_FLOW_ERROR_TYPE_ITEM, i,
1028 "Item not supported");
1030 ret = idx->fptr(idx->dmask, i, &flow->fs, e);
1037 cxgbe_fill_filter_region(adap, &flow->fs);
1038 cxgbe_tweak_filter_spec(adap, &flow->fs);
1044 cxgbe_flow_parse(struct rte_flow *flow,
1045 const struct rte_flow_attr *attr,
1046 const struct rte_flow_item item[],
1047 const struct rte_flow_action action[],
1048 struct rte_flow_error *e)
1051 /* parse user request into ch_filter_specification */
1052 ret = cxgbe_rtef_parse_attr(flow, attr, e);
1055 ret = cxgbe_rtef_parse_items(flow, item, e);
1058 return cxgbe_rtef_parse_actions(flow, item, action, e);
1061 static int __cxgbe_flow_create(struct rte_eth_dev *dev, struct rte_flow *flow)
1063 struct ch_filter_specification *fs = &flow->fs;
1064 struct adapter *adap = ethdev2adap(dev);
1065 struct tid_info *t = &adap->tids;
1066 struct filter_ctx ctx;
1070 if (cxgbe_get_fidx(flow, &fidx))
1072 if (cxgbe_verify_fidx(flow, fidx, 0))
1075 t4_init_completion(&ctx.completion);
1076 /* go create the filter */
1077 err = cxgbe_set_filter(dev, fidx, fs, &ctx);
1079 dev_err(adap, "Error %d while creating filter.\n", err);
1083 /* Poll the FW for reply */
1084 err = cxgbe_poll_for_completion(&adap->sge.fw_evtq,
1086 CXGBE_FLOW_POLL_CNT,
1089 dev_err(adap, "Filter set operation timed out (%d)\n", err);
1093 dev_err(adap, "Hardware error %d while creating the filter.\n",
1098 if (fs->cap) { /* to destroy the filter */
1099 flow->fidx = ctx.tid;
1100 flow->f = lookup_tid(t, ctx.tid);
1103 flow->f = &adap->tids.ftid_tab[fidx];
1109 static struct rte_flow *
1110 cxgbe_flow_create(struct rte_eth_dev *dev,
1111 const struct rte_flow_attr *attr,
1112 const struct rte_flow_item item[],
1113 const struct rte_flow_action action[],
1114 struct rte_flow_error *e)
1116 struct adapter *adap = ethdev2adap(dev);
1117 struct rte_flow *flow;
1120 flow = t4_os_alloc(sizeof(struct rte_flow));
1122 rte_flow_error_set(e, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE,
1123 NULL, "Unable to allocate memory for"
1128 flow->item_parser = parseitem;
1130 flow->fs.private = (void *)flow;
1132 if (cxgbe_flow_parse(flow, attr, item, action, e)) {
1137 t4_os_lock(&adap->flow_lock);
1138 /* go, interact with cxgbe_filter */
1139 ret = __cxgbe_flow_create(dev, flow);
1140 t4_os_unlock(&adap->flow_lock);
1142 rte_flow_error_set(e, ret, RTE_FLOW_ERROR_TYPE_HANDLE,
1143 NULL, "Unable to create flow rule");
1148 flow->f->private = flow; /* Will be used during flush */
1153 static int __cxgbe_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
1155 struct adapter *adap = ethdev2adap(dev);
1156 struct filter_entry *f = flow->f;
1157 struct ch_filter_specification *fs;
1158 struct filter_ctx ctx;
1162 if (cxgbe_verify_fidx(flow, flow->fidx, 1))
1165 t4_init_completion(&ctx.completion);
1166 err = cxgbe_del_filter(dev, flow->fidx, fs, &ctx);
1168 dev_err(adap, "Error %d while deleting filter.\n", err);
1172 /* Poll the FW for reply */
1173 err = cxgbe_poll_for_completion(&adap->sge.fw_evtq,
1175 CXGBE_FLOW_POLL_CNT,
1178 dev_err(adap, "Filter delete operation timed out (%d)\n", err);
1182 dev_err(adap, "Hardware error %d while deleting the filter.\n",
1188 if (fs->mask.macidx) {
1189 struct port_info *pi = (struct port_info *)
1190 (dev->data->dev_private);
1193 ret = cxgbe_mpstcam_remove(pi, fs->val.macidx);
1202 cxgbe_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
1203 struct rte_flow_error *e)
1205 struct adapter *adap = ethdev2adap(dev);
1208 t4_os_lock(&adap->flow_lock);
1209 ret = __cxgbe_flow_destroy(dev, flow);
1210 t4_os_unlock(&adap->flow_lock);
1212 return rte_flow_error_set(e, ret, RTE_FLOW_ERROR_TYPE_HANDLE,
1213 flow, "error destroying filter.");
1218 static int __cxgbe_flow_query(struct rte_flow *flow, u64 *count,
1221 struct adapter *adap = ethdev2adap(flow->dev);
1222 struct ch_filter_specification fs = flow->f->fs;
1223 unsigned int fidx = flow->fidx;
1226 ret = cxgbe_get_filter_count(adap, fidx, count, fs.cap, 0);
1229 return cxgbe_get_filter_count(adap, fidx, byte_count, fs.cap, 1);
1233 cxgbe_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
1234 const struct rte_flow_action *action, void *data,
1235 struct rte_flow_error *e)
1237 struct adapter *adap = ethdev2adap(flow->dev);
1238 struct ch_filter_specification fs;
1239 struct rte_flow_query_count *c;
1240 struct filter_entry *f;
1248 if (action->type != RTE_FLOW_ACTION_TYPE_COUNT)
1249 return rte_flow_error_set(e, ENOTSUP,
1250 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1251 "only count supported for query");
1254 * This is a valid operation, Since we are allowed to do chelsio
1255 * specific operations in rte side of our code but not vise-versa
1257 * So, fs can be queried/modified here BUT rte_flow_query_count
1258 * cannot be worked on by the lower layer since we want to maintain
1259 * it as rte_flow agnostic.
1262 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
1263 &fs, "filter hit counters were not"
1264 " enabled during filter creation");
1266 c = (struct rte_flow_query_count *)data;
1268 t4_os_lock(&adap->flow_lock);
1269 ret = __cxgbe_flow_query(flow, &c->hits, &c->bytes);
1271 rte_flow_error_set(e, -ret, RTE_FLOW_ERROR_TYPE_ACTION,
1272 f, "cxgbe pmd failed to perform query");
1276 /* Query was successful */
1280 cxgbe_clear_filter_count(adap, flow->fidx, f->fs.cap, true);
1283 t4_os_unlock(&adap->flow_lock);
1288 cxgbe_flow_validate(struct rte_eth_dev *dev,
1289 const struct rte_flow_attr *attr,
1290 const struct rte_flow_item item[],
1291 const struct rte_flow_action action[],
1292 struct rte_flow_error *e)
1294 struct adapter *adap = ethdev2adap(dev);
1295 struct rte_flow *flow;
1299 flow = t4_os_alloc(sizeof(struct rte_flow));
1301 return rte_flow_error_set(e, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE,
1303 "Unable to allocate memory for filter_entry");
1305 flow->item_parser = parseitem;
1308 ret = cxgbe_flow_parse(flow, attr, item, action, e);
1314 if (cxgbe_validate_filter(adap, &flow->fs)) {
1316 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE,
1318 "validation failed. Check f/w config file.");
1321 t4_os_lock(&adap->flow_lock);
1322 if (cxgbe_get_fidx(flow, &fidx)) {
1323 ret = rte_flow_error_set(e, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE,
1324 NULL, "no memory in tcam.");
1328 if (cxgbe_verify_fidx(flow, fidx, 0)) {
1329 ret = rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE,
1330 NULL, "validation failed");
1335 t4_os_unlock(&adap->flow_lock);
1341 * @ret : > 0 filter destroyed succsesfully
1342 * < 0 error destroying filter
1343 * == 1 filter not active / not found
1346 cxgbe_check_n_destroy(struct filter_entry *f, struct rte_eth_dev *dev)
1348 if (f && (f->valid || f->pending) &&
1349 f->dev == dev && /* Only if user has asked for this port */
1350 f->private) /* We (rte_flow) created this filter */
1351 return __cxgbe_flow_destroy(dev, (struct rte_flow *)f->private);
1355 static int cxgbe_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *e)
1357 struct adapter *adap = ethdev2adap(dev);
1361 t4_os_lock(&adap->flow_lock);
1362 if (adap->tids.ftid_tab) {
1363 struct filter_entry *f = &adap->tids.ftid_tab[0];
1365 for (i = 0; i < adap->tids.nftids; i++, f++) {
1366 ret = cxgbe_check_n_destroy(f, dev);
1368 rte_flow_error_set(e, ret,
1369 RTE_FLOW_ERROR_TYPE_HANDLE,
1371 "error destroying TCAM "
1378 if (is_hashfilter(adap) && adap->tids.tid_tab) {
1379 struct filter_entry *f;
1381 for (i = adap->tids.hash_base; i <= adap->tids.ntids; i++) {
1382 f = (struct filter_entry *)adap->tids.tid_tab[i];
1384 ret = cxgbe_check_n_destroy(f, dev);
1386 rte_flow_error_set(e, ret,
1387 RTE_FLOW_ERROR_TYPE_HANDLE,
1389 "error destroying HASH "
1397 t4_os_unlock(&adap->flow_lock);
1398 return ret >= 0 ? 0 : ret;
1401 static const struct rte_flow_ops cxgbe_flow_ops = {
1402 .validate = cxgbe_flow_validate,
1403 .create = cxgbe_flow_create,
1404 .destroy = cxgbe_flow_destroy,
1405 .flush = cxgbe_flow_flush,
1406 .query = cxgbe_flow_query,
1411 cxgbe_dev_filter_ctrl(struct rte_eth_dev *dev,
1412 enum rte_filter_type filter_type,
1413 enum rte_filter_op filter_op,
1419 switch (filter_type) {
1420 case RTE_ETH_FILTER_GENERIC:
1421 if (filter_op != RTE_ETH_FILTER_GET)
1423 *(const void **)arg = &cxgbe_flow_ops;