1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_atomic.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_tailq.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_random.h>
34 #include <rte_kvargs.h>
36 #include "base/common.h"
37 #include "base/t4_regs.h"
38 #include "base/t4_msg.h"
40 #include "cxgbe_pfvf.h"
46 * Allocate a chunk of memory. The allocated memory is cleared.
48 void *t4_alloc_mem(size_t size)
50 return rte_zmalloc(NULL, size, 0);
54 * Free memory allocated through t4_alloc_mem().
56 void t4_free_mem(void *addr)
62 * Response queue handler for the FW event queue.
64 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
65 __rte_unused const struct pkt_gl *gl)
67 u8 opcode = ((const struct rss_header *)rsp)->opcode;
69 rsp++; /* skip RSS header */
72 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
74 if (unlikely(opcode == CPL_FW4_MSG &&
75 ((const struct cpl_fw4_msg *)rsp)->type ==
78 opcode = ((const struct rss_header *)rsp)->opcode;
80 if (opcode != CPL_SGE_EGR_UPDATE) {
81 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
87 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
89 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
90 const struct cpl_fw6_msg *msg = (const void *)rsp;
92 t4_handle_fw_rpl(q->adapter, msg->data);
93 } else if (opcode == CPL_ABORT_RPL_RSS) {
94 const struct cpl_abort_rpl_rss *p = (const void *)rsp;
96 cxgbe_hash_del_filter_rpl(q->adapter, p);
97 } else if (opcode == CPL_SET_TCB_RPL) {
98 const struct cpl_set_tcb_rpl *p = (const void *)rsp;
100 cxgbe_filter_rpl(q->adapter, p);
101 } else if (opcode == CPL_ACT_OPEN_RPL) {
102 const struct cpl_act_open_rpl *p = (const void *)rsp;
104 cxgbe_hash_filter_rpl(q->adapter, p);
105 } else if (opcode == CPL_L2T_WRITE_RPL) {
106 const struct cpl_l2t_write_rpl *p = (const void *)rsp;
108 cxgbe_do_l2t_write_rpl(q->adapter, p);
110 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
118 * Setup sge control queues to pass control information.
120 int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter)
122 struct sge *s = &adapter->sge;
125 for_each_port(adapter, i) {
126 struct port_info *pi = adap2pinfo(adapter, i);
127 char name[RTE_ETH_NAME_MAX_LEN];
128 struct sge_ctrl_txq *q = &s->ctrlq[i];
131 err = t4_sge_alloc_ctrl_txq(adapter, q,
136 dev_err(adapter, "Failed to alloc ctrl txq. Err: %d",
140 snprintf(name, sizeof(name), "%s_ctrl_pool_%d",
141 pi->eth_dev->device->driver->name,
142 pi->eth_dev->data->port_id);
143 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
146 RTE_MBUF_DEFAULT_BUF_SIZE,
151 "Can't create ctrl pool for port %d. Err: %d\n",
152 pi->eth_dev->data->port_id, err);
158 t4_free_sge_resources(adapter);
163 * cxgbe_poll_for_completion: Poll rxq for completion
165 * @ms: milliseconds to delay
166 * @cnt: number of times to poll
167 * @c: completion to check for 'done' status
169 * Polls the rxq for reples until completion is done or the count
172 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int ms,
173 unsigned int cnt, struct t4_completion *c)
176 unsigned int work_done, budget = 32;
181 for (i = 0; i < cnt; i++) {
182 cxgbe_poll(q, NULL, budget, &work_done);
183 t4_os_lock(&c->lock);
185 t4_os_unlock(&c->lock);
188 t4_os_unlock(&c->lock);
194 int cxgbe_setup_sge_fwevtq(struct adapter *adapter)
196 struct sge *s = &adapter->sge;
200 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
201 msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
206 static int closest_timer(const struct sge *s, int time)
208 unsigned int i, match = 0;
209 int delta, min_delta = INT_MAX;
211 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
212 delta = time - s->timer_val[i];
215 if (delta < min_delta) {
223 static int closest_thres(const struct sge *s, int thres)
225 unsigned int i, match = 0;
226 int delta, min_delta = INT_MAX;
228 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
229 delta = thres - s->counter_val[i];
232 if (delta < min_delta) {
241 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
243 * @us: the hold-off time in us, or 0 to disable timer
244 * @cnt: the hold-off packet count, or 0 to disable counter
246 * Sets an Rx queue's interrupt hold-off time and packet count. At least
247 * one of the two needs to be enabled for the queue to generate interrupts.
249 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
252 struct adapter *adap = q->adapter;
253 unsigned int timer_val;
259 new_idx = closest_thres(&adap->sge, cnt);
260 if (q->desc && q->pktcnt_idx != new_idx) {
261 /* the queue has already been created, update it */
262 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
264 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
265 V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
266 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
271 q->pktcnt_idx = new_idx;
274 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
275 closest_timer(&adap->sge, us);
278 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
280 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
281 V_QINTR_CNT_EN(cnt > 0);
286 * Allocate an active-open TID and set it to the supplied value.
288 int cxgbe_alloc_atid(struct tid_info *t, void *data)
292 t4_os_lock(&t->atid_lock);
294 union aopen_entry *p = t->afree;
296 atid = p - t->atid_tab;
301 t4_os_unlock(&t->atid_lock);
306 * Release an active-open TID.
308 void cxgbe_free_atid(struct tid_info *t, unsigned int atid)
310 union aopen_entry *p = &t->atid_tab[atid];
312 t4_os_lock(&t->atid_lock);
316 t4_os_unlock(&t->atid_lock);
320 * Populate a TID_RELEASE WR. Caller must properly size the skb.
322 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid)
324 struct cpl_tid_release *req;
326 req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *);
327 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
331 * Release a TID and inform HW. If we are unable to allocate the release
332 * message we defer to a work queue.
334 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
335 unsigned short family)
337 struct rte_mbuf *mbuf;
338 struct adapter *adap = container_of(t, struct adapter, tids);
340 WARN_ON(tid >= t->ntids);
342 if (t->tid_tab[tid]) {
343 t->tid_tab[tid] = NULL;
344 rte_atomic32_dec(&t->conns_in_use);
345 if (t->hash_base && tid >= t->hash_base) {
346 if (family == FILTER_TYPE_IPV4)
347 rte_atomic32_dec(&t->hash_tids_in_use);
349 if (family == FILTER_TYPE_IPV4)
350 rte_atomic32_dec(&t->tids_in_use);
354 mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool);
356 mbuf->data_len = sizeof(struct cpl_tid_release);
357 mbuf->pkt_len = mbuf->data_len;
358 mk_tid_release(mbuf, tid);
359 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf);
366 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid,
367 unsigned short family)
369 t->tid_tab[tid] = data;
370 if (t->hash_base && tid >= t->hash_base) {
371 if (family == FILTER_TYPE_IPV4)
372 rte_atomic32_inc(&t->hash_tids_in_use);
374 if (family == FILTER_TYPE_IPV4)
375 rte_atomic32_inc(&t->tids_in_use);
378 rte_atomic32_inc(&t->conns_in_use);
384 static void tid_free(struct tid_info *t)
388 rte_bitmap_free(t->ftid_bmap);
390 if (t->ftid_bmap_array)
391 t4_os_free(t->ftid_bmap_array);
393 t4_os_free(t->tid_tab);
396 memset(t, 0, sizeof(struct tid_info));
400 * Allocate and initialize the TID tables. Returns 0 on success.
402 static int tid_init(struct tid_info *t)
405 unsigned int ftid_bmap_size;
406 unsigned int natids = t->natids;
407 unsigned int max_ftids = t->nftids;
409 ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
410 size = t->ntids * sizeof(*t->tid_tab) +
411 max_ftids * sizeof(*t->ftid_tab) +
412 natids * sizeof(*t->atid_tab);
414 t->tid_tab = t4_os_alloc(size);
418 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
419 t->ftid_tab = (struct filter_entry *)&t->atid_tab[t->natids];
420 t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
421 if (!t->ftid_bmap_array) {
426 t4_os_lock_init(&t->atid_lock);
427 t4_os_lock_init(&t->ftid_lock);
431 rte_atomic32_init(&t->tids_in_use);
432 rte_atomic32_set(&t->tids_in_use, 0);
433 rte_atomic32_init(&t->conns_in_use);
434 rte_atomic32_set(&t->conns_in_use, 0);
436 /* Setup the free list for atid_tab and clear the stid bitmap. */
439 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
440 t->afree = t->atid_tab;
443 t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
453 static inline bool is_x_1g_port(const struct link_config *lc)
455 return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
458 static inline bool is_x_10g_port(const struct link_config *lc)
460 unsigned int speeds, high_speeds;
462 speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
463 high_speeds = speeds &
464 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
466 return high_speeds != 0;
469 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
470 unsigned int us, unsigned int cnt,
471 unsigned int size, unsigned int iqe_size)
474 cxgb4_set_rspq_intr_params(q, us, cnt);
475 q->iqe_len = iqe_size;
479 int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev)
481 struct port_info *pi = eth_dev->data->dev_private;
482 struct adapter *adap = pi->adapter;
483 struct sge *s = &adap->sge;
484 unsigned int max_queues = s->max_ethqsets / adap->params.nports;
486 if ((eth_dev->data->nb_rx_queues < 1) ||
487 (eth_dev->data->nb_tx_queues < 1))
490 if ((eth_dev->data->nb_rx_queues > max_queues) ||
491 (eth_dev->data->nb_tx_queues > max_queues))
494 if (eth_dev->data->nb_rx_queues > pi->rss_size)
497 /* We must configure RSS, since config has changed*/
498 pi->flags &= ~PORT_RSS_DONE;
500 pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
501 pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
506 void cxgbe_cfg_queues(struct rte_eth_dev *eth_dev)
508 struct port_info *pi = eth_dev->data->dev_private;
509 struct adapter *adap = pi->adapter;
510 struct sge *s = &adap->sge;
511 unsigned int i, nb_ports = 0, qidx = 0;
512 unsigned int q_per_port = 0;
514 if (!(adap->flags & CFG_QUEUES)) {
515 for_each_port(adap, i) {
516 struct port_info *tpi = adap2pinfo(adap, i);
518 nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
519 is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
523 * We default up to # of cores queues per 1G/10G port.
526 q_per_port = (s->max_ethqsets -
527 (adap->params.nports - nb_ports)) /
530 if (q_per_port > rte_lcore_count())
531 q_per_port = rte_lcore_count();
533 for_each_port(adap, i) {
534 struct port_info *pi = adap2pinfo(adap, i);
536 pi->first_qset = qidx;
538 /* Initially n_rx_qsets == n_tx_qsets */
539 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
540 is_x_1g_port(&pi->link_cfg)) ?
542 pi->n_tx_qsets = pi->n_rx_qsets;
544 if (pi->n_rx_qsets > pi->rss_size)
545 pi->n_rx_qsets = pi->rss_size;
547 qidx += pi->n_rx_qsets;
550 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
551 struct sge_eth_rxq *r = &s->ethrxq[i];
553 init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
555 r->fl.size = (r->usembufs ? 1024 : 72);
558 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
559 s->ethtxq[i].q.size = 1024;
561 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
562 adap->flags |= CFG_QUEUES;
566 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
568 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
572 void cxgbe_stats_reset(struct port_info *pi)
574 t4_clr_port_stats(pi->adapter, pi->tx_chan);
577 static void setup_memwin(struct adapter *adap)
581 /* For T5, only relative offset inside the PCIe BAR is passed */
582 mem_win0_base = MEMWIN0_BASE;
585 * Set up memory window for accessing adapter memory ranges. (Read
586 * back MA register to ensure that changes propagate before we attempt
587 * to use the new values.)
590 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
592 mem_win0_base | V_BIR(0) |
593 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
595 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
599 int cxgbe_init_rss(struct adapter *adap)
606 err = t4_init_rss_mode(adap, adap->mbox);
611 for_each_port(adap, i) {
612 struct port_info *pi = adap2pinfo(adap, i);
614 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
618 pi->rss_hf = CXGBE_RSS_HF_ALL;
624 * Dump basic information about the adapter.
626 void cxgbe_print_adapter_info(struct adapter *adap)
629 * Hardware/Firmware/etc. Version/Revision IDs.
631 t4_dump_version_info(adap);
634 void cxgbe_print_port_info(struct adapter *adap)
638 struct rte_pci_addr *loc = &adap->pdev->addr;
640 for_each_port(adap, i) {
641 const struct port_info *pi = adap2pinfo(adap, i);
644 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
645 bufp += sprintf(bufp, "100M/");
646 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
647 bufp += sprintf(bufp, "1G/");
648 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
649 bufp += sprintf(bufp, "10G/");
650 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
651 bufp += sprintf(bufp, "25G/");
652 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
653 bufp += sprintf(bufp, "40G/");
654 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
655 bufp += sprintf(bufp, "50G/");
656 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
657 bufp += sprintf(bufp, "100G/");
660 sprintf(bufp, "BASE-%s",
661 t4_get_port_type_description(
662 (enum fw_port_type)pi->port_type));
665 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
666 loc->domain, loc->bus, loc->devid, loc->function,
667 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
668 (adap->flags & USING_MSIX) ? " MSI-X" :
669 (adap->flags & USING_MSI) ? " MSI" : "");
673 static int check_devargs_handler(const char *key, const char *value, void *p)
675 if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) ||
676 !strncmp(key, CXGBE_DEVARG_CMN_TX_MODE_LATENCY, strlen(key)) ||
677 !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) {
678 if (!strncmp(value, "1", 1)) {
679 bool *dst_val = (bool *)p;
688 static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key,
691 struct rte_kvargs *kvlist;
697 kvlist = rte_kvargs_parse(devargs->args, NULL);
701 if (!rte_kvargs_count(kvlist, key))
704 ret = rte_kvargs_process(kvlist, key, check_devargs_handler, p);
707 rte_kvargs_free(kvlist);
712 static void cxgbe_get_devargs_int(struct adapter *adap, bool *dst,
713 const char *key, bool default_value)
715 struct rte_pci_device *pdev = adap->pdev;
717 bool devarg_value = default_value;
719 *dst = default_value;
723 ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value);
730 void cxgbe_process_devargs(struct adapter *adap)
732 cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan,
733 CXGBE_DEVARG_CMN_KEEP_OVLAN, false);
734 cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency,
735 CXGBE_DEVARG_CMN_TX_MODE_LATENCY, false);
736 cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up,
737 CXGBE_DEVARG_VF_FORCE_LINK_UP, false);
740 static void configure_vlan_types(struct adapter *adapter)
744 for_each_port(adapter, i) {
745 /* OVLAN Type 0x88a8 */
746 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
747 V_OVLAN_MASK(M_OVLAN_MASK) |
748 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
749 V_OVLAN_MASK(M_OVLAN_MASK) |
750 V_OVLAN_ETYPE(0x88a8));
751 /* OVLAN Type 0x9100 */
752 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
753 V_OVLAN_MASK(M_OVLAN_MASK) |
754 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
755 V_OVLAN_MASK(M_OVLAN_MASK) |
756 V_OVLAN_ETYPE(0x9100));
759 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
760 V_IVLAN_ETYPE(M_IVLAN_ETYPE),
761 V_IVLAN_ETYPE(0x8100));
763 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
764 F_OVLAN_EN0 | F_OVLAN_EN1 |
766 F_OVLAN_EN0 | F_OVLAN_EN1 |
770 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1),
771 V_RM_OVLAN(!adapter->devargs.keep_ovlan));
774 static void configure_pcie_ext_tag(struct adapter *adapter)
777 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
783 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
784 v |= PCI_EXP_DEVCTL_EXT_TAG;
785 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
786 if (is_t6(adapter->params.chip)) {
787 t4_set_reg_field(adapter, A_PCIE_CFG2,
788 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
790 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
791 V_T6_MINTAG(M_T6_MINTAG),
794 t4_set_reg_field(adapter, A_PCIE_CFG2,
795 V_TOTMAXTAG(M_TOTMAXTAG),
797 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
804 /* Figure out how many Queue Sets we can support */
805 void cxgbe_configure_max_ethqsets(struct adapter *adapter)
807 unsigned int ethqsets;
810 * We need to reserve an Ingress Queue for the Asynchronous Firmware
813 * For each Queue Set, we'll need the ability to allocate two Egress
814 * Contexts -- one for the Ingress Queue Free List and one for the TX
817 if (is_pf4(adapter)) {
818 struct pf_resources *pfres = &adapter->params.pfres;
820 ethqsets = pfres->niqflint - 1;
821 if (pfres->neq < ethqsets * 2)
822 ethqsets = pfres->neq / 2;
824 struct vf_resources *vfres = &adapter->params.vfres;
826 ethqsets = vfres->niqflint - 1;
827 if (vfres->nethctrl != ethqsets)
828 ethqsets = min(vfres->nethctrl, ethqsets);
829 if (vfres->neq < ethqsets * 2)
830 ethqsets = vfres->neq / 2;
833 if (ethqsets > MAX_ETH_QSETS)
834 ethqsets = MAX_ETH_QSETS;
835 adapter->sge.max_ethqsets = ethqsets;
839 * Tweak configuration based on system architecture, etc. Most of these have
840 * defaults assigned to them by Firmware Configuration Files (if we're using
841 * them) but need to be explicitly set if we're using hard-coded
842 * initialization. So these are essentially common tweaks/settings for
843 * Configuration Files and hard-coded initialization ...
845 static int adap_init0_tweaks(struct adapter *adapter)
850 * Fix up various Host-Dependent Parameters like Page Size, Cache
851 * Line Size, etc. The firmware default is for a 4KB Page Size and
852 * 64B Cache Line Size ...
854 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
858 * Keep the chip default offset to deliver Ingress packets into our
859 * DMA buffers to zero
862 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
863 V_PKTSHIFT(rx_dma_offset));
865 t4_set_reg_field(adapter, A_SGE_FLM_CFG,
866 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
867 V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
869 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
870 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
872 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
873 V_IDMAARBROUNDROBIN(1U));
876 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
877 * adds the pseudo header itself.
879 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
880 F_CSUM_HAS_PSEUDO_HDR, 0);
886 * Attempt to initialize the adapter via a Firmware Configuration File.
888 static int adap_init0_config(struct adapter *adapter, int reset)
890 struct fw_caps_config_cmd caps_cmd;
891 unsigned long mtype = 0, maddr = 0;
892 u32 finiver, finicsum, cfcsum;
894 int config_issued = 0;
896 char config_name[20];
899 * Reset device if necessary.
902 ret = t4_fw_reset(adapter, adapter->mbox,
903 F_PIORSTMODE | F_PIORST);
905 dev_warn(adapter, "Firmware reset failed, error %d\n",
911 cfg_addr = t4_flash_cfg_addr(adapter);
914 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
919 strcpy(config_name, "On Flash");
920 mtype = FW_MEMTYPE_CF_FLASH;
924 * Issue a Capability Configuration command to the firmware to get it
925 * to parse the Configuration File. We don't use t4_fw_config_file()
926 * because we want the ability to modify various features after we've
927 * processed the configuration file ...
929 memset(&caps_cmd, 0, sizeof(caps_cmd));
930 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
931 F_FW_CMD_REQUEST | F_FW_CMD_READ);
932 caps_cmd.cfvalid_to_len16 =
933 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
934 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
935 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
937 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
940 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
941 * Configuration File in FLASH), our last gasp effort is to use the
942 * Firmware Configuration File which is embedded in the firmware. A
943 * very few early versions of the firmware didn't have one embedded
944 * but we can ignore those.
946 if (ret == -ENOENT) {
947 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
950 memset(&caps_cmd, 0, sizeof(caps_cmd));
951 caps_cmd.op_to_write =
952 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
953 F_FW_CMD_REQUEST | F_FW_CMD_READ);
954 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
955 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
956 sizeof(caps_cmd), &caps_cmd);
957 strcpy(config_name, "Firmware Default");
964 finiver = be32_to_cpu(caps_cmd.finiver);
965 finicsum = be32_to_cpu(caps_cmd.finicsum);
966 cfcsum = be32_to_cpu(caps_cmd.cfcsum);
967 if (finicsum != cfcsum)
968 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
972 * If we're a pure NIC driver then disable all offloading facilities.
973 * This will allow the firmware to optimize aspects of the hardware
974 * configuration which will result in improved performance.
976 caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD);
977 caps_cmd.toecaps = 0;
978 caps_cmd.iscsicaps = 0;
979 caps_cmd.rdmacaps = 0;
980 caps_cmd.fcoecaps = 0;
983 * And now tell the firmware to use the configuration we just loaded.
985 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
986 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
987 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
988 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
991 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
997 * Tweak configuration based on system architecture, etc.
999 ret = adap_init0_tweaks(adapter);
1001 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
1006 * And finally tell the firmware to initialize itself using the
1007 * parameters from the Configuration File.
1009 ret = t4_fw_initialize(adapter, adapter->mbox);
1011 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
1017 * Return successfully and note that we're operating with parameters
1018 * not supplied by the driver, rather than from hard-wired
1019 * initialization constants buried in the driver.
1022 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
1023 config_name, finiver, cfcsum);
1028 * Something bad happened. Return the error ... (If the "error"
1029 * is that there's no Configuration File on the adapter we don't
1030 * want to issue a warning since this is fairly common.)
1033 if (config_issued && ret != -ENOENT)
1034 dev_warn(adapter, "\"%s\" configuration file error %d\n",
1037 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
1041 static int adap_init0(struct adapter *adap)
1043 struct fw_caps_config_cmd caps_cmd;
1046 enum dev_state state;
1047 u32 params[7], val[7];
1049 int mbox = adap->mbox;
1052 * Contact FW, advertising Master capability.
1054 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
1056 dev_err(adap, "%s: could not connect to FW, error %d\n",
1061 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
1065 adap->flags |= MASTER_PF;
1067 if (state == DEV_STATE_INIT) {
1069 * Force halt and reset FW because a previous instance may have
1070 * exited abnormally without properly shutting down
1072 ret = t4_fw_halt(adap, adap->mbox, reset);
1074 dev_err(adap, "Failed to halt. Exit.\n");
1078 ret = t4_fw_restart(adap, adap->mbox, reset);
1080 dev_err(adap, "Failed to restart. Exit.\n");
1083 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
1086 t4_get_version_info(adap);
1088 ret = t4_get_core_clock(adap, &adap->params.vpd);
1090 dev_err(adap, "%s: could not get core clock, error %d\n",
1096 * If the firmware is initialized already (and we're not forcing a
1097 * master initialization), note that we're living with existing
1098 * adapter parameters. Otherwise, it's time to try initializing the
1101 if (state == DEV_STATE_INIT) {
1102 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
1103 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
1105 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
1107 ret = adap_init0_config(adap, reset);
1108 if (ret == -ENOENT) {
1110 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
1115 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
1119 /* Now that we've successfully configured and initialized the adapter
1120 * (or found it already initialized), we can ask the Firmware what
1121 * resources it has provisioned for us.
1123 ret = t4_get_pfres(adap);
1125 dev_err(adap->pdev_dev,
1126 "Unable to retrieve resource provisioning info\n");
1130 /* Find out what ports are available to us. */
1131 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1132 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
1133 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
1135 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
1140 adap->params.nports = hweight32(port_vec);
1141 adap->params.portvec = port_vec;
1143 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
1144 adap->params.nports);
1147 * Give the SGE code a chance to pull in anything that it needs ...
1148 * Note that this must be called after we retrieve our VPD parameters
1149 * in order to know how to convert core ticks to seconds, etc.
1151 ret = t4_sge_init(adap);
1153 dev_err(adap, "t4_sge_init failed with error %d\n",
1159 * Grab some of our basic fundamental operating parameters.
1161 params[0] = CXGBE_FW_PARAM_PFVF(L2T_START);
1162 params[1] = CXGBE_FW_PARAM_PFVF(L2T_END);
1163 params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START);
1164 params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END);
1165 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val);
1168 adap->l2t_start = val[0];
1169 adap->l2t_end = val[1];
1170 adap->tids.ftid_base = val[2];
1171 adap->tids.nftids = val[3] - val[2] + 1;
1173 params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START);
1174 params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END);
1175 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
1178 adap->clipt_start = val[0];
1179 adap->clipt_end = val[1];
1182 * Get device capabilities so we can determine what resources we need
1185 memset(&caps_cmd, 0, sizeof(caps_cmd));
1186 caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1187 F_FW_CMD_REQUEST | F_FW_CMD_READ);
1188 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
1189 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
1194 if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) &&
1195 is_t6(adap->params.chip)) {
1196 if (cxgbe_init_hash_filter(adap) < 0)
1200 /* See if FW supports FW_FILTER2 work request */
1201 if (is_t4(adap->params.chip)) {
1202 adap->params.filter2_wr_support = 0;
1204 params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR);
1205 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1207 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
1210 /* query tid-related parameters */
1211 params[0] = CXGBE_FW_PARAM_DEV(NTID);
1212 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
1216 adap->tids.ntids = val[0];
1217 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
1219 /* If we're running on newer firmware, let it know that we're
1220 * prepared to deal with encapsulated CPL messages. Older
1221 * firmware won't understand this and we'll just get
1222 * unencapsulated messages ...
1224 params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
1226 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1229 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
1230 * capability. Earlier versions of the firmware didn't have the
1231 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
1232 * permission to use ULPTX MEMWRITE DSGL.
1234 if (is_t4(adap->params.chip)) {
1235 adap->params.ulptx_memwrite_dsgl = false;
1237 params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
1238 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1240 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
1243 /* Query for max number of packets that can be coalesced for Tx */
1244 params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
1245 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1246 if (!ret && val[0] > 0)
1247 adap->params.max_tx_coalesce_num = val[0];
1249 adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM;
1252 * The MTU/MSS Table is initialized by now, so load their values. If
1253 * we're initializing the adapter, then we'll make any modifications
1254 * we want to the MTU/MSS Table and also initialize the congestion
1257 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
1258 if (state != DEV_STATE_INIT) {
1262 * The default MTU Table contains values 1492 and 1500.
1263 * However, for TCP, it's better to have two values which are
1264 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
1265 * This allows us to have a TCP Data Payload which is a
1266 * multiple of 8 regardless of what combination of TCP Options
1267 * are in use (always a multiple of 4 bytes) which is
1268 * important for performance reasons. For instance, if no
1269 * options are in use, then we have a 20-byte IP header and a
1270 * 20-byte TCP header. In this case, a 1500-byte MSS would
1271 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
1272 * which is not a multiple of 8. So using an MSS of 1488 in
1273 * this case results in a TCP Data Payload of 1448 bytes which
1274 * is a multiple of 8. On the other hand, if 12-byte TCP Time
1275 * Stamps have been negotiated, then an MTU of 1500 bytes
1276 * results in a TCP Data Payload of 1448 bytes which, as
1277 * above, is a multiple of 8 bytes ...
1279 for (i = 0; i < NMTUS; i++)
1280 if (adap->params.mtus[i] == 1492) {
1281 adap->params.mtus[i] = 1488;
1285 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
1286 adap->params.b_wnd);
1288 t4_init_sge_params(adap);
1289 t4_init_tp_params(adap);
1290 configure_pcie_ext_tag(adap);
1291 configure_vlan_types(adap);
1292 cxgbe_configure_max_ethqsets(adap);
1294 adap->params.drv_memwin = MEMWIN_NIC;
1295 adap->flags |= FW_OK;
1296 dev_debug(adap, "%s: returning zero..\n", __func__);
1300 * Something bad happened. If a command timed out or failed with EIO
1301 * FW does not operate within its spec or something catastrophic
1302 * happened to HW/FW, stop issuing commands.
1305 if (ret != -ETIMEDOUT && ret != -EIO)
1306 t4_fw_bye(adap, adap->mbox);
1311 * t4_os_portmod_changed - handle port module changes
1312 * @adap: the adapter associated with the module change
1313 * @port_id: the port index whose module status has changed
1315 * This is the OS-dependent handler for port module changes. It is
1316 * invoked when a port module is removed or inserted for any OS-specific
1319 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1321 static const char * const mod_str[] = {
1322 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1325 const struct port_info *pi = adap2pinfo(adap, port_id);
1327 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
1328 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1329 else if (pi->mod_type < ARRAY_SIZE(mod_str))
1330 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1331 mod_str[pi->mod_type]);
1332 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1333 dev_info(adap, "Port%d: unsupported port module inserted\n",
1335 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1336 dev_info(adap, "Port%d: unknown port module inserted\n",
1338 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
1339 dev_info(adap, "Port%d: transceiver module error\n",
1342 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1343 pi->port_id, pi->mod_type);
1346 bool cxgbe_force_linkup(struct adapter *adap)
1349 return false; /* force_linkup not required for pf driver */
1351 return adap->devargs.force_link_up;
1355 * link_start - enable a port
1356 * @dev: the port to enable
1358 * Performs the MAC and PHY actions needed to enable a port.
1360 int cxgbe_link_start(struct port_info *pi)
1362 struct adapter *adapter = pi->adapter;
1367 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1368 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN);
1370 conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads;
1373 * We do not set address filters and promiscuity here, the stack does
1374 * that step explicitly.
1376 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1,
1377 !!(conf_offloads & DEV_RX_OFFLOAD_VLAN_STRIP),
1380 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt,
1381 (u8 *)&pi->eth_dev->data->mac_addrs[0]);
1383 pi->xact_addr_filt = ret;
1387 if (ret == 0 && is_pf4(adapter))
1388 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
1392 * Enabling a Virtual Interface can result in an interrupt
1393 * during the processing of the VI Enable command and, in some
1394 * paths, result in an attempt to issue another command in the
1395 * interrupt context. Thus, we disable interrupts during the
1396 * course of the VI Enable command ...
1398 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1402 if (ret == 0 && cxgbe_force_linkup(adapter))
1403 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
1408 * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1410 * @rss_hf: Hash configuration to apply
1412 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1414 struct adapter *adapter = pi->adapter;
1415 const struct sge_eth_rxq *rxq;
1420 /* Should never be called before setting up sge eth rx queues */
1421 if (!(adapter->flags & FULL_INIT_DONE)) {
1422 dev_err(adap, "%s No RXQs available on port %d\n",
1423 __func__, pi->port_id);
1427 /* Don't allow unsupported hash functions */
1428 if (rss_hf & ~CXGBE_RSS_HF_ALL)
1431 if (rss_hf & CXGBE_RSS_HF_IPV4_MASK)
1432 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1434 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1435 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1437 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1438 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1439 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1441 if (rss_hf & CXGBE_RSS_HF_IPV6_MASK)
1442 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1444 if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK)
1445 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1446 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1448 if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK)
1449 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1450 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1451 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1453 rxq = &adapter->sge.ethrxq[pi->first_qset];
1454 rss = rxq[0].rspq.abs_id;
1456 /* If Tunnel All Lookup isn't specified in the global RSS
1457 * Configuration, then we need to specify a default Ingress
1458 * Queue for any ingress packets which aren't hashed. We'll
1459 * use our first ingress queue ...
1461 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1467 * cxgbe_write_rss - write the RSS table for a given port
1469 * @queues: array of queue indices for RSS
1471 * Sets up the portion of the HW RSS table for the port's VI to distribute
1472 * packets to the Rx queues in @queues.
1474 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1478 struct adapter *adapter = pi->adapter;
1479 const struct sge_eth_rxq *rxq;
1481 /* Should never be called before setting up sge eth rx queues */
1482 BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1484 rxq = &adapter->sge.ethrxq[pi->first_qset];
1485 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1489 /* map the queue indices to queue ids */
1490 for (i = 0; i < pi->rss_size; i++, queues++)
1491 rss[i] = rxq[*queues].rspq.abs_id;
1493 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1494 pi->rss_size, rss, pi->rss_size);
1500 * setup_rss - configure RSS
1501 * @adapter: the adapter
1503 * Sets up RSS to distribute packets to multiple receive queues. We
1504 * configure the RSS CPU lookup table to distribute to the number of HW
1505 * receive queues, and the response queue lookup table to narrow that
1506 * down to the response queues actually configured for each port.
1507 * We always configure the RSS mapping for all ports since the mapping
1508 * table has plenty of entries.
1510 int cxgbe_setup_rss(struct port_info *pi)
1513 struct adapter *adapter = pi->adapter;
1515 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1516 __func__, pi->rss_size, pi->n_rx_qsets);
1518 if (!(pi->flags & PORT_RSS_DONE)) {
1519 if (adapter->flags & FULL_INIT_DONE) {
1520 /* Fill default values with equal distribution */
1521 for (j = 0; j < pi->rss_size; j++)
1522 pi->rss[j] = j % pi->n_rx_qsets;
1524 err = cxgbe_write_rss(pi, pi->rss);
1528 err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1531 pi->flags |= PORT_RSS_DONE;
1538 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1540 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1542 /* 0-increment GTS to start the timer and enable interrupts */
1543 t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1544 T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1545 V_SEINTARM(q->intr_params) |
1546 V_INGRESSQID(q->cntxt_id));
1549 void cxgbe_enable_rx_queues(struct port_info *pi)
1551 struct adapter *adap = pi->adapter;
1552 struct sge *s = &adap->sge;
1555 for (i = 0; i < pi->n_rx_qsets; i++)
1556 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1560 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1561 * @port_type: Firmware Port Type
1562 * @fw_caps: Firmware Port Capabilities
1563 * @speed_caps: Device Info Speed Capabilities
1565 * Translate a Firmware Port Capabilities specification to Device Info
1566 * Speed Capabilities.
1568 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1569 unsigned int fw_caps,
1572 #define SET_SPEED(__speed_name) \
1574 *speed_caps |= ETH_LINK_ ## __speed_name; \
1577 #define FW_CAPS_TO_SPEED(__fw_name) \
1579 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1580 SET_SPEED(__fw_name); \
1583 switch (port_type) {
1584 case FW_PORT_TYPE_BT_SGMII:
1585 case FW_PORT_TYPE_BT_XFI:
1586 case FW_PORT_TYPE_BT_XAUI:
1587 FW_CAPS_TO_SPEED(SPEED_100M);
1588 FW_CAPS_TO_SPEED(SPEED_1G);
1589 FW_CAPS_TO_SPEED(SPEED_10G);
1592 case FW_PORT_TYPE_KX4:
1593 case FW_PORT_TYPE_KX:
1594 case FW_PORT_TYPE_FIBER_XFI:
1595 case FW_PORT_TYPE_FIBER_XAUI:
1596 case FW_PORT_TYPE_SFP:
1597 case FW_PORT_TYPE_QSFP_10G:
1598 case FW_PORT_TYPE_QSA:
1599 FW_CAPS_TO_SPEED(SPEED_1G);
1600 FW_CAPS_TO_SPEED(SPEED_10G);
1603 case FW_PORT_TYPE_KR:
1604 SET_SPEED(SPEED_10G);
1607 case FW_PORT_TYPE_BP_AP:
1608 case FW_PORT_TYPE_BP4_AP:
1609 SET_SPEED(SPEED_1G);
1610 SET_SPEED(SPEED_10G);
1613 case FW_PORT_TYPE_BP40_BA:
1614 case FW_PORT_TYPE_QSFP:
1615 SET_SPEED(SPEED_40G);
1618 case FW_PORT_TYPE_CR_QSFP:
1619 case FW_PORT_TYPE_SFP28:
1620 case FW_PORT_TYPE_KR_SFP28:
1621 FW_CAPS_TO_SPEED(SPEED_1G);
1622 FW_CAPS_TO_SPEED(SPEED_10G);
1623 FW_CAPS_TO_SPEED(SPEED_25G);
1626 case FW_PORT_TYPE_CR2_QSFP:
1627 SET_SPEED(SPEED_50G);
1630 case FW_PORT_TYPE_KR4_100G:
1631 case FW_PORT_TYPE_CR4_QSFP:
1632 FW_CAPS_TO_SPEED(SPEED_25G);
1633 FW_CAPS_TO_SPEED(SPEED_40G);
1634 FW_CAPS_TO_SPEED(SPEED_50G);
1635 FW_CAPS_TO_SPEED(SPEED_100G);
1642 #undef FW_CAPS_TO_SPEED
1647 * cxgbe_get_speed_caps - Fetch supported speed capabilities
1648 * @pi: Underlying port's info
1649 * @speed_caps: Device Info speed capabilities
1651 * Fetch supported speed capabilities of the underlying port.
1653 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1657 fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1660 if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1661 *speed_caps |= ETH_LINK_SPEED_FIXED;
1665 * cxgbe_set_link_status - Set device link up or down.
1666 * @pi: Underlying port's info
1667 * @status: 0 - down, 1 - up
1669 * Set the device link up or down.
1671 int cxgbe_set_link_status(struct port_info *pi, bool status)
1673 struct adapter *adapter = pi->adapter;
1676 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, status, status);
1678 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1683 t4_reset_link_config(adapter, pi->pidx);
1689 * cxgb_up - enable the adapter
1690 * @adap: adapter being enabled
1692 * Called when the first port is enabled, this function performs the
1693 * actions necessary to make an adapter operational, such as completing
1694 * the initialization of HW modules, and enabling interrupts.
1696 int cxgbe_up(struct adapter *adap)
1698 enable_rx(adap, &adap->sge.fw_evtq);
1699 t4_sge_tx_monitor_start(adap);
1701 t4_intr_enable(adap);
1702 adap->flags |= FULL_INIT_DONE;
1704 /* TODO: deadman watchdog ?? */
1711 int cxgbe_down(struct port_info *pi)
1713 return cxgbe_set_link_status(pi, false);
1717 * Release resources when all the ports have been stopped.
1719 void cxgbe_close(struct adapter *adapter)
1721 struct port_info *pi;
1724 if (adapter->flags & FULL_INIT_DONE) {
1725 tid_free(&adapter->tids);
1726 t4_cleanup_mpstcam(adapter);
1727 t4_cleanup_clip_tbl(adapter);
1728 t4_cleanup_l2t(adapter);
1729 if (is_pf4(adapter))
1730 t4_intr_disable(adapter);
1731 t4_sge_tx_monitor_stop(adapter);
1732 t4_free_sge_resources(adapter);
1733 for_each_port(adapter, i) {
1734 pi = adap2pinfo(adapter, i);
1736 t4_free_vi(adapter, adapter->mbox,
1737 adapter->pf, 0, pi->viid);
1738 rte_eth_dev_release_port(pi->eth_dev);
1740 adapter->flags &= ~FULL_INIT_DONE;
1743 if (is_pf4(adapter) && (adapter->flags & FW_OK))
1744 t4_fw_bye(adapter, adapter->mbox);
1747 int cxgbe_probe(struct adapter *adapter)
1749 struct port_info *pi;
1755 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1756 chip = t4_get_chip_type(adapter,
1757 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1761 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1762 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1764 adapter->mbox = func;
1767 t4_os_lock_init(&adapter->mbox_lock);
1768 TAILQ_INIT(&adapter->mbox_list);
1769 t4_os_lock_init(&adapter->win0_lock);
1771 err = t4_prep_adapter(adapter);
1775 setup_memwin(adapter);
1776 err = adap_init0(adapter);
1778 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1783 if (!is_t4(adapter->params.chip)) {
1785 * The userspace doorbell BAR is split evenly into doorbell
1786 * regions, each associated with an egress queue. If this
1787 * per-queue region is large enough (at least UDBS_SEG_SIZE)
1788 * then it can be used to submit a tx work request with an
1789 * implied doorbell. Enable write combining on the BAR if
1790 * there is room for such work requests.
1792 int s_qpp, qpp, num_seg;
1794 s_qpp = (S_QUEUESPERPAGEPF0 +
1795 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1797 qpp = 1 << ((t4_read_reg(adapter,
1798 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1799 & M_QUEUESPERPAGEPF0);
1800 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1802 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1804 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1805 if (!adapter->bar2) {
1806 dev_err(adapter, "cannot map device bar2 region\n");
1810 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1814 for_each_port(adapter, i) {
1815 const unsigned int numa_node = rte_socket_id();
1816 char name[RTE_ETH_NAME_MAX_LEN];
1817 struct rte_eth_dev *eth_dev;
1819 snprintf(name, sizeof(name), "%s_%d",
1820 adapter->pdev->device.name, i);
1823 /* First port is already allocated by DPDK */
1824 eth_dev = adapter->eth_dev;
1829 * now do all data allocation - for eth_dev structure,
1830 * and internal (private) data for the remaining ports
1833 /* reserve an ethdev entry */
1834 eth_dev = rte_eth_dev_allocate(name);
1838 eth_dev->data->dev_private =
1839 rte_zmalloc_socket(name, sizeof(struct port_info),
1840 RTE_CACHE_LINE_SIZE, numa_node);
1841 if (!eth_dev->data->dev_private)
1845 pi = eth_dev->data->dev_private;
1846 adapter->port[i] = pi;
1847 pi->eth_dev = eth_dev;
1848 pi->adapter = adapter;
1849 pi->xact_addr_filt = -1;
1853 pi->eth_dev->device = &adapter->pdev->device;
1854 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1855 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1856 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1858 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1860 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1861 RTE_ETHER_ADDR_LEN, 0);
1862 if (!pi->eth_dev->data->mac_addrs) {
1863 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1870 /* First port will be notified by upper layer */
1871 rte_eth_dev_probing_finish(eth_dev);
1875 if (adapter->flags & FW_OK) {
1876 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1878 dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1884 cxgbe_cfg_queues(adapter->eth_dev);
1886 cxgbe_print_adapter_info(adapter);
1887 cxgbe_print_port_info(adapter);
1889 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
1890 adapter->clipt_end);
1891 if (!adapter->clipt) {
1892 /* We tolerate a lack of clip_table, giving up some
1895 dev_warn(adapter, "could not allocate CLIP. Continuing\n");
1898 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
1899 if (!adapter->l2t) {
1900 /* We tolerate a lack of L2T, giving up some functionality */
1901 dev_warn(adapter, "could not allocate L2T. Continuing\n");
1904 if (tid_init(&adapter->tids) < 0) {
1905 /* Disable filtering support */
1906 dev_warn(adapter, "could not allocate TID table, "
1907 "filter support disabled. Continuing\n");
1910 t4_os_lock_init(&adapter->flow_lock);
1912 adapter->mpstcam = t4_init_mpstcam(adapter);
1913 if (!adapter->mpstcam)
1914 dev_warn(adapter, "could not allocate mps tcam table."
1917 if (is_hashfilter(adapter)) {
1918 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) {
1919 u32 hash_base, hash_reg;
1921 hash_reg = A_LE_DB_TID_HASHBASE;
1922 hash_base = t4_read_reg(adapter, hash_reg);
1923 adapter->tids.hash_base = hash_base / 4;
1926 /* Disable hash filtering support */
1928 "Maskless filter support disabled. Continuing\n");
1931 err = cxgbe_init_rss(adapter);
1938 for_each_port(adapter, i) {
1939 pi = adap2pinfo(adapter, i);
1941 t4_free_vi(adapter, adapter->mbox, adapter->pf,
1943 rte_eth_dev_release_port(pi->eth_dev);
1946 if (adapter->flags & FW_OK)
1947 t4_fw_bye(adapter, adapter->mbox);