1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_atomic.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_tailq.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_random.h>
34 #include <rte_kvargs.h>
36 #include "base/common.h"
37 #include "base/t4_regs.h"
38 #include "base/t4_msg.h"
40 #include "cxgbe_pfvf.h"
47 * Allocate a chunk of memory. The allocated memory is cleared.
49 void *t4_alloc_mem(size_t size)
51 return rte_zmalloc(NULL, size, 0);
55 * Free memory allocated through t4_alloc_mem().
57 void t4_free_mem(void *addr)
63 * Response queue handler for the FW event queue.
65 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
66 __rte_unused const struct pkt_gl *gl)
68 u8 opcode = ((const struct rss_header *)rsp)->opcode;
70 rsp++; /* skip RSS header */
73 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
75 if (unlikely(opcode == CPL_FW4_MSG &&
76 ((const struct cpl_fw4_msg *)rsp)->type ==
79 opcode = ((const struct rss_header *)rsp)->opcode;
81 if (opcode != CPL_SGE_EGR_UPDATE) {
82 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
88 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
90 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
91 const struct cpl_fw6_msg *msg = (const void *)rsp;
93 t4_handle_fw_rpl(q->adapter, msg->data);
94 } else if (opcode == CPL_ABORT_RPL_RSS) {
95 const struct cpl_abort_rpl_rss *p = (const void *)rsp;
97 cxgbe_hash_del_filter_rpl(q->adapter, p);
98 } else if (opcode == CPL_SET_TCB_RPL) {
99 const struct cpl_set_tcb_rpl *p = (const void *)rsp;
101 cxgbe_filter_rpl(q->adapter, p);
102 } else if (opcode == CPL_ACT_OPEN_RPL) {
103 const struct cpl_act_open_rpl *p = (const void *)rsp;
105 cxgbe_hash_filter_rpl(q->adapter, p);
106 } else if (opcode == CPL_L2T_WRITE_RPL) {
107 const struct cpl_l2t_write_rpl *p = (const void *)rsp;
109 cxgbe_do_l2t_write_rpl(q->adapter, p);
111 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
119 * Setup sge control queues to pass control information.
121 int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter)
123 struct sge *s = &adapter->sge;
126 for_each_port(adapter, i) {
127 struct port_info *pi = adap2pinfo(adapter, i);
128 char name[RTE_ETH_NAME_MAX_LEN];
129 struct sge_ctrl_txq *q = &s->ctrlq[i];
132 err = t4_sge_alloc_ctrl_txq(adapter, q,
137 dev_err(adapter, "Failed to alloc ctrl txq. Err: %d",
141 snprintf(name, sizeof(name), "%s_ctrl_pool_%d",
142 pi->eth_dev->device->driver->name,
143 pi->eth_dev->data->port_id);
144 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
147 RTE_MBUF_DEFAULT_BUF_SIZE,
152 "Can't create ctrl pool for port %d. Err: %d\n",
153 pi->eth_dev->data->port_id, err);
159 t4_free_sge_resources(adapter);
164 * cxgbe_poll_for_completion: Poll rxq for completion
166 * @ms: milliseconds to delay
167 * @cnt: number of times to poll
168 * @c: completion to check for 'done' status
170 * Polls the rxq for reples until completion is done or the count
173 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int ms,
174 unsigned int cnt, struct t4_completion *c)
177 unsigned int work_done, budget = 32;
182 for (i = 0; i < cnt; i++) {
183 cxgbe_poll(q, NULL, budget, &work_done);
184 t4_os_lock(&c->lock);
186 t4_os_unlock(&c->lock);
189 t4_os_unlock(&c->lock);
195 int cxgbe_setup_sge_fwevtq(struct adapter *adapter)
197 struct sge *s = &adapter->sge;
201 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
202 msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
207 static int closest_timer(const struct sge *s, int time)
209 unsigned int i, match = 0;
210 int delta, min_delta = INT_MAX;
212 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
213 delta = time - s->timer_val[i];
216 if (delta < min_delta) {
224 static int closest_thres(const struct sge *s, int thres)
226 unsigned int i, match = 0;
227 int delta, min_delta = INT_MAX;
229 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
230 delta = thres - s->counter_val[i];
233 if (delta < min_delta) {
242 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
244 * @us: the hold-off time in us, or 0 to disable timer
245 * @cnt: the hold-off packet count, or 0 to disable counter
247 * Sets an Rx queue's interrupt hold-off time and packet count. At least
248 * one of the two needs to be enabled for the queue to generate interrupts.
250 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
253 struct adapter *adap = q->adapter;
254 unsigned int timer_val;
260 new_idx = closest_thres(&adap->sge, cnt);
261 if (q->desc && q->pktcnt_idx != new_idx) {
262 /* the queue has already been created, update it */
263 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
265 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
266 V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
267 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
272 q->pktcnt_idx = new_idx;
275 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
276 closest_timer(&adap->sge, us);
279 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
281 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
282 V_QINTR_CNT_EN(cnt > 0);
287 * Allocate an active-open TID and set it to the supplied value.
289 int cxgbe_alloc_atid(struct tid_info *t, void *data)
293 t4_os_lock(&t->atid_lock);
295 union aopen_entry *p = t->afree;
297 atid = p - t->atid_tab;
302 t4_os_unlock(&t->atid_lock);
307 * Release an active-open TID.
309 void cxgbe_free_atid(struct tid_info *t, unsigned int atid)
311 union aopen_entry *p = &t->atid_tab[atid];
313 t4_os_lock(&t->atid_lock);
317 t4_os_unlock(&t->atid_lock);
321 * Populate a TID_RELEASE WR. Caller must properly size the skb.
323 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid)
325 struct cpl_tid_release *req;
327 req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *);
328 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
332 * Release a TID and inform HW. If we are unable to allocate the release
333 * message we defer to a work queue.
335 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
336 unsigned short family)
338 struct rte_mbuf *mbuf;
339 struct adapter *adap = container_of(t, struct adapter, tids);
341 WARN_ON(tid >= t->ntids);
343 if (t->tid_tab[tid]) {
344 t->tid_tab[tid] = NULL;
345 rte_atomic32_dec(&t->conns_in_use);
346 if (t->hash_base && tid >= t->hash_base) {
347 if (family == FILTER_TYPE_IPV4)
348 rte_atomic32_dec(&t->hash_tids_in_use);
350 if (family == FILTER_TYPE_IPV4)
351 rte_atomic32_dec(&t->tids_in_use);
355 mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool);
357 mbuf->data_len = sizeof(struct cpl_tid_release);
358 mbuf->pkt_len = mbuf->data_len;
359 mk_tid_release(mbuf, tid);
360 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf);
367 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid,
368 unsigned short family)
370 t->tid_tab[tid] = data;
371 if (t->hash_base && tid >= t->hash_base) {
372 if (family == FILTER_TYPE_IPV4)
373 rte_atomic32_inc(&t->hash_tids_in_use);
375 if (family == FILTER_TYPE_IPV4)
376 rte_atomic32_inc(&t->tids_in_use);
379 rte_atomic32_inc(&t->conns_in_use);
385 static void tid_free(struct tid_info *t)
389 rte_bitmap_free(t->ftid_bmap);
391 if (t->ftid_bmap_array)
392 t4_os_free(t->ftid_bmap_array);
394 t4_os_free(t->tid_tab);
397 memset(t, 0, sizeof(struct tid_info));
401 * Allocate and initialize the TID tables. Returns 0 on success.
403 static int tid_init(struct tid_info *t)
406 unsigned int ftid_bmap_size;
407 unsigned int natids = t->natids;
408 unsigned int max_ftids = t->nftids;
410 ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
411 size = t->ntids * sizeof(*t->tid_tab) +
412 max_ftids * sizeof(*t->ftid_tab) +
413 natids * sizeof(*t->atid_tab);
415 t->tid_tab = t4_os_alloc(size);
419 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
420 t->ftid_tab = (struct filter_entry *)&t->atid_tab[t->natids];
421 t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
422 if (!t->ftid_bmap_array) {
427 t4_os_lock_init(&t->atid_lock);
428 t4_os_lock_init(&t->ftid_lock);
432 rte_atomic32_init(&t->tids_in_use);
433 rte_atomic32_set(&t->tids_in_use, 0);
434 rte_atomic32_init(&t->conns_in_use);
435 rte_atomic32_set(&t->conns_in_use, 0);
437 /* Setup the free list for atid_tab and clear the stid bitmap. */
440 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
441 t->afree = t->atid_tab;
444 t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
454 static inline bool is_x_1g_port(const struct link_config *lc)
456 return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
459 static inline bool is_x_10g_port(const struct link_config *lc)
461 unsigned int speeds, high_speeds;
463 speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
464 high_speeds = speeds &
465 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
467 return high_speeds != 0;
470 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
471 unsigned int us, unsigned int cnt,
472 unsigned int size, unsigned int iqe_size)
475 cxgb4_set_rspq_intr_params(q, us, cnt);
476 q->iqe_len = iqe_size;
480 int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev)
482 struct port_info *pi = eth_dev->data->dev_private;
483 struct adapter *adap = pi->adapter;
484 struct sge *s = &adap->sge;
485 unsigned int max_queues = s->max_ethqsets / adap->params.nports;
487 if ((eth_dev->data->nb_rx_queues < 1) ||
488 (eth_dev->data->nb_tx_queues < 1))
491 if ((eth_dev->data->nb_rx_queues > max_queues) ||
492 (eth_dev->data->nb_tx_queues > max_queues))
495 if (eth_dev->data->nb_rx_queues > pi->rss_size)
498 /* We must configure RSS, since config has changed*/
499 pi->flags &= ~PORT_RSS_DONE;
501 pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
502 pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
507 void cxgbe_cfg_queues(struct rte_eth_dev *eth_dev)
509 struct port_info *pi = eth_dev->data->dev_private;
510 struct adapter *adap = pi->adapter;
511 struct sge *s = &adap->sge;
512 unsigned int i, nb_ports = 0, qidx = 0;
513 unsigned int q_per_port = 0;
515 if (!(adap->flags & CFG_QUEUES)) {
516 for_each_port(adap, i) {
517 struct port_info *tpi = adap2pinfo(adap, i);
519 nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
520 is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
524 * We default up to # of cores queues per 1G/10G port.
527 q_per_port = (s->max_ethqsets -
528 (adap->params.nports - nb_ports)) /
531 if (q_per_port > rte_lcore_count())
532 q_per_port = rte_lcore_count();
534 for_each_port(adap, i) {
535 struct port_info *pi = adap2pinfo(adap, i);
537 pi->first_qset = qidx;
539 /* Initially n_rx_qsets == n_tx_qsets */
540 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
541 is_x_1g_port(&pi->link_cfg)) ?
543 pi->n_tx_qsets = pi->n_rx_qsets;
545 if (pi->n_rx_qsets > pi->rss_size)
546 pi->n_rx_qsets = pi->rss_size;
548 qidx += pi->n_rx_qsets;
551 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
552 struct sge_eth_rxq *r = &s->ethrxq[i];
554 init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
556 r->fl.size = (r->usembufs ? 1024 : 72);
559 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
560 s->ethtxq[i].q.size = 1024;
562 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
563 adap->flags |= CFG_QUEUES;
567 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
569 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
573 void cxgbe_stats_reset(struct port_info *pi)
575 t4_clr_port_stats(pi->adapter, pi->tx_chan);
578 static void setup_memwin(struct adapter *adap)
582 /* For T5, only relative offset inside the PCIe BAR is passed */
583 mem_win0_base = MEMWIN0_BASE;
586 * Set up memory window for accessing adapter memory ranges. (Read
587 * back MA register to ensure that changes propagate before we attempt
588 * to use the new values.)
591 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
593 mem_win0_base | V_BIR(0) |
594 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
596 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
600 int cxgbe_init_rss(struct adapter *adap)
607 err = t4_init_rss_mode(adap, adap->mbox);
612 for_each_port(adap, i) {
613 struct port_info *pi = adap2pinfo(adap, i);
615 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
619 pi->rss_hf = CXGBE_RSS_HF_ALL;
625 * Dump basic information about the adapter.
627 void cxgbe_print_adapter_info(struct adapter *adap)
630 * Hardware/Firmware/etc. Version/Revision IDs.
632 t4_dump_version_info(adap);
635 void cxgbe_print_port_info(struct adapter *adap)
639 struct rte_pci_addr *loc = &adap->pdev->addr;
641 for_each_port(adap, i) {
642 const struct port_info *pi = adap2pinfo(adap, i);
645 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
646 bufp += sprintf(bufp, "100M/");
647 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
648 bufp += sprintf(bufp, "1G/");
649 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
650 bufp += sprintf(bufp, "10G/");
651 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
652 bufp += sprintf(bufp, "25G/");
653 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
654 bufp += sprintf(bufp, "40G/");
655 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
656 bufp += sprintf(bufp, "50G/");
657 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
658 bufp += sprintf(bufp, "100G/");
661 sprintf(bufp, "BASE-%s",
662 t4_get_port_type_description(
663 (enum fw_port_type)pi->port_type));
666 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
667 loc->domain, loc->bus, loc->devid, loc->function,
668 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
669 (adap->flags & USING_MSIX) ? " MSI-X" :
670 (adap->flags & USING_MSI) ? " MSI" : "");
674 static int check_devargs_handler(const char *key, const char *value, void *p)
676 if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) ||
677 !strncmp(key, CXGBE_DEVARG_CMN_TX_MODE_LATENCY, strlen(key)) ||
678 !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) {
679 if (!strncmp(value, "1", 1)) {
680 bool *dst_val = (bool *)p;
689 static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key,
692 struct rte_kvargs *kvlist;
698 kvlist = rte_kvargs_parse(devargs->args, NULL);
702 if (!rte_kvargs_count(kvlist, key))
705 ret = rte_kvargs_process(kvlist, key, check_devargs_handler, p);
708 rte_kvargs_free(kvlist);
713 static void cxgbe_get_devargs_int(struct adapter *adap, bool *dst,
714 const char *key, bool default_value)
716 struct rte_pci_device *pdev = adap->pdev;
718 bool devarg_value = default_value;
720 *dst = default_value;
724 ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value);
731 void cxgbe_process_devargs(struct adapter *adap)
733 cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan,
734 CXGBE_DEVARG_CMN_KEEP_OVLAN, false);
735 cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency,
736 CXGBE_DEVARG_CMN_TX_MODE_LATENCY, false);
737 cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up,
738 CXGBE_DEVARG_VF_FORCE_LINK_UP, false);
741 static void configure_vlan_types(struct adapter *adapter)
745 for_each_port(adapter, i) {
746 /* OVLAN Type 0x88a8 */
747 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
748 V_OVLAN_MASK(M_OVLAN_MASK) |
749 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
750 V_OVLAN_MASK(M_OVLAN_MASK) |
751 V_OVLAN_ETYPE(0x88a8));
752 /* OVLAN Type 0x9100 */
753 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
754 V_OVLAN_MASK(M_OVLAN_MASK) |
755 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
756 V_OVLAN_MASK(M_OVLAN_MASK) |
757 V_OVLAN_ETYPE(0x9100));
760 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
761 V_IVLAN_ETYPE(M_IVLAN_ETYPE),
762 V_IVLAN_ETYPE(0x8100));
764 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
765 F_OVLAN_EN0 | F_OVLAN_EN1 |
767 F_OVLAN_EN0 | F_OVLAN_EN1 |
771 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1),
772 V_RM_OVLAN(!adapter->devargs.keep_ovlan));
775 static void configure_pcie_ext_tag(struct adapter *adapter)
778 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
784 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
785 v |= PCI_EXP_DEVCTL_EXT_TAG;
786 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
787 if (is_t6(adapter->params.chip)) {
788 t4_set_reg_field(adapter, A_PCIE_CFG2,
789 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
791 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
792 V_T6_MINTAG(M_T6_MINTAG),
795 t4_set_reg_field(adapter, A_PCIE_CFG2,
796 V_TOTMAXTAG(M_TOTMAXTAG),
798 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
805 /* Figure out how many Queue Sets we can support */
806 void cxgbe_configure_max_ethqsets(struct adapter *adapter)
808 unsigned int ethqsets;
811 * We need to reserve an Ingress Queue for the Asynchronous Firmware
814 * For each Queue Set, we'll need the ability to allocate two Egress
815 * Contexts -- one for the Ingress Queue Free List and one for the TX
818 if (is_pf4(adapter)) {
819 struct pf_resources *pfres = &adapter->params.pfres;
821 ethqsets = pfres->niqflint - 1;
822 if (pfres->neq < ethqsets * 2)
823 ethqsets = pfres->neq / 2;
825 struct vf_resources *vfres = &adapter->params.vfres;
827 ethqsets = vfres->niqflint - 1;
828 if (vfres->nethctrl != ethqsets)
829 ethqsets = min(vfres->nethctrl, ethqsets);
830 if (vfres->neq < ethqsets * 2)
831 ethqsets = vfres->neq / 2;
834 if (ethqsets > MAX_ETH_QSETS)
835 ethqsets = MAX_ETH_QSETS;
836 adapter->sge.max_ethqsets = ethqsets;
840 * Tweak configuration based on system architecture, etc. Most of these have
841 * defaults assigned to them by Firmware Configuration Files (if we're using
842 * them) but need to be explicitly set if we're using hard-coded
843 * initialization. So these are essentially common tweaks/settings for
844 * Configuration Files and hard-coded initialization ...
846 static int adap_init0_tweaks(struct adapter *adapter)
851 * Fix up various Host-Dependent Parameters like Page Size, Cache
852 * Line Size, etc. The firmware default is for a 4KB Page Size and
853 * 64B Cache Line Size ...
855 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
859 * Keep the chip default offset to deliver Ingress packets into our
860 * DMA buffers to zero
863 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
864 V_PKTSHIFT(rx_dma_offset));
866 t4_set_reg_field(adapter, A_SGE_FLM_CFG,
867 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
868 V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
870 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
871 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
873 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
874 V_IDMAARBROUNDROBIN(1U));
877 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
878 * adds the pseudo header itself.
880 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
881 F_CSUM_HAS_PSEUDO_HDR, 0);
887 * Attempt to initialize the adapter via a Firmware Configuration File.
889 static int adap_init0_config(struct adapter *adapter, int reset)
891 struct fw_caps_config_cmd caps_cmd;
892 unsigned long mtype = 0, maddr = 0;
893 u32 finiver, finicsum, cfcsum;
895 int config_issued = 0;
897 char config_name[20];
900 * Reset device if necessary.
903 ret = t4_fw_reset(adapter, adapter->mbox,
904 F_PIORSTMODE | F_PIORST);
906 dev_warn(adapter, "Firmware reset failed, error %d\n",
912 cfg_addr = t4_flash_cfg_addr(adapter);
915 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
920 strcpy(config_name, "On Flash");
921 mtype = FW_MEMTYPE_CF_FLASH;
925 * Issue a Capability Configuration command to the firmware to get it
926 * to parse the Configuration File. We don't use t4_fw_config_file()
927 * because we want the ability to modify various features after we've
928 * processed the configuration file ...
930 memset(&caps_cmd, 0, sizeof(caps_cmd));
931 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
932 F_FW_CMD_REQUEST | F_FW_CMD_READ);
933 caps_cmd.cfvalid_to_len16 =
934 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
935 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
936 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
938 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
941 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
942 * Configuration File in FLASH), our last gasp effort is to use the
943 * Firmware Configuration File which is embedded in the firmware. A
944 * very few early versions of the firmware didn't have one embedded
945 * but we can ignore those.
947 if (ret == -ENOENT) {
948 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
951 memset(&caps_cmd, 0, sizeof(caps_cmd));
952 caps_cmd.op_to_write =
953 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
954 F_FW_CMD_REQUEST | F_FW_CMD_READ);
955 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
956 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
957 sizeof(caps_cmd), &caps_cmd);
958 strcpy(config_name, "Firmware Default");
965 finiver = be32_to_cpu(caps_cmd.finiver);
966 finicsum = be32_to_cpu(caps_cmd.finicsum);
967 cfcsum = be32_to_cpu(caps_cmd.cfcsum);
968 if (finicsum != cfcsum)
969 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
973 * If we're a pure NIC driver then disable all offloading facilities.
974 * This will allow the firmware to optimize aspects of the hardware
975 * configuration which will result in improved performance.
977 caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD);
978 caps_cmd.toecaps = 0;
979 caps_cmd.iscsicaps = 0;
980 caps_cmd.rdmacaps = 0;
981 caps_cmd.fcoecaps = 0;
984 * And now tell the firmware to use the configuration we just loaded.
986 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
987 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
988 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
989 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
992 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
998 * Tweak configuration based on system architecture, etc.
1000 ret = adap_init0_tweaks(adapter);
1002 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
1007 * And finally tell the firmware to initialize itself using the
1008 * parameters from the Configuration File.
1010 ret = t4_fw_initialize(adapter, adapter->mbox);
1012 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
1018 * Return successfully and note that we're operating with parameters
1019 * not supplied by the driver, rather than from hard-wired
1020 * initialization constants buried in the driver.
1023 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
1024 config_name, finiver, cfcsum);
1029 * Something bad happened. Return the error ... (If the "error"
1030 * is that there's no Configuration File on the adapter we don't
1031 * want to issue a warning since this is fairly common.)
1034 if (config_issued && ret != -ENOENT)
1035 dev_warn(adapter, "\"%s\" configuration file error %d\n",
1038 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
1042 static int adap_init0(struct adapter *adap)
1044 struct fw_caps_config_cmd caps_cmd;
1047 enum dev_state state;
1048 u32 params[7], val[7];
1050 int mbox = adap->mbox;
1053 * Contact FW, advertising Master capability.
1055 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
1057 dev_err(adap, "%s: could not connect to FW, error %d\n",
1062 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
1066 adap->flags |= MASTER_PF;
1068 if (state == DEV_STATE_INIT) {
1070 * Force halt and reset FW because a previous instance may have
1071 * exited abnormally without properly shutting down
1073 ret = t4_fw_halt(adap, adap->mbox, reset);
1075 dev_err(adap, "Failed to halt. Exit.\n");
1079 ret = t4_fw_restart(adap, adap->mbox, reset);
1081 dev_err(adap, "Failed to restart. Exit.\n");
1084 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
1087 t4_get_version_info(adap);
1089 ret = t4_get_core_clock(adap, &adap->params.vpd);
1091 dev_err(adap, "%s: could not get core clock, error %d\n",
1097 * If the firmware is initialized already (and we're not forcing a
1098 * master initialization), note that we're living with existing
1099 * adapter parameters. Otherwise, it's time to try initializing the
1102 if (state == DEV_STATE_INIT) {
1103 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
1104 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
1106 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
1108 ret = adap_init0_config(adap, reset);
1109 if (ret == -ENOENT) {
1111 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
1116 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
1120 /* Now that we've successfully configured and initialized the adapter
1121 * (or found it already initialized), we can ask the Firmware what
1122 * resources it has provisioned for us.
1124 ret = t4_get_pfres(adap);
1126 dev_err(adap->pdev_dev,
1127 "Unable to retrieve resource provisioning info\n");
1131 /* Find out what ports are available to us. */
1132 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1133 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
1134 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
1136 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
1141 adap->params.nports = hweight32(port_vec);
1142 adap->params.portvec = port_vec;
1144 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
1145 adap->params.nports);
1148 * Give the SGE code a chance to pull in anything that it needs ...
1149 * Note that this must be called after we retrieve our VPD parameters
1150 * in order to know how to convert core ticks to seconds, etc.
1152 ret = t4_sge_init(adap);
1154 dev_err(adap, "t4_sge_init failed with error %d\n",
1160 * Grab some of our basic fundamental operating parameters.
1162 params[0] = CXGBE_FW_PARAM_PFVF(L2T_START);
1163 params[1] = CXGBE_FW_PARAM_PFVF(L2T_END);
1164 params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START);
1165 params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END);
1166 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val);
1169 adap->l2t_start = val[0];
1170 adap->l2t_end = val[1];
1171 adap->tids.ftid_base = val[2];
1172 adap->tids.nftids = val[3] - val[2] + 1;
1174 params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START);
1175 params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END);
1176 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
1179 adap->clipt_start = val[0];
1180 adap->clipt_end = val[1];
1183 * Get device capabilities so we can determine what resources we need
1186 memset(&caps_cmd, 0, sizeof(caps_cmd));
1187 caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1188 F_FW_CMD_REQUEST | F_FW_CMD_READ);
1189 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
1190 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
1195 if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) &&
1196 is_t6(adap->params.chip)) {
1197 if (cxgbe_init_hash_filter(adap) < 0)
1201 /* See if FW supports FW_FILTER2 work request */
1202 if (is_t4(adap->params.chip)) {
1203 adap->params.filter2_wr_support = 0;
1205 params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR);
1206 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1208 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
1211 /* Check if FW supports returning vin.
1212 * If this is not supported, driver will interpret
1213 * these values from viid.
1215 params[0] = CXGBE_FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
1216 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1218 adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
1220 /* query tid-related parameters */
1221 params[0] = CXGBE_FW_PARAM_DEV(NTID);
1222 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
1226 adap->tids.ntids = val[0];
1227 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
1229 /* If we're running on newer firmware, let it know that we're
1230 * prepared to deal with encapsulated CPL messages. Older
1231 * firmware won't understand this and we'll just get
1232 * unencapsulated messages ...
1234 params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
1236 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1239 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
1240 * capability. Earlier versions of the firmware didn't have the
1241 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
1242 * permission to use ULPTX MEMWRITE DSGL.
1244 if (is_t4(adap->params.chip)) {
1245 adap->params.ulptx_memwrite_dsgl = false;
1247 params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
1248 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1250 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
1253 /* Query for max number of packets that can be coalesced for Tx */
1254 params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
1255 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1256 if (!ret && val[0] > 0)
1257 adap->params.max_tx_coalesce_num = val[0];
1259 adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM;
1262 * The MTU/MSS Table is initialized by now, so load their values. If
1263 * we're initializing the adapter, then we'll make any modifications
1264 * we want to the MTU/MSS Table and also initialize the congestion
1267 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
1268 if (state != DEV_STATE_INIT) {
1272 * The default MTU Table contains values 1492 and 1500.
1273 * However, for TCP, it's better to have two values which are
1274 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
1275 * This allows us to have a TCP Data Payload which is a
1276 * multiple of 8 regardless of what combination of TCP Options
1277 * are in use (always a multiple of 4 bytes) which is
1278 * important for performance reasons. For instance, if no
1279 * options are in use, then we have a 20-byte IP header and a
1280 * 20-byte TCP header. In this case, a 1500-byte MSS would
1281 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
1282 * which is not a multiple of 8. So using an MSS of 1488 in
1283 * this case results in a TCP Data Payload of 1448 bytes which
1284 * is a multiple of 8. On the other hand, if 12-byte TCP Time
1285 * Stamps have been negotiated, then an MTU of 1500 bytes
1286 * results in a TCP Data Payload of 1448 bytes which, as
1287 * above, is a multiple of 8 bytes ...
1289 for (i = 0; i < NMTUS; i++)
1290 if (adap->params.mtus[i] == 1492) {
1291 adap->params.mtus[i] = 1488;
1295 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
1296 adap->params.b_wnd);
1298 t4_init_sge_params(adap);
1299 t4_init_tp_params(adap);
1300 configure_pcie_ext_tag(adap);
1301 configure_vlan_types(adap);
1302 cxgbe_configure_max_ethqsets(adap);
1304 adap->params.drv_memwin = MEMWIN_NIC;
1305 adap->flags |= FW_OK;
1306 dev_debug(adap, "%s: returning zero..\n", __func__);
1310 * Something bad happened. If a command timed out or failed with EIO
1311 * FW does not operate within its spec or something catastrophic
1312 * happened to HW/FW, stop issuing commands.
1315 if (ret != -ETIMEDOUT && ret != -EIO)
1316 t4_fw_bye(adap, adap->mbox);
1321 * t4_os_portmod_changed - handle port module changes
1322 * @adap: the adapter associated with the module change
1323 * @port_id: the port index whose module status has changed
1325 * This is the OS-dependent handler for port module changes. It is
1326 * invoked when a port module is removed or inserted for any OS-specific
1329 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1331 static const char * const mod_str[] = {
1332 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1335 const struct port_info *pi = adap2pinfo(adap, port_id);
1337 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
1338 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1339 else if (pi->mod_type < ARRAY_SIZE(mod_str))
1340 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1341 mod_str[pi->mod_type]);
1342 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1343 dev_info(adap, "Port%d: unsupported port module inserted\n",
1345 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1346 dev_info(adap, "Port%d: unknown port module inserted\n",
1348 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
1349 dev_info(adap, "Port%d: transceiver module error\n",
1352 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1353 pi->port_id, pi->mod_type);
1356 bool cxgbe_force_linkup(struct adapter *adap)
1359 return false; /* force_linkup not required for pf driver */
1361 return adap->devargs.force_link_up;
1365 * link_start - enable a port
1366 * @dev: the port to enable
1368 * Performs the MAC and PHY actions needed to enable a port.
1370 int cxgbe_link_start(struct port_info *pi)
1372 struct adapter *adapter = pi->adapter;
1377 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1378 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN);
1380 conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads;
1383 * We do not set address filters and promiscuity here, the stack does
1384 * that step explicitly.
1386 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1,
1387 !!(conf_offloads & DEV_RX_OFFLOAD_VLAN_STRIP),
1390 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt,
1391 (u8 *)&pi->eth_dev->data->mac_addrs[0]);
1393 pi->xact_addr_filt = ret;
1397 if (ret == 0 && is_pf4(adapter))
1398 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
1402 * Enabling a Virtual Interface can result in an interrupt
1403 * during the processing of the VI Enable command and, in some
1404 * paths, result in an attempt to issue another command in the
1405 * interrupt context. Thus, we disable interrupts during the
1406 * course of the VI Enable command ...
1408 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1412 if (ret == 0 && cxgbe_force_linkup(adapter))
1413 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
1418 * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1420 * @rss_hf: Hash configuration to apply
1422 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1424 struct adapter *adapter = pi->adapter;
1425 const struct sge_eth_rxq *rxq;
1430 /* Should never be called before setting up sge eth rx queues */
1431 if (!(adapter->flags & FULL_INIT_DONE)) {
1432 dev_err(adap, "%s No RXQs available on port %d\n",
1433 __func__, pi->port_id);
1437 /* Don't allow unsupported hash functions */
1438 if (rss_hf & ~CXGBE_RSS_HF_ALL)
1441 if (rss_hf & CXGBE_RSS_HF_IPV4_MASK)
1442 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1444 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1445 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1447 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1448 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1449 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1451 if (rss_hf & CXGBE_RSS_HF_IPV6_MASK)
1452 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1454 if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK)
1455 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1456 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1458 if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK)
1459 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1460 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1461 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1463 rxq = &adapter->sge.ethrxq[pi->first_qset];
1464 rss = rxq[0].rspq.abs_id;
1466 /* If Tunnel All Lookup isn't specified in the global RSS
1467 * Configuration, then we need to specify a default Ingress
1468 * Queue for any ingress packets which aren't hashed. We'll
1469 * use our first ingress queue ...
1471 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1477 * cxgbe_write_rss - write the RSS table for a given port
1479 * @queues: array of queue indices for RSS
1481 * Sets up the portion of the HW RSS table for the port's VI to distribute
1482 * packets to the Rx queues in @queues.
1484 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1488 struct adapter *adapter = pi->adapter;
1489 const struct sge_eth_rxq *rxq;
1491 /* Should never be called before setting up sge eth rx queues */
1492 BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1494 rxq = &adapter->sge.ethrxq[pi->first_qset];
1495 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1499 /* map the queue indices to queue ids */
1500 for (i = 0; i < pi->rss_size; i++, queues++)
1501 rss[i] = rxq[*queues].rspq.abs_id;
1503 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1504 pi->rss_size, rss, pi->rss_size);
1510 * setup_rss - configure RSS
1511 * @adapter: the adapter
1513 * Sets up RSS to distribute packets to multiple receive queues. We
1514 * configure the RSS CPU lookup table to distribute to the number of HW
1515 * receive queues, and the response queue lookup table to narrow that
1516 * down to the response queues actually configured for each port.
1517 * We always configure the RSS mapping for all ports since the mapping
1518 * table has plenty of entries.
1520 int cxgbe_setup_rss(struct port_info *pi)
1523 struct adapter *adapter = pi->adapter;
1525 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1526 __func__, pi->rss_size, pi->n_rx_qsets);
1528 if (!(pi->flags & PORT_RSS_DONE)) {
1529 if (adapter->flags & FULL_INIT_DONE) {
1530 /* Fill default values with equal distribution */
1531 for (j = 0; j < pi->rss_size; j++)
1532 pi->rss[j] = j % pi->n_rx_qsets;
1534 err = cxgbe_write_rss(pi, pi->rss);
1538 err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1541 pi->flags |= PORT_RSS_DONE;
1548 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1550 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1552 /* 0-increment GTS to start the timer and enable interrupts */
1553 t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1554 T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1555 V_SEINTARM(q->intr_params) |
1556 V_INGRESSQID(q->cntxt_id));
1559 void cxgbe_enable_rx_queues(struct port_info *pi)
1561 struct adapter *adap = pi->adapter;
1562 struct sge *s = &adap->sge;
1565 for (i = 0; i < pi->n_rx_qsets; i++)
1566 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1570 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1571 * @port_type: Firmware Port Type
1572 * @fw_caps: Firmware Port Capabilities
1573 * @speed_caps: Device Info Speed Capabilities
1575 * Translate a Firmware Port Capabilities specification to Device Info
1576 * Speed Capabilities.
1578 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1579 unsigned int fw_caps,
1582 #define SET_SPEED(__speed_name) \
1584 *speed_caps |= ETH_LINK_ ## __speed_name; \
1587 #define FW_CAPS_TO_SPEED(__fw_name) \
1589 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1590 SET_SPEED(__fw_name); \
1593 switch (port_type) {
1594 case FW_PORT_TYPE_BT_SGMII:
1595 case FW_PORT_TYPE_BT_XFI:
1596 case FW_PORT_TYPE_BT_XAUI:
1597 FW_CAPS_TO_SPEED(SPEED_100M);
1598 FW_CAPS_TO_SPEED(SPEED_1G);
1599 FW_CAPS_TO_SPEED(SPEED_10G);
1602 case FW_PORT_TYPE_KX4:
1603 case FW_PORT_TYPE_KX:
1604 case FW_PORT_TYPE_FIBER_XFI:
1605 case FW_PORT_TYPE_FIBER_XAUI:
1606 case FW_PORT_TYPE_SFP:
1607 case FW_PORT_TYPE_QSFP_10G:
1608 case FW_PORT_TYPE_QSA:
1609 FW_CAPS_TO_SPEED(SPEED_1G);
1610 FW_CAPS_TO_SPEED(SPEED_10G);
1613 case FW_PORT_TYPE_KR:
1614 SET_SPEED(SPEED_10G);
1617 case FW_PORT_TYPE_BP_AP:
1618 case FW_PORT_TYPE_BP4_AP:
1619 SET_SPEED(SPEED_1G);
1620 SET_SPEED(SPEED_10G);
1623 case FW_PORT_TYPE_BP40_BA:
1624 case FW_PORT_TYPE_QSFP:
1625 SET_SPEED(SPEED_40G);
1628 case FW_PORT_TYPE_CR_QSFP:
1629 case FW_PORT_TYPE_SFP28:
1630 case FW_PORT_TYPE_KR_SFP28:
1631 FW_CAPS_TO_SPEED(SPEED_1G);
1632 FW_CAPS_TO_SPEED(SPEED_10G);
1633 FW_CAPS_TO_SPEED(SPEED_25G);
1636 case FW_PORT_TYPE_CR2_QSFP:
1637 SET_SPEED(SPEED_50G);
1640 case FW_PORT_TYPE_KR4_100G:
1641 case FW_PORT_TYPE_CR4_QSFP:
1642 FW_CAPS_TO_SPEED(SPEED_25G);
1643 FW_CAPS_TO_SPEED(SPEED_40G);
1644 FW_CAPS_TO_SPEED(SPEED_50G);
1645 FW_CAPS_TO_SPEED(SPEED_100G);
1652 #undef FW_CAPS_TO_SPEED
1657 * cxgbe_get_speed_caps - Fetch supported speed capabilities
1658 * @pi: Underlying port's info
1659 * @speed_caps: Device Info speed capabilities
1661 * Fetch supported speed capabilities of the underlying port.
1663 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1667 fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1670 if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1671 *speed_caps |= ETH_LINK_SPEED_FIXED;
1675 * cxgbe_set_link_status - Set device link up or down.
1676 * @pi: Underlying port's info
1677 * @status: 0 - down, 1 - up
1679 * Set the device link up or down.
1681 int cxgbe_set_link_status(struct port_info *pi, bool status)
1683 struct adapter *adapter = pi->adapter;
1686 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, status, status);
1688 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1693 t4_reset_link_config(adapter, pi->pidx);
1699 * cxgb_up - enable the adapter
1700 * @adap: adapter being enabled
1702 * Called when the first port is enabled, this function performs the
1703 * actions necessary to make an adapter operational, such as completing
1704 * the initialization of HW modules, and enabling interrupts.
1706 int cxgbe_up(struct adapter *adap)
1708 enable_rx(adap, &adap->sge.fw_evtq);
1709 t4_sge_tx_monitor_start(adap);
1711 t4_intr_enable(adap);
1712 adap->flags |= FULL_INIT_DONE;
1714 /* TODO: deadman watchdog ?? */
1721 int cxgbe_down(struct port_info *pi)
1723 return cxgbe_set_link_status(pi, false);
1727 * Release resources when all the ports have been stopped.
1729 void cxgbe_close(struct adapter *adapter)
1731 struct port_info *pi;
1734 if (adapter->flags & FULL_INIT_DONE) {
1735 tid_free(&adapter->tids);
1736 t4_cleanup_mpstcam(adapter);
1737 t4_cleanup_clip_tbl(adapter);
1738 t4_cleanup_l2t(adapter);
1739 t4_cleanup_smt(adapter);
1740 if (is_pf4(adapter))
1741 t4_intr_disable(adapter);
1742 t4_sge_tx_monitor_stop(adapter);
1743 t4_free_sge_resources(adapter);
1744 for_each_port(adapter, i) {
1745 pi = adap2pinfo(adapter, i);
1747 t4_free_vi(adapter, adapter->mbox,
1748 adapter->pf, 0, pi->viid);
1749 rte_eth_dev_release_port(pi->eth_dev);
1751 adapter->flags &= ~FULL_INIT_DONE;
1754 if (is_pf4(adapter) && (adapter->flags & FW_OK))
1755 t4_fw_bye(adapter, adapter->mbox);
1758 static void adap_smt_index(struct adapter *adapter, u32 *smt_start_idx,
1761 u32 params[2], smt_val[2];
1764 params[0] = CXGBE_FW_PARAM_PFVF(GET_SMT_START);
1765 params[1] = CXGBE_FW_PARAM_PFVF(GET_SMT_SIZE);
1767 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
1768 2, params, smt_val);
1770 /* if FW doesn't recognize this command then set it to default setting
1771 * which is start index as 0 and size as 256.
1775 *smt_size = SMT_SIZE;
1777 *smt_start_idx = smt_val[0];
1778 /* smt size can be zero, if nsmt is not yet configured in
1779 * the config file or set as zero, then configure all the
1780 * remaining entries to this PF itself.
1783 *smt_size = SMT_SIZE - *smt_start_idx;
1785 *smt_size = smt_val[1];
1789 int cxgbe_probe(struct adapter *adapter)
1791 u32 smt_start_idx, smt_size;
1792 struct port_info *pi;
1798 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1799 chip = t4_get_chip_type(adapter,
1800 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1804 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1805 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1807 adapter->mbox = func;
1810 t4_os_lock_init(&adapter->mbox_lock);
1811 TAILQ_INIT(&adapter->mbox_list);
1812 t4_os_lock_init(&adapter->win0_lock);
1814 err = t4_prep_adapter(adapter);
1818 setup_memwin(adapter);
1819 err = adap_init0(adapter);
1821 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1826 if (!is_t4(adapter->params.chip)) {
1828 * The userspace doorbell BAR is split evenly into doorbell
1829 * regions, each associated with an egress queue. If this
1830 * per-queue region is large enough (at least UDBS_SEG_SIZE)
1831 * then it can be used to submit a tx work request with an
1832 * implied doorbell. Enable write combining on the BAR if
1833 * there is room for such work requests.
1835 int s_qpp, qpp, num_seg;
1837 s_qpp = (S_QUEUESPERPAGEPF0 +
1838 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1840 qpp = 1 << ((t4_read_reg(adapter,
1841 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1842 & M_QUEUESPERPAGEPF0);
1843 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1845 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1847 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1848 if (!adapter->bar2) {
1849 dev_err(adapter, "cannot map device bar2 region\n");
1853 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1857 for_each_port(adapter, i) {
1858 const unsigned int numa_node = rte_socket_id();
1859 char name[RTE_ETH_NAME_MAX_LEN];
1860 struct rte_eth_dev *eth_dev;
1862 snprintf(name, sizeof(name), "%s_%d",
1863 adapter->pdev->device.name, i);
1866 /* First port is already allocated by DPDK */
1867 eth_dev = adapter->eth_dev;
1872 * now do all data allocation - for eth_dev structure,
1873 * and internal (private) data for the remaining ports
1876 /* reserve an ethdev entry */
1877 eth_dev = rte_eth_dev_allocate(name);
1881 eth_dev->data->dev_private =
1882 rte_zmalloc_socket(name, sizeof(struct port_info),
1883 RTE_CACHE_LINE_SIZE, numa_node);
1884 if (!eth_dev->data->dev_private)
1888 pi = eth_dev->data->dev_private;
1889 adapter->port[i] = pi;
1890 pi->eth_dev = eth_dev;
1891 pi->adapter = adapter;
1892 pi->xact_addr_filt = -1;
1896 pi->eth_dev->device = &adapter->pdev->device;
1897 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1898 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1899 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1901 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1903 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1904 RTE_ETHER_ADDR_LEN, 0);
1905 if (!pi->eth_dev->data->mac_addrs) {
1906 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1913 /* First port will be notified by upper layer */
1914 rte_eth_dev_probing_finish(eth_dev);
1918 if (adapter->flags & FW_OK) {
1919 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1921 dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1927 cxgbe_cfg_queues(adapter->eth_dev);
1929 cxgbe_print_adapter_info(adapter);
1930 cxgbe_print_port_info(adapter);
1932 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
1933 adapter->clipt_end);
1934 if (!adapter->clipt) {
1935 /* We tolerate a lack of clip_table, giving up some
1938 dev_warn(adapter, "could not allocate CLIP. Continuing\n");
1941 adap_smt_index(adapter, &smt_start_idx, &smt_size);
1942 adapter->smt = t4_init_smt(smt_start_idx, smt_size);
1944 dev_warn(adapter, "could not allocate SMT, continuing\n");
1946 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
1947 if (!adapter->l2t) {
1948 /* We tolerate a lack of L2T, giving up some functionality */
1949 dev_warn(adapter, "could not allocate L2T. Continuing\n");
1952 if (tid_init(&adapter->tids) < 0) {
1953 /* Disable filtering support */
1954 dev_warn(adapter, "could not allocate TID table, "
1955 "filter support disabled. Continuing\n");
1958 t4_os_lock_init(&adapter->flow_lock);
1960 adapter->mpstcam = t4_init_mpstcam(adapter);
1961 if (!adapter->mpstcam)
1962 dev_warn(adapter, "could not allocate mps tcam table."
1965 if (is_hashfilter(adapter)) {
1966 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) {
1967 u32 hash_base, hash_reg;
1969 hash_reg = A_LE_DB_TID_HASHBASE;
1970 hash_base = t4_read_reg(adapter, hash_reg);
1971 adapter->tids.hash_base = hash_base / 4;
1974 /* Disable hash filtering support */
1976 "Maskless filter support disabled. Continuing\n");
1979 err = cxgbe_init_rss(adapter);
1986 for_each_port(adapter, i) {
1987 pi = adap2pinfo(adapter, i);
1989 t4_free_vi(adapter, adapter->mbox, adapter->pf,
1991 rte_eth_dev_release_port(pi->eth_dev);
1994 if (adapter->flags & FW_OK)
1995 t4_fw_bye(adapter, adapter->mbox);