drivers/net/cxgbe/cxgbe_main.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_atomic.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_tailq.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_kvargs.h>
  35
  36 #include "base/common.h"
  37 #include "base/t4_regs.h"
  38 #include "base/t4_msg.h"
  39 #include "cxgbe.h"
  40 #include "clip_tbl.h"
  41 #include "l2t.h"
  42 #include "mps_tcam.h"
  43
  44 /**
  45  * Allocate a chunk of memory. The allocated memory is cleared.
  46  */
  47 void *t4_alloc_mem(size_t size)
  48 {
  49         return rte_zmalloc(NULL, size, 0);
  50 }
  51
  52 /**
  53  * Free memory allocated through t4_alloc_mem().
  54  */
  55 void t4_free_mem(void *addr)
  56 {
  57         rte_free(addr);
  58 }
  59
  60 /*
  61  * Response queue handler for the FW event queue.
  62  */
  63 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
  64                           __rte_unused const struct pkt_gl *gl)
  65 {
  66         u8 opcode = ((const struct rss_header *)rsp)->opcode;
  67
  68         rsp++;                                          /* skip RSS header */
  69
  70         /*
  71          * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
  72          */
  73         if (unlikely(opcode == CPL_FW4_MSG &&
  74                      ((const struct cpl_fw4_msg *)rsp)->type ==
  75                       FW_TYPE_RSSCPL)) {
  76                 rsp++;
  77                 opcode = ((const struct rss_header *)rsp)->opcode;
  78                 rsp++;
  79                 if (opcode != CPL_SGE_EGR_UPDATE) {
  80                         dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
  81                                 opcode);
  82                         goto out;
  83                 }
  84         }
  85
  86         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
  87                 /* do nothing */
  88         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
  89                 const struct cpl_fw6_msg *msg = (const void *)rsp;
  90
  91                 t4_handle_fw_rpl(q->adapter, msg->data);
  92         } else if (opcode == CPL_ABORT_RPL_RSS) {
  93                 const struct cpl_abort_rpl_rss *p = (const void *)rsp;
  94
  95                 cxgbe_hash_del_filter_rpl(q->adapter, p);
  96         } else if (opcode == CPL_SET_TCB_RPL) {
  97                 const struct cpl_set_tcb_rpl *p = (const void *)rsp;
  98
  99                 cxgbe_filter_rpl(q->adapter, p);
 100         } else if (opcode == CPL_ACT_OPEN_RPL) {
 101                 const struct cpl_act_open_rpl *p = (const void *)rsp;
 102
 103                 cxgbe_hash_filter_rpl(q->adapter, p);
 104         } else if (opcode == CPL_L2T_WRITE_RPL) {
 105                 const struct cpl_l2t_write_rpl *p = (const void *)rsp;
 106
 107                 cxgbe_do_l2t_write_rpl(q->adapter, p);
 108         } else {
 109                 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
 110                         opcode);
 111         }
 112 out:
 113         return 0;
 114 }
 115
 116 /**
 117  * Setup sge control queues to pass control information.
 118  */
 119 int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter)
 120 {
 121         struct sge *s = &adapter->sge;
 122         int err = 0, i = 0;
 123
 124         for_each_port(adapter, i) {
 125                 struct port_info *pi = adap2pinfo(adapter, i);
 126                 char name[RTE_ETH_NAME_MAX_LEN];
 127                 struct sge_ctrl_txq *q = &s->ctrlq[i];
 128
 129                 q->q.size = 1024;
 130                 err = t4_sge_alloc_ctrl_txq(adapter, q,
 131                                             adapter->eth_dev,  i,
 132                                             s->fw_evtq.cntxt_id,
 133                                             rte_socket_id());
 134                 if (err) {
 135                         dev_err(adapter, "Failed to alloc ctrl txq. Err: %d",
 136                                 err);
 137                         goto out;
 138                 }
 139                 snprintf(name, sizeof(name), "%s_ctrl_pool_%d",
 140                          pi->eth_dev->device->driver->name,
 141                          pi->eth_dev->data->port_id);
 142                 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
 143                                                      RTE_CACHE_LINE_SIZE,
 144                                                      RTE_MBUF_PRIV_ALIGN,
 145                                                      RTE_MBUF_DEFAULT_BUF_SIZE,
 146                                                      SOCKET_ID_ANY);
 147                 if (!q->mb_pool) {
 148                         err = -rte_errno;
 149                         dev_err(adapter,
 150                                 "Can't create ctrl pool for port %d. Err: %d\n",
 151                                 pi->eth_dev->data->port_id, err);
 152                         goto out;
 153                 }
 154         }
 155         return 0;
 156 out:
 157         t4_free_sge_resources(adapter);
 158         return err;
 159 }
 160
 161 /**
 162  * cxgbe_poll_for_completion: Poll rxq for completion
 163  * @q: rxq to poll
 164  * @ms: milliseconds to delay
 165  * @cnt: number of times to poll
 166  * @c: completion to check for 'done' status
 167  *
 168  * Polls the rxq for reples until completion is done or the count
 169  * expires.
 170  */
 171 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int ms,
 172                               unsigned int cnt, struct t4_completion *c)
 173 {
 174         unsigned int i;
 175         unsigned int work_done, budget = 32;
 176
 177         if (!c)
 178                 return -EINVAL;
 179
 180         for (i = 0; i < cnt; i++) {
 181                 cxgbe_poll(q, NULL, budget, &work_done);
 182                 t4_os_lock(&c->lock);
 183                 if (c->done) {
 184                         t4_os_unlock(&c->lock);
 185                         return 0;
 186                 }
 187                 t4_os_unlock(&c->lock);
 188                 rte_delay_ms(ms);
 189         }
 190         return -ETIMEDOUT;
 191 }
 192
 193 int cxgbe_setup_sge_fwevtq(struct adapter *adapter)
 194 {
 195         struct sge *s = &adapter->sge;
 196         int err = 0;
 197         int msi_idx = 0;
 198
 199         err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
 200                                msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
 201                                rte_socket_id());
 202         return err;
 203 }
 204
 205 static int closest_timer(const struct sge *s, int time)
 206 {
 207         unsigned int i, match = 0;
 208         int delta, min_delta = INT_MAX;
 209
 210         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 211                 delta = time - s->timer_val[i];
 212                 if (delta < 0)
 213                         delta = -delta;
 214                 if (delta < min_delta) {
 215                         min_delta = delta;
 216                         match = i;
 217                 }
 218         }
 219         return match;
 220 }
 221
 222 static int closest_thres(const struct sge *s, int thres)
 223 {
 224         unsigned int i, match = 0;
 225         int delta, min_delta = INT_MAX;
 226
 227         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 228                 delta = thres - s->counter_val[i];
 229                 if (delta < 0)
 230                         delta = -delta;
 231                 if (delta < min_delta) {
 232                         min_delta = delta;
 233                         match = i;
 234                 }
 235         }
 236         return match;
 237 }
 238
 239 /**
 240  * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 241  * @q: the Rx queue
 242  * @us: the hold-off time in us, or 0 to disable timer
 243  * @cnt: the hold-off packet count, or 0 to disable counter
 244  *
 245  * Sets an Rx queue's interrupt hold-off time and packet count.  At least
 246  * one of the two needs to be enabled for the queue to generate interrupts.
 247  */
 248 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
 249                                unsigned int cnt)
 250 {
 251         struct adapter *adap = q->adapter;
 252         unsigned int timer_val;
 253
 254         if (cnt) {
 255                 int err;
 256                 u32 v, new_idx;
 257
 258                 new_idx = closest_thres(&adap->sge, cnt);
 259                 if (q->desc && q->pktcnt_idx != new_idx) {
 260                         /* the queue has already been created, update it */
 261                         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 262                             V_FW_PARAMS_PARAM_X(
 263                             FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 264                             V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
 265                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 266                                             &v, &new_idx);
 267                         if (err)
 268                                 return err;
 269                 }
 270                 q->pktcnt_idx = new_idx;
 271         }
 272
 273         timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
 274                                 closest_timer(&adap->sge, us);
 275
 276         if ((us | cnt) == 0)
 277                 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
 278         else
 279                 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
 280                                  V_QINTR_CNT_EN(cnt > 0);
 281         return 0;
 282 }
 283
 284 /**
 285  * Allocate an active-open TID and set it to the supplied value.
 286  */
 287 int cxgbe_alloc_atid(struct tid_info *t, void *data)
 288 {
 289         int atid = -1;
 290
 291         t4_os_lock(&t->atid_lock);
 292         if (t->afree) {
 293                 union aopen_entry *p = t->afree;
 294
 295                 atid = p - t->atid_tab;
 296                 t->afree = p->next;
 297                 p->data = data;
 298                 t->atids_in_use++;
 299         }
 300         t4_os_unlock(&t->atid_lock);
 301         return atid;
 302 }
 303
 304 /**
 305  * Release an active-open TID.
 306  */
 307 void cxgbe_free_atid(struct tid_info *t, unsigned int atid)
 308 {
 309         union aopen_entry *p = &t->atid_tab[atid];
 310
 311         t4_os_lock(&t->atid_lock);
 312         p->next = t->afree;
 313         t->afree = p;
 314         t->atids_in_use--;
 315         t4_os_unlock(&t->atid_lock);
 316 }
 317
 318 /**
 319  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
 320  */
 321 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid)
 322 {
 323         struct cpl_tid_release *req;
 324
 325         req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *);
 326         INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
 327 }
 328
 329 /**
 330  * Release a TID and inform HW.  If we are unable to allocate the release
 331  * message we defer to a work queue.
 332  */
 333 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
 334                       unsigned short family)
 335 {
 336         struct rte_mbuf *mbuf;
 337         struct adapter *adap = container_of(t, struct adapter, tids);
 338
 339         WARN_ON(tid >= t->ntids);
 340
 341         if (t->tid_tab[tid]) {
 342                 t->tid_tab[tid] = NULL;
 343                 rte_atomic32_dec(&t->conns_in_use);
 344                 if (t->hash_base && tid >= t->hash_base) {
 345                         if (family == FILTER_TYPE_IPV4)
 346                                 rte_atomic32_dec(&t->hash_tids_in_use);
 347                 } else {
 348                         if (family == FILTER_TYPE_IPV4)
 349                                 rte_atomic32_dec(&t->tids_in_use);
 350                 }
 351         }
 352
 353         mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool);
 354         if (mbuf) {
 355                 mbuf->data_len = sizeof(struct cpl_tid_release);
 356                 mbuf->pkt_len = mbuf->data_len;
 357                 mk_tid_release(mbuf, tid);
 358                 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf);
 359         }
 360 }
 361
 362 /**
 363  * Insert a TID.
 364  */
 365 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid,
 366                       unsigned short family)
 367 {
 368         t->tid_tab[tid] = data;
 369         if (t->hash_base && tid >= t->hash_base) {
 370                 if (family == FILTER_TYPE_IPV4)
 371                         rte_atomic32_inc(&t->hash_tids_in_use);
 372         } else {
 373                 if (family == FILTER_TYPE_IPV4)
 374                         rte_atomic32_inc(&t->tids_in_use);
 375         }
 376
 377         rte_atomic32_inc(&t->conns_in_use);
 378 }
 379
 380 /**
 381  * Free TID tables.
 382  */
 383 static void tid_free(struct tid_info *t)
 384 {
 385         if (t->tid_tab) {
 386                 if (t->ftid_bmap)
 387                         rte_bitmap_free(t->ftid_bmap);
 388
 389                 if (t->ftid_bmap_array)
 390                         t4_os_free(t->ftid_bmap_array);
 391
 392                 t4_os_free(t->tid_tab);
 393         }
 394
 395         memset(t, 0, sizeof(struct tid_info));
 396 }
 397
 398 /**
 399  * Allocate and initialize the TID tables.  Returns 0 on success.
 400  */
 401 static int tid_init(struct tid_info *t)
 402 {
 403         size_t size;
 404         unsigned int ftid_bmap_size;
 405         unsigned int natids = t->natids;
 406         unsigned int max_ftids = t->nftids;
 407
 408         ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
 409         size = t->ntids * sizeof(*t->tid_tab) +
 410                 max_ftids * sizeof(*t->ftid_tab) +
 411                 natids * sizeof(*t->atid_tab);
 412
 413         t->tid_tab = t4_os_alloc(size);
 414         if (!t->tid_tab)
 415                 return -ENOMEM;
 416
 417         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
 418         t->ftid_tab = (struct filter_entry *)&t->atid_tab[t->natids];
 419         t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
 420         if (!t->ftid_bmap_array) {
 421                 tid_free(t);
 422                 return -ENOMEM;
 423         }
 424
 425         t4_os_lock_init(&t->atid_lock);
 426         t4_os_lock_init(&t->ftid_lock);
 427
 428         t->afree = NULL;
 429         t->atids_in_use = 0;
 430         rte_atomic32_init(&t->tids_in_use);
 431         rte_atomic32_set(&t->tids_in_use, 0);
 432         rte_atomic32_init(&t->conns_in_use);
 433         rte_atomic32_set(&t->conns_in_use, 0);
 434
 435         /* Setup the free list for atid_tab and clear the stid bitmap. */
 436         if (natids) {
 437                 while (--natids)
 438                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
 439                 t->afree = t->atid_tab;
 440         }
 441
 442         t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
 443                                        ftid_bmap_size);
 444         if (!t->ftid_bmap) {
 445                 tid_free(t);
 446                 return -ENOMEM;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static inline bool is_x_1g_port(const struct link_config *lc)
 453 {
 454         return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
 455 }
 456
 457 static inline bool is_x_10g_port(const struct link_config *lc)
 458 {
 459         unsigned int speeds, high_speeds;
 460
 461         speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
 462         high_speeds = speeds &
 463                       ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
 464
 465         return high_speeds != 0;
 466 }
 467
 468 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
 469                       unsigned int us, unsigned int cnt,
 470                       unsigned int size, unsigned int iqe_size)
 471 {
 472         q->adapter = adap;
 473         cxgb4_set_rspq_intr_params(q, us, cnt);
 474         q->iqe_len = iqe_size;
 475         q->size = size;
 476 }
 477
 478 int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev)
 479 {
 480         struct port_info *pi = eth_dev->data->dev_private;
 481         struct adapter *adap = pi->adapter;
 482         struct sge *s = &adap->sge;
 483         unsigned int max_queues = s->max_ethqsets / adap->params.nports;
 484
 485         if ((eth_dev->data->nb_rx_queues < 1) ||
 486             (eth_dev->data->nb_tx_queues < 1))
 487                 return -EINVAL;
 488
 489         if ((eth_dev->data->nb_rx_queues > max_queues) ||
 490             (eth_dev->data->nb_tx_queues > max_queues))
 491                 return -EINVAL;
 492
 493         if (eth_dev->data->nb_rx_queues > pi->rss_size)
 494                 return -EINVAL;
 495
 496         /* We must configure RSS, since config has changed*/
 497         pi->flags &= ~PORT_RSS_DONE;
 498
 499         pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
 500         pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
 501
 502         return 0;
 503 }
 504
 505 void cxgbe_cfg_queues(struct rte_eth_dev *eth_dev)
 506 {
 507         struct port_info *pi = eth_dev->data->dev_private;
 508         struct adapter *adap = pi->adapter;
 509         struct sge *s = &adap->sge;
 510         unsigned int i, nb_ports = 0, qidx = 0;
 511         unsigned int q_per_port = 0;
 512
 513         if (!(adap->flags & CFG_QUEUES)) {
 514                 for_each_port(adap, i) {
 515                         struct port_info *tpi = adap2pinfo(adap, i);
 516
 517                         nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
 518                                      is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
 519                 }
 520
 521                 /*
 522                  * We default up to # of cores queues per 1G/10G port.
 523                  */
 524                 if (nb_ports)
 525                         q_per_port = (s->max_ethqsets -
 526                                      (adap->params.nports - nb_ports)) /
 527                                      nb_ports;
 528
 529                 if (q_per_port > rte_lcore_count())
 530                         q_per_port = rte_lcore_count();
 531
 532                 for_each_port(adap, i) {
 533                         struct port_info *pi = adap2pinfo(adap, i);
 534
 535                         pi->first_qset = qidx;
 536
 537                         /* Initially n_rx_qsets == n_tx_qsets */
 538                         pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
 539                                           is_x_1g_port(&pi->link_cfg)) ?
 540                                           q_per_port : 1;
 541                         pi->n_tx_qsets = pi->n_rx_qsets;
 542
 543                         if (pi->n_rx_qsets > pi->rss_size)
 544                                 pi->n_rx_qsets = pi->rss_size;
 545
 546                         qidx += pi->n_rx_qsets;
 547                 }
 548
 549                 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
 550                         struct sge_eth_rxq *r = &s->ethrxq[i];
 551
 552                         init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
 553                         r->usembufs = 1;
 554                         r->fl.size = (r->usembufs ? 1024 : 72);
 555                 }
 556
 557                 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
 558                         s->ethtxq[i].q.size = 1024;
 559
 560                 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
 561                 adap->flags |= CFG_QUEUES;
 562         }
 563 }
 564
 565 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
 566 {
 567         t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
 568                                  &pi->stats_base);
 569 }
 570
 571 void cxgbe_stats_reset(struct port_info *pi)
 572 {
 573         t4_clr_port_stats(pi->adapter, pi->tx_chan);
 574 }
 575
 576 static void setup_memwin(struct adapter *adap)
 577 {
 578         u32 mem_win0_base;
 579
 580         /* For T5, only relative offset inside the PCIe BAR is passed */
 581         mem_win0_base = MEMWIN0_BASE;
 582
 583         /*
 584          * Set up memory window for accessing adapter memory ranges.  (Read
 585          * back MA register to ensure that changes propagate before we attempt
 586          * to use the new values.)
 587          */
 588         t4_write_reg(adap,
 589                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 590                                          MEMWIN_NIC),
 591                      mem_win0_base | V_BIR(0) |
 592                      V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
 593         t4_read_reg(adap,
 594                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 595                                         MEMWIN_NIC));
 596 }
 597
 598 int cxgbe_init_rss(struct adapter *adap)
 599 {
 600         unsigned int i;
 601
 602         if (is_pf4(adap)) {
 603                 int err;
 604
 605                 err = t4_init_rss_mode(adap, adap->mbox);
 606                 if (err)
 607                         return err;
 608         }
 609
 610         for_each_port(adap, i) {
 611                 struct port_info *pi = adap2pinfo(adap, i);
 612
 613                 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 614                 if (!pi->rss)
 615                         return -ENOMEM;
 616
 617                 pi->rss_hf = CXGBE_RSS_HF_ALL;
 618         }
 619         return 0;
 620 }
 621
 622 /**
 623  * Dump basic information about the adapter.
 624  */
 625 void cxgbe_print_adapter_info(struct adapter *adap)
 626 {
 627         /**
 628          * Hardware/Firmware/etc. Version/Revision IDs.
 629          */
 630         t4_dump_version_info(adap);
 631 }
 632
 633 void cxgbe_print_port_info(struct adapter *adap)
 634 {
 635         int i;
 636         char buf[80];
 637         struct rte_pci_addr *loc = &adap->pdev->addr;
 638
 639         for_each_port(adap, i) {
 640                 const struct port_info *pi = adap2pinfo(adap, i);
 641                 char *bufp = buf;
 642
 643                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
 644                         bufp += sprintf(bufp, "100M/");
 645                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
 646                         bufp += sprintf(bufp, "1G/");
 647                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
 648                         bufp += sprintf(bufp, "10G/");
 649                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
 650                         bufp += sprintf(bufp, "25G/");
 651                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
 652                         bufp += sprintf(bufp, "40G/");
 653                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
 654                         bufp += sprintf(bufp, "50G/");
 655                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
 656                         bufp += sprintf(bufp, "100G/");
 657                 if (bufp != buf)
 658                         --bufp;
 659                 sprintf(bufp, "BASE-%s",
 660                         t4_get_port_type_description(
 661                                         (enum fw_port_type)pi->port_type));
 662
 663                 dev_info(adap,
 664                          " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
 665                          loc->domain, loc->bus, loc->devid, loc->function,
 666                          CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
 667                          (adap->flags & USING_MSIX) ? " MSI-X" :
 668                          (adap->flags & USING_MSI) ? " MSI" : "");
 669         }
 670 }
 671
 672 static int check_devargs_handler(const char *key, const char *value, void *p)
 673 {
 674         if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) ||
 675             !strncmp(key, CXGBE_DEVARG_CMN_TX_MODE_LATENCY, strlen(key)) ||
 676             !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) {
 677                 if (!strncmp(value, "1", 1)) {
 678                         bool *dst_val = (bool *)p;
 679
 680                         *dst_val = true;
 681                 }
 682         }
 683
 684         return 0;
 685 }
 686
 687 static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key,
 688                              void *p)
 689 {
 690         struct rte_kvargs *kvlist;
 691         int ret = 0;
 692
 693         if (!devargs)
 694                 return 0;
 695
 696         kvlist = rte_kvargs_parse(devargs->args, NULL);
 697         if (!kvlist)
 698                 return 0;
 699
 700         if (!rte_kvargs_count(kvlist, key))
 701                 goto out;
 702
 703         ret = rte_kvargs_process(kvlist, key, check_devargs_handler, p);
 704
 705 out:
 706         rte_kvargs_free(kvlist);
 707
 708         return ret;
 709 }
 710
 711 static void cxgbe_get_devargs_int(struct adapter *adap, int *dst,
 712                                   const char *key, int default_value)
 713 {
 714         struct rte_pci_device *pdev = adap->pdev;
 715         int ret, devarg_value = default_value;
 716
 717         *dst = default_value;
 718         if (!pdev)
 719                 return;
 720
 721         ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value);
 722         if (ret)
 723                 return;
 724
 725         *dst = devarg_value;
 726 }
 727
 728 void cxgbe_process_devargs(struct adapter *adap)
 729 {
 730         cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan,
 731                               CXGBE_DEVARG_CMN_KEEP_OVLAN, 0);
 732         cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency,
 733                               CXGBE_DEVARG_CMN_TX_MODE_LATENCY, 0);
 734         cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up,
 735                               CXGBE_DEVARG_VF_FORCE_LINK_UP, 0);
 736 }
 737
 738 static void configure_vlan_types(struct adapter *adapter)
 739 {
 740         int i;
 741
 742         for_each_port(adapter, i) {
 743                 /* OVLAN Type 0x88a8 */
 744                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
 745                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 746                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 747                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 748                                  V_OVLAN_ETYPE(0x88a8));
 749                 /* OVLAN Type 0x9100 */
 750                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
 751                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 752                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 753                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 754                                  V_OVLAN_ETYPE(0x9100));
 755                 /* OVLAN Type 0x8100 */
 756                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
 757                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 758                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 759                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 760                                  V_OVLAN_ETYPE(0x8100));
 761
 762                 /* IVLAN 0X8100 */
 763                 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
 764                                  V_IVLAN_ETYPE(M_IVLAN_ETYPE),
 765                                  V_IVLAN_ETYPE(0x8100));
 766
 767                 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
 768                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 769                                  F_OVLAN_EN2 | F_IVLAN_EN,
 770                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 771                                  F_OVLAN_EN2 | F_IVLAN_EN);
 772         }
 773
 774         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1),
 775                                V_RM_OVLAN(!adapter->devargs.keep_ovlan));
 776 }
 777
 778 static void configure_pcie_ext_tag(struct adapter *adapter)
 779 {
 780         u16 v;
 781         int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
 782
 783         if (!pos)
 784                 return;
 785
 786         if (pos > 0) {
 787                 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
 788                 v |= PCI_EXP_DEVCTL_EXT_TAG;
 789                 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
 790                 if (is_t6(adapter->params.chip)) {
 791                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 792                                          V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
 793                                          V_T6_TOTMAXTAG(7));
 794                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 795                                          V_T6_MINTAG(M_T6_MINTAG),
 796                                          V_T6_MINTAG(8));
 797                 } else {
 798                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 799                                          V_TOTMAXTAG(M_TOTMAXTAG),
 800                                          V_TOTMAXTAG(3));
 801                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 802                                          V_MINTAG(M_MINTAG),
 803                                          V_MINTAG(8));
 804                 }
 805         }
 806 }
 807
 808 /* Figure out how many Queue Sets we can support */
 809 void cxgbe_configure_max_ethqsets(struct adapter *adapter)
 810 {
 811         unsigned int ethqsets;
 812
 813         /*
 814          * We need to reserve an Ingress Queue for the Asynchronous Firmware
 815          * Event Queue.
 816          *
 817          * For each Queue Set, we'll need the ability to allocate two Egress
 818          * Contexts -- one for the Ingress Queue Free List and one for the TX
 819          * Ethernet Queue.
 820          */
 821         if (is_pf4(adapter)) {
 822                 struct pf_resources *pfres = &adapter->params.pfres;
 823
 824                 ethqsets = pfres->niqflint - 1;
 825                 if (pfres->neq < ethqsets * 2)
 826                         ethqsets = pfres->neq / 2;
 827         } else {
 828                 struct vf_resources *vfres = &adapter->params.vfres;
 829
 830                 ethqsets = vfres->niqflint - 1;
 831                 if (vfres->nethctrl != ethqsets)
 832                         ethqsets = min(vfres->nethctrl, ethqsets);
 833                 if (vfres->neq < ethqsets * 2)
 834                         ethqsets = vfres->neq / 2;
 835         }
 836
 837         if (ethqsets > MAX_ETH_QSETS)
 838                 ethqsets = MAX_ETH_QSETS;
 839         adapter->sge.max_ethqsets = ethqsets;
 840 }
 841
 842 /*
 843  * Tweak configuration based on system architecture, etc.  Most of these have
 844  * defaults assigned to them by Firmware Configuration Files (if we're using
 845  * them) but need to be explicitly set if we're using hard-coded
 846  * initialization. So these are essentially common tweaks/settings for
 847  * Configuration Files and hard-coded initialization ...
 848  */
 849 static int adap_init0_tweaks(struct adapter *adapter)
 850 {
 851         u8 rx_dma_offset;
 852
 853         /*
 854          * Fix up various Host-Dependent Parameters like Page Size, Cache
 855          * Line Size, etc.  The firmware default is for a 4KB Page Size and
 856          * 64B Cache Line Size ...
 857          */
 858         t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
 859                                     T5_LAST_REV);
 860
 861         /*
 862          * Keep the chip default offset to deliver Ingress packets into our
 863          * DMA buffers to zero
 864          */
 865         rx_dma_offset = 0;
 866         t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
 867                          V_PKTSHIFT(rx_dma_offset));
 868
 869         t4_set_reg_field(adapter, A_SGE_FLM_CFG,
 870                          V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
 871                          V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
 872
 873         t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
 874                          V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
 875
 876         t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
 877                          V_IDMAARBROUNDROBIN(1U));
 878
 879         /*
 880          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
 881          * adds the pseudo header itself.
 882          */
 883         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 884                                F_CSUM_HAS_PSEUDO_HDR, 0);
 885
 886         return 0;
 887 }
 888
 889 /*
 890  * Attempt to initialize the adapter via a Firmware Configuration File.
 891  */
 892 static int adap_init0_config(struct adapter *adapter, int reset)
 893 {
 894         struct fw_caps_config_cmd caps_cmd;
 895         unsigned long mtype = 0, maddr = 0;
 896         u32 finiver, finicsum, cfcsum;
 897         int ret;
 898         int config_issued = 0;
 899         int cfg_addr;
 900         char config_name[20];
 901
 902         /*
 903          * Reset device if necessary.
 904          */
 905         if (reset) {
 906                 ret = t4_fw_reset(adapter, adapter->mbox,
 907                                   F_PIORSTMODE | F_PIORST);
 908                 if (ret < 0) {
 909                         dev_warn(adapter, "Firmware reset failed, error %d\n",
 910                                  -ret);
 911                         goto bye;
 912                 }
 913         }
 914
 915         cfg_addr = t4_flash_cfg_addr(adapter);
 916         if (cfg_addr < 0) {
 917                 ret = cfg_addr;
 918                 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
 919                          -ret);
 920                 goto bye;
 921         }
 922
 923         strcpy(config_name, "On Flash");
 924         mtype = FW_MEMTYPE_CF_FLASH;
 925         maddr = cfg_addr;
 926
 927         /*
 928          * Issue a Capability Configuration command to the firmware to get it
 929          * to parse the Configuration File.  We don't use t4_fw_config_file()
 930          * because we want the ability to modify various features after we've
 931          * processed the configuration file ...
 932          */
 933         memset(&caps_cmd, 0, sizeof(caps_cmd));
 934         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 935                                            F_FW_CMD_REQUEST | F_FW_CMD_READ);
 936         caps_cmd.cfvalid_to_len16 =
 937                 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
 938                             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
 939                             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
 940                             FW_LEN16(caps_cmd));
 941         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 942                          &caps_cmd);
 943         /*
 944          * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
 945          * Configuration File in FLASH), our last gasp effort is to use the
 946          * Firmware Configuration File which is embedded in the firmware.  A
 947          * very few early versions of the firmware didn't have one embedded
 948          * but we can ignore those.
 949          */
 950         if (ret == -ENOENT) {
 951                 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
 952                          __func__);
 953
 954                 memset(&caps_cmd, 0, sizeof(caps_cmd));
 955                 caps_cmd.op_to_write =
 956                         cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 957                                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
 958                 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
 959                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
 960                                  sizeof(caps_cmd), &caps_cmd);
 961                 strcpy(config_name, "Firmware Default");
 962         }
 963
 964         config_issued = 1;
 965         if (ret < 0)
 966                 goto bye;
 967
 968         finiver = be32_to_cpu(caps_cmd.finiver);
 969         finicsum = be32_to_cpu(caps_cmd.finicsum);
 970         cfcsum = be32_to_cpu(caps_cmd.cfcsum);
 971         if (finicsum != cfcsum)
 972                 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
 973                          finicsum, cfcsum);
 974
 975         /*
 976          * If we're a pure NIC driver then disable all offloading facilities.
 977          * This will allow the firmware to optimize aspects of the hardware
 978          * configuration which will result in improved performance.
 979          */
 980         caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD);
 981         caps_cmd.toecaps = 0;
 982         caps_cmd.iscsicaps = 0;
 983         caps_cmd.rdmacaps = 0;
 984         caps_cmd.fcoecaps = 0;
 985
 986         /*
 987          * And now tell the firmware to use the configuration we just loaded.
 988          */
 989         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 990                                            F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
 991         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 992         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 993                          NULL);
 994         if (ret < 0) {
 995                 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
 996                          -ret);
 997                 goto bye;
 998         }
 999
1000         /*
1001          * Tweak configuration based on system architecture, etc.
1002          */
1003         ret = adap_init0_tweaks(adapter);
1004         if (ret < 0) {
1005                 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
1006                 goto bye;
1007         }
1008
1009         /*
1010          * And finally tell the firmware to initialize itself using the
1011          * parameters from the Configuration File.
1012          */
1013         ret = t4_fw_initialize(adapter, adapter->mbox);
1014         if (ret < 0) {
1015                 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
1016                          -ret);
1017                 goto bye;
1018         }
1019
1020         /*
1021          * Return successfully and note that we're operating with parameters
1022          * not supplied by the driver, rather than from hard-wired
1023          * initialization constants buried in the driver.
1024          */
1025         dev_info(adapter,
1026                  "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
1027                  config_name, finiver, cfcsum);
1028
1029         return 0;
1030
1031         /*
1032          * Something bad happened.  Return the error ...  (If the "error"
1033          * is that there's no Configuration File on the adapter we don't
1034          * want to issue a warning since this is fairly common.)
1035          */
1036 bye:
1037         if (config_issued && ret != -ENOENT)
1038                 dev_warn(adapter, "\"%s\" configuration file error %d\n",
1039                          config_name, -ret);
1040
1041         dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
1042         return ret;
1043 }
1044
1045 static int adap_init0(struct adapter *adap)
1046 {
1047         struct fw_caps_config_cmd caps_cmd;
1048         int ret = 0;
1049         u32 v, port_vec;
1050         enum dev_state state;
1051         u32 params[7], val[7];
1052         int reset = 1;
1053         int mbox = adap->mbox;
1054
1055         /*
1056          * Contact FW, advertising Master capability.
1057          */
1058         ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
1059         if (ret < 0) {
1060                 dev_err(adap, "%s: could not connect to FW, error %d\n",
1061                         __func__, -ret);
1062                 goto bye;
1063         }
1064
1065         CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
1066                          adap->mbox, ret);
1067
1068         if (ret == mbox)
1069                 adap->flags |= MASTER_PF;
1070
1071         if (state == DEV_STATE_INIT) {
1072                 /*
1073                  * Force halt and reset FW because a previous instance may have
1074                  * exited abnormally without properly shutting down
1075                  */
1076                 ret = t4_fw_halt(adap, adap->mbox, reset);
1077                 if (ret < 0) {
1078                         dev_err(adap, "Failed to halt. Exit.\n");
1079                         goto bye;
1080                 }
1081
1082                 ret = t4_fw_restart(adap, adap->mbox, reset);
1083                 if (ret < 0) {
1084                         dev_err(adap, "Failed to restart. Exit.\n");
1085                         goto bye;
1086                 }
1087                 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
1088         }
1089
1090         t4_get_version_info(adap);
1091
1092         ret = t4_get_core_clock(adap, &adap->params.vpd);
1093         if (ret < 0) {
1094                 dev_err(adap, "%s: could not get core clock, error %d\n",
1095                         __func__, -ret);
1096                 goto bye;
1097         }
1098
1099         /*
1100          * If the firmware is initialized already (and we're not forcing a
1101          * master initialization), note that we're living with existing
1102          * adapter parameters.  Otherwise, it's time to try initializing the
1103          * adapter ...
1104          */
1105         if (state == DEV_STATE_INIT) {
1106                 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
1107                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
1108         } else {
1109                 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
1110
1111                 ret = adap_init0_config(adap, reset);
1112                 if (ret == -ENOENT) {
1113                         dev_err(adap,
1114                                 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
1115                         goto bye;
1116                 }
1117         }
1118         if (ret < 0) {
1119                 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
1120                 goto bye;
1121         }
1122
1123         /* Now that we've successfully configured and initialized the adapter
1124          * (or found it already initialized), we can ask the Firmware what
1125          * resources it has provisioned for us.
1126          */
1127         ret = t4_get_pfres(adap);
1128         if (ret) {
1129                 dev_err(adap->pdev_dev,
1130                         "Unable to retrieve resource provisioning info\n");
1131                 goto bye;
1132         }
1133
1134         /* Find out what ports are available to us. */
1135         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1136             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
1137         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
1138         if (ret < 0) {
1139                 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
1140                         __func__, ret);
1141                 goto bye;
1142         }
1143
1144         adap->params.nports = hweight32(port_vec);
1145         adap->params.portvec = port_vec;
1146
1147         dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
1148                   adap->params.nports);
1149
1150         /*
1151          * Give the SGE code a chance to pull in anything that it needs ...
1152          * Note that this must be called after we retrieve our VPD parameters
1153          * in order to know how to convert core ticks to seconds, etc.
1154          */
1155         ret = t4_sge_init(adap);
1156         if (ret < 0) {
1157                 dev_err(adap, "t4_sge_init failed with error %d\n",
1158                         -ret);
1159                 goto bye;
1160         }
1161
1162         /*
1163          * Grab some of our basic fundamental operating parameters.
1164          */
1165 #define FW_PARAM_DEV(param) \
1166         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
1167          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
1168
1169 #define FW_PARAM_PFVF(param) \
1170         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
1171          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
1172          V_FW_PARAMS_PARAM_Y(0) | \
1173          V_FW_PARAMS_PARAM_Z(0))
1174
1175         params[0] = FW_PARAM_PFVF(L2T_START);
1176         params[1] = FW_PARAM_PFVF(L2T_END);
1177         params[2] = FW_PARAM_PFVF(FILTER_START);
1178         params[3] = FW_PARAM_PFVF(FILTER_END);
1179         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val);
1180         if (ret < 0)
1181                 goto bye;
1182         adap->l2t_start = val[0];
1183         adap->l2t_end = val[1];
1184         adap->tids.ftid_base = val[2];
1185         adap->tids.nftids = val[3] - val[2] + 1;
1186
1187         params[0] = FW_PARAM_PFVF(CLIP_START);
1188         params[1] = FW_PARAM_PFVF(CLIP_END);
1189         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
1190         if (ret < 0)
1191                 goto bye;
1192         adap->clipt_start = val[0];
1193         adap->clipt_end = val[1];
1194
1195         /*
1196          * Get device capabilities so we can determine what resources we need
1197          * to manage.
1198          */
1199         memset(&caps_cmd, 0, sizeof(caps_cmd));
1200         caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1201                                      F_FW_CMD_REQUEST | F_FW_CMD_READ);
1202         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
1203         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
1204                          &caps_cmd);
1205         if (ret < 0)
1206                 goto bye;
1207
1208         if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) &&
1209             is_t6(adap->params.chip)) {
1210                 if (cxgbe_init_hash_filter(adap) < 0)
1211                         goto bye;
1212         }
1213
1214         /* See if FW supports FW_FILTER2 work request */
1215         if (is_t4(adap->params.chip)) {
1216                 adap->params.filter2_wr_support = 0;
1217         } else {
1218                 params[0] = FW_PARAM_DEV(FILTER2_WR);
1219                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1220                                       1, params, val);
1221                 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
1222         }
1223
1224         /* query tid-related parameters */
1225         params[0] = FW_PARAM_DEV(NTID);
1226         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
1227                               params, val);
1228         if (ret < 0)
1229                 goto bye;
1230         adap->tids.ntids = val[0];
1231         adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
1232
1233         /* If we're running on newer firmware, let it know that we're
1234          * prepared to deal with encapsulated CPL messages.  Older
1235          * firmware won't understand this and we'll just get
1236          * unencapsulated messages ...
1237          */
1238         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
1239         val[0] = 1;
1240         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1241
1242         /*
1243          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
1244          * capability.  Earlier versions of the firmware didn't have the
1245          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
1246          * permission to use ULPTX MEMWRITE DSGL.
1247          */
1248         if (is_t4(adap->params.chip)) {
1249                 adap->params.ulptx_memwrite_dsgl = false;
1250         } else {
1251                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
1252                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1253                                       1, params, val);
1254                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
1255         }
1256
1257         /*
1258          * The MTU/MSS Table is initialized by now, so load their values.  If
1259          * we're initializing the adapter, then we'll make any modifications
1260          * we want to the MTU/MSS Table and also initialize the congestion
1261          * parameters.
1262          */
1263         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
1264         if (state != DEV_STATE_INIT) {
1265                 int i;
1266
1267                 /*
1268                  * The default MTU Table contains values 1492 and 1500.
1269                  * However, for TCP, it's better to have two values which are
1270                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
1271                  * This allows us to have a TCP Data Payload which is a
1272                  * multiple of 8 regardless of what combination of TCP Options
1273                  * are in use (always a multiple of 4 bytes) which is
1274                  * important for performance reasons.  For instance, if no
1275                  * options are in use, then we have a 20-byte IP header and a
1276                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
1277                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
1278                  * which is not a multiple of 8.  So using an MSS of 1488 in
1279                  * this case results in a TCP Data Payload of 1448 bytes which
1280                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
1281                  * Stamps have been negotiated, then an MTU of 1500 bytes
1282                  * results in a TCP Data Payload of 1448 bytes which, as
1283                  * above, is a multiple of 8 bytes ...
1284                  */
1285                 for (i = 0; i < NMTUS; i++)
1286                         if (adap->params.mtus[i] == 1492) {
1287                                 adap->params.mtus[i] = 1488;
1288                                 break;
1289                         }
1290
1291                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
1292                              adap->params.b_wnd);
1293         }
1294         t4_init_sge_params(adap);
1295         t4_init_tp_params(adap);
1296         configure_pcie_ext_tag(adap);
1297         configure_vlan_types(adap);
1298         cxgbe_configure_max_ethqsets(adap);
1299
1300         adap->params.drv_memwin = MEMWIN_NIC;
1301         adap->flags |= FW_OK;
1302         dev_debug(adap, "%s: returning zero..\n", __func__);
1303         return 0;
1304
1305         /*
1306          * Something bad happened.  If a command timed out or failed with EIO
1307          * FW does not operate within its spec or something catastrophic
1308          * happened to HW/FW, stop issuing commands.
1309          */
1310 bye:
1311         if (ret != -ETIMEDOUT && ret != -EIO)
1312                 t4_fw_bye(adap, adap->mbox);
1313         return ret;
1314 }
1315
1316 /**
1317  * t4_os_portmod_changed - handle port module changes
1318  * @adap: the adapter associated with the module change
1319  * @port_id: the port index whose module status has changed
1320  *
1321  * This is the OS-dependent handler for port module changes.  It is
1322  * invoked when a port module is removed or inserted for any OS-specific
1323  * processing.
1324  */
1325 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1326 {
1327         static const char * const mod_str[] = {
1328                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1329         };
1330
1331         const struct port_info *pi = adap2pinfo(adap, port_id);
1332
1333         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
1334                 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1335         else if (pi->mod_type < ARRAY_SIZE(mod_str))
1336                 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1337                          mod_str[pi->mod_type]);
1338         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1339                 dev_info(adap, "Port%d: unsupported port module inserted\n",
1340                          pi->port_id);
1341         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1342                 dev_info(adap, "Port%d: unknown port module inserted\n",
1343                          pi->port_id);
1344         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
1345                 dev_info(adap, "Port%d: transceiver module error\n",
1346                          pi->port_id);
1347         else
1348                 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1349                          pi->port_id, pi->mod_type);
1350 }
1351
1352 bool cxgbe_force_linkup(struct adapter *adap)
1353 {
1354         if (is_pf4(adap))
1355                 return false;   /* force_linkup not required for pf driver */
1356
1357         return adap->devargs.force_link_up;
1358 }
1359
1360 /**
1361  * link_start - enable a port
1362  * @dev: the port to enable
1363  *
1364  * Performs the MAC and PHY actions needed to enable a port.
1365  */
1366 int cxgbe_link_start(struct port_info *pi)
1367 {
1368         struct adapter *adapter = pi->adapter;
1369         u64 conf_offloads;
1370         unsigned int mtu;
1371         int ret;
1372
1373         mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1374               (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN);
1375
1376         conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads;
1377
1378         /*
1379          * We do not set address filters and promiscuity here, the stack does
1380          * that step explicitly.
1381          */
1382         ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1,
1383                             !!(conf_offloads & DEV_RX_OFFLOAD_VLAN_STRIP),
1384                             true);
1385         if (ret == 0) {
1386                 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt,
1387                                 (u8 *)&pi->eth_dev->data->mac_addrs[0]);
1388                 if (ret >= 0) {
1389                         pi->xact_addr_filt = ret;
1390                         ret = 0;
1391                 }
1392         }
1393         if (ret == 0 && is_pf4(adapter))
1394                 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
1395                                     &pi->link_cfg);
1396         if (ret == 0) {
1397                 /*
1398                  * Enabling a Virtual Interface can result in an interrupt
1399                  * during the processing of the VI Enable command and, in some
1400                  * paths, result in an attempt to issue another command in the
1401                  * interrupt context.  Thus, we disable interrupts during the
1402                  * course of the VI Enable command ...
1403                  */
1404                 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1405                                           true, true, false);
1406         }
1407
1408         if (ret == 0 && cxgbe_force_linkup(adapter))
1409                 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
1410         return ret;
1411 }
1412
1413 /**
1414  * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1415  * @pi: the port
1416  * @rss_hf: Hash configuration to apply
1417  */
1418 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1419 {
1420         struct adapter *adapter = pi->adapter;
1421         const struct sge_eth_rxq *rxq;
1422         u64 flags = 0;
1423         u16 rss;
1424         int err;
1425
1426         /*  Should never be called before setting up sge eth rx queues */
1427         if (!(adapter->flags & FULL_INIT_DONE)) {
1428                 dev_err(adap, "%s No RXQs available on port %d\n",
1429                         __func__, pi->port_id);
1430                 return -EINVAL;
1431         }
1432
1433         /* Don't allow unsupported hash functions */
1434         if (rss_hf & ~CXGBE_RSS_HF_ALL)
1435                 return -EINVAL;
1436
1437         if (rss_hf & CXGBE_RSS_HF_IPV4_MASK)
1438                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1439
1440         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1441                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1442
1443         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1444                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1445                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1446
1447         if (rss_hf & CXGBE_RSS_HF_IPV6_MASK)
1448                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1449
1450         if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK)
1451                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1452                          F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1453
1454         if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK)
1455                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1456                          F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1457                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1458
1459         rxq = &adapter->sge.ethrxq[pi->first_qset];
1460         rss = rxq[0].rspq.abs_id;
1461
1462         /* If Tunnel All Lookup isn't specified in the global RSS
1463          * Configuration, then we need to specify a default Ingress
1464          * Queue for any ingress packets which aren't hashed.  We'll
1465          * use our first ingress queue ...
1466          */
1467         err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1468                                flags, rss);
1469         return err;
1470 }
1471
1472 /**
1473  * cxgbe_write_rss - write the RSS table for a given port
1474  * @pi: the port
1475  * @queues: array of queue indices for RSS
1476  *
1477  * Sets up the portion of the HW RSS table for the port's VI to distribute
1478  * packets to the Rx queues in @queues.
1479  */
1480 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1481 {
1482         u16 *rss;
1483         int i, err;
1484         struct adapter *adapter = pi->adapter;
1485         const struct sge_eth_rxq *rxq;
1486
1487         /*  Should never be called before setting up sge eth rx queues */
1488         BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1489
1490         rxq = &adapter->sge.ethrxq[pi->first_qset];
1491         rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1492         if (!rss)
1493                 return -ENOMEM;
1494
1495         /* map the queue indices to queue ids */
1496         for (i = 0; i < pi->rss_size; i++, queues++)
1497                 rss[i] = rxq[*queues].rspq.abs_id;
1498
1499         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1500                                   pi->rss_size, rss, pi->rss_size);
1501         rte_free(rss);
1502         return err;
1503 }
1504
1505 /**
1506  * setup_rss - configure RSS
1507  * @adapter: the adapter
1508  *
1509  * Sets up RSS to distribute packets to multiple receive queues.  We
1510  * configure the RSS CPU lookup table to distribute to the number of HW
1511  * receive queues, and the response queue lookup table to narrow that
1512  * down to the response queues actually configured for each port.
1513  * We always configure the RSS mapping for all ports since the mapping
1514  * table has plenty of entries.
1515  */
1516 int cxgbe_setup_rss(struct port_info *pi)
1517 {
1518         int j, err;
1519         struct adapter *adapter = pi->adapter;
1520
1521         dev_debug(adapter, "%s:  pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1522                   __func__, pi->rss_size, pi->n_rx_qsets);
1523
1524         if (!(pi->flags & PORT_RSS_DONE)) {
1525                 if (adapter->flags & FULL_INIT_DONE) {
1526                         /* Fill default values with equal distribution */
1527                         for (j = 0; j < pi->rss_size; j++)
1528                                 pi->rss[j] = j % pi->n_rx_qsets;
1529
1530                         err = cxgbe_write_rss(pi, pi->rss);
1531                         if (err)
1532                                 return err;
1533
1534                         err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1535                         if (err)
1536                                 return err;
1537                         pi->flags |= PORT_RSS_DONE;
1538                 }
1539         }
1540         return 0;
1541 }
1542
1543 /*
1544  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1545  */
1546 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1547 {
1548         /* 0-increment GTS to start the timer and enable interrupts */
1549         t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1550                                           T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1551                      V_SEINTARM(q->intr_params) |
1552                      V_INGRESSQID(q->cntxt_id));
1553 }
1554
1555 void cxgbe_enable_rx_queues(struct port_info *pi)
1556 {
1557         struct adapter *adap = pi->adapter;
1558         struct sge *s = &adap->sge;
1559         unsigned int i;
1560
1561         for (i = 0; i < pi->n_rx_qsets; i++)
1562                 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1563 }
1564
1565 /**
1566  * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1567  * @port_type: Firmware Port Type
1568  * @fw_caps: Firmware Port Capabilities
1569  * @speed_caps: Device Info Speed Capabilities
1570  *
1571  * Translate a Firmware Port Capabilities specification to Device Info
1572  * Speed Capabilities.
1573  */
1574 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1575                                   unsigned int fw_caps,
1576                                   u32 *speed_caps)
1577 {
1578 #define SET_SPEED(__speed_name) \
1579         do { \
1580                 *speed_caps |= ETH_LINK_ ## __speed_name; \
1581         } while (0)
1582
1583 #define FW_CAPS_TO_SPEED(__fw_name) \
1584         do { \
1585                 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1586                         SET_SPEED(__fw_name); \
1587         } while (0)
1588
1589         switch (port_type) {
1590         case FW_PORT_TYPE_BT_SGMII:
1591         case FW_PORT_TYPE_BT_XFI:
1592         case FW_PORT_TYPE_BT_XAUI:
1593                 FW_CAPS_TO_SPEED(SPEED_100M);
1594                 FW_CAPS_TO_SPEED(SPEED_1G);
1595                 FW_CAPS_TO_SPEED(SPEED_10G);
1596                 break;
1597
1598         case FW_PORT_TYPE_KX4:
1599         case FW_PORT_TYPE_KX:
1600         case FW_PORT_TYPE_FIBER_XFI:
1601         case FW_PORT_TYPE_FIBER_XAUI:
1602         case FW_PORT_TYPE_SFP:
1603         case FW_PORT_TYPE_QSFP_10G:
1604         case FW_PORT_TYPE_QSA:
1605                 FW_CAPS_TO_SPEED(SPEED_1G);
1606                 FW_CAPS_TO_SPEED(SPEED_10G);
1607                 break;
1608
1609         case FW_PORT_TYPE_KR:
1610                 SET_SPEED(SPEED_10G);
1611                 break;
1612
1613         case FW_PORT_TYPE_BP_AP:
1614         case FW_PORT_TYPE_BP4_AP:
1615                 SET_SPEED(SPEED_1G);
1616                 SET_SPEED(SPEED_10G);
1617                 break;
1618
1619         case FW_PORT_TYPE_BP40_BA:
1620         case FW_PORT_TYPE_QSFP:
1621                 SET_SPEED(SPEED_40G);
1622                 break;
1623
1624         case FW_PORT_TYPE_CR_QSFP:
1625         case FW_PORT_TYPE_SFP28:
1626         case FW_PORT_TYPE_KR_SFP28:
1627                 FW_CAPS_TO_SPEED(SPEED_1G);
1628                 FW_CAPS_TO_SPEED(SPEED_10G);
1629                 FW_CAPS_TO_SPEED(SPEED_25G);
1630                 break;
1631
1632         case FW_PORT_TYPE_CR2_QSFP:
1633                 SET_SPEED(SPEED_50G);
1634                 break;
1635
1636         case FW_PORT_TYPE_KR4_100G:
1637         case FW_PORT_TYPE_CR4_QSFP:
1638                 FW_CAPS_TO_SPEED(SPEED_25G);
1639                 FW_CAPS_TO_SPEED(SPEED_40G);
1640                 FW_CAPS_TO_SPEED(SPEED_50G);
1641                 FW_CAPS_TO_SPEED(SPEED_100G);
1642                 break;
1643
1644         default:
1645                 break;
1646         }
1647
1648 #undef FW_CAPS_TO_SPEED
1649 #undef SET_SPEED
1650 }
1651
1652 /**
1653  * cxgbe_get_speed_caps - Fetch supported speed capabilities
1654  * @pi: Underlying port's info
1655  * @speed_caps: Device Info speed capabilities
1656  *
1657  * Fetch supported speed capabilities of the underlying port.
1658  */
1659 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1660 {
1661         *speed_caps = 0;
1662
1663         fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1664                               speed_caps);
1665
1666         if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1667                 *speed_caps |= ETH_LINK_SPEED_FIXED;
1668 }
1669
1670 /**
1671  * cxgbe_set_link_status - Set device link up or down.
1672  * @pi: Underlying port's info
1673  * @status: 0 - down, 1 - up
1674  *
1675  * Set the device link up or down.
1676  */
1677 int cxgbe_set_link_status(struct port_info *pi, bool status)
1678 {
1679         struct adapter *adapter = pi->adapter;
1680         int err = 0;
1681
1682         err = t4_enable_vi(adapter, adapter->mbox, pi->viid, status, status);
1683         if (err) {
1684                 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1685                 return err;
1686         }
1687
1688         if (!status)
1689                 t4_reset_link_config(adapter, pi->pidx);
1690
1691         return 0;
1692 }
1693
1694 /**
1695  * cxgb_up - enable the adapter
1696  * @adap: adapter being enabled
1697  *
1698  * Called when the first port is enabled, this function performs the
1699  * actions necessary to make an adapter operational, such as completing
1700  * the initialization of HW modules, and enabling interrupts.
1701  */
1702 int cxgbe_up(struct adapter *adap)
1703 {
1704         enable_rx(adap, &adap->sge.fw_evtq);
1705         t4_sge_tx_monitor_start(adap);
1706         if (is_pf4(adap))
1707                 t4_intr_enable(adap);
1708         adap->flags |= FULL_INIT_DONE;
1709
1710         /* TODO: deadman watchdog ?? */
1711         return 0;
1712 }
1713
1714 /*
1715  * Close the port
1716  */
1717 int cxgbe_down(struct port_info *pi)
1718 {
1719         return cxgbe_set_link_status(pi, false);
1720 }
1721
1722 /*
1723  * Release resources when all the ports have been stopped.
1724  */
1725 void cxgbe_close(struct adapter *adapter)
1726 {
1727         struct port_info *pi;
1728         int i;
1729
1730         if (adapter->flags & FULL_INIT_DONE) {
1731                 tid_free(&adapter->tids);
1732                 t4_cleanup_mpstcam(adapter);
1733                 t4_cleanup_clip_tbl(adapter);
1734                 t4_cleanup_l2t(adapter);
1735                 if (is_pf4(adapter))
1736                         t4_intr_disable(adapter);
1737                 t4_sge_tx_monitor_stop(adapter);
1738                 t4_free_sge_resources(adapter);
1739                 for_each_port(adapter, i) {
1740                         pi = adap2pinfo(adapter, i);
1741                         if (pi->viid != 0)
1742                                 t4_free_vi(adapter, adapter->mbox,
1743                                            adapter->pf, 0, pi->viid);
1744                         rte_eth_dev_release_port(pi->eth_dev);
1745                 }
1746                 adapter->flags &= ~FULL_INIT_DONE;
1747         }
1748
1749         if (is_pf4(adapter) && (adapter->flags & FW_OK))
1750                 t4_fw_bye(adapter, adapter->mbox);
1751 }
1752
1753 int cxgbe_probe(struct adapter *adapter)
1754 {
1755         struct port_info *pi;
1756         int chip;
1757         int func, i;
1758         int err = 0;
1759         u32 whoami;
1760
1761         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1762         chip = t4_get_chip_type(adapter,
1763                         CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1764         if (chip < 0)
1765                 return chip;
1766
1767         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1768                G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1769
1770         adapter->mbox = func;
1771         adapter->pf = func;
1772
1773         t4_os_lock_init(&adapter->mbox_lock);
1774         TAILQ_INIT(&adapter->mbox_list);
1775         t4_os_lock_init(&adapter->win0_lock);
1776
1777         err = t4_prep_adapter(adapter);
1778         if (err)
1779                 return err;
1780
1781         setup_memwin(adapter);
1782         err = adap_init0(adapter);
1783         if (err) {
1784                 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1785                         __func__, err);
1786                 goto out_free;
1787         }
1788
1789         if (!is_t4(adapter->params.chip)) {
1790                 /*
1791                  * The userspace doorbell BAR is split evenly into doorbell
1792                  * regions, each associated with an egress queue.  If this
1793                  * per-queue region is large enough (at least UDBS_SEG_SIZE)
1794                  * then it can be used to submit a tx work request with an
1795                  * implied doorbell.  Enable write combining on the BAR if
1796                  * there is room for such work requests.
1797                  */
1798                 int s_qpp, qpp, num_seg;
1799
1800                 s_qpp = (S_QUEUESPERPAGEPF0 +
1801                         (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1802                         adapter->pf);
1803                 qpp = 1 << ((t4_read_reg(adapter,
1804                                 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1805                                 & M_QUEUESPERPAGEPF0);
1806                 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1807                 if (qpp > num_seg)
1808                         dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1809
1810                 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1811                 if (!adapter->bar2) {
1812                         dev_err(adapter, "cannot map device bar2 region\n");
1813                         err = -ENOMEM;
1814                         goto out_free;
1815                 }
1816                 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1817                              V_STATMODE(0));
1818         }
1819
1820         for_each_port(adapter, i) {
1821                 const unsigned int numa_node = rte_socket_id();
1822                 char name[RTE_ETH_NAME_MAX_LEN];
1823                 struct rte_eth_dev *eth_dev;
1824
1825                 snprintf(name, sizeof(name), "%s_%d",
1826                          adapter->pdev->device.name, i);
1827
1828                 if (i == 0) {
1829                         /* First port is already allocated by DPDK */
1830                         eth_dev = adapter->eth_dev;
1831                         goto allocate_mac;
1832                 }
1833
1834                 /*
1835                  * now do all data allocation - for eth_dev structure,
1836                  * and internal (private) data for the remaining ports
1837                  */
1838
1839                 /* reserve an ethdev entry */
1840                 eth_dev = rte_eth_dev_allocate(name);
1841                 if (!eth_dev)
1842                         goto out_free;
1843
1844                 eth_dev->data->dev_private =
1845                         rte_zmalloc_socket(name, sizeof(struct port_info),
1846                                            RTE_CACHE_LINE_SIZE, numa_node);
1847                 if (!eth_dev->data->dev_private)
1848                         goto out_free;
1849
1850 allocate_mac:
1851                 pi = eth_dev->data->dev_private;
1852                 adapter->port[i] = pi;
1853                 pi->eth_dev = eth_dev;
1854                 pi->adapter = adapter;
1855                 pi->xact_addr_filt = -1;
1856                 pi->port_id = i;
1857                 pi->pidx = i;
1858
1859                 pi->eth_dev->device = &adapter->pdev->device;
1860                 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1861                 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1862                 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1863
1864                 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1865
1866                 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1867                                                         RTE_ETHER_ADDR_LEN, 0);
1868                 if (!pi->eth_dev->data->mac_addrs) {
1869                         dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1870                                 __func__);
1871                         err = -1;
1872                         goto out_free;
1873                 }
1874
1875                 if (i > 0) {
1876                         /* First port will be notified by upper layer */
1877                         rte_eth_dev_probing_finish(eth_dev);
1878                 }
1879         }
1880
1881         if (adapter->flags & FW_OK) {
1882                 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1883                 if (err) {
1884                         dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1885                                 __func__, err);
1886                         goto out_free;
1887                 }
1888         }
1889
1890         cxgbe_cfg_queues(adapter->eth_dev);
1891
1892         cxgbe_print_adapter_info(adapter);
1893         cxgbe_print_port_info(adapter);
1894
1895         adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
1896                                           adapter->clipt_end);
1897         if (!adapter->clipt) {
1898                 /* We tolerate a lack of clip_table, giving up some
1899                  * functionality
1900                  */
1901                 dev_warn(adapter, "could not allocate CLIP. Continuing\n");
1902         }
1903
1904         adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
1905         if (!adapter->l2t) {
1906                 /* We tolerate a lack of L2T, giving up some functionality */
1907                 dev_warn(adapter, "could not allocate L2T. Continuing\n");
1908         }
1909
1910         if (tid_init(&adapter->tids) < 0) {
1911                 /* Disable filtering support */
1912                 dev_warn(adapter, "could not allocate TID table, "
1913                          "filter support disabled. Continuing\n");
1914         }
1915
1916         adapter->mpstcam = t4_init_mpstcam(adapter);
1917         if (!adapter->mpstcam)
1918                 dev_warn(adapter, "could not allocate mps tcam table."
1919                          " Continuing\n");
1920
1921         if (is_hashfilter(adapter)) {
1922                 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) {
1923                         u32 hash_base, hash_reg;
1924
1925                         hash_reg = A_LE_DB_TID_HASHBASE;
1926                         hash_base = t4_read_reg(adapter, hash_reg);
1927                         adapter->tids.hash_base = hash_base / 4;
1928                 }
1929         } else {
1930                 /* Disable hash filtering support */
1931                 dev_warn(adapter,
1932                          "Maskless filter support disabled. Continuing\n");
1933         }
1934
1935         err = cxgbe_init_rss(adapter);
1936         if (err)
1937                 goto out_free;
1938
1939         return 0;
1940
1941 out_free:
1942         for_each_port(adapter, i) {
1943                 pi = adap2pinfo(adapter, i);
1944                 if (pi->viid != 0)
1945                         t4_free_vi(adapter, adapter->mbox, adapter->pf,
1946                                    0, pi->viid);
1947                 rte_eth_dev_release_port(pi->eth_dev);
1948         }
1949
1950         if (adapter->flags & FW_OK)
1951                 t4_fw_bye(adapter, adapter->mbox);
1952         return -err;
1953 }