4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
46 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_ethdev_pci.h>
61 #include <rte_atomic.h>
62 #include <rte_malloc.h>
63 #include <rte_random.h>
72 * Response queue handler for the FW event queue.
74 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
75 __rte_unused const struct pkt_gl *gl)
77 u8 opcode = ((const struct rss_header *)rsp)->opcode;
79 rsp++; /* skip RSS header */
82 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
84 if (unlikely(opcode == CPL_FW4_MSG &&
85 ((const struct cpl_fw4_msg *)rsp)->type ==
88 opcode = ((const struct rss_header *)rsp)->opcode;
90 if (opcode != CPL_SGE_EGR_UPDATE) {
91 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
97 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
99 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
100 const struct cpl_fw6_msg *msg = (const void *)rsp;
102 t4_handle_fw_rpl(q->adapter, msg->data);
104 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
111 int setup_sge_fwevtq(struct adapter *adapter)
113 struct sge *s = &adapter->sge;
117 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
118 msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
123 static int closest_timer(const struct sge *s, int time)
125 unsigned int i, match = 0;
126 int delta, min_delta = INT_MAX;
128 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
129 delta = time - s->timer_val[i];
132 if (delta < min_delta) {
140 static int closest_thres(const struct sge *s, int thres)
142 unsigned int i, match = 0;
143 int delta, min_delta = INT_MAX;
145 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
146 delta = thres - s->counter_val[i];
149 if (delta < min_delta) {
158 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
160 * @us: the hold-off time in us, or 0 to disable timer
161 * @cnt: the hold-off packet count, or 0 to disable counter
163 * Sets an Rx queue's interrupt hold-off time and packet count. At least
164 * one of the two needs to be enabled for the queue to generate interrupts.
166 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
169 struct adapter *adap = q->adapter;
170 unsigned int timer_val;
176 new_idx = closest_thres(&adap->sge, cnt);
177 if (q->desc && q->pktcnt_idx != new_idx) {
178 /* the queue has already been created, update it */
179 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
181 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
182 V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
183 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
188 q->pktcnt_idx = new_idx;
191 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
192 closest_timer(&adap->sge, us);
195 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
197 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
198 V_QINTR_CNT_EN(cnt > 0);
202 static inline bool is_x_1g_port(const struct link_config *lc)
204 return (lc->supported & FW_PORT_CAP_SPEED_1G) != 0;
207 static inline bool is_x_10g_port(const struct link_config *lc)
209 unsigned int speeds, high_speeds;
211 speeds = V_FW_PORT_CAP_SPEED(G_FW_PORT_CAP_SPEED(lc->supported));
212 high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G);
214 return high_speeds != 0;
217 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
218 unsigned int us, unsigned int cnt,
219 unsigned int size, unsigned int iqe_size)
222 cxgb4_set_rspq_intr_params(q, us, cnt);
223 q->iqe_len = iqe_size;
227 int cfg_queue_count(struct rte_eth_dev *eth_dev)
229 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
230 struct adapter *adap = pi->adapter;
231 struct sge *s = &adap->sge;
232 unsigned int max_queues = s->max_ethqsets / adap->params.nports;
234 if ((eth_dev->data->nb_rx_queues < 1) ||
235 (eth_dev->data->nb_tx_queues < 1))
238 if ((eth_dev->data->nb_rx_queues > max_queues) ||
239 (eth_dev->data->nb_tx_queues > max_queues))
242 if (eth_dev->data->nb_rx_queues > pi->rss_size)
245 /* We must configure RSS, since config has changed*/
246 pi->flags &= ~PORT_RSS_DONE;
248 pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
249 pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
254 void cfg_queues(struct rte_eth_dev *eth_dev)
256 struct rte_config *config = rte_eal_get_configuration();
257 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
258 struct adapter *adap = pi->adapter;
259 struct sge *s = &adap->sge;
260 unsigned int i, nb_ports = 0, qidx = 0;
261 unsigned int q_per_port = 0;
263 if (!(adap->flags & CFG_QUEUES)) {
264 for_each_port(adap, i) {
265 struct port_info *tpi = adap2pinfo(adap, i);
267 nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
268 is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
272 * We default up to # of cores queues per 1G/10G port.
275 q_per_port = (MAX_ETH_QSETS -
276 (adap->params.nports - nb_ports)) /
279 if (q_per_port > config->lcore_count)
280 q_per_port = config->lcore_count;
282 for_each_port(adap, i) {
283 struct port_info *pi = adap2pinfo(adap, i);
285 pi->first_qset = qidx;
287 /* Initially n_rx_qsets == n_tx_qsets */
288 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
289 is_x_1g_port(&pi->link_cfg)) ?
291 pi->n_tx_qsets = pi->n_rx_qsets;
293 if (pi->n_rx_qsets > pi->rss_size)
294 pi->n_rx_qsets = pi->rss_size;
296 qidx += pi->n_rx_qsets;
299 s->max_ethqsets = qidx;
301 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
302 struct sge_eth_rxq *r = &s->ethrxq[i];
304 init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
306 r->fl.size = (r->usembufs ? 1024 : 72);
309 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
310 s->ethtxq[i].q.size = 1024;
312 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
313 adap->flags |= CFG_QUEUES;
317 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
319 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
323 void cxgbe_stats_reset(struct port_info *pi)
325 t4_clr_port_stats(pi->adapter, pi->tx_chan);
328 static void setup_memwin(struct adapter *adap)
332 /* For T5, only relative offset inside the PCIe BAR is passed */
333 mem_win0_base = MEMWIN0_BASE;
336 * Set up memory window for accessing adapter memory ranges. (Read
337 * back MA register to ensure that changes propagate before we attempt
338 * to use the new values.)
341 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
343 mem_win0_base | V_BIR(0) |
344 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
346 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
350 static int init_rss(struct adapter *adap)
355 err = t4_init_rss_mode(adap, adap->mbox);
359 for_each_port(adap, i) {
360 struct port_info *pi = adap2pinfo(adap, i);
362 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
370 * Dump basic information about the adapter.
372 static void print_adapter_info(struct adapter *adap)
375 * Hardware/Firmware/etc. Version/Revision IDs.
377 t4_dump_version_info(adap);
380 static void print_port_info(struct adapter *adap)
384 struct rte_pci_addr *loc = &adap->pdev->addr;
386 for_each_port(adap, i) {
387 const struct port_info *pi = &adap->port[i];
390 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
391 bufp += sprintf(bufp, "100M/");
392 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
393 bufp += sprintf(bufp, "1G/");
394 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
395 bufp += sprintf(bufp, "10G/");
396 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
397 bufp += sprintf(bufp, "25G/");
398 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
399 bufp += sprintf(bufp, "40G/");
400 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
401 bufp += sprintf(bufp, "100G/");
404 sprintf(bufp, "BASE-%s",
405 t4_get_port_type_description(
406 (enum fw_port_type)pi->port_type));
409 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
410 loc->domain, loc->bus, loc->devid, loc->function,
411 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
412 (adap->flags & USING_MSIX) ? " MSI-X" :
413 (adap->flags & USING_MSI) ? " MSI" : "");
418 * Tweak configuration based on system architecture, etc. Most of these have
419 * defaults assigned to them by Firmware Configuration Files (if we're using
420 * them) but need to be explicitly set if we're using hard-coded
421 * initialization. So these are essentially common tweaks/settings for
422 * Configuration Files and hard-coded initialization ...
424 static int adap_init0_tweaks(struct adapter *adapter)
429 * Fix up various Host-Dependent Parameters like Page Size, Cache
430 * Line Size, etc. The firmware default is for a 4KB Page Size and
431 * 64B Cache Line Size ...
433 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
437 * Keep the chip default offset to deliver Ingress packets into our
438 * DMA buffers to zero
441 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
442 V_PKTSHIFT(rx_dma_offset));
444 t4_set_reg_field(adapter, A_SGE_FLM_CFG,
445 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
446 V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
448 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
449 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
451 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
452 V_IDMAARBROUNDROBIN(1U));
455 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
456 * adds the pseudo header itself.
458 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
459 F_CSUM_HAS_PSEUDO_HDR, 0);
465 * Attempt to initialize the adapter via a Firmware Configuration File.
467 static int adap_init0_config(struct adapter *adapter, int reset)
469 struct fw_caps_config_cmd caps_cmd;
470 unsigned long mtype = 0, maddr = 0;
471 u32 finiver, finicsum, cfcsum;
473 int config_issued = 0;
475 char config_name[20];
478 * Reset device if necessary.
481 ret = t4_fw_reset(adapter, adapter->mbox,
482 F_PIORSTMODE | F_PIORST);
484 dev_warn(adapter, "Firmware reset failed, error %d\n",
490 cfg_addr = t4_flash_cfg_addr(adapter);
493 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
498 strcpy(config_name, "On Flash");
499 mtype = FW_MEMTYPE_CF_FLASH;
503 * Issue a Capability Configuration command to the firmware to get it
504 * to parse the Configuration File. We don't use t4_fw_config_file()
505 * because we want the ability to modify various features after we've
506 * processed the configuration file ...
508 memset(&caps_cmd, 0, sizeof(caps_cmd));
509 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
510 F_FW_CMD_REQUEST | F_FW_CMD_READ);
511 caps_cmd.cfvalid_to_len16 =
512 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
513 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
514 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
516 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
519 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
520 * Configuration File in FLASH), our last gasp effort is to use the
521 * Firmware Configuration File which is embedded in the firmware. A
522 * very few early versions of the firmware didn't have one embedded
523 * but we can ignore those.
525 if (ret == -ENOENT) {
526 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
529 memset(&caps_cmd, 0, sizeof(caps_cmd));
530 caps_cmd.op_to_write =
531 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
532 F_FW_CMD_REQUEST | F_FW_CMD_READ);
533 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
534 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
535 sizeof(caps_cmd), &caps_cmd);
536 strcpy(config_name, "Firmware Default");
543 finiver = be32_to_cpu(caps_cmd.finiver);
544 finicsum = be32_to_cpu(caps_cmd.finicsum);
545 cfcsum = be32_to_cpu(caps_cmd.cfcsum);
546 if (finicsum != cfcsum)
547 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
551 * If we're a pure NIC driver then disable all offloading facilities.
552 * This will allow the firmware to optimize aspects of the hardware
553 * configuration which will result in improved performance.
555 caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
556 FW_CAPS_CONFIG_NIC_ETHOFLD));
557 caps_cmd.toecaps = 0;
558 caps_cmd.iscsicaps = 0;
559 caps_cmd.rdmacaps = 0;
560 caps_cmd.fcoecaps = 0;
563 * And now tell the firmware to use the configuration we just loaded.
565 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
566 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
567 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
568 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
571 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
577 * Tweak configuration based on system architecture, etc.
579 ret = adap_init0_tweaks(adapter);
581 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
586 * And finally tell the firmware to initialize itself using the
587 * parameters from the Configuration File.
589 ret = t4_fw_initialize(adapter, adapter->mbox);
591 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
597 * Return successfully and note that we're operating with parameters
598 * not supplied by the driver, rather than from hard-wired
599 * initialization constants burried in the driver.
602 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
603 config_name, finiver, cfcsum);
608 * Something bad happened. Return the error ... (If the "error"
609 * is that there's no Configuration File on the adapter we don't
610 * want to issue a warning since this is fairly common.)
613 if (config_issued && ret != -ENOENT)
614 dev_warn(adapter, "\"%s\" configuration file error %d\n",
617 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
621 static int adap_init0(struct adapter *adap)
625 enum dev_state state;
626 u32 params[7], val[7];
628 int mbox = adap->mbox;
631 * Contact FW, advertising Master capability.
633 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
635 dev_err(adap, "%s: could not connect to FW, error %d\n",
640 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
644 adap->flags |= MASTER_PF;
646 if (state == DEV_STATE_INIT) {
648 * Force halt and reset FW because a previous instance may have
649 * exited abnormally without properly shutting down
651 ret = t4_fw_halt(adap, adap->mbox, reset);
653 dev_err(adap, "Failed to halt. Exit.\n");
657 ret = t4_fw_restart(adap, adap->mbox, reset);
659 dev_err(adap, "Failed to restart. Exit.\n");
662 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
665 t4_get_version_info(adap);
667 ret = t4_get_core_clock(adap, &adap->params.vpd);
669 dev_err(adap, "%s: could not get core clock, error %d\n",
675 * If the firmware is initialized already (and we're not forcing a
676 * master initialization), note that we're living with existing
677 * adapter parameters. Otherwise, it's time to try initializing the
680 if (state == DEV_STATE_INIT) {
681 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
682 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
684 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
686 ret = adap_init0_config(adap, reset);
687 if (ret == -ENOENT) {
689 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
694 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
698 /* Find out what ports are available to us. */
699 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
700 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
701 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
703 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
708 adap->params.nports = hweight32(port_vec);
709 adap->params.portvec = port_vec;
711 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
712 adap->params.nports);
715 * Give the SGE code a chance to pull in anything that it needs ...
716 * Note that this must be called after we retrieve our VPD parameters
717 * in order to know how to convert core ticks to seconds, etc.
719 ret = t4_sge_init(adap);
721 dev_err(adap, "t4_sge_init failed with error %d\n",
727 * Grab some of our basic fundamental operating parameters.
729 #define FW_PARAM_DEV(param) \
730 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
731 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
733 #define FW_PARAM_PFVF(param) \
734 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
735 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
736 V_FW_PARAMS_PARAM_Y(0) | \
737 V_FW_PARAMS_PARAM_Z(0))
739 /* If we're running on newer firmware, let it know that we're
740 * prepared to deal with encapsulated CPL messages. Older
741 * firmware won't understand this and we'll just get
742 * unencapsulated messages ...
744 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
746 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
749 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
750 * capability. Earlier versions of the firmware didn't have the
751 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
752 * permission to use ULPTX MEMWRITE DSGL.
754 if (is_t4(adap->params.chip)) {
755 adap->params.ulptx_memwrite_dsgl = false;
757 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
758 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
760 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
764 * The MTU/MSS Table is initialized by now, so load their values. If
765 * we're initializing the adapter, then we'll make any modifications
766 * we want to the MTU/MSS Table and also initialize the congestion
769 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
770 if (state != DEV_STATE_INIT) {
774 * The default MTU Table contains values 1492 and 1500.
775 * However, for TCP, it's better to have two values which are
776 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
777 * This allows us to have a TCP Data Payload which is a
778 * multiple of 8 regardless of what combination of TCP Options
779 * are in use (always a multiple of 4 bytes) which is
780 * important for performance reasons. For instance, if no
781 * options are in use, then we have a 20-byte IP header and a
782 * 20-byte TCP header. In this case, a 1500-byte MSS would
783 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
784 * which is not a multiple of 8. So using an MSS of 1488 in
785 * this case results in a TCP Data Payload of 1448 bytes which
786 * is a multiple of 8. On the other hand, if 12-byte TCP Time
787 * Stamps have been negotiated, then an MTU of 1500 bytes
788 * results in a TCP Data Payload of 1448 bytes which, as
789 * above, is a multiple of 8 bytes ...
791 for (i = 0; i < NMTUS; i++)
792 if (adap->params.mtus[i] == 1492) {
793 adap->params.mtus[i] = 1488;
797 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
800 t4_init_sge_params(adap);
801 t4_init_tp_params(adap);
803 adap->params.drv_memwin = MEMWIN_NIC;
804 adap->flags |= FW_OK;
805 dev_debug(adap, "%s: returning zero..\n", __func__);
809 * Something bad happened. If a command timed out or failed with EIO
810 * FW does not operate within its spec or something catastrophic
811 * happened to HW/FW, stop issuing commands.
814 if (ret != -ETIMEDOUT && ret != -EIO)
815 t4_fw_bye(adap, adap->mbox);
820 * t4_os_portmod_changed - handle port module changes
821 * @adap: the adapter associated with the module change
822 * @port_id: the port index whose module status has changed
824 * This is the OS-dependent handler for port module changes. It is
825 * invoked when a port module is removed or inserted for any OS-specific
828 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
830 static const char * const mod_str[] = {
831 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
834 const struct port_info *pi = &adap->port[port_id];
836 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
837 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
838 else if (pi->mod_type < ARRAY_SIZE(mod_str))
839 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
840 mod_str[pi->mod_type]);
841 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
842 dev_info(adap, "Port%d: unsupported port module inserted\n",
844 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
845 dev_info(adap, "Port%d: unknown port module inserted\n",
847 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
848 dev_info(adap, "Port%d: transceiver module error\n",
851 dev_info(adap, "Port%d: unknown module type %d inserted\n",
852 pi->port_id, pi->mod_type);
856 * link_start - enable a port
857 * @dev: the port to enable
859 * Performs the MAC and PHY actions needed to enable a port.
861 int link_start(struct port_info *pi)
863 struct adapter *adapter = pi->adapter;
867 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
868 (ETHER_HDR_LEN + ETHER_CRC_LEN);
871 * We do not set address filters and promiscuity here, the stack does
872 * that step explicitly.
874 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
877 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
879 (u8 *)&pi->eth_dev->data->mac_addrs[0],
882 pi->xact_addr_filt = ret;
887 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
891 * Enabling a Virtual Interface can result in an interrupt
892 * during the processing of the VI Enable command and, in some
893 * paths, result in an attempt to issue another command in the
894 * interrupt context. Thus, we disable interrupts during the
895 * course of the VI Enable command ...
897 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
904 * cxgb4_write_rss - write the RSS table for a given port
906 * @queues: array of queue indices for RSS
908 * Sets up the portion of the HW RSS table for the port's VI to distribute
909 * packets to the Rx queues in @queues.
911 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
915 struct adapter *adapter = pi->adapter;
916 const struct sge_eth_rxq *rxq;
918 /* Should never be called before setting up sge eth rx queues */
919 BUG_ON(!(adapter->flags & FULL_INIT_DONE));
921 rxq = &adapter->sge.ethrxq[pi->first_qset];
922 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
926 /* map the queue indices to queue ids */
927 for (i = 0; i < pi->rss_size; i++, queues++)
928 rss[i] = rxq[*queues].rspq.abs_id;
930 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
931 pi->rss_size, rss, pi->rss_size);
933 * If Tunnel All Lookup isn't specified in the global RSS
934 * Configuration, then we need to specify a default Ingress
935 * Queue for any ingress packets which aren't hashed. We'll
936 * use our first ingress queue ...
939 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
940 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
941 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
942 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
943 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN |
944 F_FW_RSS_VI_CONFIG_CMD_UDPEN,
951 * setup_rss - configure RSS
952 * @adapter: the adapter
954 * Sets up RSS to distribute packets to multiple receive queues. We
955 * configure the RSS CPU lookup table to distribute to the number of HW
956 * receive queues, and the response queue lookup table to narrow that
957 * down to the response queues actually configured for each port.
958 * We always configure the RSS mapping for all ports since the mapping
959 * table has plenty of entries.
961 int setup_rss(struct port_info *pi)
964 struct adapter *adapter = pi->adapter;
966 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n",
967 __func__, pi->rss_size, pi->n_rx_qsets);
969 if (!(pi->flags & PORT_RSS_DONE)) {
970 if (adapter->flags & FULL_INIT_DONE) {
971 /* Fill default values with equal distribution */
972 for (j = 0; j < pi->rss_size; j++)
973 pi->rss[j] = j % pi->n_rx_qsets;
975 err = cxgb4_write_rss(pi, pi->rss);
978 pi->flags |= PORT_RSS_DONE;
985 * Enable NAPI scheduling and interrupt generation for all Rx queues.
987 static void enable_rx(struct adapter *adap)
989 struct sge *s = &adap->sge;
990 struct sge_rspq *q = &s->fw_evtq;
993 /* 0-increment GTS to start the timer and enable interrupts */
994 t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS),
995 V_SEINTARM(q->intr_params) |
996 V_INGRESSQID(q->cntxt_id));
998 for_each_port(adap, i) {
999 const struct port_info *pi = &adap->port[i];
1000 struct rte_eth_dev *eth_dev = pi->eth_dev;
1002 for (j = 0; j < eth_dev->data->nb_rx_queues; j++) {
1003 q = eth_dev->data->rx_queues[j];
1006 * 0-increment GTS to start the timer and enable
1009 t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS),
1010 V_SEINTARM(q->intr_params) |
1011 V_INGRESSQID(q->cntxt_id));
1017 * cxgb_up - enable the adapter
1018 * @adap: adapter being enabled
1020 * Called when the first port is enabled, this function performs the
1021 * actions necessary to make an adapter operational, such as completing
1022 * the initialization of HW modules, and enabling interrupts.
1024 int cxgbe_up(struct adapter *adap)
1027 t4_sge_tx_monitor_start(adap);
1028 t4_intr_enable(adap);
1029 adap->flags |= FULL_INIT_DONE;
1031 /* TODO: deadman watchdog ?? */
1038 int cxgbe_down(struct port_info *pi)
1040 struct adapter *adapter = pi->adapter;
1043 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1045 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1049 t4_reset_link_config(adapter, pi->port_id);
1054 * Release resources when all the ports have been stopped.
1056 void cxgbe_close(struct adapter *adapter)
1058 struct port_info *pi;
1061 if (adapter->flags & FULL_INIT_DONE) {
1062 t4_intr_disable(adapter);
1063 t4_sge_tx_monitor_stop(adapter);
1064 t4_free_sge_resources(adapter);
1065 for_each_port(adapter, i) {
1066 pi = adap2pinfo(adapter, i);
1068 t4_free_vi(adapter, adapter->mbox,
1069 adapter->pf, 0, pi->viid);
1070 rte_free(pi->eth_dev->data->mac_addrs);
1072 adapter->flags &= ~FULL_INIT_DONE;
1075 if (adapter->flags & FW_OK)
1076 t4_fw_bye(adapter, adapter->mbox);
1079 int cxgbe_probe(struct adapter *adapter)
1081 struct port_info *pi;
1087 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1088 chip = t4_get_chip_type(adapter,
1089 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1093 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1094 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1096 adapter->mbox = func;
1099 t4_os_lock_init(&adapter->mbox_lock);
1100 TAILQ_INIT(&adapter->mbox_list);
1102 err = t4_prep_adapter(adapter);
1106 setup_memwin(adapter);
1107 err = adap_init0(adapter);
1109 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1114 if (!is_t4(adapter->params.chip)) {
1116 * The userspace doorbell BAR is split evenly into doorbell
1117 * regions, each associated with an egress queue. If this
1118 * per-queue region is large enough (at least UDBS_SEG_SIZE)
1119 * then it can be used to submit a tx work request with an
1120 * implied doorbell. Enable write combining on the BAR if
1121 * there is room for such work requests.
1123 int s_qpp, qpp, num_seg;
1125 s_qpp = (S_QUEUESPERPAGEPF0 +
1126 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1128 qpp = 1 << ((t4_read_reg(adapter,
1129 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1130 & M_QUEUESPERPAGEPF0);
1131 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1133 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1135 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1136 if (!adapter->bar2) {
1137 dev_err(adapter, "cannot map device bar2 region\n");
1141 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1145 for_each_port(adapter, i) {
1146 char name[RTE_ETH_NAME_MAX_LEN];
1147 struct rte_eth_dev_data *data = NULL;
1148 const unsigned int numa_node = rte_socket_id();
1150 pi = &adapter->port[i];
1151 pi->adapter = adapter;
1152 pi->xact_addr_filt = -1;
1155 snprintf(name, sizeof(name), "cxgbe%d",
1156 adapter->eth_dev->data->port_id + i);
1159 /* First port is already allocated by DPDK */
1160 pi->eth_dev = adapter->eth_dev;
1165 * now do all data allocation - for eth_dev structure,
1166 * and internal (private) data for the remaining ports
1169 /* reserve an ethdev entry */
1170 pi->eth_dev = rte_eth_dev_allocate(name);
1174 data = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node);
1178 data->port_id = adapter->eth_dev->data->port_id + i;
1180 pi->eth_dev->data = data;
1183 pi->eth_dev->device = &adapter->pdev->device;
1184 pi->eth_dev->data->dev_private = pi;
1185 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1186 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1187 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1189 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1191 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1193 if (!pi->eth_dev->data->mac_addrs) {
1194 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1201 if (adapter->flags & FW_OK) {
1202 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1204 dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1210 cfg_queues(adapter->eth_dev);
1212 print_adapter_info(adapter);
1213 print_port_info(adapter);
1215 err = init_rss(adapter);
1222 for_each_port(adapter, i) {
1223 pi = adap2pinfo(adapter, i);
1225 t4_free_vi(adapter, adapter->mbox, adapter->pf,
1227 /* Skip first port since it'll be de-allocated by DPDK */
1230 if (pi->eth_dev->data)
1231 rte_free(pi->eth_dev->data);
1234 if (adapter->flags & FW_OK)
1235 t4_fw_bye(adapter, adapter->mbox);