1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_atomic.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_tailq.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_random.h>
34 #include <rte_kvargs.h>
42 * Allocate a chunk of memory. The allocated memory is cleared.
44 void *t4_alloc_mem(size_t size)
46 return rte_zmalloc(NULL, size, 0);
50 * Free memory allocated through t4_alloc_mem().
52 void t4_free_mem(void *addr)
58 * Response queue handler for the FW event queue.
60 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
61 __rte_unused const struct pkt_gl *gl)
63 u8 opcode = ((const struct rss_header *)rsp)->opcode;
65 rsp++; /* skip RSS header */
68 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
70 if (unlikely(opcode == CPL_FW4_MSG &&
71 ((const struct cpl_fw4_msg *)rsp)->type ==
74 opcode = ((const struct rss_header *)rsp)->opcode;
76 if (opcode != CPL_SGE_EGR_UPDATE) {
77 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
83 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
85 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
86 const struct cpl_fw6_msg *msg = (const void *)rsp;
88 t4_handle_fw_rpl(q->adapter, msg->data);
90 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
98 * Setup sge control queues to pass control information.
100 int setup_sge_ctrl_txq(struct adapter *adapter)
102 struct sge *s = &adapter->sge;
105 for_each_port(adapter, i) {
106 char name[RTE_ETH_NAME_MAX_LEN];
107 struct sge_ctrl_txq *q = &s->ctrlq[i];
110 err = t4_sge_alloc_ctrl_txq(adapter, q,
115 dev_err(adapter, "Failed to alloc ctrl txq. Err: %d",
119 snprintf(name, sizeof(name), "cxgbe_ctrl_pool_%d", i);
120 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
123 RTE_MBUF_DEFAULT_BUF_SIZE,
126 dev_err(adapter, "Can't create ctrl pool for port: %d",
134 t4_free_sge_resources(adapter);
138 int setup_sge_fwevtq(struct adapter *adapter)
140 struct sge *s = &adapter->sge;
144 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
145 msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
150 static int closest_timer(const struct sge *s, int time)
152 unsigned int i, match = 0;
153 int delta, min_delta = INT_MAX;
155 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
156 delta = time - s->timer_val[i];
159 if (delta < min_delta) {
167 static int closest_thres(const struct sge *s, int thres)
169 unsigned int i, match = 0;
170 int delta, min_delta = INT_MAX;
172 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
173 delta = thres - s->counter_val[i];
176 if (delta < min_delta) {
185 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
187 * @us: the hold-off time in us, or 0 to disable timer
188 * @cnt: the hold-off packet count, or 0 to disable counter
190 * Sets an Rx queue's interrupt hold-off time and packet count. At least
191 * one of the two needs to be enabled for the queue to generate interrupts.
193 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
196 struct adapter *adap = q->adapter;
197 unsigned int timer_val;
203 new_idx = closest_thres(&adap->sge, cnt);
204 if (q->desc && q->pktcnt_idx != new_idx) {
205 /* the queue has already been created, update it */
206 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
208 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
209 V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
210 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
215 q->pktcnt_idx = new_idx;
218 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
219 closest_timer(&adap->sge, us);
222 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
224 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
225 V_QINTR_CNT_EN(cnt > 0);
232 static void tid_free(struct tid_info *t)
236 rte_bitmap_free(t->ftid_bmap);
238 if (t->ftid_bmap_array)
239 t4_os_free(t->ftid_bmap_array);
241 t4_os_free(t->tid_tab);
244 memset(t, 0, sizeof(struct tid_info));
248 * Allocate and initialize the TID tables. Returns 0 on success.
250 static int tid_init(struct tid_info *t)
253 unsigned int ftid_bmap_size;
254 unsigned int max_ftids = t->nftids;
256 ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
257 size = t->ntids * sizeof(*t->tid_tab) +
258 max_ftids * sizeof(*t->ftid_tab);
260 t->tid_tab = t4_os_alloc(size);
264 t->ftid_tab = (struct filter_entry *)&t->tid_tab[t->ntids];
265 t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
266 if (!t->ftid_bmap_array) {
271 t4_os_lock_init(&t->ftid_lock);
272 t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
282 static inline bool is_x_1g_port(const struct link_config *lc)
284 return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
287 static inline bool is_x_10g_port(const struct link_config *lc)
289 unsigned int speeds, high_speeds;
291 speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
292 high_speeds = speeds &
293 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
295 return high_speeds != 0;
298 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
299 unsigned int us, unsigned int cnt,
300 unsigned int size, unsigned int iqe_size)
303 cxgb4_set_rspq_intr_params(q, us, cnt);
304 q->iqe_len = iqe_size;
308 int cfg_queue_count(struct rte_eth_dev *eth_dev)
310 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
311 struct adapter *adap = pi->adapter;
312 struct sge *s = &adap->sge;
313 unsigned int max_queues = s->max_ethqsets / adap->params.nports;
315 if ((eth_dev->data->nb_rx_queues < 1) ||
316 (eth_dev->data->nb_tx_queues < 1))
319 if ((eth_dev->data->nb_rx_queues > max_queues) ||
320 (eth_dev->data->nb_tx_queues > max_queues))
323 if (eth_dev->data->nb_rx_queues > pi->rss_size)
326 /* We must configure RSS, since config has changed*/
327 pi->flags &= ~PORT_RSS_DONE;
329 pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
330 pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
335 void cfg_queues(struct rte_eth_dev *eth_dev)
337 struct rte_config *config = rte_eal_get_configuration();
338 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
339 struct adapter *adap = pi->adapter;
340 struct sge *s = &adap->sge;
341 unsigned int i, nb_ports = 0, qidx = 0;
342 unsigned int q_per_port = 0;
344 if (!(adap->flags & CFG_QUEUES)) {
345 for_each_port(adap, i) {
346 struct port_info *tpi = adap2pinfo(adap, i);
348 nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
349 is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
353 * We default up to # of cores queues per 1G/10G port.
356 q_per_port = (MAX_ETH_QSETS -
357 (adap->params.nports - nb_ports)) /
360 if (q_per_port > config->lcore_count)
361 q_per_port = config->lcore_count;
363 for_each_port(adap, i) {
364 struct port_info *pi = adap2pinfo(adap, i);
366 pi->first_qset = qidx;
368 /* Initially n_rx_qsets == n_tx_qsets */
369 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
370 is_x_1g_port(&pi->link_cfg)) ?
372 pi->n_tx_qsets = pi->n_rx_qsets;
374 if (pi->n_rx_qsets > pi->rss_size)
375 pi->n_rx_qsets = pi->rss_size;
377 qidx += pi->n_rx_qsets;
380 s->max_ethqsets = qidx;
382 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
383 struct sge_eth_rxq *r = &s->ethrxq[i];
385 init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
387 r->fl.size = (r->usembufs ? 1024 : 72);
390 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
391 s->ethtxq[i].q.size = 1024;
393 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
394 adap->flags |= CFG_QUEUES;
398 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
400 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
404 void cxgbe_stats_reset(struct port_info *pi)
406 t4_clr_port_stats(pi->adapter, pi->tx_chan);
409 static void setup_memwin(struct adapter *adap)
413 /* For T5, only relative offset inside the PCIe BAR is passed */
414 mem_win0_base = MEMWIN0_BASE;
417 * Set up memory window for accessing adapter memory ranges. (Read
418 * back MA register to ensure that changes propagate before we attempt
419 * to use the new values.)
422 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
424 mem_win0_base | V_BIR(0) |
425 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
427 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
431 int init_rss(struct adapter *adap)
438 err = t4_init_rss_mode(adap, adap->mbox);
443 for_each_port(adap, i) {
444 struct port_info *pi = adap2pinfo(adap, i);
446 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
450 pi->rss_hf = CXGBE_RSS_HF_ALL;
456 * Dump basic information about the adapter.
458 void print_adapter_info(struct adapter *adap)
461 * Hardware/Firmware/etc. Version/Revision IDs.
463 t4_dump_version_info(adap);
466 void print_port_info(struct adapter *adap)
470 struct rte_pci_addr *loc = &adap->pdev->addr;
472 for_each_port(adap, i) {
473 const struct port_info *pi = adap2pinfo(adap, i);
476 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
477 bufp += sprintf(bufp, "100M/");
478 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
479 bufp += sprintf(bufp, "1G/");
480 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
481 bufp += sprintf(bufp, "10G/");
482 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
483 bufp += sprintf(bufp, "25G/");
484 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
485 bufp += sprintf(bufp, "40G/");
486 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
487 bufp += sprintf(bufp, "50G/");
488 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
489 bufp += sprintf(bufp, "100G/");
492 sprintf(bufp, "BASE-%s",
493 t4_get_port_type_description(
494 (enum fw_port_type)pi->port_type));
497 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
498 loc->domain, loc->bus, loc->devid, loc->function,
499 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
500 (adap->flags & USING_MSIX) ? " MSI-X" :
501 (adap->flags & USING_MSI) ? " MSI" : "");
506 check_devargs_handler(__rte_unused const char *key, const char *value,
507 __rte_unused void *opaque)
509 if (strcmp(value, "1"))
515 int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key)
517 struct rte_kvargs *kvlist;
522 kvlist = rte_kvargs_parse(devargs->args, NULL);
526 if (!rte_kvargs_count(kvlist, key)) {
527 rte_kvargs_free(kvlist);
531 if (rte_kvargs_process(kvlist, key,
532 check_devargs_handler, NULL) < 0) {
533 rte_kvargs_free(kvlist);
536 rte_kvargs_free(kvlist);
541 static void configure_vlan_types(struct adapter *adapter)
543 struct rte_pci_device *pdev = adapter->pdev;
546 for_each_port(adapter, i) {
547 /* OVLAN Type 0x88a8 */
548 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
549 V_OVLAN_MASK(M_OVLAN_MASK) |
550 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
551 V_OVLAN_MASK(M_OVLAN_MASK) |
552 V_OVLAN_ETYPE(0x88a8));
553 /* OVLAN Type 0x9100 */
554 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
555 V_OVLAN_MASK(M_OVLAN_MASK) |
556 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
557 V_OVLAN_MASK(M_OVLAN_MASK) |
558 V_OVLAN_ETYPE(0x9100));
559 /* OVLAN Type 0x8100 */
560 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
561 V_OVLAN_MASK(M_OVLAN_MASK) |
562 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
563 V_OVLAN_MASK(M_OVLAN_MASK) |
564 V_OVLAN_ETYPE(0x8100));
567 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
568 V_IVLAN_ETYPE(M_IVLAN_ETYPE),
569 V_IVLAN_ETYPE(0x8100));
571 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
572 F_OVLAN_EN0 | F_OVLAN_EN1 |
573 F_OVLAN_EN2 | F_IVLAN_EN,
574 F_OVLAN_EN0 | F_OVLAN_EN1 |
575 F_OVLAN_EN2 | F_IVLAN_EN);
578 if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN))
579 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
580 V_RM_OVLAN(1), V_RM_OVLAN(0));
583 static void configure_pcie_ext_tag(struct adapter *adapter)
586 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
592 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
593 v |= PCI_EXP_DEVCTL_EXT_TAG;
594 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
595 if (is_t6(adapter->params.chip)) {
596 t4_set_reg_field(adapter, A_PCIE_CFG2,
597 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
599 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
600 V_T6_MINTAG(M_T6_MINTAG),
603 t4_set_reg_field(adapter, A_PCIE_CFG2,
604 V_TOTMAXTAG(M_TOTMAXTAG),
606 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
614 * Tweak configuration based on system architecture, etc. Most of these have
615 * defaults assigned to them by Firmware Configuration Files (if we're using
616 * them) but need to be explicitly set if we're using hard-coded
617 * initialization. So these are essentially common tweaks/settings for
618 * Configuration Files and hard-coded initialization ...
620 static int adap_init0_tweaks(struct adapter *adapter)
625 * Fix up various Host-Dependent Parameters like Page Size, Cache
626 * Line Size, etc. The firmware default is for a 4KB Page Size and
627 * 64B Cache Line Size ...
629 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
633 * Keep the chip default offset to deliver Ingress packets into our
634 * DMA buffers to zero
637 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
638 V_PKTSHIFT(rx_dma_offset));
640 t4_set_reg_field(adapter, A_SGE_FLM_CFG,
641 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
642 V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
644 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
645 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
647 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
648 V_IDMAARBROUNDROBIN(1U));
651 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
652 * adds the pseudo header itself.
654 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
655 F_CSUM_HAS_PSEUDO_HDR, 0);
661 * Attempt to initialize the adapter via a Firmware Configuration File.
663 static int adap_init0_config(struct adapter *adapter, int reset)
665 struct fw_caps_config_cmd caps_cmd;
666 unsigned long mtype = 0, maddr = 0;
667 u32 finiver, finicsum, cfcsum;
669 int config_issued = 0;
671 char config_name[20];
674 * Reset device if necessary.
677 ret = t4_fw_reset(adapter, adapter->mbox,
678 F_PIORSTMODE | F_PIORST);
680 dev_warn(adapter, "Firmware reset failed, error %d\n",
686 cfg_addr = t4_flash_cfg_addr(adapter);
689 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
694 strcpy(config_name, "On Flash");
695 mtype = FW_MEMTYPE_CF_FLASH;
699 * Issue a Capability Configuration command to the firmware to get it
700 * to parse the Configuration File. We don't use t4_fw_config_file()
701 * because we want the ability to modify various features after we've
702 * processed the configuration file ...
704 memset(&caps_cmd, 0, sizeof(caps_cmd));
705 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
706 F_FW_CMD_REQUEST | F_FW_CMD_READ);
707 caps_cmd.cfvalid_to_len16 =
708 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
709 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
710 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
712 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
715 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
716 * Configuration File in FLASH), our last gasp effort is to use the
717 * Firmware Configuration File which is embedded in the firmware. A
718 * very few early versions of the firmware didn't have one embedded
719 * but we can ignore those.
721 if (ret == -ENOENT) {
722 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
725 memset(&caps_cmd, 0, sizeof(caps_cmd));
726 caps_cmd.op_to_write =
727 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
728 F_FW_CMD_REQUEST | F_FW_CMD_READ);
729 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
730 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
731 sizeof(caps_cmd), &caps_cmd);
732 strcpy(config_name, "Firmware Default");
739 finiver = be32_to_cpu(caps_cmd.finiver);
740 finicsum = be32_to_cpu(caps_cmd.finicsum);
741 cfcsum = be32_to_cpu(caps_cmd.cfcsum);
742 if (finicsum != cfcsum)
743 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
747 * If we're a pure NIC driver then disable all offloading facilities.
748 * This will allow the firmware to optimize aspects of the hardware
749 * configuration which will result in improved performance.
751 caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
752 FW_CAPS_CONFIG_NIC_ETHOFLD));
753 caps_cmd.toecaps = 0;
754 caps_cmd.iscsicaps = 0;
755 caps_cmd.rdmacaps = 0;
756 caps_cmd.fcoecaps = 0;
759 * And now tell the firmware to use the configuration we just loaded.
761 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
762 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
763 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
764 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
767 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
773 * Tweak configuration based on system architecture, etc.
775 ret = adap_init0_tweaks(adapter);
777 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
782 * And finally tell the firmware to initialize itself using the
783 * parameters from the Configuration File.
785 ret = t4_fw_initialize(adapter, adapter->mbox);
787 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
793 * Return successfully and note that we're operating with parameters
794 * not supplied by the driver, rather than from hard-wired
795 * initialization constants buried in the driver.
798 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
799 config_name, finiver, cfcsum);
804 * Something bad happened. Return the error ... (If the "error"
805 * is that there's no Configuration File on the adapter we don't
806 * want to issue a warning since this is fairly common.)
809 if (config_issued && ret != -ENOENT)
810 dev_warn(adapter, "\"%s\" configuration file error %d\n",
813 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
817 static int adap_init0(struct adapter *adap)
819 struct fw_caps_config_cmd caps_cmd;
822 enum dev_state state;
823 u32 params[7], val[7];
825 int mbox = adap->mbox;
828 * Contact FW, advertising Master capability.
830 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
832 dev_err(adap, "%s: could not connect to FW, error %d\n",
837 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
841 adap->flags |= MASTER_PF;
843 if (state == DEV_STATE_INIT) {
845 * Force halt and reset FW because a previous instance may have
846 * exited abnormally without properly shutting down
848 ret = t4_fw_halt(adap, adap->mbox, reset);
850 dev_err(adap, "Failed to halt. Exit.\n");
854 ret = t4_fw_restart(adap, adap->mbox, reset);
856 dev_err(adap, "Failed to restart. Exit.\n");
859 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
862 t4_get_version_info(adap);
864 ret = t4_get_core_clock(adap, &adap->params.vpd);
866 dev_err(adap, "%s: could not get core clock, error %d\n",
872 * If the firmware is initialized already (and we're not forcing a
873 * master initialization), note that we're living with existing
874 * adapter parameters. Otherwise, it's time to try initializing the
877 if (state == DEV_STATE_INIT) {
878 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
879 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
881 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
883 ret = adap_init0_config(adap, reset);
884 if (ret == -ENOENT) {
886 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
891 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
895 /* Find out what ports are available to us. */
896 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
897 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
898 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
900 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
905 adap->params.nports = hweight32(port_vec);
906 adap->params.portvec = port_vec;
908 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
909 adap->params.nports);
912 * Give the SGE code a chance to pull in anything that it needs ...
913 * Note that this must be called after we retrieve our VPD parameters
914 * in order to know how to convert core ticks to seconds, etc.
916 ret = t4_sge_init(adap);
918 dev_err(adap, "t4_sge_init failed with error %d\n",
924 * Grab some of our basic fundamental operating parameters.
926 #define FW_PARAM_DEV(param) \
927 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
928 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
930 #define FW_PARAM_PFVF(param) \
931 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
932 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
933 V_FW_PARAMS_PARAM_Y(0) | \
934 V_FW_PARAMS_PARAM_Z(0))
936 params[0] = FW_PARAM_PFVF(FILTER_START);
937 params[1] = FW_PARAM_PFVF(FILTER_END);
938 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
941 adap->tids.ftid_base = val[0];
942 adap->tids.nftids = val[1] - val[0] + 1;
945 * Get device capabilities so we can determine what resources we need
948 memset(&caps_cmd, 0, sizeof(caps_cmd));
949 caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
950 F_FW_CMD_REQUEST | F_FW_CMD_READ);
951 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
952 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
957 /* query tid-related parameters */
958 params[0] = FW_PARAM_DEV(NTID);
959 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
963 adap->tids.ntids = val[0];
965 /* If we're running on newer firmware, let it know that we're
966 * prepared to deal with encapsulated CPL messages. Older
967 * firmware won't understand this and we'll just get
968 * unencapsulated messages ...
970 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
972 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
975 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
976 * capability. Earlier versions of the firmware didn't have the
977 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
978 * permission to use ULPTX MEMWRITE DSGL.
980 if (is_t4(adap->params.chip)) {
981 adap->params.ulptx_memwrite_dsgl = false;
983 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
984 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
986 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
990 * The MTU/MSS Table is initialized by now, so load their values. If
991 * we're initializing the adapter, then we'll make any modifications
992 * we want to the MTU/MSS Table and also initialize the congestion
995 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
996 if (state != DEV_STATE_INIT) {
1000 * The default MTU Table contains values 1492 and 1500.
1001 * However, for TCP, it's better to have two values which are
1002 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
1003 * This allows us to have a TCP Data Payload which is a
1004 * multiple of 8 regardless of what combination of TCP Options
1005 * are in use (always a multiple of 4 bytes) which is
1006 * important for performance reasons. For instance, if no
1007 * options are in use, then we have a 20-byte IP header and a
1008 * 20-byte TCP header. In this case, a 1500-byte MSS would
1009 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
1010 * which is not a multiple of 8. So using an MSS of 1488 in
1011 * this case results in a TCP Data Payload of 1448 bytes which
1012 * is a multiple of 8. On the other hand, if 12-byte TCP Time
1013 * Stamps have been negotiated, then an MTU of 1500 bytes
1014 * results in a TCP Data Payload of 1448 bytes which, as
1015 * above, is a multiple of 8 bytes ...
1017 for (i = 0; i < NMTUS; i++)
1018 if (adap->params.mtus[i] == 1492) {
1019 adap->params.mtus[i] = 1488;
1023 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
1024 adap->params.b_wnd);
1026 t4_init_sge_params(adap);
1027 t4_init_tp_params(adap);
1028 configure_pcie_ext_tag(adap);
1029 configure_vlan_types(adap);
1031 adap->params.drv_memwin = MEMWIN_NIC;
1032 adap->flags |= FW_OK;
1033 dev_debug(adap, "%s: returning zero..\n", __func__);
1037 * Something bad happened. If a command timed out or failed with EIO
1038 * FW does not operate within its spec or something catastrophic
1039 * happened to HW/FW, stop issuing commands.
1042 if (ret != -ETIMEDOUT && ret != -EIO)
1043 t4_fw_bye(adap, adap->mbox);
1048 * t4_os_portmod_changed - handle port module changes
1049 * @adap: the adapter associated with the module change
1050 * @port_id: the port index whose module status has changed
1052 * This is the OS-dependent handler for port module changes. It is
1053 * invoked when a port module is removed or inserted for any OS-specific
1056 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1058 static const char * const mod_str[] = {
1059 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1062 const struct port_info *pi = adap2pinfo(adap, port_id);
1064 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
1065 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1066 else if (pi->mod_type < ARRAY_SIZE(mod_str))
1067 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1068 mod_str[pi->mod_type]);
1069 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1070 dev_info(adap, "Port%d: unsupported port module inserted\n",
1072 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1073 dev_info(adap, "Port%d: unknown port module inserted\n",
1075 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
1076 dev_info(adap, "Port%d: transceiver module error\n",
1079 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1080 pi->port_id, pi->mod_type);
1083 inline bool force_linkup(struct adapter *adap)
1085 struct rte_pci_device *pdev = adap->pdev;
1088 return false; /* force_linkup not required for pf driver*/
1089 if (!cxgbe_get_devargs(pdev->device.devargs,
1090 CXGBE_DEVARG_FORCE_LINK_UP))
1096 * link_start - enable a port
1097 * @dev: the port to enable
1099 * Performs the MAC and PHY actions needed to enable a port.
1101 int link_start(struct port_info *pi)
1103 struct adapter *adapter = pi->adapter;
1107 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1108 (ETHER_HDR_LEN + ETHER_CRC_LEN);
1111 * We do not set address filters and promiscuity here, the stack does
1112 * that step explicitly.
1114 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
1117 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1119 (u8 *)&pi->eth_dev->data->mac_addrs[0],
1122 pi->xact_addr_filt = ret;
1126 if (ret == 0 && is_pf4(adapter))
1127 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
1131 * Enabling a Virtual Interface can result in an interrupt
1132 * during the processing of the VI Enable command and, in some
1133 * paths, result in an attempt to issue another command in the
1134 * interrupt context. Thus, we disable interrupts during the
1135 * course of the VI Enable command ...
1137 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1141 if (ret == 0 && force_linkup(adapter))
1142 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
1147 * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1149 * @rss_hf: Hash configuration to apply
1151 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1153 struct adapter *adapter = pi->adapter;
1154 const struct sge_eth_rxq *rxq;
1159 /* Should never be called before setting up sge eth rx queues */
1160 if (!(adapter->flags & FULL_INIT_DONE)) {
1161 dev_err(adap, "%s No RXQs available on port %d\n",
1162 __func__, pi->port_id);
1166 /* Don't allow unsupported hash functions */
1167 if (rss_hf & ~CXGBE_RSS_HF_ALL)
1170 if (rss_hf & ETH_RSS_IPV4)
1171 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1173 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1174 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1176 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1177 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1178 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1180 if (rss_hf & ETH_RSS_IPV6)
1181 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1183 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1184 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1186 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1187 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1188 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1190 rxq = &adapter->sge.ethrxq[pi->first_qset];
1191 rss = rxq[0].rspq.abs_id;
1193 /* If Tunnel All Lookup isn't specified in the global RSS
1194 * Configuration, then we need to specify a default Ingress
1195 * Queue for any ingress packets which aren't hashed. We'll
1196 * use our first ingress queue ...
1198 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1204 * cxgbe_write_rss - write the RSS table for a given port
1206 * @queues: array of queue indices for RSS
1208 * Sets up the portion of the HW RSS table for the port's VI to distribute
1209 * packets to the Rx queues in @queues.
1211 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1215 struct adapter *adapter = pi->adapter;
1216 const struct sge_eth_rxq *rxq;
1218 /* Should never be called before setting up sge eth rx queues */
1219 BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1221 rxq = &adapter->sge.ethrxq[pi->first_qset];
1222 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1226 /* map the queue indices to queue ids */
1227 for (i = 0; i < pi->rss_size; i++, queues++)
1228 rss[i] = rxq[*queues].rspq.abs_id;
1230 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1231 pi->rss_size, rss, pi->rss_size);
1237 * setup_rss - configure RSS
1238 * @adapter: the adapter
1240 * Sets up RSS to distribute packets to multiple receive queues. We
1241 * configure the RSS CPU lookup table to distribute to the number of HW
1242 * receive queues, and the response queue lookup table to narrow that
1243 * down to the response queues actually configured for each port.
1244 * We always configure the RSS mapping for all ports since the mapping
1245 * table has plenty of entries.
1247 int setup_rss(struct port_info *pi)
1250 struct adapter *adapter = pi->adapter;
1252 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1253 __func__, pi->rss_size, pi->n_rx_qsets);
1255 if (!(pi->flags & PORT_RSS_DONE)) {
1256 if (adapter->flags & FULL_INIT_DONE) {
1257 /* Fill default values with equal distribution */
1258 for (j = 0; j < pi->rss_size; j++)
1259 pi->rss[j] = j % pi->n_rx_qsets;
1261 err = cxgbe_write_rss(pi, pi->rss);
1265 err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1268 pi->flags |= PORT_RSS_DONE;
1275 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1277 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1279 /* 0-increment GTS to start the timer and enable interrupts */
1280 t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1281 T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1282 V_SEINTARM(q->intr_params) |
1283 V_INGRESSQID(q->cntxt_id));
1286 void cxgbe_enable_rx_queues(struct port_info *pi)
1288 struct adapter *adap = pi->adapter;
1289 struct sge *s = &adap->sge;
1292 for (i = 0; i < pi->n_rx_qsets; i++)
1293 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1297 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1298 * @port_type: Firmware Port Type
1299 * @fw_caps: Firmware Port Capabilities
1300 * @speed_caps: Device Info Speed Capabilities
1302 * Translate a Firmware Port Capabilities specification to Device Info
1303 * Speed Capabilities.
1305 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1306 unsigned int fw_caps,
1309 #define SET_SPEED(__speed_name) \
1311 *speed_caps |= ETH_LINK_ ## __speed_name; \
1314 #define FW_CAPS_TO_SPEED(__fw_name) \
1316 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1317 SET_SPEED(__fw_name); \
1320 switch (port_type) {
1321 case FW_PORT_TYPE_BT_SGMII:
1322 case FW_PORT_TYPE_BT_XFI:
1323 case FW_PORT_TYPE_BT_XAUI:
1324 FW_CAPS_TO_SPEED(SPEED_100M);
1325 FW_CAPS_TO_SPEED(SPEED_1G);
1326 FW_CAPS_TO_SPEED(SPEED_10G);
1329 case FW_PORT_TYPE_KX4:
1330 case FW_PORT_TYPE_KX:
1331 case FW_PORT_TYPE_FIBER_XFI:
1332 case FW_PORT_TYPE_FIBER_XAUI:
1333 case FW_PORT_TYPE_SFP:
1334 case FW_PORT_TYPE_QSFP_10G:
1335 case FW_PORT_TYPE_QSA:
1336 FW_CAPS_TO_SPEED(SPEED_1G);
1337 FW_CAPS_TO_SPEED(SPEED_10G);
1340 case FW_PORT_TYPE_KR:
1341 SET_SPEED(SPEED_10G);
1344 case FW_PORT_TYPE_BP_AP:
1345 case FW_PORT_TYPE_BP4_AP:
1346 SET_SPEED(SPEED_1G);
1347 SET_SPEED(SPEED_10G);
1350 case FW_PORT_TYPE_BP40_BA:
1351 case FW_PORT_TYPE_QSFP:
1352 SET_SPEED(SPEED_40G);
1355 case FW_PORT_TYPE_CR_QSFP:
1356 case FW_PORT_TYPE_SFP28:
1357 case FW_PORT_TYPE_KR_SFP28:
1358 FW_CAPS_TO_SPEED(SPEED_1G);
1359 FW_CAPS_TO_SPEED(SPEED_10G);
1360 FW_CAPS_TO_SPEED(SPEED_25G);
1363 case FW_PORT_TYPE_CR2_QSFP:
1364 SET_SPEED(SPEED_50G);
1367 case FW_PORT_TYPE_KR4_100G:
1368 case FW_PORT_TYPE_CR4_QSFP:
1369 FW_CAPS_TO_SPEED(SPEED_25G);
1370 FW_CAPS_TO_SPEED(SPEED_40G);
1371 FW_CAPS_TO_SPEED(SPEED_50G);
1372 FW_CAPS_TO_SPEED(SPEED_100G);
1379 #undef FW_CAPS_TO_SPEED
1384 * cxgbe_get_speed_caps - Fetch supported speed capabilities
1385 * @pi: Underlying port's info
1386 * @speed_caps: Device Info speed capabilities
1388 * Fetch supported speed capabilities of the underlying port.
1390 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1394 fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1397 if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1398 *speed_caps |= ETH_LINK_SPEED_FIXED;
1402 * cxgb_up - enable the adapter
1403 * @adap: adapter being enabled
1405 * Called when the first port is enabled, this function performs the
1406 * actions necessary to make an adapter operational, such as completing
1407 * the initialization of HW modules, and enabling interrupts.
1409 int cxgbe_up(struct adapter *adap)
1411 enable_rx(adap, &adap->sge.fw_evtq);
1412 t4_sge_tx_monitor_start(adap);
1414 t4_intr_enable(adap);
1415 adap->flags |= FULL_INIT_DONE;
1417 /* TODO: deadman watchdog ?? */
1424 int cxgbe_down(struct port_info *pi)
1426 struct adapter *adapter = pi->adapter;
1429 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1431 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1435 t4_reset_link_config(adapter, pi->pidx);
1440 * Release resources when all the ports have been stopped.
1442 void cxgbe_close(struct adapter *adapter)
1444 struct port_info *pi;
1447 if (adapter->flags & FULL_INIT_DONE) {
1448 if (is_pf4(adapter))
1449 t4_intr_disable(adapter);
1450 tid_free(&adapter->tids);
1451 t4_sge_tx_monitor_stop(adapter);
1452 t4_free_sge_resources(adapter);
1453 for_each_port(adapter, i) {
1454 pi = adap2pinfo(adapter, i);
1456 t4_free_vi(adapter, adapter->mbox,
1457 adapter->pf, 0, pi->viid);
1458 rte_free(pi->eth_dev->data->mac_addrs);
1459 /* Skip first port since it'll be freed by DPDK stack */
1461 rte_free(pi->eth_dev->data->dev_private);
1462 rte_eth_dev_release_port(pi->eth_dev);
1465 adapter->flags &= ~FULL_INIT_DONE;
1468 if (is_pf4(adapter) && (adapter->flags & FW_OK))
1469 t4_fw_bye(adapter, adapter->mbox);
1472 int cxgbe_probe(struct adapter *adapter)
1474 struct port_info *pi;
1480 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1481 chip = t4_get_chip_type(adapter,
1482 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1486 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1487 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1489 adapter->mbox = func;
1492 t4_os_lock_init(&adapter->mbox_lock);
1493 TAILQ_INIT(&adapter->mbox_list);
1495 err = t4_prep_adapter(adapter);
1499 setup_memwin(adapter);
1500 err = adap_init0(adapter);
1502 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1507 if (!is_t4(adapter->params.chip)) {
1509 * The userspace doorbell BAR is split evenly into doorbell
1510 * regions, each associated with an egress queue. If this
1511 * per-queue region is large enough (at least UDBS_SEG_SIZE)
1512 * then it can be used to submit a tx work request with an
1513 * implied doorbell. Enable write combining on the BAR if
1514 * there is room for such work requests.
1516 int s_qpp, qpp, num_seg;
1518 s_qpp = (S_QUEUESPERPAGEPF0 +
1519 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1521 qpp = 1 << ((t4_read_reg(adapter,
1522 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1523 & M_QUEUESPERPAGEPF0);
1524 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1526 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1528 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1529 if (!adapter->bar2) {
1530 dev_err(adapter, "cannot map device bar2 region\n");
1534 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1538 for_each_port(adapter, i) {
1539 const unsigned int numa_node = rte_socket_id();
1540 char name[RTE_ETH_NAME_MAX_LEN];
1541 struct rte_eth_dev *eth_dev;
1543 snprintf(name, sizeof(name), "%s_%d",
1544 adapter->pdev->device.name, i);
1547 /* First port is already allocated by DPDK */
1548 eth_dev = adapter->eth_dev;
1553 * now do all data allocation - for eth_dev structure,
1554 * and internal (private) data for the remaining ports
1557 /* reserve an ethdev entry */
1558 eth_dev = rte_eth_dev_allocate(name);
1562 eth_dev->data->dev_private =
1563 rte_zmalloc_socket(name, sizeof(struct port_info),
1564 RTE_CACHE_LINE_SIZE, numa_node);
1565 if (!eth_dev->data->dev_private)
1569 pi = (struct port_info *)eth_dev->data->dev_private;
1570 adapter->port[i] = pi;
1571 pi->eth_dev = eth_dev;
1572 pi->adapter = adapter;
1573 pi->xact_addr_filt = -1;
1577 pi->eth_dev->device = &adapter->pdev->device;
1578 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1579 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1580 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1582 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1584 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1586 if (!pi->eth_dev->data->mac_addrs) {
1587 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1594 /* First port will be notified by upper layer */
1595 rte_eth_dev_probing_finish(eth_dev);
1599 if (adapter->flags & FW_OK) {
1600 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1602 dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1608 cfg_queues(adapter->eth_dev);
1610 print_adapter_info(adapter);
1611 print_port_info(adapter);
1613 if (tid_init(&adapter->tids) < 0) {
1614 /* Disable filtering support */
1615 dev_warn(adapter, "could not allocate TID table, "
1616 "filter support disabled. Continuing\n");
1619 err = init_rss(adapter);
1626 for_each_port(adapter, i) {
1627 pi = adap2pinfo(adapter, i);
1629 t4_free_vi(adapter, adapter->mbox, adapter->pf,
1631 /* Skip first port since it'll be de-allocated by DPDK */
1635 if (pi->eth_dev->data->dev_private)
1636 rte_free(pi->eth_dev->data->dev_private);
1637 rte_eth_dev_release_port(pi->eth_dev);
1641 if (adapter->flags & FW_OK)
1642 t4_fw_bye(adapter, adapter->mbox);