4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
46 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_tailq.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
70 * Response queue handler for the FW event queue.
72 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
73 __rte_unused const struct pkt_gl *gl)
75 u8 opcode = ((const struct rss_header *)rsp)->opcode;
77 rsp++; /* skip RSS header */
80 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
82 if (unlikely(opcode == CPL_FW4_MSG &&
83 ((const struct cpl_fw4_msg *)rsp)->type ==
86 opcode = ((const struct rss_header *)rsp)->opcode;
88 if (opcode != CPL_SGE_EGR_UPDATE) {
89 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
95 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
97 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
98 const struct cpl_fw6_msg *msg = (const void *)rsp;
100 t4_handle_fw_rpl(q->adapter, msg->data);
102 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
109 int setup_sge_fwevtq(struct adapter *adapter)
111 struct sge *s = &adapter->sge;
115 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
116 msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
121 static int closest_timer(const struct sge *s, int time)
123 unsigned int i, match = 0;
124 int delta, min_delta = INT_MAX;
126 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
127 delta = time - s->timer_val[i];
130 if (delta < min_delta) {
138 static int closest_thres(const struct sge *s, int thres)
140 unsigned int i, match = 0;
141 int delta, min_delta = INT_MAX;
143 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
144 delta = thres - s->counter_val[i];
147 if (delta < min_delta) {
156 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
158 * @us: the hold-off time in us, or 0 to disable timer
159 * @cnt: the hold-off packet count, or 0 to disable counter
161 * Sets an Rx queue's interrupt hold-off time and packet count. At least
162 * one of the two needs to be enabled for the queue to generate interrupts.
164 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
167 struct adapter *adap = q->adapter;
168 unsigned int timer_val;
174 new_idx = closest_thres(&adap->sge, cnt);
175 if (q->desc && q->pktcnt_idx != new_idx) {
176 /* the queue has already been created, update it */
177 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
179 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
180 V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
181 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
186 q->pktcnt_idx = new_idx;
189 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
190 closest_timer(&adap->sge, us);
193 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
195 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
196 V_QINTR_CNT_EN(cnt > 0);
200 static inline bool is_x_1g_port(const struct link_config *lc)
202 return (lc->supported & FW_PORT_CAP_SPEED_1G) != 0;
205 static inline bool is_x_10g_port(const struct link_config *lc)
207 unsigned int speeds, high_speeds;
209 speeds = V_FW_PORT_CAP_SPEED(G_FW_PORT_CAP_SPEED(lc->supported));
210 high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G);
212 return high_speeds != 0;
215 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
216 unsigned int us, unsigned int cnt,
217 unsigned int size, unsigned int iqe_size)
220 cxgb4_set_rspq_intr_params(q, us, cnt);
221 q->iqe_len = iqe_size;
225 int cfg_queue_count(struct rte_eth_dev *eth_dev)
227 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
228 struct adapter *adap = pi->adapter;
229 struct sge *s = &adap->sge;
230 unsigned int max_queues = s->max_ethqsets / adap->params.nports;
232 if ((eth_dev->data->nb_rx_queues < 1) ||
233 (eth_dev->data->nb_tx_queues < 1))
236 if ((eth_dev->data->nb_rx_queues > max_queues) ||
237 (eth_dev->data->nb_tx_queues > max_queues))
240 if (eth_dev->data->nb_rx_queues > pi->rss_size)
243 /* We must configure RSS, since config has changed*/
244 pi->flags &= ~PORT_RSS_DONE;
246 pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
247 pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
252 void cfg_queues(struct rte_eth_dev *eth_dev)
254 struct rte_config *config = rte_eal_get_configuration();
255 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
256 struct adapter *adap = pi->adapter;
257 struct sge *s = &adap->sge;
258 unsigned int i, nb_ports = 0, qidx = 0;
259 unsigned int q_per_port = 0;
261 if (!(adap->flags & CFG_QUEUES)) {
262 for_each_port(adap, i) {
263 struct port_info *tpi = adap2pinfo(adap, i);
265 nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
266 is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
270 * We default up to # of cores queues per 1G/10G port.
273 q_per_port = (MAX_ETH_QSETS -
274 (adap->params.nports - nb_ports)) /
277 if (q_per_port > config->lcore_count)
278 q_per_port = config->lcore_count;
280 for_each_port(adap, i) {
281 struct port_info *pi = adap2pinfo(adap, i);
283 pi->first_qset = qidx;
285 /* Initially n_rx_qsets == n_tx_qsets */
286 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
287 is_x_1g_port(&pi->link_cfg)) ?
289 pi->n_tx_qsets = pi->n_rx_qsets;
291 if (pi->n_rx_qsets > pi->rss_size)
292 pi->n_rx_qsets = pi->rss_size;
294 qidx += pi->n_rx_qsets;
297 s->max_ethqsets = qidx;
299 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
300 struct sge_eth_rxq *r = &s->ethrxq[i];
302 init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
304 r->fl.size = (r->usembufs ? 1024 : 72);
307 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
308 s->ethtxq[i].q.size = 1024;
310 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
311 adap->flags |= CFG_QUEUES;
315 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
317 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
321 void cxgbe_stats_reset(struct port_info *pi)
323 t4_clr_port_stats(pi->adapter, pi->tx_chan);
326 static void setup_memwin(struct adapter *adap)
330 /* For T5, only relative offset inside the PCIe BAR is passed */
331 mem_win0_base = MEMWIN0_BASE;
334 * Set up memory window for accessing adapter memory ranges. (Read
335 * back MA register to ensure that changes propagate before we attempt
336 * to use the new values.)
339 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
341 mem_win0_base | V_BIR(0) |
342 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
344 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
348 static int init_rss(struct adapter *adap)
353 err = t4_init_rss_mode(adap, adap->mbox);
357 for_each_port(adap, i) {
358 struct port_info *pi = adap2pinfo(adap, i);
360 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
368 * Dump basic information about the adapter.
370 static void print_adapter_info(struct adapter *adap)
373 * Hardware/Firmware/etc. Version/Revision IDs.
375 t4_dump_version_info(adap);
378 static void print_port_info(struct adapter *adap)
382 struct rte_pci_addr *loc = &adap->pdev->addr;
384 for_each_port(adap, i) {
385 const struct port_info *pi = &adap->port[i];
388 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
389 bufp += sprintf(bufp, "100M/");
390 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
391 bufp += sprintf(bufp, "1G/");
392 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
393 bufp += sprintf(bufp, "10G/");
394 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
395 bufp += sprintf(bufp, "25G/");
396 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
397 bufp += sprintf(bufp, "40G/");
398 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
399 bufp += sprintf(bufp, "100G/");
402 sprintf(bufp, "BASE-%s",
403 t4_get_port_type_description(
404 (enum fw_port_type)pi->port_type));
407 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
408 loc->domain, loc->bus, loc->devid, loc->function,
409 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
410 (adap->flags & USING_MSIX) ? " MSI-X" :
411 (adap->flags & USING_MSI) ? " MSI" : "");
415 static void configure_pcie_ext_tag(struct adapter *adapter)
418 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
424 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
425 v |= PCI_EXP_DEVCTL_EXT_TAG;
426 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
427 if (is_t6(adapter->params.chip)) {
428 t4_set_reg_field(adapter, A_PCIE_CFG2,
429 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
431 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
432 V_T6_MINTAG(M_T6_MINTAG),
435 t4_set_reg_field(adapter, A_PCIE_CFG2,
436 V_TOTMAXTAG(M_TOTMAXTAG),
438 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
446 * Tweak configuration based on system architecture, etc. Most of these have
447 * defaults assigned to them by Firmware Configuration Files (if we're using
448 * them) but need to be explicitly set if we're using hard-coded
449 * initialization. So these are essentially common tweaks/settings for
450 * Configuration Files and hard-coded initialization ...
452 static int adap_init0_tweaks(struct adapter *adapter)
457 * Fix up various Host-Dependent Parameters like Page Size, Cache
458 * Line Size, etc. The firmware default is for a 4KB Page Size and
459 * 64B Cache Line Size ...
461 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
465 * Keep the chip default offset to deliver Ingress packets into our
466 * DMA buffers to zero
469 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
470 V_PKTSHIFT(rx_dma_offset));
472 t4_set_reg_field(adapter, A_SGE_FLM_CFG,
473 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
474 V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
476 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
477 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
479 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
480 V_IDMAARBROUNDROBIN(1U));
483 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
484 * adds the pseudo header itself.
486 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
487 F_CSUM_HAS_PSEUDO_HDR, 0);
493 * Attempt to initialize the adapter via a Firmware Configuration File.
495 static int adap_init0_config(struct adapter *adapter, int reset)
497 struct fw_caps_config_cmd caps_cmd;
498 unsigned long mtype = 0, maddr = 0;
499 u32 finiver, finicsum, cfcsum;
501 int config_issued = 0;
503 char config_name[20];
506 * Reset device if necessary.
509 ret = t4_fw_reset(adapter, adapter->mbox,
510 F_PIORSTMODE | F_PIORST);
512 dev_warn(adapter, "Firmware reset failed, error %d\n",
518 cfg_addr = t4_flash_cfg_addr(adapter);
521 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
526 strcpy(config_name, "On Flash");
527 mtype = FW_MEMTYPE_CF_FLASH;
531 * Issue a Capability Configuration command to the firmware to get it
532 * to parse the Configuration File. We don't use t4_fw_config_file()
533 * because we want the ability to modify various features after we've
534 * processed the configuration file ...
536 memset(&caps_cmd, 0, sizeof(caps_cmd));
537 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
538 F_FW_CMD_REQUEST | F_FW_CMD_READ);
539 caps_cmd.cfvalid_to_len16 =
540 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
541 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
542 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
544 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
547 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
548 * Configuration File in FLASH), our last gasp effort is to use the
549 * Firmware Configuration File which is embedded in the firmware. A
550 * very few early versions of the firmware didn't have one embedded
551 * but we can ignore those.
553 if (ret == -ENOENT) {
554 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
557 memset(&caps_cmd, 0, sizeof(caps_cmd));
558 caps_cmd.op_to_write =
559 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
560 F_FW_CMD_REQUEST | F_FW_CMD_READ);
561 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
562 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
563 sizeof(caps_cmd), &caps_cmd);
564 strcpy(config_name, "Firmware Default");
571 finiver = be32_to_cpu(caps_cmd.finiver);
572 finicsum = be32_to_cpu(caps_cmd.finicsum);
573 cfcsum = be32_to_cpu(caps_cmd.cfcsum);
574 if (finicsum != cfcsum)
575 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
579 * If we're a pure NIC driver then disable all offloading facilities.
580 * This will allow the firmware to optimize aspects of the hardware
581 * configuration which will result in improved performance.
583 caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
584 FW_CAPS_CONFIG_NIC_ETHOFLD));
585 caps_cmd.toecaps = 0;
586 caps_cmd.iscsicaps = 0;
587 caps_cmd.rdmacaps = 0;
588 caps_cmd.fcoecaps = 0;
591 * And now tell the firmware to use the configuration we just loaded.
593 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
594 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
595 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
596 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
599 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
605 * Tweak configuration based on system architecture, etc.
607 ret = adap_init0_tweaks(adapter);
609 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
614 * And finally tell the firmware to initialize itself using the
615 * parameters from the Configuration File.
617 ret = t4_fw_initialize(adapter, adapter->mbox);
619 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
625 * Return successfully and note that we're operating with parameters
626 * not supplied by the driver, rather than from hard-wired
627 * initialization constants buried in the driver.
630 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
631 config_name, finiver, cfcsum);
636 * Something bad happened. Return the error ... (If the "error"
637 * is that there's no Configuration File on the adapter we don't
638 * want to issue a warning since this is fairly common.)
641 if (config_issued && ret != -ENOENT)
642 dev_warn(adapter, "\"%s\" configuration file error %d\n",
645 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
649 static int adap_init0(struct adapter *adap)
653 enum dev_state state;
654 u32 params[7], val[7];
656 int mbox = adap->mbox;
659 * Contact FW, advertising Master capability.
661 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
663 dev_err(adap, "%s: could not connect to FW, error %d\n",
668 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
672 adap->flags |= MASTER_PF;
674 if (state == DEV_STATE_INIT) {
676 * Force halt and reset FW because a previous instance may have
677 * exited abnormally without properly shutting down
679 ret = t4_fw_halt(adap, adap->mbox, reset);
681 dev_err(adap, "Failed to halt. Exit.\n");
685 ret = t4_fw_restart(adap, adap->mbox, reset);
687 dev_err(adap, "Failed to restart. Exit.\n");
690 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
693 t4_get_version_info(adap);
695 ret = t4_get_core_clock(adap, &adap->params.vpd);
697 dev_err(adap, "%s: could not get core clock, error %d\n",
703 * If the firmware is initialized already (and we're not forcing a
704 * master initialization), note that we're living with existing
705 * adapter parameters. Otherwise, it's time to try initializing the
708 if (state == DEV_STATE_INIT) {
709 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
710 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
712 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
714 ret = adap_init0_config(adap, reset);
715 if (ret == -ENOENT) {
717 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
722 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
726 /* Find out what ports are available to us. */
727 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
728 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
729 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
731 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
736 adap->params.nports = hweight32(port_vec);
737 adap->params.portvec = port_vec;
739 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
740 adap->params.nports);
743 * Give the SGE code a chance to pull in anything that it needs ...
744 * Note that this must be called after we retrieve our VPD parameters
745 * in order to know how to convert core ticks to seconds, etc.
747 ret = t4_sge_init(adap);
749 dev_err(adap, "t4_sge_init failed with error %d\n",
755 * Grab some of our basic fundamental operating parameters.
757 #define FW_PARAM_DEV(param) \
758 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
759 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
761 #define FW_PARAM_PFVF(param) \
762 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
763 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
764 V_FW_PARAMS_PARAM_Y(0) | \
765 V_FW_PARAMS_PARAM_Z(0))
767 /* If we're running on newer firmware, let it know that we're
768 * prepared to deal with encapsulated CPL messages. Older
769 * firmware won't understand this and we'll just get
770 * unencapsulated messages ...
772 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
774 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
777 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
778 * capability. Earlier versions of the firmware didn't have the
779 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
780 * permission to use ULPTX MEMWRITE DSGL.
782 if (is_t4(adap->params.chip)) {
783 adap->params.ulptx_memwrite_dsgl = false;
785 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
786 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
788 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
792 * The MTU/MSS Table is initialized by now, so load their values. If
793 * we're initializing the adapter, then we'll make any modifications
794 * we want to the MTU/MSS Table and also initialize the congestion
797 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
798 if (state != DEV_STATE_INIT) {
802 * The default MTU Table contains values 1492 and 1500.
803 * However, for TCP, it's better to have two values which are
804 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
805 * This allows us to have a TCP Data Payload which is a
806 * multiple of 8 regardless of what combination of TCP Options
807 * are in use (always a multiple of 4 bytes) which is
808 * important for performance reasons. For instance, if no
809 * options are in use, then we have a 20-byte IP header and a
810 * 20-byte TCP header. In this case, a 1500-byte MSS would
811 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
812 * which is not a multiple of 8. So using an MSS of 1488 in
813 * this case results in a TCP Data Payload of 1448 bytes which
814 * is a multiple of 8. On the other hand, if 12-byte TCP Time
815 * Stamps have been negotiated, then an MTU of 1500 bytes
816 * results in a TCP Data Payload of 1448 bytes which, as
817 * above, is a multiple of 8 bytes ...
819 for (i = 0; i < NMTUS; i++)
820 if (adap->params.mtus[i] == 1492) {
821 adap->params.mtus[i] = 1488;
825 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
828 t4_init_sge_params(adap);
829 t4_init_tp_params(adap);
830 configure_pcie_ext_tag(adap);
832 adap->params.drv_memwin = MEMWIN_NIC;
833 adap->flags |= FW_OK;
834 dev_debug(adap, "%s: returning zero..\n", __func__);
838 * Something bad happened. If a command timed out or failed with EIO
839 * FW does not operate within its spec or something catastrophic
840 * happened to HW/FW, stop issuing commands.
843 if (ret != -ETIMEDOUT && ret != -EIO)
844 t4_fw_bye(adap, adap->mbox);
849 * t4_os_portmod_changed - handle port module changes
850 * @adap: the adapter associated with the module change
851 * @port_id: the port index whose module status has changed
853 * This is the OS-dependent handler for port module changes. It is
854 * invoked when a port module is removed or inserted for any OS-specific
857 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
859 static const char * const mod_str[] = {
860 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
863 const struct port_info *pi = &adap->port[port_id];
865 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
866 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
867 else if (pi->mod_type < ARRAY_SIZE(mod_str))
868 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
869 mod_str[pi->mod_type]);
870 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
871 dev_info(adap, "Port%d: unsupported port module inserted\n",
873 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
874 dev_info(adap, "Port%d: unknown port module inserted\n",
876 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
877 dev_info(adap, "Port%d: transceiver module error\n",
880 dev_info(adap, "Port%d: unknown module type %d inserted\n",
881 pi->port_id, pi->mod_type);
885 * link_start - enable a port
886 * @dev: the port to enable
888 * Performs the MAC and PHY actions needed to enable a port.
890 int link_start(struct port_info *pi)
892 struct adapter *adapter = pi->adapter;
896 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
897 (ETHER_HDR_LEN + ETHER_CRC_LEN);
900 * We do not set address filters and promiscuity here, the stack does
901 * that step explicitly.
903 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
906 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
908 (u8 *)&pi->eth_dev->data->mac_addrs[0],
911 pi->xact_addr_filt = ret;
916 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
920 * Enabling a Virtual Interface can result in an interrupt
921 * during the processing of the VI Enable command and, in some
922 * paths, result in an attempt to issue another command in the
923 * interrupt context. Thus, we disable interrupts during the
924 * course of the VI Enable command ...
926 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
933 * cxgb4_write_rss - write the RSS table for a given port
935 * @queues: array of queue indices for RSS
937 * Sets up the portion of the HW RSS table for the port's VI to distribute
938 * packets to the Rx queues in @queues.
940 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
944 struct adapter *adapter = pi->adapter;
945 const struct sge_eth_rxq *rxq;
947 /* Should never be called before setting up sge eth rx queues */
948 BUG_ON(!(adapter->flags & FULL_INIT_DONE));
950 rxq = &adapter->sge.ethrxq[pi->first_qset];
951 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
955 /* map the queue indices to queue ids */
956 for (i = 0; i < pi->rss_size; i++, queues++)
957 rss[i] = rxq[*queues].rspq.abs_id;
959 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
960 pi->rss_size, rss, pi->rss_size);
962 * If Tunnel All Lookup isn't specified in the global RSS
963 * Configuration, then we need to specify a default Ingress
964 * Queue for any ingress packets which aren't hashed. We'll
965 * use our first ingress queue ...
968 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
969 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
970 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
971 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
972 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN |
973 F_FW_RSS_VI_CONFIG_CMD_UDPEN,
980 * setup_rss - configure RSS
981 * @adapter: the adapter
983 * Sets up RSS to distribute packets to multiple receive queues. We
984 * configure the RSS CPU lookup table to distribute to the number of HW
985 * receive queues, and the response queue lookup table to narrow that
986 * down to the response queues actually configured for each port.
987 * We always configure the RSS mapping for all ports since the mapping
988 * table has plenty of entries.
990 int setup_rss(struct port_info *pi)
993 struct adapter *adapter = pi->adapter;
995 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n",
996 __func__, pi->rss_size, pi->n_rx_qsets);
998 if (!(pi->flags & PORT_RSS_DONE)) {
999 if (adapter->flags & FULL_INIT_DONE) {
1000 /* Fill default values with equal distribution */
1001 for (j = 0; j < pi->rss_size; j++)
1002 pi->rss[j] = j % pi->n_rx_qsets;
1004 err = cxgb4_write_rss(pi, pi->rss);
1007 pi->flags |= PORT_RSS_DONE;
1014 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1016 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1018 /* 0-increment GTS to start the timer and enable interrupts */
1019 t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS),
1020 V_SEINTARM(q->intr_params) |
1021 V_INGRESSQID(q->cntxt_id));
1024 void cxgbe_enable_rx_queues(struct port_info *pi)
1026 struct adapter *adap = pi->adapter;
1027 struct sge *s = &adap->sge;
1030 for (i = 0; i < pi->n_rx_qsets; i++)
1031 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1035 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1036 * @port_type: Firmware Port Type
1037 * @fw_caps: Firmware Port Capabilities
1038 * @speed_caps: Device Info Speed Capabilities
1040 * Translate a Firmware Port Capabilities specification to Device Info
1041 * Speed Capabilities.
1043 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1044 unsigned int fw_caps,
1047 #define SET_SPEED(__speed_name) \
1049 *speed_caps |= ETH_LINK_ ## __speed_name; \
1052 #define FW_CAPS_TO_SPEED(__fw_name) \
1054 if (fw_caps & FW_PORT_CAP_ ## __fw_name) \
1055 SET_SPEED(__fw_name); \
1058 switch (port_type) {
1059 case FW_PORT_TYPE_BT_SGMII:
1060 case FW_PORT_TYPE_BT_XFI:
1061 case FW_PORT_TYPE_BT_XAUI:
1062 FW_CAPS_TO_SPEED(SPEED_100M);
1063 FW_CAPS_TO_SPEED(SPEED_1G);
1064 FW_CAPS_TO_SPEED(SPEED_10G);
1067 case FW_PORT_TYPE_KX4:
1068 case FW_PORT_TYPE_KX:
1069 case FW_PORT_TYPE_FIBER_XFI:
1070 case FW_PORT_TYPE_FIBER_XAUI:
1071 case FW_PORT_TYPE_SFP:
1072 case FW_PORT_TYPE_QSFP_10G:
1073 case FW_PORT_TYPE_QSA:
1074 FW_CAPS_TO_SPEED(SPEED_1G);
1075 FW_CAPS_TO_SPEED(SPEED_10G);
1078 case FW_PORT_TYPE_KR:
1079 SET_SPEED(SPEED_10G);
1082 case FW_PORT_TYPE_BP_AP:
1083 case FW_PORT_TYPE_BP4_AP:
1084 SET_SPEED(SPEED_1G);
1085 SET_SPEED(SPEED_10G);
1088 case FW_PORT_TYPE_BP40_BA:
1089 case FW_PORT_TYPE_QSFP:
1090 SET_SPEED(SPEED_40G);
1093 case FW_PORT_TYPE_CR_QSFP:
1094 case FW_PORT_TYPE_SFP28:
1095 case FW_PORT_TYPE_KR_SFP28:
1096 FW_CAPS_TO_SPEED(SPEED_1G);
1097 FW_CAPS_TO_SPEED(SPEED_10G);
1098 FW_CAPS_TO_SPEED(SPEED_25G);
1101 case FW_PORT_TYPE_CR2_QSFP:
1102 SET_SPEED(SPEED_50G);
1105 case FW_PORT_TYPE_KR4_100G:
1106 case FW_PORT_TYPE_CR4_QSFP:
1107 FW_CAPS_TO_SPEED(SPEED_25G);
1108 FW_CAPS_TO_SPEED(SPEED_40G);
1109 FW_CAPS_TO_SPEED(SPEED_100G);
1116 #undef FW_CAPS_TO_SPEED
1121 * cxgbe_get_speed_caps - Fetch supported speed capabilities
1122 * @pi: Underlying port's info
1123 * @speed_caps: Device Info speed capabilities
1125 * Fetch supported speed capabilities of the underlying port.
1127 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1131 fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.supported,
1134 if (!(pi->link_cfg.supported & FW_PORT_CAP_ANEG))
1135 *speed_caps |= ETH_LINK_SPEED_FIXED;
1139 * cxgb_up - enable the adapter
1140 * @adap: adapter being enabled
1142 * Called when the first port is enabled, this function performs the
1143 * actions necessary to make an adapter operational, such as completing
1144 * the initialization of HW modules, and enabling interrupts.
1146 int cxgbe_up(struct adapter *adap)
1148 enable_rx(adap, &adap->sge.fw_evtq);
1149 t4_sge_tx_monitor_start(adap);
1150 t4_intr_enable(adap);
1151 adap->flags |= FULL_INIT_DONE;
1153 /* TODO: deadman watchdog ?? */
1160 int cxgbe_down(struct port_info *pi)
1162 struct adapter *adapter = pi->adapter;
1165 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1167 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1171 t4_reset_link_config(adapter, pi->port_id);
1176 * Release resources when all the ports have been stopped.
1178 void cxgbe_close(struct adapter *adapter)
1180 struct port_info *pi;
1183 if (adapter->flags & FULL_INIT_DONE) {
1184 t4_intr_disable(adapter);
1185 t4_sge_tx_monitor_stop(adapter);
1186 t4_free_sge_resources(adapter);
1187 for_each_port(adapter, i) {
1188 pi = adap2pinfo(adapter, i);
1190 t4_free_vi(adapter, adapter->mbox,
1191 adapter->pf, 0, pi->viid);
1192 rte_free(pi->eth_dev->data->mac_addrs);
1194 adapter->flags &= ~FULL_INIT_DONE;
1197 if (adapter->flags & FW_OK)
1198 t4_fw_bye(adapter, adapter->mbox);
1201 int cxgbe_probe(struct adapter *adapter)
1203 struct port_info *pi;
1209 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1210 chip = t4_get_chip_type(adapter,
1211 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1215 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1216 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1218 adapter->mbox = func;
1221 t4_os_lock_init(&adapter->mbox_lock);
1222 TAILQ_INIT(&adapter->mbox_list);
1224 err = t4_prep_adapter(adapter);
1228 setup_memwin(adapter);
1229 err = adap_init0(adapter);
1231 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1236 if (!is_t4(adapter->params.chip)) {
1238 * The userspace doorbell BAR is split evenly into doorbell
1239 * regions, each associated with an egress queue. If this
1240 * per-queue region is large enough (at least UDBS_SEG_SIZE)
1241 * then it can be used to submit a tx work request with an
1242 * implied doorbell. Enable write combining on the BAR if
1243 * there is room for such work requests.
1245 int s_qpp, qpp, num_seg;
1247 s_qpp = (S_QUEUESPERPAGEPF0 +
1248 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1250 qpp = 1 << ((t4_read_reg(adapter,
1251 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1252 & M_QUEUESPERPAGEPF0);
1253 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1255 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1257 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1258 if (!adapter->bar2) {
1259 dev_err(adapter, "cannot map device bar2 region\n");
1263 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1267 for_each_port(adapter, i) {
1268 char name[RTE_ETH_NAME_MAX_LEN];
1269 struct rte_eth_dev_data *data = NULL;
1270 const unsigned int numa_node = rte_socket_id();
1272 pi = &adapter->port[i];
1273 pi->adapter = adapter;
1274 pi->xact_addr_filt = -1;
1277 snprintf(name, sizeof(name), "cxgbe%d",
1278 adapter->eth_dev->data->port_id + i);
1281 /* First port is already allocated by DPDK */
1282 pi->eth_dev = adapter->eth_dev;
1287 * now do all data allocation - for eth_dev structure,
1288 * and internal (private) data for the remaining ports
1291 /* reserve an ethdev entry */
1292 pi->eth_dev = rte_eth_dev_allocate(name);
1296 data = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node);
1300 data->port_id = adapter->eth_dev->data->port_id + i;
1302 pi->eth_dev->data = data;
1305 pi->eth_dev->device = &adapter->pdev->device;
1306 pi->eth_dev->data->dev_private = pi;
1307 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1308 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1309 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1311 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1313 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1315 if (!pi->eth_dev->data->mac_addrs) {
1316 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1323 if (adapter->flags & FW_OK) {
1324 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1326 dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1332 cfg_queues(adapter->eth_dev);
1334 print_adapter_info(adapter);
1335 print_port_info(adapter);
1337 err = init_rss(adapter);
1344 for_each_port(adapter, i) {
1345 pi = adap2pinfo(adapter, i);
1347 t4_free_vi(adapter, adapter->mbox, adapter->pf,
1349 /* Skip first port since it'll be de-allocated by DPDK */
1352 if (pi->eth_dev->data)
1353 rte_free(pi->eth_dev->data);
1356 if (adapter->flags & FW_OK)
1357 t4_fw_bye(adapter, adapter->mbox);