drivers/net/cxgbe/cxgbe_main.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2014-2017 Chelsio Communications.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Chelsio Communications nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43
  44 #include <rte_byteorder.h>
  45 #include <rte_common.h>
  46 #include <rte_cycles.h>
  47 #include <rte_interrupts.h>
  48 #include <rte_log.h>
  49 #include <rte_debug.h>
  50 #include <rte_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_memzone.h>
  55 #include <rte_tailq.h>
  56 #include <rte_eal.h>
  57 #include <rte_alarm.h>
  58 #include <rte_ether.h>
  59 #include <rte_ethdev.h>
  60 #include <rte_ethdev_pci.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_dev.h>
  64
  65 #include "common.h"
  66 #include "t4_regs.h"
  67 #include "t4_msg.h"
  68 #include "cxgbe.h"
  69
  70 /*
  71  * Response queue handler for the FW event queue.
  72  */
  73 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
  74                           __rte_unused const struct pkt_gl *gl)
  75 {
  76         u8 opcode = ((const struct rss_header *)rsp)->opcode;
  77
  78         rsp++;                                          /* skip RSS header */
  79
  80         /*
  81          * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
  82          */
  83         if (unlikely(opcode == CPL_FW4_MSG &&
  84                      ((const struct cpl_fw4_msg *)rsp)->type ==
  85                       FW_TYPE_RSSCPL)) {
  86                 rsp++;
  87                 opcode = ((const struct rss_header *)rsp)->opcode;
  88                 rsp++;
  89                 if (opcode != CPL_SGE_EGR_UPDATE) {
  90                         dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
  91                                 opcode);
  92                         goto out;
  93                 }
  94         }
  95
  96         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
  97                 /* do nothing */
  98         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
  99                 const struct cpl_fw6_msg *msg = (const void *)rsp;
 100
 101                 t4_handle_fw_rpl(q->adapter, msg->data);
 102         } else {
 103                 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
 104                         opcode);
 105         }
 106 out:
 107         return 0;
 108 }
 109
 110 int setup_sge_fwevtq(struct adapter *adapter)
 111 {
 112         struct sge *s = &adapter->sge;
 113         int err = 0;
 114         int msi_idx = 0;
 115
 116         err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
 117                                msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
 118                                rte_socket_id());
 119         return err;
 120 }
 121
 122 static int closest_timer(const struct sge *s, int time)
 123 {
 124         unsigned int i, match = 0;
 125         int delta, min_delta = INT_MAX;
 126
 127         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 128                 delta = time - s->timer_val[i];
 129                 if (delta < 0)
 130                         delta = -delta;
 131                 if (delta < min_delta) {
 132                         min_delta = delta;
 133                         match = i;
 134                 }
 135         }
 136         return match;
 137 }
 138
 139 static int closest_thres(const struct sge *s, int thres)
 140 {
 141         unsigned int i, match = 0;
 142         int delta, min_delta = INT_MAX;
 143
 144         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 145                 delta = thres - s->counter_val[i];
 146                 if (delta < 0)
 147                         delta = -delta;
 148                 if (delta < min_delta) {
 149                         min_delta = delta;
 150                         match = i;
 151                 }
 152         }
 153         return match;
 154 }
 155
 156 /**
 157  * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 158  * @q: the Rx queue
 159  * @us: the hold-off time in us, or 0 to disable timer
 160  * @cnt: the hold-off packet count, or 0 to disable counter
 161  *
 162  * Sets an Rx queue's interrupt hold-off time and packet count.  At least
 163  * one of the two needs to be enabled for the queue to generate interrupts.
 164  */
 165 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
 166                                unsigned int cnt)
 167 {
 168         struct adapter *adap = q->adapter;
 169         unsigned int timer_val;
 170
 171         if (cnt) {
 172                 int err;
 173                 u32 v, new_idx;
 174
 175                 new_idx = closest_thres(&adap->sge, cnt);
 176                 if (q->desc && q->pktcnt_idx != new_idx) {
 177                         /* the queue has already been created, update it */
 178                         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 179                             V_FW_PARAMS_PARAM_X(
 180                             FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 181                             V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
 182                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 183                                             &v, &new_idx);
 184                         if (err)
 185                                 return err;
 186                 }
 187                 q->pktcnt_idx = new_idx;
 188         }
 189
 190         timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
 191                                 closest_timer(&adap->sge, us);
 192
 193         if ((us | cnt) == 0)
 194                 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
 195         else
 196                 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
 197                                  V_QINTR_CNT_EN(cnt > 0);
 198         return 0;
 199 }
 200
 201 static inline bool is_x_1g_port(const struct link_config *lc)
 202 {
 203         return (lc->supported & FW_PORT_CAP_SPEED_1G) != 0;
 204 }
 205
 206 static inline bool is_x_10g_port(const struct link_config *lc)
 207 {
 208         unsigned int speeds, high_speeds;
 209
 210         speeds = V_FW_PORT_CAP_SPEED(G_FW_PORT_CAP_SPEED(lc->supported));
 211         high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G);
 212
 213         return high_speeds != 0;
 214 }
 215
 216 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
 217                       unsigned int us, unsigned int cnt,
 218                       unsigned int size, unsigned int iqe_size)
 219 {
 220         q->adapter = adap;
 221         cxgb4_set_rspq_intr_params(q, us, cnt);
 222         q->iqe_len = iqe_size;
 223         q->size = size;
 224 }
 225
 226 int cfg_queue_count(struct rte_eth_dev *eth_dev)
 227 {
 228         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 229         struct adapter *adap = pi->adapter;
 230         struct sge *s = &adap->sge;
 231         unsigned int max_queues = s->max_ethqsets / adap->params.nports;
 232
 233         if ((eth_dev->data->nb_rx_queues < 1) ||
 234             (eth_dev->data->nb_tx_queues < 1))
 235                 return -EINVAL;
 236
 237         if ((eth_dev->data->nb_rx_queues > max_queues) ||
 238             (eth_dev->data->nb_tx_queues > max_queues))
 239                 return -EINVAL;
 240
 241         if (eth_dev->data->nb_rx_queues > pi->rss_size)
 242                 return -EINVAL;
 243
 244         /* We must configure RSS, since config has changed*/
 245         pi->flags &= ~PORT_RSS_DONE;
 246
 247         pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
 248         pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
 249
 250         return 0;
 251 }
 252
 253 void cfg_queues(struct rte_eth_dev *eth_dev)
 254 {
 255         struct rte_config *config = rte_eal_get_configuration();
 256         struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
 257         struct adapter *adap = pi->adapter;
 258         struct sge *s = &adap->sge;
 259         unsigned int i, nb_ports = 0, qidx = 0;
 260         unsigned int q_per_port = 0;
 261
 262         if (!(adap->flags & CFG_QUEUES)) {
 263                 for_each_port(adap, i) {
 264                         struct port_info *tpi = adap2pinfo(adap, i);
 265
 266                         nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
 267                                      is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
 268                 }
 269
 270                 /*
 271                  * We default up to # of cores queues per 1G/10G port.
 272                  */
 273                 if (nb_ports)
 274                         q_per_port = (MAX_ETH_QSETS -
 275                                      (adap->params.nports - nb_ports)) /
 276                                      nb_ports;
 277
 278                 if (q_per_port > config->lcore_count)
 279                         q_per_port = config->lcore_count;
 280
 281                 for_each_port(adap, i) {
 282                         struct port_info *pi = adap2pinfo(adap, i);
 283
 284                         pi->first_qset = qidx;
 285
 286                         /* Initially n_rx_qsets == n_tx_qsets */
 287                         pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
 288                                           is_x_1g_port(&pi->link_cfg)) ?
 289                                           q_per_port : 1;
 290                         pi->n_tx_qsets = pi->n_rx_qsets;
 291
 292                         if (pi->n_rx_qsets > pi->rss_size)
 293                                 pi->n_rx_qsets = pi->rss_size;
 294
 295                         qidx += pi->n_rx_qsets;
 296                 }
 297
 298                 s->max_ethqsets = qidx;
 299
 300                 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
 301                         struct sge_eth_rxq *r = &s->ethrxq[i];
 302
 303                         init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
 304                         r->usembufs = 1;
 305                         r->fl.size = (r->usembufs ? 1024 : 72);
 306                 }
 307
 308                 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
 309                         s->ethtxq[i].q.size = 1024;
 310
 311                 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
 312                 adap->flags |= CFG_QUEUES;
 313         }
 314 }
 315
 316 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
 317 {
 318         t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
 319                                  &pi->stats_base);
 320 }
 321
 322 void cxgbe_stats_reset(struct port_info *pi)
 323 {
 324         t4_clr_port_stats(pi->adapter, pi->tx_chan);
 325 }
 326
 327 static void setup_memwin(struct adapter *adap)
 328 {
 329         u32 mem_win0_base;
 330
 331         /* For T5, only relative offset inside the PCIe BAR is passed */
 332         mem_win0_base = MEMWIN0_BASE;
 333
 334         /*
 335          * Set up memory window for accessing adapter memory ranges.  (Read
 336          * back MA register to ensure that changes propagate before we attempt
 337          * to use the new values.)
 338          */
 339         t4_write_reg(adap,
 340                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 341                                          MEMWIN_NIC),
 342                      mem_win0_base | V_BIR(0) |
 343                      V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
 344         t4_read_reg(adap,
 345                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 346                                         MEMWIN_NIC));
 347 }
 348
 349 static int init_rss(struct adapter *adap)
 350 {
 351         unsigned int i;
 352         int err;
 353
 354         err = t4_init_rss_mode(adap, adap->mbox);
 355         if (err)
 356                 return err;
 357
 358         for_each_port(adap, i) {
 359                 struct port_info *pi = adap2pinfo(adap, i);
 360
 361                 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 362                 if (!pi->rss)
 363                         return -ENOMEM;
 364         }
 365         return 0;
 366 }
 367
 368 /**
 369  * Dump basic information about the adapter.
 370  */
 371 static void print_adapter_info(struct adapter *adap)
 372 {
 373         /**
 374          * Hardware/Firmware/etc. Version/Revision IDs.
 375          */
 376         t4_dump_version_info(adap);
 377 }
 378
 379 static void print_port_info(struct adapter *adap)
 380 {
 381         int i;
 382         char buf[80];
 383         struct rte_pci_addr *loc = &adap->pdev->addr;
 384
 385         for_each_port(adap, i) {
 386                 const struct port_info *pi = &adap->port[i];
 387                 char *bufp = buf;
 388
 389                 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
 390                         bufp += sprintf(bufp, "100M/");
 391                 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
 392                         bufp += sprintf(bufp, "1G/");
 393                 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
 394                         bufp += sprintf(bufp, "10G/");
 395                 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
 396                         bufp += sprintf(bufp, "25G/");
 397                 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
 398                         bufp += sprintf(bufp, "40G/");
 399                 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
 400                         bufp += sprintf(bufp, "100G/");
 401                 if (bufp != buf)
 402                         --bufp;
 403                 sprintf(bufp, "BASE-%s",
 404                         t4_get_port_type_description(
 405                                         (enum fw_port_type)pi->port_type));
 406
 407                 dev_info(adap,
 408                          " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
 409                          loc->domain, loc->bus, loc->devid, loc->function,
 410                          CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
 411                          (adap->flags & USING_MSIX) ? " MSI-X" :
 412                          (adap->flags & USING_MSI) ? " MSI" : "");
 413         }
 414 }
 415
 416 static void configure_pcie_ext_tag(struct adapter *adapter)
 417 {
 418         u16 v;
 419         int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
 420
 421         if (!pos)
 422                 return;
 423
 424         if (pos > 0) {
 425                 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
 426                 v |= PCI_EXP_DEVCTL_EXT_TAG;
 427                 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
 428                 if (is_t6(adapter->params.chip)) {
 429                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 430                                          V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
 431                                          V_T6_TOTMAXTAG(7));
 432                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 433                                          V_T6_MINTAG(M_T6_MINTAG),
 434                                          V_T6_MINTAG(8));
 435                 } else {
 436                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 437                                          V_TOTMAXTAG(M_TOTMAXTAG),
 438                                          V_TOTMAXTAG(3));
 439                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 440                                          V_MINTAG(M_MINTAG),
 441                                          V_MINTAG(8));
 442                 }
 443         }
 444 }
 445
 446 /*
 447  * Tweak configuration based on system architecture, etc.  Most of these have
 448  * defaults assigned to them by Firmware Configuration Files (if we're using
 449  * them) but need to be explicitly set if we're using hard-coded
 450  * initialization. So these are essentially common tweaks/settings for
 451  * Configuration Files and hard-coded initialization ...
 452  */
 453 static int adap_init0_tweaks(struct adapter *adapter)
 454 {
 455         u8 rx_dma_offset;
 456
 457         /*
 458          * Fix up various Host-Dependent Parameters like Page Size, Cache
 459          * Line Size, etc.  The firmware default is for a 4KB Page Size and
 460          * 64B Cache Line Size ...
 461          */
 462         t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
 463                                     T5_LAST_REV);
 464
 465         /*
 466          * Keep the chip default offset to deliver Ingress packets into our
 467          * DMA buffers to zero
 468          */
 469         rx_dma_offset = 0;
 470         t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
 471                          V_PKTSHIFT(rx_dma_offset));
 472
 473         t4_set_reg_field(adapter, A_SGE_FLM_CFG,
 474                          V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
 475                          V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
 476
 477         t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
 478                          V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
 479
 480         t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
 481                          V_IDMAARBROUNDROBIN(1U));
 482
 483         /*
 484          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
 485          * adds the pseudo header itself.
 486          */
 487         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 488                                F_CSUM_HAS_PSEUDO_HDR, 0);
 489
 490         return 0;
 491 }
 492
 493 /*
 494  * Attempt to initialize the adapter via a Firmware Configuration File.
 495  */
 496 static int adap_init0_config(struct adapter *adapter, int reset)
 497 {
 498         struct fw_caps_config_cmd caps_cmd;
 499         unsigned long mtype = 0, maddr = 0;
 500         u32 finiver, finicsum, cfcsum;
 501         int ret;
 502         int config_issued = 0;
 503         int cfg_addr;
 504         char config_name[20];
 505
 506         /*
 507          * Reset device if necessary.
 508          */
 509         if (reset) {
 510                 ret = t4_fw_reset(adapter, adapter->mbox,
 511                                   F_PIORSTMODE | F_PIORST);
 512                 if (ret < 0) {
 513                         dev_warn(adapter, "Firmware reset failed, error %d\n",
 514                                  -ret);
 515                         goto bye;
 516                 }
 517         }
 518
 519         cfg_addr = t4_flash_cfg_addr(adapter);
 520         if (cfg_addr < 0) {
 521                 ret = cfg_addr;
 522                 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
 523                          -ret);
 524                 goto bye;
 525         }
 526
 527         strcpy(config_name, "On Flash");
 528         mtype = FW_MEMTYPE_CF_FLASH;
 529         maddr = cfg_addr;
 530
 531         /*
 532          * Issue a Capability Configuration command to the firmware to get it
 533          * to parse the Configuration File.  We don't use t4_fw_config_file()
 534          * because we want the ability to modify various features after we've
 535          * processed the configuration file ...
 536          */
 537         memset(&caps_cmd, 0, sizeof(caps_cmd));
 538         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 539                                            F_FW_CMD_REQUEST | F_FW_CMD_READ);
 540         caps_cmd.cfvalid_to_len16 =
 541                 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
 542                             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
 543                             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
 544                             FW_LEN16(caps_cmd));
 545         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 546                          &caps_cmd);
 547         /*
 548          * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
 549          * Configuration File in FLASH), our last gasp effort is to use the
 550          * Firmware Configuration File which is embedded in the firmware.  A
 551          * very few early versions of the firmware didn't have one embedded
 552          * but we can ignore those.
 553          */
 554         if (ret == -ENOENT) {
 555                 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
 556                          __func__);
 557
 558                 memset(&caps_cmd, 0, sizeof(caps_cmd));
 559                 caps_cmd.op_to_write =
 560                         cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 561                                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
 562                 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
 563                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
 564                                  sizeof(caps_cmd), &caps_cmd);
 565                 strcpy(config_name, "Firmware Default");
 566         }
 567
 568         config_issued = 1;
 569         if (ret < 0)
 570                 goto bye;
 571
 572         finiver = be32_to_cpu(caps_cmd.finiver);
 573         finicsum = be32_to_cpu(caps_cmd.finicsum);
 574         cfcsum = be32_to_cpu(caps_cmd.cfcsum);
 575         if (finicsum != cfcsum)
 576                 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
 577                          finicsum, cfcsum);
 578
 579         /*
 580          * If we're a pure NIC driver then disable all offloading facilities.
 581          * This will allow the firmware to optimize aspects of the hardware
 582          * configuration which will result in improved performance.
 583          */
 584         caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
 585                                           FW_CAPS_CONFIG_NIC_ETHOFLD));
 586         caps_cmd.toecaps = 0;
 587         caps_cmd.iscsicaps = 0;
 588         caps_cmd.rdmacaps = 0;
 589         caps_cmd.fcoecaps = 0;
 590
 591         /*
 592          * And now tell the firmware to use the configuration we just loaded.
 593          */
 594         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 595                                            F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
 596         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 597         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 598                          NULL);
 599         if (ret < 0) {
 600                 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
 601                          -ret);
 602                 goto bye;
 603         }
 604
 605         /*
 606          * Tweak configuration based on system architecture, etc.
 607          */
 608         ret = adap_init0_tweaks(adapter);
 609         if (ret < 0) {
 610                 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
 611                 goto bye;
 612         }
 613
 614         /*
 615          * And finally tell the firmware to initialize itself using the
 616          * parameters from the Configuration File.
 617          */
 618         ret = t4_fw_initialize(adapter, adapter->mbox);
 619         if (ret < 0) {
 620                 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
 621                          -ret);
 622                 goto bye;
 623         }
 624
 625         /*
 626          * Return successfully and note that we're operating with parameters
 627          * not supplied by the driver, rather than from hard-wired
 628          * initialization constants buried in the driver.
 629          */
 630         dev_info(adapter,
 631                  "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
 632                  config_name, finiver, cfcsum);
 633
 634         return 0;
 635
 636         /*
 637          * Something bad happened.  Return the error ...  (If the "error"
 638          * is that there's no Configuration File on the adapter we don't
 639          * want to issue a warning since this is fairly common.)
 640          */
 641 bye:
 642         if (config_issued && ret != -ENOENT)
 643                 dev_warn(adapter, "\"%s\" configuration file error %d\n",
 644                          config_name, -ret);
 645
 646         dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
 647         return ret;
 648 }
 649
 650 static int adap_init0(struct adapter *adap)
 651 {
 652         int ret = 0;
 653         u32 v, port_vec;
 654         enum dev_state state;
 655         u32 params[7], val[7];
 656         int reset = 1;
 657         int mbox = adap->mbox;
 658
 659         /*
 660          * Contact FW, advertising Master capability.
 661          */
 662         ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
 663         if (ret < 0) {
 664                 dev_err(adap, "%s: could not connect to FW, error %d\n",
 665                         __func__, -ret);
 666                 goto bye;
 667         }
 668
 669         CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
 670                          adap->mbox, ret);
 671
 672         if (ret == mbox)
 673                 adap->flags |= MASTER_PF;
 674
 675         if (state == DEV_STATE_INIT) {
 676                 /*
 677                  * Force halt and reset FW because a previous instance may have
 678                  * exited abnormally without properly shutting down
 679                  */
 680                 ret = t4_fw_halt(adap, adap->mbox, reset);
 681                 if (ret < 0) {
 682                         dev_err(adap, "Failed to halt. Exit.\n");
 683                         goto bye;
 684                 }
 685
 686                 ret = t4_fw_restart(adap, adap->mbox, reset);
 687                 if (ret < 0) {
 688                         dev_err(adap, "Failed to restart. Exit.\n");
 689                         goto bye;
 690                 }
 691                 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
 692         }
 693
 694         t4_get_version_info(adap);
 695
 696         ret = t4_get_core_clock(adap, &adap->params.vpd);
 697         if (ret < 0) {
 698                 dev_err(adap, "%s: could not get core clock, error %d\n",
 699                         __func__, -ret);
 700                 goto bye;
 701         }
 702
 703         /*
 704          * If the firmware is initialized already (and we're not forcing a
 705          * master initialization), note that we're living with existing
 706          * adapter parameters.  Otherwise, it's time to try initializing the
 707          * adapter ...
 708          */
 709         if (state == DEV_STATE_INIT) {
 710                 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
 711                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
 712         } else {
 713                 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
 714
 715                 ret = adap_init0_config(adap, reset);
 716                 if (ret == -ENOENT) {
 717                         dev_err(adap,
 718                                 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
 719                         goto bye;
 720                 }
 721         }
 722         if (ret < 0) {
 723                 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
 724                 goto bye;
 725         }
 726
 727         /* Find out what ports are available to us. */
 728         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
 729             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
 730         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
 731         if (ret < 0) {
 732                 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
 733                         __func__, ret);
 734                 goto bye;
 735         }
 736
 737         adap->params.nports = hweight32(port_vec);
 738         adap->params.portvec = port_vec;
 739
 740         dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
 741                   adap->params.nports);
 742
 743         /*
 744          * Give the SGE code a chance to pull in anything that it needs ...
 745          * Note that this must be called after we retrieve our VPD parameters
 746          * in order to know how to convert core ticks to seconds, etc.
 747          */
 748         ret = t4_sge_init(adap);
 749         if (ret < 0) {
 750                 dev_err(adap, "t4_sge_init failed with error %d\n",
 751                         -ret);
 752                 goto bye;
 753         }
 754
 755         /*
 756          * Grab some of our basic fundamental operating parameters.
 757          */
 758 #define FW_PARAM_DEV(param) \
 759         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
 760          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
 761
 762 #define FW_PARAM_PFVF(param) \
 763         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
 764          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
 765          V_FW_PARAMS_PARAM_Y(0) | \
 766          V_FW_PARAMS_PARAM_Z(0))
 767
 768         /* If we're running on newer firmware, let it know that we're
 769          * prepared to deal with encapsulated CPL messages.  Older
 770          * firmware won't understand this and we'll just get
 771          * unencapsulated messages ...
 772          */
 773         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
 774         val[0] = 1;
 775         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
 776
 777         /*
 778          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
 779          * capability.  Earlier versions of the firmware didn't have the
 780          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
 781          * permission to use ULPTX MEMWRITE DSGL.
 782          */
 783         if (is_t4(adap->params.chip)) {
 784                 adap->params.ulptx_memwrite_dsgl = false;
 785         } else {
 786                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
 787                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
 788                                       1, params, val);
 789                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
 790         }
 791
 792         /*
 793          * The MTU/MSS Table is initialized by now, so load their values.  If
 794          * we're initializing the adapter, then we'll make any modifications
 795          * we want to the MTU/MSS Table and also initialize the congestion
 796          * parameters.
 797          */
 798         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
 799         if (state != DEV_STATE_INIT) {
 800                 int i;
 801
 802                 /*
 803                  * The default MTU Table contains values 1492 and 1500.
 804                  * However, for TCP, it's better to have two values which are
 805                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
 806                  * This allows us to have a TCP Data Payload which is a
 807                  * multiple of 8 regardless of what combination of TCP Options
 808                  * are in use (always a multiple of 4 bytes) which is
 809                  * important for performance reasons.  For instance, if no
 810                  * options are in use, then we have a 20-byte IP header and a
 811                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
 812                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
 813                  * which is not a multiple of 8.  So using an MSS of 1488 in
 814                  * this case results in a TCP Data Payload of 1448 bytes which
 815                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
 816                  * Stamps have been negotiated, then an MTU of 1500 bytes
 817                  * results in a TCP Data Payload of 1448 bytes which, as
 818                  * above, is a multiple of 8 bytes ...
 819                  */
 820                 for (i = 0; i < NMTUS; i++)
 821                         if (adap->params.mtus[i] == 1492) {
 822                                 adap->params.mtus[i] = 1488;
 823                                 break;
 824                         }
 825
 826                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
 827                              adap->params.b_wnd);
 828         }
 829         t4_init_sge_params(adap);
 830         t4_init_tp_params(adap);
 831         configure_pcie_ext_tag(adap);
 832
 833         adap->params.drv_memwin = MEMWIN_NIC;
 834         adap->flags |= FW_OK;
 835         dev_debug(adap, "%s: returning zero..\n", __func__);
 836         return 0;
 837
 838         /*
 839          * Something bad happened.  If a command timed out or failed with EIO
 840          * FW does not operate within its spec or something catastrophic
 841          * happened to HW/FW, stop issuing commands.
 842          */
 843 bye:
 844         if (ret != -ETIMEDOUT && ret != -EIO)
 845                 t4_fw_bye(adap, adap->mbox);
 846         return ret;
 847 }
 848
 849 /**
 850  * t4_os_portmod_changed - handle port module changes
 851  * @adap: the adapter associated with the module change
 852  * @port_id: the port index whose module status has changed
 853  *
 854  * This is the OS-dependent handler for port module changes.  It is
 855  * invoked when a port module is removed or inserted for any OS-specific
 856  * processing.
 857  */
 858 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 859 {
 860         static const char * const mod_str[] = {
 861                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 862         };
 863
 864         const struct port_info *pi = &adap->port[port_id];
 865
 866         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 867                 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
 868         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 869                 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
 870                          mod_str[pi->mod_type]);
 871         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
 872                 dev_info(adap, "Port%d: unsupported port module inserted\n",
 873                          pi->port_id);
 874         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
 875                 dev_info(adap, "Port%d: unknown port module inserted\n",
 876                          pi->port_id);
 877         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
 878                 dev_info(adap, "Port%d: transceiver module error\n",
 879                          pi->port_id);
 880         else
 881                 dev_info(adap, "Port%d: unknown module type %d inserted\n",
 882                          pi->port_id, pi->mod_type);
 883 }
 884
 885 /**
 886  * link_start - enable a port
 887  * @dev: the port to enable
 888  *
 889  * Performs the MAC and PHY actions needed to enable a port.
 890  */
 891 int link_start(struct port_info *pi)
 892 {
 893         struct adapter *adapter = pi->adapter;
 894         int ret;
 895         unsigned int mtu;
 896
 897         mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
 898               (ETHER_HDR_LEN + ETHER_CRC_LEN);
 899
 900         /*
 901          * We do not set address filters and promiscuity here, the stack does
 902          * that step explicitly.
 903          */
 904         ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
 905                             -1, 1, true);
 906         if (ret == 0) {
 907                 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
 908                                     pi->xact_addr_filt,
 909                                     (u8 *)&pi->eth_dev->data->mac_addrs[0],
 910                                     true, true);
 911                 if (ret >= 0) {
 912                         pi->xact_addr_filt = ret;
 913                         ret = 0;
 914                 }
 915         }
 916         if (ret == 0)
 917                 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
 918                                     &pi->link_cfg);
 919         if (ret == 0) {
 920                 /*
 921                  * Enabling a Virtual Interface can result in an interrupt
 922                  * during the processing of the VI Enable command and, in some
 923                  * paths, result in an attempt to issue another command in the
 924                  * interrupt context.  Thus, we disable interrupts during the
 925                  * course of the VI Enable command ...
 926                  */
 927                 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
 928                                           true, true, false);
 929         }
 930         return ret;
 931 }
 932
 933 /**
 934  * cxgb4_write_rss - write the RSS table for a given port
 935  * @pi: the port
 936  * @queues: array of queue indices for RSS
 937  *
 938  * Sets up the portion of the HW RSS table for the port's VI to distribute
 939  * packets to the Rx queues in @queues.
 940  */
 941 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
 942 {
 943         u16 *rss;
 944         int i, err;
 945         struct adapter *adapter = pi->adapter;
 946         const struct sge_eth_rxq *rxq;
 947
 948         /*  Should never be called before setting up sge eth rx queues */
 949         BUG_ON(!(adapter->flags & FULL_INIT_DONE));
 950
 951         rxq = &adapter->sge.ethrxq[pi->first_qset];
 952         rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 953         if (!rss)
 954                 return -ENOMEM;
 955
 956         /* map the queue indices to queue ids */
 957         for (i = 0; i < pi->rss_size; i++, queues++)
 958                 rss[i] = rxq[*queues].rspq.abs_id;
 959
 960         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
 961                                   pi->rss_size, rss, pi->rss_size);
 962         /*
 963          * If Tunnel All Lookup isn't specified in the global RSS
 964          * Configuration, then we need to specify a default Ingress
 965          * Queue for any ingress packets which aren't hashed.  We'll
 966          * use our first ingress queue ...
 967          */
 968         if (!err)
 969                 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
 970                                        F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
 971                                        F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
 972                                        F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
 973                                        F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN |
 974                                        F_FW_RSS_VI_CONFIG_CMD_UDPEN,
 975                                        rss[0]);
 976         rte_free(rss);
 977         return err;
 978 }
 979
 980 /**
 981  * setup_rss - configure RSS
 982  * @adapter: the adapter
 983  *
 984  * Sets up RSS to distribute packets to multiple receive queues.  We
 985  * configure the RSS CPU lookup table to distribute to the number of HW
 986  * receive queues, and the response queue lookup table to narrow that
 987  * down to the response queues actually configured for each port.
 988  * We always configure the RSS mapping for all ports since the mapping
 989  * table has plenty of entries.
 990  */
 991 int setup_rss(struct port_info *pi)
 992 {
 993         int j, err;
 994         struct adapter *adapter = pi->adapter;
 995
 996         dev_debug(adapter, "%s:  pi->rss_size = %u; pi->n_rx_qsets = %u\n",
 997                   __func__, pi->rss_size, pi->n_rx_qsets);
 998
 999         if (!(pi->flags & PORT_RSS_DONE)) {
1000                 if (adapter->flags & FULL_INIT_DONE) {
1001                         /* Fill default values with equal distribution */
1002                         for (j = 0; j < pi->rss_size; j++)
1003                                 pi->rss[j] = j % pi->n_rx_qsets;
1004
1005                         err = cxgb4_write_rss(pi, pi->rss);
1006                         if (err)
1007                                 return err;
1008                         pi->flags |= PORT_RSS_DONE;
1009                 }
1010         }
1011         return 0;
1012 }
1013
1014 /*
1015  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1016  */
1017 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1018 {
1019         /* 0-increment GTS to start the timer and enable interrupts */
1020         t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS),
1021                      V_SEINTARM(q->intr_params) |
1022                      V_INGRESSQID(q->cntxt_id));
1023 }
1024
1025 void cxgbe_enable_rx_queues(struct port_info *pi)
1026 {
1027         struct adapter *adap = pi->adapter;
1028         struct sge *s = &adap->sge;
1029         unsigned int i;
1030
1031         for (i = 0; i < pi->n_rx_qsets; i++)
1032                 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1033 }
1034
1035 /**
1036  * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1037  * @port_type: Firmware Port Type
1038  * @fw_caps: Firmware Port Capabilities
1039  * @speed_caps: Device Info Speed Capabilities
1040  *
1041  * Translate a Firmware Port Capabilities specification to Device Info
1042  * Speed Capabilities.
1043  */
1044 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1045                                   unsigned int fw_caps,
1046                                   u32 *speed_caps)
1047 {
1048 #define SET_SPEED(__speed_name) \
1049         do { \
1050                 *speed_caps |= ETH_LINK_ ## __speed_name; \
1051         } while (0)
1052
1053 #define FW_CAPS_TO_SPEED(__fw_name) \
1054         do { \
1055                 if (fw_caps & FW_PORT_CAP_ ## __fw_name) \
1056                         SET_SPEED(__fw_name); \
1057         } while (0)
1058
1059         switch (port_type) {
1060         case FW_PORT_TYPE_BT_SGMII:
1061         case FW_PORT_TYPE_BT_XFI:
1062         case FW_PORT_TYPE_BT_XAUI:
1063                 FW_CAPS_TO_SPEED(SPEED_100M);
1064                 FW_CAPS_TO_SPEED(SPEED_1G);
1065                 FW_CAPS_TO_SPEED(SPEED_10G);
1066                 break;
1067
1068         case FW_PORT_TYPE_KX4:
1069         case FW_PORT_TYPE_KX:
1070         case FW_PORT_TYPE_FIBER_XFI:
1071         case FW_PORT_TYPE_FIBER_XAUI:
1072         case FW_PORT_TYPE_SFP:
1073         case FW_PORT_TYPE_QSFP_10G:
1074         case FW_PORT_TYPE_QSA:
1075                 FW_CAPS_TO_SPEED(SPEED_1G);
1076                 FW_CAPS_TO_SPEED(SPEED_10G);
1077                 break;
1078
1079         case FW_PORT_TYPE_KR:
1080                 SET_SPEED(SPEED_10G);
1081                 break;
1082
1083         case FW_PORT_TYPE_BP_AP:
1084         case FW_PORT_TYPE_BP4_AP:
1085                 SET_SPEED(SPEED_1G);
1086                 SET_SPEED(SPEED_10G);
1087                 break;
1088
1089         case FW_PORT_TYPE_BP40_BA:
1090         case FW_PORT_TYPE_QSFP:
1091                 SET_SPEED(SPEED_40G);
1092                 break;
1093
1094         case FW_PORT_TYPE_CR_QSFP:
1095         case FW_PORT_TYPE_SFP28:
1096         case FW_PORT_TYPE_KR_SFP28:
1097                 FW_CAPS_TO_SPEED(SPEED_1G);
1098                 FW_CAPS_TO_SPEED(SPEED_10G);
1099                 FW_CAPS_TO_SPEED(SPEED_25G);
1100                 break;
1101
1102         case FW_PORT_TYPE_CR2_QSFP:
1103                 SET_SPEED(SPEED_50G);
1104                 break;
1105
1106         case FW_PORT_TYPE_KR4_100G:
1107         case FW_PORT_TYPE_CR4_QSFP:
1108                 FW_CAPS_TO_SPEED(SPEED_25G);
1109                 FW_CAPS_TO_SPEED(SPEED_40G);
1110                 FW_CAPS_TO_SPEED(SPEED_100G);
1111                 break;
1112
1113         default:
1114                 break;
1115         }
1116
1117 #undef FW_CAPS_TO_SPEED
1118 #undef SET_SPEED
1119 }
1120
1121 /**
1122  * cxgbe_get_speed_caps - Fetch supported speed capabilities
1123  * @pi: Underlying port's info
1124  * @speed_caps: Device Info speed capabilities
1125  *
1126  * Fetch supported speed capabilities of the underlying port.
1127  */
1128 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1129 {
1130         *speed_caps = 0;
1131
1132         fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.supported,
1133                               speed_caps);
1134
1135         if (!(pi->link_cfg.supported & FW_PORT_CAP_ANEG))
1136                 *speed_caps |= ETH_LINK_SPEED_FIXED;
1137 }
1138
1139 /**
1140  * cxgb_up - enable the adapter
1141  * @adap: adapter being enabled
1142  *
1143  * Called when the first port is enabled, this function performs the
1144  * actions necessary to make an adapter operational, such as completing
1145  * the initialization of HW modules, and enabling interrupts.
1146  */
1147 int cxgbe_up(struct adapter *adap)
1148 {
1149         enable_rx(adap, &adap->sge.fw_evtq);
1150         t4_sge_tx_monitor_start(adap);
1151         t4_intr_enable(adap);
1152         adap->flags |= FULL_INIT_DONE;
1153
1154         /* TODO: deadman watchdog ?? */
1155         return 0;
1156 }
1157
1158 /*
1159  * Close the port
1160  */
1161 int cxgbe_down(struct port_info *pi)
1162 {
1163         struct adapter *adapter = pi->adapter;
1164         int err = 0;
1165
1166         err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1167         if (err) {
1168                 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1169                 return err;
1170         }
1171
1172         t4_reset_link_config(adapter, pi->port_id);
1173         return 0;
1174 }
1175
1176 /*
1177  * Release resources when all the ports have been stopped.
1178  */
1179 void cxgbe_close(struct adapter *adapter)
1180 {
1181         struct port_info *pi;
1182         int i;
1183
1184         if (adapter->flags & FULL_INIT_DONE) {
1185                 t4_intr_disable(adapter);
1186                 t4_sge_tx_monitor_stop(adapter);
1187                 t4_free_sge_resources(adapter);
1188                 for_each_port(adapter, i) {
1189                         pi = adap2pinfo(adapter, i);
1190                         if (pi->viid != 0)
1191                                 t4_free_vi(adapter, adapter->mbox,
1192                                            adapter->pf, 0, pi->viid);
1193                         rte_free(pi->eth_dev->data->mac_addrs);
1194                 }
1195                 adapter->flags &= ~FULL_INIT_DONE;
1196         }
1197
1198         if (adapter->flags & FW_OK)
1199                 t4_fw_bye(adapter, adapter->mbox);
1200 }
1201
1202 int cxgbe_probe(struct adapter *adapter)
1203 {
1204         struct port_info *pi;
1205         int chip;
1206         int func, i;
1207         int err = 0;
1208         u32 whoami;
1209
1210         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1211         chip = t4_get_chip_type(adapter,
1212                         CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1213         if (chip < 0)
1214                 return chip;
1215
1216         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1217                G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1218
1219         adapter->mbox = func;
1220         adapter->pf = func;
1221
1222         t4_os_lock_init(&adapter->mbox_lock);
1223         TAILQ_INIT(&adapter->mbox_list);
1224
1225         err = t4_prep_adapter(adapter);
1226         if (err)
1227                 return err;
1228
1229         setup_memwin(adapter);
1230         err = adap_init0(adapter);
1231         if (err) {
1232                 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1233                         __func__, err);
1234                 goto out_free;
1235         }
1236
1237         if (!is_t4(adapter->params.chip)) {
1238                 /*
1239                  * The userspace doorbell BAR is split evenly into doorbell
1240                  * regions, each associated with an egress queue.  If this
1241                  * per-queue region is large enough (at least UDBS_SEG_SIZE)
1242                  * then it can be used to submit a tx work request with an
1243                  * implied doorbell.  Enable write combining on the BAR if
1244                  * there is room for such work requests.
1245                  */
1246                 int s_qpp, qpp, num_seg;
1247
1248                 s_qpp = (S_QUEUESPERPAGEPF0 +
1249                         (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1250                         adapter->pf);
1251                 qpp = 1 << ((t4_read_reg(adapter,
1252                                 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1253                                 & M_QUEUESPERPAGEPF0);
1254                 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1255                 if (qpp > num_seg)
1256                         dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1257
1258                 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1259                 if (!adapter->bar2) {
1260                         dev_err(adapter, "cannot map device bar2 region\n");
1261                         err = -ENOMEM;
1262                         goto out_free;
1263                 }
1264                 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1265                              V_STATMODE(0));
1266         }
1267
1268         for_each_port(adapter, i) {
1269                 char name[RTE_ETH_NAME_MAX_LEN];
1270                 struct rte_eth_dev_data *data = NULL;
1271                 const unsigned int numa_node = rte_socket_id();
1272
1273                 pi = &adapter->port[i];
1274                 pi->adapter = adapter;
1275                 pi->xact_addr_filt = -1;
1276                 pi->port_id = i;
1277
1278                 snprintf(name, sizeof(name), "cxgbe%d",
1279                          adapter->eth_dev->data->port_id + i);
1280
1281                 if (i == 0) {
1282                         /* First port is already allocated by DPDK */
1283                         pi->eth_dev = adapter->eth_dev;
1284                         goto allocate_mac;
1285                 }
1286
1287                 /*
1288                  * now do all data allocation - for eth_dev structure,
1289                  * and internal (private) data for the remaining ports
1290                  */
1291
1292                 /* reserve an ethdev entry */
1293                 pi->eth_dev = rte_eth_dev_allocate(name);
1294                 if (!pi->eth_dev)
1295                         goto out_free;
1296
1297                 data = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node);
1298                 if (!data)
1299                         goto out_free;
1300
1301                 data->port_id = adapter->eth_dev->data->port_id + i;
1302
1303                 pi->eth_dev->data = data;
1304
1305 allocate_mac:
1306                 pi->eth_dev->device = &adapter->pdev->device;
1307                 pi->eth_dev->data->dev_private = pi;
1308                 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1309                 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1310                 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1311
1312                 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1313
1314                 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1315                                                            ETHER_ADDR_LEN, 0);
1316                 if (!pi->eth_dev->data->mac_addrs) {
1317                         dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1318                                 __func__);
1319                         err = -1;
1320                         goto out_free;
1321                 }
1322         }
1323
1324         if (adapter->flags & FW_OK) {
1325                 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1326                 if (err) {
1327                         dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1328                                 __func__, err);
1329                         goto out_free;
1330                 }
1331         }
1332
1333         cfg_queues(adapter->eth_dev);
1334
1335         print_adapter_info(adapter);
1336         print_port_info(adapter);
1337
1338         err = init_rss(adapter);
1339         if (err)
1340                 goto out_free;
1341
1342         return 0;
1343
1344 out_free:
1345         for_each_port(adapter, i) {
1346                 pi = adap2pinfo(adapter, i);
1347                 if (pi->viid != 0)
1348                         t4_free_vi(adapter, adapter->mbox, adapter->pf,
1349                                    0, pi->viid);
1350                 /* Skip first port since it'll be de-allocated by DPDK */
1351                 if (i == 0)
1352                         continue;
1353                 if (pi->eth_dev->data)
1354                         rte_free(pi->eth_dev->data);
1355         }
1356
1357         if (adapter->flags & FW_OK)
1358                 t4_fw_bye(adapter, adapter->mbox);
1359         return -err;
1360 }