1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_atomic.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_tailq.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_random.h>
34 #include <rte_kvargs.h>
43 * Allocate a chunk of memory. The allocated memory is cleared.
45 void *t4_alloc_mem(size_t size)
47 return rte_zmalloc(NULL, size, 0);
51 * Free memory allocated through t4_alloc_mem().
53 void t4_free_mem(void *addr)
59 * Response queue handler for the FW event queue.
61 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
62 __rte_unused const struct pkt_gl *gl)
64 u8 opcode = ((const struct rss_header *)rsp)->opcode;
66 rsp++; /* skip RSS header */
69 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
71 if (unlikely(opcode == CPL_FW4_MSG &&
72 ((const struct cpl_fw4_msg *)rsp)->type ==
75 opcode = ((const struct rss_header *)rsp)->opcode;
77 if (opcode != CPL_SGE_EGR_UPDATE) {
78 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
84 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
86 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
87 const struct cpl_fw6_msg *msg = (const void *)rsp;
89 t4_handle_fw_rpl(q->adapter, msg->data);
90 } else if (opcode == CPL_ABORT_RPL_RSS) {
91 const struct cpl_abort_rpl_rss *p = (const void *)rsp;
93 hash_del_filter_rpl(q->adapter, p);
94 } else if (opcode == CPL_SET_TCB_RPL) {
95 const struct cpl_set_tcb_rpl *p = (const void *)rsp;
97 filter_rpl(q->adapter, p);
98 } else if (opcode == CPL_ACT_OPEN_RPL) {
99 const struct cpl_act_open_rpl *p = (const void *)rsp;
101 hash_filter_rpl(q->adapter, p);
103 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
111 * Setup sge control queues to pass control information.
113 int setup_sge_ctrl_txq(struct adapter *adapter)
115 struct sge *s = &adapter->sge;
118 for_each_port(adapter, i) {
119 char name[RTE_ETH_NAME_MAX_LEN];
120 struct sge_ctrl_txq *q = &s->ctrlq[i];
123 err = t4_sge_alloc_ctrl_txq(adapter, q,
128 dev_err(adapter, "Failed to alloc ctrl txq. Err: %d",
132 snprintf(name, sizeof(name), "cxgbe_ctrl_pool_%d", i);
133 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
136 RTE_MBUF_DEFAULT_BUF_SIZE,
139 dev_err(adapter, "Can't create ctrl pool for port: %d",
147 t4_free_sge_resources(adapter);
152 * cxgbe_poll_for_completion: Poll rxq for completion
154 * @us: microseconds to delay
155 * @cnt: number of times to poll
156 * @c: completion to check for 'done' status
158 * Polls the rxq for reples until completion is done or the count
161 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int us,
162 unsigned int cnt, struct t4_completion *c)
165 unsigned int work_done, budget = 4;
170 for (i = 0; i < cnt; i++) {
171 cxgbe_poll(q, NULL, budget, &work_done);
172 t4_os_lock(&c->lock);
174 t4_os_unlock(&c->lock);
177 t4_os_unlock(&c->lock);
183 int setup_sge_fwevtq(struct adapter *adapter)
185 struct sge *s = &adapter->sge;
189 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
190 msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
195 static int closest_timer(const struct sge *s, int time)
197 unsigned int i, match = 0;
198 int delta, min_delta = INT_MAX;
200 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
201 delta = time - s->timer_val[i];
204 if (delta < min_delta) {
212 static int closest_thres(const struct sge *s, int thres)
214 unsigned int i, match = 0;
215 int delta, min_delta = INT_MAX;
217 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
218 delta = thres - s->counter_val[i];
221 if (delta < min_delta) {
230 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
232 * @us: the hold-off time in us, or 0 to disable timer
233 * @cnt: the hold-off packet count, or 0 to disable counter
235 * Sets an Rx queue's interrupt hold-off time and packet count. At least
236 * one of the two needs to be enabled for the queue to generate interrupts.
238 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
241 struct adapter *adap = q->adapter;
242 unsigned int timer_val;
248 new_idx = closest_thres(&adap->sge, cnt);
249 if (q->desc && q->pktcnt_idx != new_idx) {
250 /* the queue has already been created, update it */
251 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
253 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
254 V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
255 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
260 q->pktcnt_idx = new_idx;
263 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
264 closest_timer(&adap->sge, us);
267 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
269 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
270 V_QINTR_CNT_EN(cnt > 0);
275 * Allocate an active-open TID and set it to the supplied value.
277 int cxgbe_alloc_atid(struct tid_info *t, void *data)
281 t4_os_lock(&t->atid_lock);
283 union aopen_entry *p = t->afree;
285 atid = p - t->atid_tab;
290 t4_os_unlock(&t->atid_lock);
295 * Release an active-open TID.
297 void cxgbe_free_atid(struct tid_info *t, unsigned int atid)
299 union aopen_entry *p = &t->atid_tab[atid];
301 t4_os_lock(&t->atid_lock);
305 t4_os_unlock(&t->atid_lock);
309 * Populate a TID_RELEASE WR. Caller must properly size the skb.
311 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid)
313 struct cpl_tid_release *req;
315 req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *);
316 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
320 * Release a TID and inform HW. If we are unable to allocate the release
321 * message we defer to a work queue.
323 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
324 unsigned short family)
326 struct rte_mbuf *mbuf;
327 struct adapter *adap = container_of(t, struct adapter, tids);
329 WARN_ON(tid >= t->ntids);
331 if (t->tid_tab[tid]) {
332 t->tid_tab[tid] = NULL;
333 rte_atomic32_dec(&t->conns_in_use);
334 if (t->hash_base && tid >= t->hash_base) {
335 if (family == FILTER_TYPE_IPV4)
336 rte_atomic32_dec(&t->hash_tids_in_use);
338 if (family == FILTER_TYPE_IPV4)
339 rte_atomic32_dec(&t->tids_in_use);
343 mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool);
345 mbuf->data_len = sizeof(struct cpl_tid_release);
346 mbuf->pkt_len = mbuf->data_len;
347 mk_tid_release(mbuf, tid);
348 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf);
355 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid,
356 unsigned short family)
358 t->tid_tab[tid] = data;
359 if (t->hash_base && tid >= t->hash_base) {
360 if (family == FILTER_TYPE_IPV4)
361 rte_atomic32_inc(&t->hash_tids_in_use);
363 if (family == FILTER_TYPE_IPV4)
364 rte_atomic32_inc(&t->tids_in_use);
367 rte_atomic32_inc(&t->conns_in_use);
373 static void tid_free(struct tid_info *t)
377 rte_bitmap_free(t->ftid_bmap);
379 if (t->ftid_bmap_array)
380 t4_os_free(t->ftid_bmap_array);
382 t4_os_free(t->tid_tab);
385 memset(t, 0, sizeof(struct tid_info));
389 * Allocate and initialize the TID tables. Returns 0 on success.
391 static int tid_init(struct tid_info *t)
394 unsigned int ftid_bmap_size;
395 unsigned int natids = t->natids;
396 unsigned int max_ftids = t->nftids;
398 ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
399 size = t->ntids * sizeof(*t->tid_tab) +
400 max_ftids * sizeof(*t->ftid_tab) +
401 natids * sizeof(*t->atid_tab);
403 t->tid_tab = t4_os_alloc(size);
407 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
408 t->ftid_tab = (struct filter_entry *)&t->tid_tab[t->natids];
409 t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
410 if (!t->ftid_bmap_array) {
415 t4_os_lock_init(&t->atid_lock);
416 t4_os_lock_init(&t->ftid_lock);
420 rte_atomic32_init(&t->tids_in_use);
421 rte_atomic32_set(&t->tids_in_use, 0);
422 rte_atomic32_init(&t->conns_in_use);
423 rte_atomic32_set(&t->conns_in_use, 0);
425 /* Setup the free list for atid_tab and clear the stid bitmap. */
428 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
429 t->afree = t->atid_tab;
432 t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
442 static inline bool is_x_1g_port(const struct link_config *lc)
444 return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
447 static inline bool is_x_10g_port(const struct link_config *lc)
449 unsigned int speeds, high_speeds;
451 speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
452 high_speeds = speeds &
453 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
455 return high_speeds != 0;
458 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
459 unsigned int us, unsigned int cnt,
460 unsigned int size, unsigned int iqe_size)
463 cxgb4_set_rspq_intr_params(q, us, cnt);
464 q->iqe_len = iqe_size;
468 int cfg_queue_count(struct rte_eth_dev *eth_dev)
470 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
471 struct adapter *adap = pi->adapter;
472 struct sge *s = &adap->sge;
473 unsigned int max_queues = s->max_ethqsets / adap->params.nports;
475 if ((eth_dev->data->nb_rx_queues < 1) ||
476 (eth_dev->data->nb_tx_queues < 1))
479 if ((eth_dev->data->nb_rx_queues > max_queues) ||
480 (eth_dev->data->nb_tx_queues > max_queues))
483 if (eth_dev->data->nb_rx_queues > pi->rss_size)
486 /* We must configure RSS, since config has changed*/
487 pi->flags &= ~PORT_RSS_DONE;
489 pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
490 pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
495 void cfg_queues(struct rte_eth_dev *eth_dev)
497 struct rte_config *config = rte_eal_get_configuration();
498 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
499 struct adapter *adap = pi->adapter;
500 struct sge *s = &adap->sge;
501 unsigned int i, nb_ports = 0, qidx = 0;
502 unsigned int q_per_port = 0;
504 if (!(adap->flags & CFG_QUEUES)) {
505 for_each_port(adap, i) {
506 struct port_info *tpi = adap2pinfo(adap, i);
508 nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
509 is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
513 * We default up to # of cores queues per 1G/10G port.
516 q_per_port = (MAX_ETH_QSETS -
517 (adap->params.nports - nb_ports)) /
520 if (q_per_port > config->lcore_count)
521 q_per_port = config->lcore_count;
523 for_each_port(adap, i) {
524 struct port_info *pi = adap2pinfo(adap, i);
526 pi->first_qset = qidx;
528 /* Initially n_rx_qsets == n_tx_qsets */
529 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
530 is_x_1g_port(&pi->link_cfg)) ?
532 pi->n_tx_qsets = pi->n_rx_qsets;
534 if (pi->n_rx_qsets > pi->rss_size)
535 pi->n_rx_qsets = pi->rss_size;
537 qidx += pi->n_rx_qsets;
540 s->max_ethqsets = qidx;
542 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
543 struct sge_eth_rxq *r = &s->ethrxq[i];
545 init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
547 r->fl.size = (r->usembufs ? 1024 : 72);
550 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
551 s->ethtxq[i].q.size = 1024;
553 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
554 adap->flags |= CFG_QUEUES;
558 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
560 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
564 void cxgbe_stats_reset(struct port_info *pi)
566 t4_clr_port_stats(pi->adapter, pi->tx_chan);
569 static void setup_memwin(struct adapter *adap)
573 /* For T5, only relative offset inside the PCIe BAR is passed */
574 mem_win0_base = MEMWIN0_BASE;
577 * Set up memory window for accessing adapter memory ranges. (Read
578 * back MA register to ensure that changes propagate before we attempt
579 * to use the new values.)
582 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
584 mem_win0_base | V_BIR(0) |
585 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
587 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
591 int init_rss(struct adapter *adap)
598 err = t4_init_rss_mode(adap, adap->mbox);
603 for_each_port(adap, i) {
604 struct port_info *pi = adap2pinfo(adap, i);
606 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
610 pi->rss_hf = CXGBE_RSS_HF_ALL;
616 * Dump basic information about the adapter.
618 void print_adapter_info(struct adapter *adap)
621 * Hardware/Firmware/etc. Version/Revision IDs.
623 t4_dump_version_info(adap);
626 void print_port_info(struct adapter *adap)
630 struct rte_pci_addr *loc = &adap->pdev->addr;
632 for_each_port(adap, i) {
633 const struct port_info *pi = adap2pinfo(adap, i);
636 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
637 bufp += sprintf(bufp, "100M/");
638 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
639 bufp += sprintf(bufp, "1G/");
640 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
641 bufp += sprintf(bufp, "10G/");
642 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
643 bufp += sprintf(bufp, "25G/");
644 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
645 bufp += sprintf(bufp, "40G/");
646 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
647 bufp += sprintf(bufp, "50G/");
648 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
649 bufp += sprintf(bufp, "100G/");
652 sprintf(bufp, "BASE-%s",
653 t4_get_port_type_description(
654 (enum fw_port_type)pi->port_type));
657 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
658 loc->domain, loc->bus, loc->devid, loc->function,
659 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
660 (adap->flags & USING_MSIX) ? " MSI-X" :
661 (adap->flags & USING_MSI) ? " MSI" : "");
666 check_devargs_handler(__rte_unused const char *key, const char *value,
667 __rte_unused void *opaque)
669 if (strcmp(value, "1"))
675 int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key)
677 struct rte_kvargs *kvlist;
682 kvlist = rte_kvargs_parse(devargs->args, NULL);
686 if (!rte_kvargs_count(kvlist, key)) {
687 rte_kvargs_free(kvlist);
691 if (rte_kvargs_process(kvlist, key,
692 check_devargs_handler, NULL) < 0) {
693 rte_kvargs_free(kvlist);
696 rte_kvargs_free(kvlist);
701 static void configure_vlan_types(struct adapter *adapter)
703 struct rte_pci_device *pdev = adapter->pdev;
706 for_each_port(adapter, i) {
707 /* OVLAN Type 0x88a8 */
708 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
709 V_OVLAN_MASK(M_OVLAN_MASK) |
710 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
711 V_OVLAN_MASK(M_OVLAN_MASK) |
712 V_OVLAN_ETYPE(0x88a8));
713 /* OVLAN Type 0x9100 */
714 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
715 V_OVLAN_MASK(M_OVLAN_MASK) |
716 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
717 V_OVLAN_MASK(M_OVLAN_MASK) |
718 V_OVLAN_ETYPE(0x9100));
719 /* OVLAN Type 0x8100 */
720 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
721 V_OVLAN_MASK(M_OVLAN_MASK) |
722 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
723 V_OVLAN_MASK(M_OVLAN_MASK) |
724 V_OVLAN_ETYPE(0x8100));
727 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
728 V_IVLAN_ETYPE(M_IVLAN_ETYPE),
729 V_IVLAN_ETYPE(0x8100));
731 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
732 F_OVLAN_EN0 | F_OVLAN_EN1 |
733 F_OVLAN_EN2 | F_IVLAN_EN,
734 F_OVLAN_EN0 | F_OVLAN_EN1 |
735 F_OVLAN_EN2 | F_IVLAN_EN);
738 if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN))
739 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
740 V_RM_OVLAN(1), V_RM_OVLAN(0));
743 static void configure_pcie_ext_tag(struct adapter *adapter)
746 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
752 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
753 v |= PCI_EXP_DEVCTL_EXT_TAG;
754 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
755 if (is_t6(adapter->params.chip)) {
756 t4_set_reg_field(adapter, A_PCIE_CFG2,
757 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
759 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
760 V_T6_MINTAG(M_T6_MINTAG),
763 t4_set_reg_field(adapter, A_PCIE_CFG2,
764 V_TOTMAXTAG(M_TOTMAXTAG),
766 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
774 * Tweak configuration based on system architecture, etc. Most of these have
775 * defaults assigned to them by Firmware Configuration Files (if we're using
776 * them) but need to be explicitly set if we're using hard-coded
777 * initialization. So these are essentially common tweaks/settings for
778 * Configuration Files and hard-coded initialization ...
780 static int adap_init0_tweaks(struct adapter *adapter)
785 * Fix up various Host-Dependent Parameters like Page Size, Cache
786 * Line Size, etc. The firmware default is for a 4KB Page Size and
787 * 64B Cache Line Size ...
789 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
793 * Keep the chip default offset to deliver Ingress packets into our
794 * DMA buffers to zero
797 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
798 V_PKTSHIFT(rx_dma_offset));
800 t4_set_reg_field(adapter, A_SGE_FLM_CFG,
801 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
802 V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
804 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
805 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
807 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
808 V_IDMAARBROUNDROBIN(1U));
811 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
812 * adds the pseudo header itself.
814 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
815 F_CSUM_HAS_PSEUDO_HDR, 0);
821 * Attempt to initialize the adapter via a Firmware Configuration File.
823 static int adap_init0_config(struct adapter *adapter, int reset)
825 struct fw_caps_config_cmd caps_cmd;
826 unsigned long mtype = 0, maddr = 0;
827 u32 finiver, finicsum, cfcsum;
829 int config_issued = 0;
831 char config_name[20];
834 * Reset device if necessary.
837 ret = t4_fw_reset(adapter, adapter->mbox,
838 F_PIORSTMODE | F_PIORST);
840 dev_warn(adapter, "Firmware reset failed, error %d\n",
846 cfg_addr = t4_flash_cfg_addr(adapter);
849 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
854 strcpy(config_name, "On Flash");
855 mtype = FW_MEMTYPE_CF_FLASH;
859 * Issue a Capability Configuration command to the firmware to get it
860 * to parse the Configuration File. We don't use t4_fw_config_file()
861 * because we want the ability to modify various features after we've
862 * processed the configuration file ...
864 memset(&caps_cmd, 0, sizeof(caps_cmd));
865 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
866 F_FW_CMD_REQUEST | F_FW_CMD_READ);
867 caps_cmd.cfvalid_to_len16 =
868 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
869 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
870 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
872 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
875 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
876 * Configuration File in FLASH), our last gasp effort is to use the
877 * Firmware Configuration File which is embedded in the firmware. A
878 * very few early versions of the firmware didn't have one embedded
879 * but we can ignore those.
881 if (ret == -ENOENT) {
882 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
885 memset(&caps_cmd, 0, sizeof(caps_cmd));
886 caps_cmd.op_to_write =
887 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
888 F_FW_CMD_REQUEST | F_FW_CMD_READ);
889 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
890 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
891 sizeof(caps_cmd), &caps_cmd);
892 strcpy(config_name, "Firmware Default");
899 finiver = be32_to_cpu(caps_cmd.finiver);
900 finicsum = be32_to_cpu(caps_cmd.finicsum);
901 cfcsum = be32_to_cpu(caps_cmd.cfcsum);
902 if (finicsum != cfcsum)
903 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
907 * If we're a pure NIC driver then disable all offloading facilities.
908 * This will allow the firmware to optimize aspects of the hardware
909 * configuration which will result in improved performance.
911 caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD);
912 caps_cmd.toecaps = 0;
913 caps_cmd.iscsicaps = 0;
914 caps_cmd.rdmacaps = 0;
915 caps_cmd.fcoecaps = 0;
918 * And now tell the firmware to use the configuration we just loaded.
920 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
921 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
922 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
923 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
926 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
932 * Tweak configuration based on system architecture, etc.
934 ret = adap_init0_tweaks(adapter);
936 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
941 * And finally tell the firmware to initialize itself using the
942 * parameters from the Configuration File.
944 ret = t4_fw_initialize(adapter, adapter->mbox);
946 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
952 * Return successfully and note that we're operating with parameters
953 * not supplied by the driver, rather than from hard-wired
954 * initialization constants buried in the driver.
957 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
958 config_name, finiver, cfcsum);
963 * Something bad happened. Return the error ... (If the "error"
964 * is that there's no Configuration File on the adapter we don't
965 * want to issue a warning since this is fairly common.)
968 if (config_issued && ret != -ENOENT)
969 dev_warn(adapter, "\"%s\" configuration file error %d\n",
972 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
976 static int adap_init0(struct adapter *adap)
978 struct fw_caps_config_cmd caps_cmd;
981 enum dev_state state;
982 u32 params[7], val[7];
984 int mbox = adap->mbox;
987 * Contact FW, advertising Master capability.
989 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
991 dev_err(adap, "%s: could not connect to FW, error %d\n",
996 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
1000 adap->flags |= MASTER_PF;
1002 if (state == DEV_STATE_INIT) {
1004 * Force halt and reset FW because a previous instance may have
1005 * exited abnormally without properly shutting down
1007 ret = t4_fw_halt(adap, adap->mbox, reset);
1009 dev_err(adap, "Failed to halt. Exit.\n");
1013 ret = t4_fw_restart(adap, adap->mbox, reset);
1015 dev_err(adap, "Failed to restart. Exit.\n");
1018 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
1021 t4_get_version_info(adap);
1023 ret = t4_get_core_clock(adap, &adap->params.vpd);
1025 dev_err(adap, "%s: could not get core clock, error %d\n",
1031 * If the firmware is initialized already (and we're not forcing a
1032 * master initialization), note that we're living with existing
1033 * adapter parameters. Otherwise, it's time to try initializing the
1036 if (state == DEV_STATE_INIT) {
1037 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
1038 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
1040 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
1042 ret = adap_init0_config(adap, reset);
1043 if (ret == -ENOENT) {
1045 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
1050 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
1054 /* Find out what ports are available to us. */
1055 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1056 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
1057 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
1059 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
1064 adap->params.nports = hweight32(port_vec);
1065 adap->params.portvec = port_vec;
1067 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
1068 adap->params.nports);
1071 * Give the SGE code a chance to pull in anything that it needs ...
1072 * Note that this must be called after we retrieve our VPD parameters
1073 * in order to know how to convert core ticks to seconds, etc.
1075 ret = t4_sge_init(adap);
1077 dev_err(adap, "t4_sge_init failed with error %d\n",
1083 * Grab some of our basic fundamental operating parameters.
1085 #define FW_PARAM_DEV(param) \
1086 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
1087 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
1089 #define FW_PARAM_PFVF(param) \
1090 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
1091 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
1092 V_FW_PARAMS_PARAM_Y(0) | \
1093 V_FW_PARAMS_PARAM_Z(0))
1095 params[0] = FW_PARAM_PFVF(FILTER_START);
1096 params[1] = FW_PARAM_PFVF(FILTER_END);
1097 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
1100 adap->tids.ftid_base = val[0];
1101 adap->tids.nftids = val[1] - val[0] + 1;
1103 params[0] = FW_PARAM_PFVF(CLIP_START);
1104 params[1] = FW_PARAM_PFVF(CLIP_END);
1105 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
1108 adap->clipt_start = val[0];
1109 adap->clipt_end = val[1];
1112 * Get device capabilities so we can determine what resources we need
1115 memset(&caps_cmd, 0, sizeof(caps_cmd));
1116 caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1117 F_FW_CMD_REQUEST | F_FW_CMD_READ);
1118 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
1119 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
1124 if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) &&
1125 is_t6(adap->params.chip)) {
1126 if (init_hash_filter(adap) < 0)
1130 /* query tid-related parameters */
1131 params[0] = FW_PARAM_DEV(NTID);
1132 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
1136 adap->tids.ntids = val[0];
1137 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
1139 /* If we're running on newer firmware, let it know that we're
1140 * prepared to deal with encapsulated CPL messages. Older
1141 * firmware won't understand this and we'll just get
1142 * unencapsulated messages ...
1144 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
1146 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1149 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
1150 * capability. Earlier versions of the firmware didn't have the
1151 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
1152 * permission to use ULPTX MEMWRITE DSGL.
1154 if (is_t4(adap->params.chip)) {
1155 adap->params.ulptx_memwrite_dsgl = false;
1157 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
1158 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1160 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
1164 * The MTU/MSS Table is initialized by now, so load their values. If
1165 * we're initializing the adapter, then we'll make any modifications
1166 * we want to the MTU/MSS Table and also initialize the congestion
1169 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
1170 if (state != DEV_STATE_INIT) {
1174 * The default MTU Table contains values 1492 and 1500.
1175 * However, for TCP, it's better to have two values which are
1176 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
1177 * This allows us to have a TCP Data Payload which is a
1178 * multiple of 8 regardless of what combination of TCP Options
1179 * are in use (always a multiple of 4 bytes) which is
1180 * important for performance reasons. For instance, if no
1181 * options are in use, then we have a 20-byte IP header and a
1182 * 20-byte TCP header. In this case, a 1500-byte MSS would
1183 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
1184 * which is not a multiple of 8. So using an MSS of 1488 in
1185 * this case results in a TCP Data Payload of 1448 bytes which
1186 * is a multiple of 8. On the other hand, if 12-byte TCP Time
1187 * Stamps have been negotiated, then an MTU of 1500 bytes
1188 * results in a TCP Data Payload of 1448 bytes which, as
1189 * above, is a multiple of 8 bytes ...
1191 for (i = 0; i < NMTUS; i++)
1192 if (adap->params.mtus[i] == 1492) {
1193 adap->params.mtus[i] = 1488;
1197 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
1198 adap->params.b_wnd);
1200 t4_init_sge_params(adap);
1201 t4_init_tp_params(adap);
1202 configure_pcie_ext_tag(adap);
1203 configure_vlan_types(adap);
1205 adap->params.drv_memwin = MEMWIN_NIC;
1206 adap->flags |= FW_OK;
1207 dev_debug(adap, "%s: returning zero..\n", __func__);
1211 * Something bad happened. If a command timed out or failed with EIO
1212 * FW does not operate within its spec or something catastrophic
1213 * happened to HW/FW, stop issuing commands.
1216 if (ret != -ETIMEDOUT && ret != -EIO)
1217 t4_fw_bye(adap, adap->mbox);
1222 * t4_os_portmod_changed - handle port module changes
1223 * @adap: the adapter associated with the module change
1224 * @port_id: the port index whose module status has changed
1226 * This is the OS-dependent handler for port module changes. It is
1227 * invoked when a port module is removed or inserted for any OS-specific
1230 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1232 static const char * const mod_str[] = {
1233 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1236 const struct port_info *pi = adap2pinfo(adap, port_id);
1238 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
1239 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1240 else if (pi->mod_type < ARRAY_SIZE(mod_str))
1241 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1242 mod_str[pi->mod_type]);
1243 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1244 dev_info(adap, "Port%d: unsupported port module inserted\n",
1246 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1247 dev_info(adap, "Port%d: unknown port module inserted\n",
1249 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
1250 dev_info(adap, "Port%d: transceiver module error\n",
1253 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1254 pi->port_id, pi->mod_type);
1257 inline bool force_linkup(struct adapter *adap)
1259 struct rte_pci_device *pdev = adap->pdev;
1262 return false; /* force_linkup not required for pf driver*/
1263 if (!cxgbe_get_devargs(pdev->device.devargs,
1264 CXGBE_DEVARG_FORCE_LINK_UP))
1270 * link_start - enable a port
1271 * @dev: the port to enable
1273 * Performs the MAC and PHY actions needed to enable a port.
1275 int link_start(struct port_info *pi)
1277 struct adapter *adapter = pi->adapter;
1281 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1282 (ETHER_HDR_LEN + ETHER_CRC_LEN);
1285 * We do not set address filters and promiscuity here, the stack does
1286 * that step explicitly.
1288 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
1291 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1293 (u8 *)&pi->eth_dev->data->mac_addrs[0],
1296 pi->xact_addr_filt = ret;
1300 if (ret == 0 && is_pf4(adapter))
1301 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
1305 * Enabling a Virtual Interface can result in an interrupt
1306 * during the processing of the VI Enable command and, in some
1307 * paths, result in an attempt to issue another command in the
1308 * interrupt context. Thus, we disable interrupts during the
1309 * course of the VI Enable command ...
1311 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1315 if (ret == 0 && force_linkup(adapter))
1316 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
1321 * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1323 * @rss_hf: Hash configuration to apply
1325 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1327 struct adapter *adapter = pi->adapter;
1328 const struct sge_eth_rxq *rxq;
1333 /* Should never be called before setting up sge eth rx queues */
1334 if (!(adapter->flags & FULL_INIT_DONE)) {
1335 dev_err(adap, "%s No RXQs available on port %d\n",
1336 __func__, pi->port_id);
1340 /* Don't allow unsupported hash functions */
1341 if (rss_hf & ~CXGBE_RSS_HF_ALL)
1344 if (rss_hf & ETH_RSS_IPV4)
1345 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1347 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1348 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1350 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1351 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1352 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1354 if (rss_hf & ETH_RSS_IPV6)
1355 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1357 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1358 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1360 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1361 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1362 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1364 rxq = &adapter->sge.ethrxq[pi->first_qset];
1365 rss = rxq[0].rspq.abs_id;
1367 /* If Tunnel All Lookup isn't specified in the global RSS
1368 * Configuration, then we need to specify a default Ingress
1369 * Queue for any ingress packets which aren't hashed. We'll
1370 * use our first ingress queue ...
1372 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1378 * cxgbe_write_rss - write the RSS table for a given port
1380 * @queues: array of queue indices for RSS
1382 * Sets up the portion of the HW RSS table for the port's VI to distribute
1383 * packets to the Rx queues in @queues.
1385 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1389 struct adapter *adapter = pi->adapter;
1390 const struct sge_eth_rxq *rxq;
1392 /* Should never be called before setting up sge eth rx queues */
1393 BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1395 rxq = &adapter->sge.ethrxq[pi->first_qset];
1396 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1400 /* map the queue indices to queue ids */
1401 for (i = 0; i < pi->rss_size; i++, queues++)
1402 rss[i] = rxq[*queues].rspq.abs_id;
1404 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1405 pi->rss_size, rss, pi->rss_size);
1411 * setup_rss - configure RSS
1412 * @adapter: the adapter
1414 * Sets up RSS to distribute packets to multiple receive queues. We
1415 * configure the RSS CPU lookup table to distribute to the number of HW
1416 * receive queues, and the response queue lookup table to narrow that
1417 * down to the response queues actually configured for each port.
1418 * We always configure the RSS mapping for all ports since the mapping
1419 * table has plenty of entries.
1421 int setup_rss(struct port_info *pi)
1424 struct adapter *adapter = pi->adapter;
1426 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1427 __func__, pi->rss_size, pi->n_rx_qsets);
1429 if (!(pi->flags & PORT_RSS_DONE)) {
1430 if (adapter->flags & FULL_INIT_DONE) {
1431 /* Fill default values with equal distribution */
1432 for (j = 0; j < pi->rss_size; j++)
1433 pi->rss[j] = j % pi->n_rx_qsets;
1435 err = cxgbe_write_rss(pi, pi->rss);
1439 err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1442 pi->flags |= PORT_RSS_DONE;
1449 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1451 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1453 /* 0-increment GTS to start the timer and enable interrupts */
1454 t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1455 T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1456 V_SEINTARM(q->intr_params) |
1457 V_INGRESSQID(q->cntxt_id));
1460 void cxgbe_enable_rx_queues(struct port_info *pi)
1462 struct adapter *adap = pi->adapter;
1463 struct sge *s = &adap->sge;
1466 for (i = 0; i < pi->n_rx_qsets; i++)
1467 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1471 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1472 * @port_type: Firmware Port Type
1473 * @fw_caps: Firmware Port Capabilities
1474 * @speed_caps: Device Info Speed Capabilities
1476 * Translate a Firmware Port Capabilities specification to Device Info
1477 * Speed Capabilities.
1479 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1480 unsigned int fw_caps,
1483 #define SET_SPEED(__speed_name) \
1485 *speed_caps |= ETH_LINK_ ## __speed_name; \
1488 #define FW_CAPS_TO_SPEED(__fw_name) \
1490 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1491 SET_SPEED(__fw_name); \
1494 switch (port_type) {
1495 case FW_PORT_TYPE_BT_SGMII:
1496 case FW_PORT_TYPE_BT_XFI:
1497 case FW_PORT_TYPE_BT_XAUI:
1498 FW_CAPS_TO_SPEED(SPEED_100M);
1499 FW_CAPS_TO_SPEED(SPEED_1G);
1500 FW_CAPS_TO_SPEED(SPEED_10G);
1503 case FW_PORT_TYPE_KX4:
1504 case FW_PORT_TYPE_KX:
1505 case FW_PORT_TYPE_FIBER_XFI:
1506 case FW_PORT_TYPE_FIBER_XAUI:
1507 case FW_PORT_TYPE_SFP:
1508 case FW_PORT_TYPE_QSFP_10G:
1509 case FW_PORT_TYPE_QSA:
1510 FW_CAPS_TO_SPEED(SPEED_1G);
1511 FW_CAPS_TO_SPEED(SPEED_10G);
1514 case FW_PORT_TYPE_KR:
1515 SET_SPEED(SPEED_10G);
1518 case FW_PORT_TYPE_BP_AP:
1519 case FW_PORT_TYPE_BP4_AP:
1520 SET_SPEED(SPEED_1G);
1521 SET_SPEED(SPEED_10G);
1524 case FW_PORT_TYPE_BP40_BA:
1525 case FW_PORT_TYPE_QSFP:
1526 SET_SPEED(SPEED_40G);
1529 case FW_PORT_TYPE_CR_QSFP:
1530 case FW_PORT_TYPE_SFP28:
1531 case FW_PORT_TYPE_KR_SFP28:
1532 FW_CAPS_TO_SPEED(SPEED_1G);
1533 FW_CAPS_TO_SPEED(SPEED_10G);
1534 FW_CAPS_TO_SPEED(SPEED_25G);
1537 case FW_PORT_TYPE_CR2_QSFP:
1538 SET_SPEED(SPEED_50G);
1541 case FW_PORT_TYPE_KR4_100G:
1542 case FW_PORT_TYPE_CR4_QSFP:
1543 FW_CAPS_TO_SPEED(SPEED_25G);
1544 FW_CAPS_TO_SPEED(SPEED_40G);
1545 FW_CAPS_TO_SPEED(SPEED_50G);
1546 FW_CAPS_TO_SPEED(SPEED_100G);
1553 #undef FW_CAPS_TO_SPEED
1558 * cxgbe_get_speed_caps - Fetch supported speed capabilities
1559 * @pi: Underlying port's info
1560 * @speed_caps: Device Info speed capabilities
1562 * Fetch supported speed capabilities of the underlying port.
1564 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1568 fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1571 if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1572 *speed_caps |= ETH_LINK_SPEED_FIXED;
1576 * cxgbe_set_link_status - Set device link up or down.
1577 * @pi: Underlying port's info
1578 * @status: 0 - down, 1 - up
1580 * Set the device link up or down.
1582 int cxgbe_set_link_status(struct port_info *pi, bool status)
1584 struct adapter *adapter = pi->adapter;
1587 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, status, status);
1589 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1594 t4_reset_link_config(adapter, pi->pidx);
1600 * cxgb_up - enable the adapter
1601 * @adap: adapter being enabled
1603 * Called when the first port is enabled, this function performs the
1604 * actions necessary to make an adapter operational, such as completing
1605 * the initialization of HW modules, and enabling interrupts.
1607 int cxgbe_up(struct adapter *adap)
1609 enable_rx(adap, &adap->sge.fw_evtq);
1610 t4_sge_tx_monitor_start(adap);
1612 t4_intr_enable(adap);
1613 adap->flags |= FULL_INIT_DONE;
1615 /* TODO: deadman watchdog ?? */
1622 int cxgbe_down(struct port_info *pi)
1624 return cxgbe_set_link_status(pi, false);
1628 * Release resources when all the ports have been stopped.
1630 void cxgbe_close(struct adapter *adapter)
1632 struct port_info *pi;
1635 if (adapter->flags & FULL_INIT_DONE) {
1636 if (is_pf4(adapter))
1637 t4_intr_disable(adapter);
1638 tid_free(&adapter->tids);
1639 t4_cleanup_clip_tbl(adapter);
1640 t4_sge_tx_monitor_stop(adapter);
1641 t4_free_sge_resources(adapter);
1642 for_each_port(adapter, i) {
1643 pi = adap2pinfo(adapter, i);
1645 t4_free_vi(adapter, adapter->mbox,
1646 adapter->pf, 0, pi->viid);
1647 rte_free(pi->eth_dev->data->mac_addrs);
1648 /* Skip first port since it'll be freed by DPDK stack */
1650 rte_free(pi->eth_dev->data->dev_private);
1651 rte_eth_dev_release_port(pi->eth_dev);
1654 adapter->flags &= ~FULL_INIT_DONE;
1657 if (is_pf4(adapter) && (adapter->flags & FW_OK))
1658 t4_fw_bye(adapter, adapter->mbox);
1661 int cxgbe_probe(struct adapter *adapter)
1663 struct port_info *pi;
1669 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1670 chip = t4_get_chip_type(adapter,
1671 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1675 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1676 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1678 adapter->mbox = func;
1681 t4_os_lock_init(&adapter->mbox_lock);
1682 TAILQ_INIT(&adapter->mbox_list);
1683 t4_os_lock_init(&adapter->win0_lock);
1685 err = t4_prep_adapter(adapter);
1689 setup_memwin(adapter);
1690 err = adap_init0(adapter);
1692 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1697 if (!is_t4(adapter->params.chip)) {
1699 * The userspace doorbell BAR is split evenly into doorbell
1700 * regions, each associated with an egress queue. If this
1701 * per-queue region is large enough (at least UDBS_SEG_SIZE)
1702 * then it can be used to submit a tx work request with an
1703 * implied doorbell. Enable write combining on the BAR if
1704 * there is room for such work requests.
1706 int s_qpp, qpp, num_seg;
1708 s_qpp = (S_QUEUESPERPAGEPF0 +
1709 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1711 qpp = 1 << ((t4_read_reg(adapter,
1712 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1713 & M_QUEUESPERPAGEPF0);
1714 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1716 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1718 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1719 if (!adapter->bar2) {
1720 dev_err(adapter, "cannot map device bar2 region\n");
1724 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1728 for_each_port(adapter, i) {
1729 const unsigned int numa_node = rte_socket_id();
1730 char name[RTE_ETH_NAME_MAX_LEN];
1731 struct rte_eth_dev *eth_dev;
1733 snprintf(name, sizeof(name), "%s_%d",
1734 adapter->pdev->device.name, i);
1737 /* First port is already allocated by DPDK */
1738 eth_dev = adapter->eth_dev;
1743 * now do all data allocation - for eth_dev structure,
1744 * and internal (private) data for the remaining ports
1747 /* reserve an ethdev entry */
1748 eth_dev = rte_eth_dev_allocate(name);
1752 eth_dev->data->dev_private =
1753 rte_zmalloc_socket(name, sizeof(struct port_info),
1754 RTE_CACHE_LINE_SIZE, numa_node);
1755 if (!eth_dev->data->dev_private)
1759 pi = (struct port_info *)eth_dev->data->dev_private;
1760 adapter->port[i] = pi;
1761 pi->eth_dev = eth_dev;
1762 pi->adapter = adapter;
1763 pi->xact_addr_filt = -1;
1767 pi->eth_dev->device = &adapter->pdev->device;
1768 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1769 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1770 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1772 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1774 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1776 if (!pi->eth_dev->data->mac_addrs) {
1777 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1784 /* First port will be notified by upper layer */
1785 rte_eth_dev_probing_finish(eth_dev);
1789 if (adapter->flags & FW_OK) {
1790 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1792 dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1798 cfg_queues(adapter->eth_dev);
1800 print_adapter_info(adapter);
1801 print_port_info(adapter);
1803 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
1804 adapter->clipt_end);
1805 if (!adapter->clipt) {
1806 /* We tolerate a lack of clip_table, giving up some
1809 dev_warn(adapter, "could not allocate CLIP. Continuing\n");
1812 if (tid_init(&adapter->tids) < 0) {
1813 /* Disable filtering support */
1814 dev_warn(adapter, "could not allocate TID table, "
1815 "filter support disabled. Continuing\n");
1818 if (is_hashfilter(adapter)) {
1819 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) {
1820 u32 hash_base, hash_reg;
1822 hash_reg = A_LE_DB_TID_HASHBASE;
1823 hash_base = t4_read_reg(adapter, hash_reg);
1824 adapter->tids.hash_base = hash_base / 4;
1827 /* Disable hash filtering support */
1829 "Maskless filter support disabled. Continuing\n");
1832 err = init_rss(adapter);
1839 for_each_port(adapter, i) {
1840 pi = adap2pinfo(adapter, i);
1842 t4_free_vi(adapter, adapter->mbox, adapter->pf,
1844 /* Skip first port since it'll be de-allocated by DPDK */
1848 if (pi->eth_dev->data->dev_private)
1849 rte_free(pi->eth_dev->data->dev_private);
1850 rte_eth_dev_release_port(pi->eth_dev);
1854 if (adapter->flags & FW_OK)
1855 t4_fw_bye(adapter, adapter->mbox);