1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_atomic.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_tailq.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
35 #include <rte_kvargs.h>
42 #define CXGBE_DEVARG_KEEP_OVLAN "keep_ovlan"
45 * Response queue handler for the FW event queue.
47 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
48 __rte_unused const struct pkt_gl *gl)
50 u8 opcode = ((const struct rss_header *)rsp)->opcode;
52 rsp++; /* skip RSS header */
55 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
57 if (unlikely(opcode == CPL_FW4_MSG &&
58 ((const struct cpl_fw4_msg *)rsp)->type ==
61 opcode = ((const struct rss_header *)rsp)->opcode;
63 if (opcode != CPL_SGE_EGR_UPDATE) {
64 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
70 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
72 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
73 const struct cpl_fw6_msg *msg = (const void *)rsp;
75 t4_handle_fw_rpl(q->adapter, msg->data);
77 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
84 int setup_sge_fwevtq(struct adapter *adapter)
86 struct sge *s = &adapter->sge;
90 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
91 msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
96 static int closest_timer(const struct sge *s, int time)
98 unsigned int i, match = 0;
99 int delta, min_delta = INT_MAX;
101 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
102 delta = time - s->timer_val[i];
105 if (delta < min_delta) {
113 static int closest_thres(const struct sge *s, int thres)
115 unsigned int i, match = 0;
116 int delta, min_delta = INT_MAX;
118 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
119 delta = thres - s->counter_val[i];
122 if (delta < min_delta) {
131 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
133 * @us: the hold-off time in us, or 0 to disable timer
134 * @cnt: the hold-off packet count, or 0 to disable counter
136 * Sets an Rx queue's interrupt hold-off time and packet count. At least
137 * one of the two needs to be enabled for the queue to generate interrupts.
139 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
142 struct adapter *adap = q->adapter;
143 unsigned int timer_val;
149 new_idx = closest_thres(&adap->sge, cnt);
150 if (q->desc && q->pktcnt_idx != new_idx) {
151 /* the queue has already been created, update it */
152 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
154 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
155 V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
156 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
161 q->pktcnt_idx = new_idx;
164 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
165 closest_timer(&adap->sge, us);
168 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
170 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
171 V_QINTR_CNT_EN(cnt > 0);
175 static inline bool is_x_1g_port(const struct link_config *lc)
177 return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
180 static inline bool is_x_10g_port(const struct link_config *lc)
182 unsigned int speeds, high_speeds;
184 speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
185 high_speeds = speeds &
186 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
188 return high_speeds != 0;
191 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
192 unsigned int us, unsigned int cnt,
193 unsigned int size, unsigned int iqe_size)
196 cxgb4_set_rspq_intr_params(q, us, cnt);
197 q->iqe_len = iqe_size;
201 int cfg_queue_count(struct rte_eth_dev *eth_dev)
203 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
204 struct adapter *adap = pi->adapter;
205 struct sge *s = &adap->sge;
206 unsigned int max_queues = s->max_ethqsets / adap->params.nports;
208 if ((eth_dev->data->nb_rx_queues < 1) ||
209 (eth_dev->data->nb_tx_queues < 1))
212 if ((eth_dev->data->nb_rx_queues > max_queues) ||
213 (eth_dev->data->nb_tx_queues > max_queues))
216 if (eth_dev->data->nb_rx_queues > pi->rss_size)
219 /* We must configure RSS, since config has changed*/
220 pi->flags &= ~PORT_RSS_DONE;
222 pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
223 pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
228 void cfg_queues(struct rte_eth_dev *eth_dev)
230 struct rte_config *config = rte_eal_get_configuration();
231 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
232 struct adapter *adap = pi->adapter;
233 struct sge *s = &adap->sge;
234 unsigned int i, nb_ports = 0, qidx = 0;
235 unsigned int q_per_port = 0;
237 if (!(adap->flags & CFG_QUEUES)) {
238 for_each_port(adap, i) {
239 struct port_info *tpi = adap2pinfo(adap, i);
241 nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
242 is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
246 * We default up to # of cores queues per 1G/10G port.
249 q_per_port = (MAX_ETH_QSETS -
250 (adap->params.nports - nb_ports)) /
253 if (q_per_port > config->lcore_count)
254 q_per_port = config->lcore_count;
256 for_each_port(adap, i) {
257 struct port_info *pi = adap2pinfo(adap, i);
259 pi->first_qset = qidx;
261 /* Initially n_rx_qsets == n_tx_qsets */
262 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
263 is_x_1g_port(&pi->link_cfg)) ?
265 pi->n_tx_qsets = pi->n_rx_qsets;
267 if (pi->n_rx_qsets > pi->rss_size)
268 pi->n_rx_qsets = pi->rss_size;
270 qidx += pi->n_rx_qsets;
273 s->max_ethqsets = qidx;
275 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
276 struct sge_eth_rxq *r = &s->ethrxq[i];
278 init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
280 r->fl.size = (r->usembufs ? 1024 : 72);
283 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
284 s->ethtxq[i].q.size = 1024;
286 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
287 adap->flags |= CFG_QUEUES;
291 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
293 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
297 void cxgbe_stats_reset(struct port_info *pi)
299 t4_clr_port_stats(pi->adapter, pi->tx_chan);
302 static void setup_memwin(struct adapter *adap)
306 /* For T5, only relative offset inside the PCIe BAR is passed */
307 mem_win0_base = MEMWIN0_BASE;
310 * Set up memory window for accessing adapter memory ranges. (Read
311 * back MA register to ensure that changes propagate before we attempt
312 * to use the new values.)
315 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
317 mem_win0_base | V_BIR(0) |
318 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
320 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
324 int init_rss(struct adapter *adap)
331 err = t4_init_rss_mode(adap, adap->mbox);
336 for_each_port(adap, i) {
337 struct port_info *pi = adap2pinfo(adap, i);
339 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
343 pi->rss_hf = CXGBE_RSS_HF_ALL;
349 * Dump basic information about the adapter.
351 void print_adapter_info(struct adapter *adap)
354 * Hardware/Firmware/etc. Version/Revision IDs.
356 t4_dump_version_info(adap);
359 void print_port_info(struct adapter *adap)
363 struct rte_pci_addr *loc = &adap->pdev->addr;
365 for_each_port(adap, i) {
366 const struct port_info *pi = adap2pinfo(adap, i);
369 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
370 bufp += sprintf(bufp, "100M/");
371 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
372 bufp += sprintf(bufp, "1G/");
373 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
374 bufp += sprintf(bufp, "10G/");
375 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
376 bufp += sprintf(bufp, "25G/");
377 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
378 bufp += sprintf(bufp, "40G/");
379 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
380 bufp += sprintf(bufp, "50G/");
381 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
382 bufp += sprintf(bufp, "100G/");
385 sprintf(bufp, "BASE-%s",
386 t4_get_port_type_description(
387 (enum fw_port_type)pi->port_type));
390 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
391 loc->domain, loc->bus, loc->devid, loc->function,
392 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
393 (adap->flags & USING_MSIX) ? " MSI-X" :
394 (adap->flags & USING_MSI) ? " MSI" : "");
399 check_devargs_handler(__rte_unused const char *key, const char *value,
400 __rte_unused void *opaque)
402 if (strcmp(value, "1"))
408 static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key)
410 struct rte_kvargs *kvlist;
415 kvlist = rte_kvargs_parse(devargs->args, NULL);
419 if (!rte_kvargs_count(kvlist, key)) {
420 rte_kvargs_free(kvlist);
424 if (rte_kvargs_process(kvlist, key,
425 check_devargs_handler, NULL) < 0) {
426 rte_kvargs_free(kvlist);
429 rte_kvargs_free(kvlist);
434 static void configure_vlan_types(struct adapter *adapter)
436 struct rte_pci_device *pdev = adapter->pdev;
439 for_each_port(adapter, i) {
440 /* OVLAN Type 0x88a8 */
441 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
442 V_OVLAN_MASK(M_OVLAN_MASK) |
443 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
444 V_OVLAN_MASK(M_OVLAN_MASK) |
445 V_OVLAN_ETYPE(0x88a8));
446 /* OVLAN Type 0x9100 */
447 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
448 V_OVLAN_MASK(M_OVLAN_MASK) |
449 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
450 V_OVLAN_MASK(M_OVLAN_MASK) |
451 V_OVLAN_ETYPE(0x9100));
452 /* OVLAN Type 0x8100 */
453 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
454 V_OVLAN_MASK(M_OVLAN_MASK) |
455 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
456 V_OVLAN_MASK(M_OVLAN_MASK) |
457 V_OVLAN_ETYPE(0x8100));
460 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
461 V_IVLAN_ETYPE(M_IVLAN_ETYPE),
462 V_IVLAN_ETYPE(0x8100));
464 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
465 F_OVLAN_EN0 | F_OVLAN_EN1 |
466 F_OVLAN_EN2 | F_IVLAN_EN,
467 F_OVLAN_EN0 | F_OVLAN_EN1 |
468 F_OVLAN_EN2 | F_IVLAN_EN);
471 if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN))
472 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
473 V_RM_OVLAN(1), V_RM_OVLAN(0));
476 static void configure_pcie_ext_tag(struct adapter *adapter)
479 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
485 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
486 v |= PCI_EXP_DEVCTL_EXT_TAG;
487 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
488 if (is_t6(adapter->params.chip)) {
489 t4_set_reg_field(adapter, A_PCIE_CFG2,
490 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
492 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
493 V_T6_MINTAG(M_T6_MINTAG),
496 t4_set_reg_field(adapter, A_PCIE_CFG2,
497 V_TOTMAXTAG(M_TOTMAXTAG),
499 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
507 * Tweak configuration based on system architecture, etc. Most of these have
508 * defaults assigned to them by Firmware Configuration Files (if we're using
509 * them) but need to be explicitly set if we're using hard-coded
510 * initialization. So these are essentially common tweaks/settings for
511 * Configuration Files and hard-coded initialization ...
513 static int adap_init0_tweaks(struct adapter *adapter)
518 * Fix up various Host-Dependent Parameters like Page Size, Cache
519 * Line Size, etc. The firmware default is for a 4KB Page Size and
520 * 64B Cache Line Size ...
522 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
526 * Keep the chip default offset to deliver Ingress packets into our
527 * DMA buffers to zero
530 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
531 V_PKTSHIFT(rx_dma_offset));
533 t4_set_reg_field(adapter, A_SGE_FLM_CFG,
534 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
535 V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
537 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
538 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
540 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
541 V_IDMAARBROUNDROBIN(1U));
544 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
545 * adds the pseudo header itself.
547 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
548 F_CSUM_HAS_PSEUDO_HDR, 0);
554 * Attempt to initialize the adapter via a Firmware Configuration File.
556 static int adap_init0_config(struct adapter *adapter, int reset)
558 struct fw_caps_config_cmd caps_cmd;
559 unsigned long mtype = 0, maddr = 0;
560 u32 finiver, finicsum, cfcsum;
562 int config_issued = 0;
564 char config_name[20];
567 * Reset device if necessary.
570 ret = t4_fw_reset(adapter, adapter->mbox,
571 F_PIORSTMODE | F_PIORST);
573 dev_warn(adapter, "Firmware reset failed, error %d\n",
579 cfg_addr = t4_flash_cfg_addr(adapter);
582 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
587 strcpy(config_name, "On Flash");
588 mtype = FW_MEMTYPE_CF_FLASH;
592 * Issue a Capability Configuration command to the firmware to get it
593 * to parse the Configuration File. We don't use t4_fw_config_file()
594 * because we want the ability to modify various features after we've
595 * processed the configuration file ...
597 memset(&caps_cmd, 0, sizeof(caps_cmd));
598 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
599 F_FW_CMD_REQUEST | F_FW_CMD_READ);
600 caps_cmd.cfvalid_to_len16 =
601 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
602 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
603 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
605 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
608 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
609 * Configuration File in FLASH), our last gasp effort is to use the
610 * Firmware Configuration File which is embedded in the firmware. A
611 * very few early versions of the firmware didn't have one embedded
612 * but we can ignore those.
614 if (ret == -ENOENT) {
615 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
618 memset(&caps_cmd, 0, sizeof(caps_cmd));
619 caps_cmd.op_to_write =
620 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
621 F_FW_CMD_REQUEST | F_FW_CMD_READ);
622 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
623 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
624 sizeof(caps_cmd), &caps_cmd);
625 strcpy(config_name, "Firmware Default");
632 finiver = be32_to_cpu(caps_cmd.finiver);
633 finicsum = be32_to_cpu(caps_cmd.finicsum);
634 cfcsum = be32_to_cpu(caps_cmd.cfcsum);
635 if (finicsum != cfcsum)
636 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
640 * If we're a pure NIC driver then disable all offloading facilities.
641 * This will allow the firmware to optimize aspects of the hardware
642 * configuration which will result in improved performance.
644 caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
645 FW_CAPS_CONFIG_NIC_ETHOFLD));
646 caps_cmd.toecaps = 0;
647 caps_cmd.iscsicaps = 0;
648 caps_cmd.rdmacaps = 0;
649 caps_cmd.fcoecaps = 0;
652 * And now tell the firmware to use the configuration we just loaded.
654 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
655 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
656 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
657 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
660 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
666 * Tweak configuration based on system architecture, etc.
668 ret = adap_init0_tweaks(adapter);
670 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
675 * And finally tell the firmware to initialize itself using the
676 * parameters from the Configuration File.
678 ret = t4_fw_initialize(adapter, adapter->mbox);
680 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
686 * Return successfully and note that we're operating with parameters
687 * not supplied by the driver, rather than from hard-wired
688 * initialization constants buried in the driver.
691 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
692 config_name, finiver, cfcsum);
697 * Something bad happened. Return the error ... (If the "error"
698 * is that there's no Configuration File on the adapter we don't
699 * want to issue a warning since this is fairly common.)
702 if (config_issued && ret != -ENOENT)
703 dev_warn(adapter, "\"%s\" configuration file error %d\n",
706 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
710 static int adap_init0(struct adapter *adap)
714 enum dev_state state;
715 u32 params[7], val[7];
717 int mbox = adap->mbox;
720 * Contact FW, advertising Master capability.
722 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
724 dev_err(adap, "%s: could not connect to FW, error %d\n",
729 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
733 adap->flags |= MASTER_PF;
735 if (state == DEV_STATE_INIT) {
737 * Force halt and reset FW because a previous instance may have
738 * exited abnormally without properly shutting down
740 ret = t4_fw_halt(adap, adap->mbox, reset);
742 dev_err(adap, "Failed to halt. Exit.\n");
746 ret = t4_fw_restart(adap, adap->mbox, reset);
748 dev_err(adap, "Failed to restart. Exit.\n");
751 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
754 t4_get_version_info(adap);
756 ret = t4_get_core_clock(adap, &adap->params.vpd);
758 dev_err(adap, "%s: could not get core clock, error %d\n",
764 * If the firmware is initialized already (and we're not forcing a
765 * master initialization), note that we're living with existing
766 * adapter parameters. Otherwise, it's time to try initializing the
769 if (state == DEV_STATE_INIT) {
770 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
771 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
773 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
775 ret = adap_init0_config(adap, reset);
776 if (ret == -ENOENT) {
778 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
783 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
787 /* Find out what ports are available to us. */
788 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
789 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
790 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
792 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
797 adap->params.nports = hweight32(port_vec);
798 adap->params.portvec = port_vec;
800 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
801 adap->params.nports);
804 * Give the SGE code a chance to pull in anything that it needs ...
805 * Note that this must be called after we retrieve our VPD parameters
806 * in order to know how to convert core ticks to seconds, etc.
808 ret = t4_sge_init(adap);
810 dev_err(adap, "t4_sge_init failed with error %d\n",
816 * Grab some of our basic fundamental operating parameters.
818 #define FW_PARAM_DEV(param) \
819 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
820 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
822 #define FW_PARAM_PFVF(param) \
823 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
824 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
825 V_FW_PARAMS_PARAM_Y(0) | \
826 V_FW_PARAMS_PARAM_Z(0))
828 /* If we're running on newer firmware, let it know that we're
829 * prepared to deal with encapsulated CPL messages. Older
830 * firmware won't understand this and we'll just get
831 * unencapsulated messages ...
833 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
835 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
838 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
839 * capability. Earlier versions of the firmware didn't have the
840 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
841 * permission to use ULPTX MEMWRITE DSGL.
843 if (is_t4(adap->params.chip)) {
844 adap->params.ulptx_memwrite_dsgl = false;
846 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
847 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
849 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
853 * The MTU/MSS Table is initialized by now, so load their values. If
854 * we're initializing the adapter, then we'll make any modifications
855 * we want to the MTU/MSS Table and also initialize the congestion
858 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
859 if (state != DEV_STATE_INIT) {
863 * The default MTU Table contains values 1492 and 1500.
864 * However, for TCP, it's better to have two values which are
865 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
866 * This allows us to have a TCP Data Payload which is a
867 * multiple of 8 regardless of what combination of TCP Options
868 * are in use (always a multiple of 4 bytes) which is
869 * important for performance reasons. For instance, if no
870 * options are in use, then we have a 20-byte IP header and a
871 * 20-byte TCP header. In this case, a 1500-byte MSS would
872 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
873 * which is not a multiple of 8. So using an MSS of 1488 in
874 * this case results in a TCP Data Payload of 1448 bytes which
875 * is a multiple of 8. On the other hand, if 12-byte TCP Time
876 * Stamps have been negotiated, then an MTU of 1500 bytes
877 * results in a TCP Data Payload of 1448 bytes which, as
878 * above, is a multiple of 8 bytes ...
880 for (i = 0; i < NMTUS; i++)
881 if (adap->params.mtus[i] == 1492) {
882 adap->params.mtus[i] = 1488;
886 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
889 t4_init_sge_params(adap);
890 t4_init_tp_params(adap);
891 configure_pcie_ext_tag(adap);
892 configure_vlan_types(adap);
894 adap->params.drv_memwin = MEMWIN_NIC;
895 adap->flags |= FW_OK;
896 dev_debug(adap, "%s: returning zero..\n", __func__);
900 * Something bad happened. If a command timed out or failed with EIO
901 * FW does not operate within its spec or something catastrophic
902 * happened to HW/FW, stop issuing commands.
905 if (ret != -ETIMEDOUT && ret != -EIO)
906 t4_fw_bye(adap, adap->mbox);
911 * t4_os_portmod_changed - handle port module changes
912 * @adap: the adapter associated with the module change
913 * @port_id: the port index whose module status has changed
915 * This is the OS-dependent handler for port module changes. It is
916 * invoked when a port module is removed or inserted for any OS-specific
919 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
921 static const char * const mod_str[] = {
922 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
925 const struct port_info *pi = adap2pinfo(adap, port_id);
927 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
928 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
929 else if (pi->mod_type < ARRAY_SIZE(mod_str))
930 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
931 mod_str[pi->mod_type]);
932 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
933 dev_info(adap, "Port%d: unsupported port module inserted\n",
935 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
936 dev_info(adap, "Port%d: unknown port module inserted\n",
938 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
939 dev_info(adap, "Port%d: transceiver module error\n",
942 dev_info(adap, "Port%d: unknown module type %d inserted\n",
943 pi->port_id, pi->mod_type);
947 * link_start - enable a port
948 * @dev: the port to enable
950 * Performs the MAC and PHY actions needed to enable a port.
952 int link_start(struct port_info *pi)
954 struct adapter *adapter = pi->adapter;
958 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
959 (ETHER_HDR_LEN + ETHER_CRC_LEN);
962 * We do not set address filters and promiscuity here, the stack does
963 * that step explicitly.
965 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
968 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
970 (u8 *)&pi->eth_dev->data->mac_addrs[0],
973 pi->xact_addr_filt = ret;
977 if (ret == 0 && is_pf4(adapter))
978 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
982 * Enabling a Virtual Interface can result in an interrupt
983 * during the processing of the VI Enable command and, in some
984 * paths, result in an attempt to issue another command in the
985 * interrupt context. Thus, we disable interrupts during the
986 * course of the VI Enable command ...
988 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
995 * cxgbe_write_rss_conf - flash the RSS configuration for a given port
997 * @rss_hf: Hash configuration to apply
999 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1001 struct adapter *adapter = pi->adapter;
1002 const struct sge_eth_rxq *rxq;
1007 /* Should never be called before setting up sge eth rx queues */
1008 if (!(adapter->flags & FULL_INIT_DONE)) {
1009 dev_err(adap, "%s No RXQs available on port %d\n",
1010 __func__, pi->port_id);
1014 /* Don't allow unsupported hash functions */
1015 if (rss_hf & ~CXGBE_RSS_HF_ALL)
1018 if (rss_hf & ETH_RSS_IPV4)
1019 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1021 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1022 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1024 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1025 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1026 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1028 if (rss_hf & ETH_RSS_IPV6)
1029 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1031 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
1032 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1034 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
1035 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1036 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1038 rxq = &adapter->sge.ethrxq[pi->first_qset];
1039 rss = rxq[0].rspq.abs_id;
1041 /* If Tunnel All Lookup isn't specified in the global RSS
1042 * Configuration, then we need to specify a default Ingress
1043 * Queue for any ingress packets which aren't hashed. We'll
1044 * use our first ingress queue ...
1046 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1052 * cxgbe_write_rss - write the RSS table for a given port
1054 * @queues: array of queue indices for RSS
1056 * Sets up the portion of the HW RSS table for the port's VI to distribute
1057 * packets to the Rx queues in @queues.
1059 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1063 struct adapter *adapter = pi->adapter;
1064 const struct sge_eth_rxq *rxq;
1066 /* Should never be called before setting up sge eth rx queues */
1067 BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1069 rxq = &adapter->sge.ethrxq[pi->first_qset];
1070 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1074 /* map the queue indices to queue ids */
1075 for (i = 0; i < pi->rss_size; i++, queues++)
1076 rss[i] = rxq[*queues].rspq.abs_id;
1078 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1079 pi->rss_size, rss, pi->rss_size);
1085 * setup_rss - configure RSS
1086 * @adapter: the adapter
1088 * Sets up RSS to distribute packets to multiple receive queues. We
1089 * configure the RSS CPU lookup table to distribute to the number of HW
1090 * receive queues, and the response queue lookup table to narrow that
1091 * down to the response queues actually configured for each port.
1092 * We always configure the RSS mapping for all ports since the mapping
1093 * table has plenty of entries.
1095 int setup_rss(struct port_info *pi)
1098 struct adapter *adapter = pi->adapter;
1100 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1101 __func__, pi->rss_size, pi->n_rx_qsets);
1103 if (!(pi->flags & PORT_RSS_DONE)) {
1104 if (adapter->flags & FULL_INIT_DONE) {
1105 /* Fill default values with equal distribution */
1106 for (j = 0; j < pi->rss_size; j++)
1107 pi->rss[j] = j % pi->n_rx_qsets;
1109 err = cxgbe_write_rss(pi, pi->rss);
1113 err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1116 pi->flags |= PORT_RSS_DONE;
1123 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1125 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1127 /* 0-increment GTS to start the timer and enable interrupts */
1128 t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1129 T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1130 V_SEINTARM(q->intr_params) |
1131 V_INGRESSQID(q->cntxt_id));
1134 void cxgbe_enable_rx_queues(struct port_info *pi)
1136 struct adapter *adap = pi->adapter;
1137 struct sge *s = &adap->sge;
1140 for (i = 0; i < pi->n_rx_qsets; i++)
1141 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1145 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1146 * @port_type: Firmware Port Type
1147 * @fw_caps: Firmware Port Capabilities
1148 * @speed_caps: Device Info Speed Capabilities
1150 * Translate a Firmware Port Capabilities specification to Device Info
1151 * Speed Capabilities.
1153 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1154 unsigned int fw_caps,
1157 #define SET_SPEED(__speed_name) \
1159 *speed_caps |= ETH_LINK_ ## __speed_name; \
1162 #define FW_CAPS_TO_SPEED(__fw_name) \
1164 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1165 SET_SPEED(__fw_name); \
1168 switch (port_type) {
1169 case FW_PORT_TYPE_BT_SGMII:
1170 case FW_PORT_TYPE_BT_XFI:
1171 case FW_PORT_TYPE_BT_XAUI:
1172 FW_CAPS_TO_SPEED(SPEED_100M);
1173 FW_CAPS_TO_SPEED(SPEED_1G);
1174 FW_CAPS_TO_SPEED(SPEED_10G);
1177 case FW_PORT_TYPE_KX4:
1178 case FW_PORT_TYPE_KX:
1179 case FW_PORT_TYPE_FIBER_XFI:
1180 case FW_PORT_TYPE_FIBER_XAUI:
1181 case FW_PORT_TYPE_SFP:
1182 case FW_PORT_TYPE_QSFP_10G:
1183 case FW_PORT_TYPE_QSA:
1184 FW_CAPS_TO_SPEED(SPEED_1G);
1185 FW_CAPS_TO_SPEED(SPEED_10G);
1188 case FW_PORT_TYPE_KR:
1189 SET_SPEED(SPEED_10G);
1192 case FW_PORT_TYPE_BP_AP:
1193 case FW_PORT_TYPE_BP4_AP:
1194 SET_SPEED(SPEED_1G);
1195 SET_SPEED(SPEED_10G);
1198 case FW_PORT_TYPE_BP40_BA:
1199 case FW_PORT_TYPE_QSFP:
1200 SET_SPEED(SPEED_40G);
1203 case FW_PORT_TYPE_CR_QSFP:
1204 case FW_PORT_TYPE_SFP28:
1205 case FW_PORT_TYPE_KR_SFP28:
1206 FW_CAPS_TO_SPEED(SPEED_1G);
1207 FW_CAPS_TO_SPEED(SPEED_10G);
1208 FW_CAPS_TO_SPEED(SPEED_25G);
1211 case FW_PORT_TYPE_CR2_QSFP:
1212 SET_SPEED(SPEED_50G);
1215 case FW_PORT_TYPE_KR4_100G:
1216 case FW_PORT_TYPE_CR4_QSFP:
1217 FW_CAPS_TO_SPEED(SPEED_25G);
1218 FW_CAPS_TO_SPEED(SPEED_40G);
1219 FW_CAPS_TO_SPEED(SPEED_50G);
1220 FW_CAPS_TO_SPEED(SPEED_100G);
1227 #undef FW_CAPS_TO_SPEED
1232 * cxgbe_get_speed_caps - Fetch supported speed capabilities
1233 * @pi: Underlying port's info
1234 * @speed_caps: Device Info speed capabilities
1236 * Fetch supported speed capabilities of the underlying port.
1238 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1242 fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1245 if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1246 *speed_caps |= ETH_LINK_SPEED_FIXED;
1250 * cxgb_up - enable the adapter
1251 * @adap: adapter being enabled
1253 * Called when the first port is enabled, this function performs the
1254 * actions necessary to make an adapter operational, such as completing
1255 * the initialization of HW modules, and enabling interrupts.
1257 int cxgbe_up(struct adapter *adap)
1259 enable_rx(adap, &adap->sge.fw_evtq);
1260 t4_sge_tx_monitor_start(adap);
1262 t4_intr_enable(adap);
1263 adap->flags |= FULL_INIT_DONE;
1265 /* TODO: deadman watchdog ?? */
1272 int cxgbe_down(struct port_info *pi)
1274 struct adapter *adapter = pi->adapter;
1277 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1279 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1283 t4_reset_link_config(adapter, pi->pidx);
1288 * Release resources when all the ports have been stopped.
1290 void cxgbe_close(struct adapter *adapter)
1292 struct port_info *pi;
1295 if (adapter->flags & FULL_INIT_DONE) {
1296 if (is_pf4(adapter))
1297 t4_intr_disable(adapter);
1298 t4_sge_tx_monitor_stop(adapter);
1299 t4_free_sge_resources(adapter);
1300 for_each_port(adapter, i) {
1301 pi = adap2pinfo(adapter, i);
1303 t4_free_vi(adapter, adapter->mbox,
1304 adapter->pf, 0, pi->viid);
1305 rte_free(pi->eth_dev->data->mac_addrs);
1306 /* Skip first port since it'll be freed by DPDK stack */
1308 rte_free(pi->eth_dev->data->dev_private);
1309 rte_eth_dev_release_port(pi->eth_dev);
1312 adapter->flags &= ~FULL_INIT_DONE;
1315 if (is_pf4(adapter) && (adapter->flags & FW_OK))
1316 t4_fw_bye(adapter, adapter->mbox);
1319 int cxgbe_probe(struct adapter *adapter)
1321 struct port_info *pi;
1327 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1328 chip = t4_get_chip_type(adapter,
1329 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1333 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1334 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1336 adapter->mbox = func;
1339 t4_os_lock_init(&adapter->mbox_lock);
1340 TAILQ_INIT(&adapter->mbox_list);
1342 err = t4_prep_adapter(adapter);
1346 setup_memwin(adapter);
1347 err = adap_init0(adapter);
1349 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1354 if (!is_t4(adapter->params.chip)) {
1356 * The userspace doorbell BAR is split evenly into doorbell
1357 * regions, each associated with an egress queue. If this
1358 * per-queue region is large enough (at least UDBS_SEG_SIZE)
1359 * then it can be used to submit a tx work request with an
1360 * implied doorbell. Enable write combining on the BAR if
1361 * there is room for such work requests.
1363 int s_qpp, qpp, num_seg;
1365 s_qpp = (S_QUEUESPERPAGEPF0 +
1366 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1368 qpp = 1 << ((t4_read_reg(adapter,
1369 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1370 & M_QUEUESPERPAGEPF0);
1371 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1373 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1375 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1376 if (!adapter->bar2) {
1377 dev_err(adapter, "cannot map device bar2 region\n");
1381 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1385 for_each_port(adapter, i) {
1386 const unsigned int numa_node = rte_socket_id();
1387 char name[RTE_ETH_NAME_MAX_LEN];
1388 struct rte_eth_dev *eth_dev;
1390 snprintf(name, sizeof(name), "%s_%d",
1391 adapter->pdev->device.name, i);
1394 /* First port is already allocated by DPDK */
1395 eth_dev = adapter->eth_dev;
1400 * now do all data allocation - for eth_dev structure,
1401 * and internal (private) data for the remaining ports
1404 /* reserve an ethdev entry */
1405 eth_dev = rte_eth_dev_allocate(name);
1409 eth_dev->data->dev_private =
1410 rte_zmalloc_socket(name, sizeof(struct port_info),
1411 RTE_CACHE_LINE_SIZE, numa_node);
1412 if (!eth_dev->data->dev_private)
1416 pi = (struct port_info *)eth_dev->data->dev_private;
1417 adapter->port[i] = pi;
1418 pi->eth_dev = eth_dev;
1419 pi->adapter = adapter;
1420 pi->xact_addr_filt = -1;
1424 pi->eth_dev->device = &adapter->pdev->device;
1425 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1426 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1427 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1429 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1431 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1433 if (!pi->eth_dev->data->mac_addrs) {
1434 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1441 if (adapter->flags & FW_OK) {
1442 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1444 dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1450 cfg_queues(adapter->eth_dev);
1452 print_adapter_info(adapter);
1453 print_port_info(adapter);
1455 err = init_rss(adapter);
1462 for_each_port(adapter, i) {
1463 pi = adap2pinfo(adapter, i);
1465 t4_free_vi(adapter, adapter->mbox, adapter->pf,
1467 /* Skip first port since it'll be de-allocated by DPDK */
1471 if (pi->eth_dev->data->dev_private)
1472 rte_free(pi->eth_dev->data->dev_private);
1473 rte_eth_dev_release_port(pi->eth_dev);
1477 if (adapter->flags & FW_OK)
1478 t4_fw_bye(adapter, adapter->mbox);