4 * Copyright(c) 2014-2017 Chelsio Communications.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Chelsio Communications nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <netinet/in.h>
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
46 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_tailq.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev_driver.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_malloc.h>
61 #include <rte_random.h>
70 * Response queue handler for the FW event queue.
72 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
73 __rte_unused const struct pkt_gl *gl)
75 u8 opcode = ((const struct rss_header *)rsp)->opcode;
77 rsp++; /* skip RSS header */
80 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
82 if (unlikely(opcode == CPL_FW4_MSG &&
83 ((const struct cpl_fw4_msg *)rsp)->type ==
86 opcode = ((const struct rss_header *)rsp)->opcode;
88 if (opcode != CPL_SGE_EGR_UPDATE) {
89 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
95 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
97 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
98 const struct cpl_fw6_msg *msg = (const void *)rsp;
100 t4_handle_fw_rpl(q->adapter, msg->data);
102 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
109 int setup_sge_fwevtq(struct adapter *adapter)
111 struct sge *s = &adapter->sge;
115 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
116 msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
121 static int closest_timer(const struct sge *s, int time)
123 unsigned int i, match = 0;
124 int delta, min_delta = INT_MAX;
126 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
127 delta = time - s->timer_val[i];
130 if (delta < min_delta) {
138 static int closest_thres(const struct sge *s, int thres)
140 unsigned int i, match = 0;
141 int delta, min_delta = INT_MAX;
143 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
144 delta = thres - s->counter_val[i];
147 if (delta < min_delta) {
156 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
158 * @us: the hold-off time in us, or 0 to disable timer
159 * @cnt: the hold-off packet count, or 0 to disable counter
161 * Sets an Rx queue's interrupt hold-off time and packet count. At least
162 * one of the two needs to be enabled for the queue to generate interrupts.
164 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
167 struct adapter *adap = q->adapter;
168 unsigned int timer_val;
174 new_idx = closest_thres(&adap->sge, cnt);
175 if (q->desc && q->pktcnt_idx != new_idx) {
176 /* the queue has already been created, update it */
177 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
179 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
180 V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
181 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
186 q->pktcnt_idx = new_idx;
189 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
190 closest_timer(&adap->sge, us);
193 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
195 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
196 V_QINTR_CNT_EN(cnt > 0);
200 static inline bool is_x_1g_port(const struct link_config *lc)
202 return (lc->supported & FW_PORT_CAP_SPEED_1G) != 0;
205 static inline bool is_x_10g_port(const struct link_config *lc)
207 unsigned int speeds, high_speeds;
209 speeds = V_FW_PORT_CAP_SPEED(G_FW_PORT_CAP_SPEED(lc->supported));
210 high_speeds = speeds & ~(FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G);
212 return high_speeds != 0;
215 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
216 unsigned int us, unsigned int cnt,
217 unsigned int size, unsigned int iqe_size)
220 cxgb4_set_rspq_intr_params(q, us, cnt);
221 q->iqe_len = iqe_size;
225 int cfg_queue_count(struct rte_eth_dev *eth_dev)
227 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
228 struct adapter *adap = pi->adapter;
229 struct sge *s = &adap->sge;
230 unsigned int max_queues = s->max_ethqsets / adap->params.nports;
232 if ((eth_dev->data->nb_rx_queues < 1) ||
233 (eth_dev->data->nb_tx_queues < 1))
236 if ((eth_dev->data->nb_rx_queues > max_queues) ||
237 (eth_dev->data->nb_tx_queues > max_queues))
240 if (eth_dev->data->nb_rx_queues > pi->rss_size)
243 /* We must configure RSS, since config has changed*/
244 pi->flags &= ~PORT_RSS_DONE;
246 pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
247 pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
252 void cfg_queues(struct rte_eth_dev *eth_dev)
254 struct rte_config *config = rte_eal_get_configuration();
255 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
256 struct adapter *adap = pi->adapter;
257 struct sge *s = &adap->sge;
258 unsigned int i, nb_ports = 0, qidx = 0;
259 unsigned int q_per_port = 0;
261 if (!(adap->flags & CFG_QUEUES)) {
262 for_each_port(adap, i) {
263 struct port_info *tpi = adap2pinfo(adap, i);
265 nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
266 is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
270 * We default up to # of cores queues per 1G/10G port.
273 q_per_port = (MAX_ETH_QSETS -
274 (adap->params.nports - nb_ports)) /
277 if (q_per_port > config->lcore_count)
278 q_per_port = config->lcore_count;
280 for_each_port(adap, i) {
281 struct port_info *pi = adap2pinfo(adap, i);
283 pi->first_qset = qidx;
285 /* Initially n_rx_qsets == n_tx_qsets */
286 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
287 is_x_1g_port(&pi->link_cfg)) ?
289 pi->n_tx_qsets = pi->n_rx_qsets;
291 if (pi->n_rx_qsets > pi->rss_size)
292 pi->n_rx_qsets = pi->rss_size;
294 qidx += pi->n_rx_qsets;
297 s->max_ethqsets = qidx;
299 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
300 struct sge_eth_rxq *r = &s->ethrxq[i];
302 init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
304 r->fl.size = (r->usembufs ? 1024 : 72);
307 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
308 s->ethtxq[i].q.size = 1024;
310 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
311 adap->flags |= CFG_QUEUES;
315 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
317 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
321 void cxgbe_stats_reset(struct port_info *pi)
323 t4_clr_port_stats(pi->adapter, pi->tx_chan);
326 static void setup_memwin(struct adapter *adap)
330 /* For T5, only relative offset inside the PCIe BAR is passed */
331 mem_win0_base = MEMWIN0_BASE;
334 * Set up memory window for accessing adapter memory ranges. (Read
335 * back MA register to ensure that changes propagate before we attempt
336 * to use the new values.)
339 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
341 mem_win0_base | V_BIR(0) |
342 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
344 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
348 static int init_rss(struct adapter *adap)
353 err = t4_init_rss_mode(adap, adap->mbox);
357 for_each_port(adap, i) {
358 struct port_info *pi = adap2pinfo(adap, i);
360 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
364 pi->rss_hf = CXGBE_RSS_HF_ALL;
370 * Dump basic information about the adapter.
372 static void print_adapter_info(struct adapter *adap)
375 * Hardware/Firmware/etc. Version/Revision IDs.
377 t4_dump_version_info(adap);
380 static void print_port_info(struct adapter *adap)
384 struct rte_pci_addr *loc = &adap->pdev->addr;
386 for_each_port(adap, i) {
387 const struct port_info *pi = adap2pinfo(adap, i);
390 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
391 bufp += sprintf(bufp, "100M/");
392 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
393 bufp += sprintf(bufp, "1G/");
394 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
395 bufp += sprintf(bufp, "10G/");
396 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
397 bufp += sprintf(bufp, "25G/");
398 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
399 bufp += sprintf(bufp, "40G/");
400 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
401 bufp += sprintf(bufp, "100G/");
404 sprintf(bufp, "BASE-%s",
405 t4_get_port_type_description(
406 (enum fw_port_type)pi->port_type));
409 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
410 loc->domain, loc->bus, loc->devid, loc->function,
411 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
412 (adap->flags & USING_MSIX) ? " MSI-X" :
413 (adap->flags & USING_MSI) ? " MSI" : "");
417 static void configure_pcie_ext_tag(struct adapter *adapter)
420 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
426 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
427 v |= PCI_EXP_DEVCTL_EXT_TAG;
428 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
429 if (is_t6(adapter->params.chip)) {
430 t4_set_reg_field(adapter, A_PCIE_CFG2,
431 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
433 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
434 V_T6_MINTAG(M_T6_MINTAG),
437 t4_set_reg_field(adapter, A_PCIE_CFG2,
438 V_TOTMAXTAG(M_TOTMAXTAG),
440 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
448 * Tweak configuration based on system architecture, etc. Most of these have
449 * defaults assigned to them by Firmware Configuration Files (if we're using
450 * them) but need to be explicitly set if we're using hard-coded
451 * initialization. So these are essentially common tweaks/settings for
452 * Configuration Files and hard-coded initialization ...
454 static int adap_init0_tweaks(struct adapter *adapter)
459 * Fix up various Host-Dependent Parameters like Page Size, Cache
460 * Line Size, etc. The firmware default is for a 4KB Page Size and
461 * 64B Cache Line Size ...
463 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
467 * Keep the chip default offset to deliver Ingress packets into our
468 * DMA buffers to zero
471 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
472 V_PKTSHIFT(rx_dma_offset));
474 t4_set_reg_field(adapter, A_SGE_FLM_CFG,
475 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
476 V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
478 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
479 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
481 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
482 V_IDMAARBROUNDROBIN(1U));
485 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
486 * adds the pseudo header itself.
488 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
489 F_CSUM_HAS_PSEUDO_HDR, 0);
495 * Attempt to initialize the adapter via a Firmware Configuration File.
497 static int adap_init0_config(struct adapter *adapter, int reset)
499 struct fw_caps_config_cmd caps_cmd;
500 unsigned long mtype = 0, maddr = 0;
501 u32 finiver, finicsum, cfcsum;
503 int config_issued = 0;
505 char config_name[20];
508 * Reset device if necessary.
511 ret = t4_fw_reset(adapter, adapter->mbox,
512 F_PIORSTMODE | F_PIORST);
514 dev_warn(adapter, "Firmware reset failed, error %d\n",
520 cfg_addr = t4_flash_cfg_addr(adapter);
523 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
528 strcpy(config_name, "On Flash");
529 mtype = FW_MEMTYPE_CF_FLASH;
533 * Issue a Capability Configuration command to the firmware to get it
534 * to parse the Configuration File. We don't use t4_fw_config_file()
535 * because we want the ability to modify various features after we've
536 * processed the configuration file ...
538 memset(&caps_cmd, 0, sizeof(caps_cmd));
539 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
540 F_FW_CMD_REQUEST | F_FW_CMD_READ);
541 caps_cmd.cfvalid_to_len16 =
542 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
543 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
544 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
546 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
549 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
550 * Configuration File in FLASH), our last gasp effort is to use the
551 * Firmware Configuration File which is embedded in the firmware. A
552 * very few early versions of the firmware didn't have one embedded
553 * but we can ignore those.
555 if (ret == -ENOENT) {
556 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
559 memset(&caps_cmd, 0, sizeof(caps_cmd));
560 caps_cmd.op_to_write =
561 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
562 F_FW_CMD_REQUEST | F_FW_CMD_READ);
563 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
564 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
565 sizeof(caps_cmd), &caps_cmd);
566 strcpy(config_name, "Firmware Default");
573 finiver = be32_to_cpu(caps_cmd.finiver);
574 finicsum = be32_to_cpu(caps_cmd.finicsum);
575 cfcsum = be32_to_cpu(caps_cmd.cfcsum);
576 if (finicsum != cfcsum)
577 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
581 * If we're a pure NIC driver then disable all offloading facilities.
582 * This will allow the firmware to optimize aspects of the hardware
583 * configuration which will result in improved performance.
585 caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER |
586 FW_CAPS_CONFIG_NIC_ETHOFLD));
587 caps_cmd.toecaps = 0;
588 caps_cmd.iscsicaps = 0;
589 caps_cmd.rdmacaps = 0;
590 caps_cmd.fcoecaps = 0;
593 * And now tell the firmware to use the configuration we just loaded.
595 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
596 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
597 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
598 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
601 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
607 * Tweak configuration based on system architecture, etc.
609 ret = adap_init0_tweaks(adapter);
611 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
616 * And finally tell the firmware to initialize itself using the
617 * parameters from the Configuration File.
619 ret = t4_fw_initialize(adapter, adapter->mbox);
621 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
627 * Return successfully and note that we're operating with parameters
628 * not supplied by the driver, rather than from hard-wired
629 * initialization constants buried in the driver.
632 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
633 config_name, finiver, cfcsum);
638 * Something bad happened. Return the error ... (If the "error"
639 * is that there's no Configuration File on the adapter we don't
640 * want to issue a warning since this is fairly common.)
643 if (config_issued && ret != -ENOENT)
644 dev_warn(adapter, "\"%s\" configuration file error %d\n",
647 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
651 static int adap_init0(struct adapter *adap)
655 enum dev_state state;
656 u32 params[7], val[7];
658 int mbox = adap->mbox;
661 * Contact FW, advertising Master capability.
663 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
665 dev_err(adap, "%s: could not connect to FW, error %d\n",
670 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
674 adap->flags |= MASTER_PF;
676 if (state == DEV_STATE_INIT) {
678 * Force halt and reset FW because a previous instance may have
679 * exited abnormally without properly shutting down
681 ret = t4_fw_halt(adap, adap->mbox, reset);
683 dev_err(adap, "Failed to halt. Exit.\n");
687 ret = t4_fw_restart(adap, adap->mbox, reset);
689 dev_err(adap, "Failed to restart. Exit.\n");
692 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
695 t4_get_version_info(adap);
697 ret = t4_get_core_clock(adap, &adap->params.vpd);
699 dev_err(adap, "%s: could not get core clock, error %d\n",
705 * If the firmware is initialized already (and we're not forcing a
706 * master initialization), note that we're living with existing
707 * adapter parameters. Otherwise, it's time to try initializing the
710 if (state == DEV_STATE_INIT) {
711 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
712 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
714 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
716 ret = adap_init0_config(adap, reset);
717 if (ret == -ENOENT) {
719 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
724 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
728 /* Find out what ports are available to us. */
729 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
730 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
731 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
733 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
738 adap->params.nports = hweight32(port_vec);
739 adap->params.portvec = port_vec;
741 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
742 adap->params.nports);
745 * Give the SGE code a chance to pull in anything that it needs ...
746 * Note that this must be called after we retrieve our VPD parameters
747 * in order to know how to convert core ticks to seconds, etc.
749 ret = t4_sge_init(adap);
751 dev_err(adap, "t4_sge_init failed with error %d\n",
757 * Grab some of our basic fundamental operating parameters.
759 #define FW_PARAM_DEV(param) \
760 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
761 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
763 #define FW_PARAM_PFVF(param) \
764 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
765 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
766 V_FW_PARAMS_PARAM_Y(0) | \
767 V_FW_PARAMS_PARAM_Z(0))
769 /* If we're running on newer firmware, let it know that we're
770 * prepared to deal with encapsulated CPL messages. Older
771 * firmware won't understand this and we'll just get
772 * unencapsulated messages ...
774 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
776 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
779 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
780 * capability. Earlier versions of the firmware didn't have the
781 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
782 * permission to use ULPTX MEMWRITE DSGL.
784 if (is_t4(adap->params.chip)) {
785 adap->params.ulptx_memwrite_dsgl = false;
787 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
788 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
790 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
794 * The MTU/MSS Table is initialized by now, so load their values. If
795 * we're initializing the adapter, then we'll make any modifications
796 * we want to the MTU/MSS Table and also initialize the congestion
799 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
800 if (state != DEV_STATE_INIT) {
804 * The default MTU Table contains values 1492 and 1500.
805 * However, for TCP, it's better to have two values which are
806 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
807 * This allows us to have a TCP Data Payload which is a
808 * multiple of 8 regardless of what combination of TCP Options
809 * are in use (always a multiple of 4 bytes) which is
810 * important for performance reasons. For instance, if no
811 * options are in use, then we have a 20-byte IP header and a
812 * 20-byte TCP header. In this case, a 1500-byte MSS would
813 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
814 * which is not a multiple of 8. So using an MSS of 1488 in
815 * this case results in a TCP Data Payload of 1448 bytes which
816 * is a multiple of 8. On the other hand, if 12-byte TCP Time
817 * Stamps have been negotiated, then an MTU of 1500 bytes
818 * results in a TCP Data Payload of 1448 bytes which, as
819 * above, is a multiple of 8 bytes ...
821 for (i = 0; i < NMTUS; i++)
822 if (adap->params.mtus[i] == 1492) {
823 adap->params.mtus[i] = 1488;
827 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
830 t4_init_sge_params(adap);
831 t4_init_tp_params(adap);
832 configure_pcie_ext_tag(adap);
834 adap->params.drv_memwin = MEMWIN_NIC;
835 adap->flags |= FW_OK;
836 dev_debug(adap, "%s: returning zero..\n", __func__);
840 * Something bad happened. If a command timed out or failed with EIO
841 * FW does not operate within its spec or something catastrophic
842 * happened to HW/FW, stop issuing commands.
845 if (ret != -ETIMEDOUT && ret != -EIO)
846 t4_fw_bye(adap, adap->mbox);
851 * t4_os_portmod_changed - handle port module changes
852 * @adap: the adapter associated with the module change
853 * @port_id: the port index whose module status has changed
855 * This is the OS-dependent handler for port module changes. It is
856 * invoked when a port module is removed or inserted for any OS-specific
859 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
861 static const char * const mod_str[] = {
862 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
865 const struct port_info *pi = adap2pinfo(adap, port_id);
867 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
868 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
869 else if (pi->mod_type < ARRAY_SIZE(mod_str))
870 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
871 mod_str[pi->mod_type]);
872 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
873 dev_info(adap, "Port%d: unsupported port module inserted\n",
875 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
876 dev_info(adap, "Port%d: unknown port module inserted\n",
878 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
879 dev_info(adap, "Port%d: transceiver module error\n",
882 dev_info(adap, "Port%d: unknown module type %d inserted\n",
883 pi->port_id, pi->mod_type);
887 * link_start - enable a port
888 * @dev: the port to enable
890 * Performs the MAC and PHY actions needed to enable a port.
892 int link_start(struct port_info *pi)
894 struct adapter *adapter = pi->adapter;
898 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
899 (ETHER_HDR_LEN + ETHER_CRC_LEN);
902 * We do not set address filters and promiscuity here, the stack does
903 * that step explicitly.
905 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
908 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
910 (u8 *)&pi->eth_dev->data->mac_addrs[0],
913 pi->xact_addr_filt = ret;
918 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
922 * Enabling a Virtual Interface can result in an interrupt
923 * during the processing of the VI Enable command and, in some
924 * paths, result in an attempt to issue another command in the
925 * interrupt context. Thus, we disable interrupts during the
926 * course of the VI Enable command ...
928 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
935 * cxgbe_write_rss_conf - flash the RSS configuration for a given port
937 * @rss_hf: Hash configuration to apply
939 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
941 struct adapter *adapter = pi->adapter;
942 const struct sge_eth_rxq *rxq;
947 /* Should never be called before setting up sge eth rx queues */
948 if (!(adapter->flags & FULL_INIT_DONE)) {
949 dev_err(adap, "%s No RXQs available on port %d\n",
950 __func__, pi->port_id);
954 /* Don't allow unsupported hash functions */
955 if (rss_hf & ~CXGBE_RSS_HF_ALL)
958 if (rss_hf & ETH_RSS_IPV4)
959 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
961 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
962 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
964 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
965 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
966 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
968 if (rss_hf & ETH_RSS_IPV6)
969 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
971 if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
972 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
974 if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
975 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
976 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
978 rxq = &adapter->sge.ethrxq[pi->first_qset];
979 rss = rxq[0].rspq.abs_id;
981 /* If Tunnel All Lookup isn't specified in the global RSS
982 * Configuration, then we need to specify a default Ingress
983 * Queue for any ingress packets which aren't hashed. We'll
984 * use our first ingress queue ...
986 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
992 * cxgbe_write_rss - write the RSS table for a given port
994 * @queues: array of queue indices for RSS
996 * Sets up the portion of the HW RSS table for the port's VI to distribute
997 * packets to the Rx queues in @queues.
999 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1003 struct adapter *adapter = pi->adapter;
1004 const struct sge_eth_rxq *rxq;
1006 /* Should never be called before setting up sge eth rx queues */
1007 BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1009 rxq = &adapter->sge.ethrxq[pi->first_qset];
1010 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1014 /* map the queue indices to queue ids */
1015 for (i = 0; i < pi->rss_size; i++, queues++)
1016 rss[i] = rxq[*queues].rspq.abs_id;
1018 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1019 pi->rss_size, rss, pi->rss_size);
1025 * setup_rss - configure RSS
1026 * @adapter: the adapter
1028 * Sets up RSS to distribute packets to multiple receive queues. We
1029 * configure the RSS CPU lookup table to distribute to the number of HW
1030 * receive queues, and the response queue lookup table to narrow that
1031 * down to the response queues actually configured for each port.
1032 * We always configure the RSS mapping for all ports since the mapping
1033 * table has plenty of entries.
1035 int setup_rss(struct port_info *pi)
1038 struct adapter *adapter = pi->adapter;
1040 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1041 __func__, pi->rss_size, pi->n_rx_qsets);
1043 if (!(pi->flags & PORT_RSS_DONE)) {
1044 if (adapter->flags & FULL_INIT_DONE) {
1045 /* Fill default values with equal distribution */
1046 for (j = 0; j < pi->rss_size; j++)
1047 pi->rss[j] = j % pi->n_rx_qsets;
1049 err = cxgbe_write_rss(pi, pi->rss);
1053 err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1056 pi->flags |= PORT_RSS_DONE;
1063 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1065 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1067 /* 0-increment GTS to start the timer and enable interrupts */
1068 t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS),
1069 V_SEINTARM(q->intr_params) |
1070 V_INGRESSQID(q->cntxt_id));
1073 void cxgbe_enable_rx_queues(struct port_info *pi)
1075 struct adapter *adap = pi->adapter;
1076 struct sge *s = &adap->sge;
1079 for (i = 0; i < pi->n_rx_qsets; i++)
1080 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1084 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1085 * @port_type: Firmware Port Type
1086 * @fw_caps: Firmware Port Capabilities
1087 * @speed_caps: Device Info Speed Capabilities
1089 * Translate a Firmware Port Capabilities specification to Device Info
1090 * Speed Capabilities.
1092 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1093 unsigned int fw_caps,
1096 #define SET_SPEED(__speed_name) \
1098 *speed_caps |= ETH_LINK_ ## __speed_name; \
1101 #define FW_CAPS_TO_SPEED(__fw_name) \
1103 if (fw_caps & FW_PORT_CAP_ ## __fw_name) \
1104 SET_SPEED(__fw_name); \
1107 switch (port_type) {
1108 case FW_PORT_TYPE_BT_SGMII:
1109 case FW_PORT_TYPE_BT_XFI:
1110 case FW_PORT_TYPE_BT_XAUI:
1111 FW_CAPS_TO_SPEED(SPEED_100M);
1112 FW_CAPS_TO_SPEED(SPEED_1G);
1113 FW_CAPS_TO_SPEED(SPEED_10G);
1116 case FW_PORT_TYPE_KX4:
1117 case FW_PORT_TYPE_KX:
1118 case FW_PORT_TYPE_FIBER_XFI:
1119 case FW_PORT_TYPE_FIBER_XAUI:
1120 case FW_PORT_TYPE_SFP:
1121 case FW_PORT_TYPE_QSFP_10G:
1122 case FW_PORT_TYPE_QSA:
1123 FW_CAPS_TO_SPEED(SPEED_1G);
1124 FW_CAPS_TO_SPEED(SPEED_10G);
1127 case FW_PORT_TYPE_KR:
1128 SET_SPEED(SPEED_10G);
1131 case FW_PORT_TYPE_BP_AP:
1132 case FW_PORT_TYPE_BP4_AP:
1133 SET_SPEED(SPEED_1G);
1134 SET_SPEED(SPEED_10G);
1137 case FW_PORT_TYPE_BP40_BA:
1138 case FW_PORT_TYPE_QSFP:
1139 SET_SPEED(SPEED_40G);
1142 case FW_PORT_TYPE_CR_QSFP:
1143 case FW_PORT_TYPE_SFP28:
1144 case FW_PORT_TYPE_KR_SFP28:
1145 FW_CAPS_TO_SPEED(SPEED_1G);
1146 FW_CAPS_TO_SPEED(SPEED_10G);
1147 FW_CAPS_TO_SPEED(SPEED_25G);
1150 case FW_PORT_TYPE_CR2_QSFP:
1151 SET_SPEED(SPEED_50G);
1154 case FW_PORT_TYPE_KR4_100G:
1155 case FW_PORT_TYPE_CR4_QSFP:
1156 FW_CAPS_TO_SPEED(SPEED_25G);
1157 FW_CAPS_TO_SPEED(SPEED_40G);
1158 FW_CAPS_TO_SPEED(SPEED_100G);
1165 #undef FW_CAPS_TO_SPEED
1170 * cxgbe_get_speed_caps - Fetch supported speed capabilities
1171 * @pi: Underlying port's info
1172 * @speed_caps: Device Info speed capabilities
1174 * Fetch supported speed capabilities of the underlying port.
1176 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1180 fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.supported,
1183 if (!(pi->link_cfg.supported & FW_PORT_CAP_ANEG))
1184 *speed_caps |= ETH_LINK_SPEED_FIXED;
1188 * cxgb_up - enable the adapter
1189 * @adap: adapter being enabled
1191 * Called when the first port is enabled, this function performs the
1192 * actions necessary to make an adapter operational, such as completing
1193 * the initialization of HW modules, and enabling interrupts.
1195 int cxgbe_up(struct adapter *adap)
1197 enable_rx(adap, &adap->sge.fw_evtq);
1198 t4_sge_tx_monitor_start(adap);
1199 t4_intr_enable(adap);
1200 adap->flags |= FULL_INIT_DONE;
1202 /* TODO: deadman watchdog ?? */
1209 int cxgbe_down(struct port_info *pi)
1211 struct adapter *adapter = pi->adapter;
1214 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false);
1216 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1220 t4_reset_link_config(adapter, pi->port_id);
1225 * Release resources when all the ports have been stopped.
1227 void cxgbe_close(struct adapter *adapter)
1229 struct port_info *pi;
1232 if (adapter->flags & FULL_INIT_DONE) {
1233 t4_intr_disable(adapter);
1234 t4_sge_tx_monitor_stop(adapter);
1235 t4_free_sge_resources(adapter);
1236 for_each_port(adapter, i) {
1237 pi = adap2pinfo(adapter, i);
1239 t4_free_vi(adapter, adapter->mbox,
1240 adapter->pf, 0, pi->viid);
1241 rte_free(pi->eth_dev->data->mac_addrs);
1242 /* Skip first port since it'll be freed by DPDK stack */
1244 rte_free(pi->eth_dev->data->dev_private);
1245 rte_eth_dev_release_port(pi->eth_dev);
1248 adapter->flags &= ~FULL_INIT_DONE;
1251 if (adapter->flags & FW_OK)
1252 t4_fw_bye(adapter, adapter->mbox);
1255 int cxgbe_probe(struct adapter *adapter)
1257 struct port_info *pi;
1263 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1264 chip = t4_get_chip_type(adapter,
1265 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1269 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1270 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1272 adapter->mbox = func;
1275 t4_os_lock_init(&adapter->mbox_lock);
1276 TAILQ_INIT(&adapter->mbox_list);
1278 err = t4_prep_adapter(adapter);
1282 setup_memwin(adapter);
1283 err = adap_init0(adapter);
1285 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1290 if (!is_t4(adapter->params.chip)) {
1292 * The userspace doorbell BAR is split evenly into doorbell
1293 * regions, each associated with an egress queue. If this
1294 * per-queue region is large enough (at least UDBS_SEG_SIZE)
1295 * then it can be used to submit a tx work request with an
1296 * implied doorbell. Enable write combining on the BAR if
1297 * there is room for such work requests.
1299 int s_qpp, qpp, num_seg;
1301 s_qpp = (S_QUEUESPERPAGEPF0 +
1302 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1304 qpp = 1 << ((t4_read_reg(adapter,
1305 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1306 & M_QUEUESPERPAGEPF0);
1307 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1309 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1311 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1312 if (!adapter->bar2) {
1313 dev_err(adapter, "cannot map device bar2 region\n");
1317 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1321 for_each_port(adapter, i) {
1322 const unsigned int numa_node = rte_socket_id();
1323 char name[RTE_ETH_NAME_MAX_LEN];
1324 struct rte_eth_dev *eth_dev;
1326 snprintf(name, sizeof(name), "%s_%d",
1327 adapter->pdev->device.name, i);
1330 /* First port is already allocated by DPDK */
1331 eth_dev = adapter->eth_dev;
1336 * now do all data allocation - for eth_dev structure,
1337 * and internal (private) data for the remaining ports
1340 /* reserve an ethdev entry */
1341 eth_dev = rte_eth_dev_allocate(name);
1345 eth_dev->data->dev_private =
1346 rte_zmalloc_socket(name, sizeof(struct port_info),
1347 RTE_CACHE_LINE_SIZE, numa_node);
1348 if (!eth_dev->data->dev_private)
1352 pi = (struct port_info *)eth_dev->data->dev_private;
1353 adapter->port[i] = pi;
1354 pi->eth_dev = eth_dev;
1355 pi->adapter = adapter;
1356 pi->xact_addr_filt = -1;
1359 pi->eth_dev->device = &adapter->pdev->device;
1360 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1361 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1362 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1364 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1366 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1368 if (!pi->eth_dev->data->mac_addrs) {
1369 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1376 if (adapter->flags & FW_OK) {
1377 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1379 dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1385 cfg_queues(adapter->eth_dev);
1387 print_adapter_info(adapter);
1388 print_port_info(adapter);
1390 err = init_rss(adapter);
1397 for_each_port(adapter, i) {
1398 pi = adap2pinfo(adapter, i);
1400 t4_free_vi(adapter, adapter->mbox, adapter->pf,
1402 /* Skip first port since it'll be de-allocated by DPDK */
1406 if (pi->eth_dev->data->dev_private)
1407 rte_free(pi->eth_dev->data->dev_private);
1408 rte_eth_dev_release_port(pi->eth_dev);
1412 if (adapter->flags & FW_OK)
1413 t4_fw_bye(adapter, adapter->mbox);