1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_atomic.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_tailq.h>
28 #include <rte_alarm.h>
29 #include <rte_ether.h>
30 #include <rte_ethdev_driver.h>
31 #include <rte_ethdev_pci.h>
32 #include <rte_random.h>
34 #include <rte_kvargs.h>
45 * Allocate a chunk of memory. The allocated memory is cleared.
47 void *t4_alloc_mem(size_t size)
49 return rte_zmalloc(NULL, size, 0);
53 * Free memory allocated through t4_alloc_mem().
55 void t4_free_mem(void *addr)
61 * Response queue handler for the FW event queue.
63 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
64 __rte_unused const struct pkt_gl *gl)
66 u8 opcode = ((const struct rss_header *)rsp)->opcode;
68 rsp++; /* skip RSS header */
71 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
73 if (unlikely(opcode == CPL_FW4_MSG &&
74 ((const struct cpl_fw4_msg *)rsp)->type ==
77 opcode = ((const struct rss_header *)rsp)->opcode;
79 if (opcode != CPL_SGE_EGR_UPDATE) {
80 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
86 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
88 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
89 const struct cpl_fw6_msg *msg = (const void *)rsp;
91 t4_handle_fw_rpl(q->adapter, msg->data);
92 } else if (opcode == CPL_ABORT_RPL_RSS) {
93 const struct cpl_abort_rpl_rss *p = (const void *)rsp;
95 hash_del_filter_rpl(q->adapter, p);
96 } else if (opcode == CPL_SET_TCB_RPL) {
97 const struct cpl_set_tcb_rpl *p = (const void *)rsp;
99 filter_rpl(q->adapter, p);
100 } else if (opcode == CPL_ACT_OPEN_RPL) {
101 const struct cpl_act_open_rpl *p = (const void *)rsp;
103 hash_filter_rpl(q->adapter, p);
104 } else if (opcode == CPL_L2T_WRITE_RPL) {
105 const struct cpl_l2t_write_rpl *p = (const void *)rsp;
107 do_l2t_write_rpl(q->adapter, p);
109 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
117 * Setup sge control queues to pass control information.
119 int setup_sge_ctrl_txq(struct adapter *adapter)
121 struct sge *s = &adapter->sge;
124 for_each_port(adapter, i) {
125 char name[RTE_ETH_NAME_MAX_LEN];
126 struct sge_ctrl_txq *q = &s->ctrlq[i];
129 err = t4_sge_alloc_ctrl_txq(adapter, q,
134 dev_err(adapter, "Failed to alloc ctrl txq. Err: %d",
138 snprintf(name, sizeof(name), "cxgbe_ctrl_pool_%d", i);
139 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
142 RTE_MBUF_DEFAULT_BUF_SIZE,
145 dev_err(adapter, "Can't create ctrl pool for port: %d",
153 t4_free_sge_resources(adapter);
158 * cxgbe_poll_for_completion: Poll rxq for completion
160 * @us: microseconds to delay
161 * @cnt: number of times to poll
162 * @c: completion to check for 'done' status
164 * Polls the rxq for reples until completion is done or the count
167 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int us,
168 unsigned int cnt, struct t4_completion *c)
171 unsigned int work_done, budget = 4;
176 for (i = 0; i < cnt; i++) {
177 cxgbe_poll(q, NULL, budget, &work_done);
178 t4_os_lock(&c->lock);
180 t4_os_unlock(&c->lock);
183 t4_os_unlock(&c->lock);
189 int setup_sge_fwevtq(struct adapter *adapter)
191 struct sge *s = &adapter->sge;
195 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
196 msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
201 static int closest_timer(const struct sge *s, int time)
203 unsigned int i, match = 0;
204 int delta, min_delta = INT_MAX;
206 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
207 delta = time - s->timer_val[i];
210 if (delta < min_delta) {
218 static int closest_thres(const struct sge *s, int thres)
220 unsigned int i, match = 0;
221 int delta, min_delta = INT_MAX;
223 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
224 delta = thres - s->counter_val[i];
227 if (delta < min_delta) {
236 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
238 * @us: the hold-off time in us, or 0 to disable timer
239 * @cnt: the hold-off packet count, or 0 to disable counter
241 * Sets an Rx queue's interrupt hold-off time and packet count. At least
242 * one of the two needs to be enabled for the queue to generate interrupts.
244 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
247 struct adapter *adap = q->adapter;
248 unsigned int timer_val;
254 new_idx = closest_thres(&adap->sge, cnt);
255 if (q->desc && q->pktcnt_idx != new_idx) {
256 /* the queue has already been created, update it */
257 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
259 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
260 V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
261 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
266 q->pktcnt_idx = new_idx;
269 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
270 closest_timer(&adap->sge, us);
273 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
275 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
276 V_QINTR_CNT_EN(cnt > 0);
281 * Allocate an active-open TID and set it to the supplied value.
283 int cxgbe_alloc_atid(struct tid_info *t, void *data)
287 t4_os_lock(&t->atid_lock);
289 union aopen_entry *p = t->afree;
291 atid = p - t->atid_tab;
296 t4_os_unlock(&t->atid_lock);
301 * Release an active-open TID.
303 void cxgbe_free_atid(struct tid_info *t, unsigned int atid)
305 union aopen_entry *p = &t->atid_tab[atid];
307 t4_os_lock(&t->atid_lock);
311 t4_os_unlock(&t->atid_lock);
315 * Populate a TID_RELEASE WR. Caller must properly size the skb.
317 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid)
319 struct cpl_tid_release *req;
321 req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *);
322 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
326 * Release a TID and inform HW. If we are unable to allocate the release
327 * message we defer to a work queue.
329 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
330 unsigned short family)
332 struct rte_mbuf *mbuf;
333 struct adapter *adap = container_of(t, struct adapter, tids);
335 WARN_ON(tid >= t->ntids);
337 if (t->tid_tab[tid]) {
338 t->tid_tab[tid] = NULL;
339 rte_atomic32_dec(&t->conns_in_use);
340 if (t->hash_base && tid >= t->hash_base) {
341 if (family == FILTER_TYPE_IPV4)
342 rte_atomic32_dec(&t->hash_tids_in_use);
344 if (family == FILTER_TYPE_IPV4)
345 rte_atomic32_dec(&t->tids_in_use);
349 mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool);
351 mbuf->data_len = sizeof(struct cpl_tid_release);
352 mbuf->pkt_len = mbuf->data_len;
353 mk_tid_release(mbuf, tid);
354 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf);
361 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid,
362 unsigned short family)
364 t->tid_tab[tid] = data;
365 if (t->hash_base && tid >= t->hash_base) {
366 if (family == FILTER_TYPE_IPV4)
367 rte_atomic32_inc(&t->hash_tids_in_use);
369 if (family == FILTER_TYPE_IPV4)
370 rte_atomic32_inc(&t->tids_in_use);
373 rte_atomic32_inc(&t->conns_in_use);
379 static void tid_free(struct tid_info *t)
383 rte_bitmap_free(t->ftid_bmap);
385 if (t->ftid_bmap_array)
386 t4_os_free(t->ftid_bmap_array);
388 t4_os_free(t->tid_tab);
391 memset(t, 0, sizeof(struct tid_info));
395 * Allocate and initialize the TID tables. Returns 0 on success.
397 static int tid_init(struct tid_info *t)
400 unsigned int ftid_bmap_size;
401 unsigned int natids = t->natids;
402 unsigned int max_ftids = t->nftids;
404 ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
405 size = t->ntids * sizeof(*t->tid_tab) +
406 max_ftids * sizeof(*t->ftid_tab) +
407 natids * sizeof(*t->atid_tab);
409 t->tid_tab = t4_os_alloc(size);
413 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
414 t->ftid_tab = (struct filter_entry *)&t->tid_tab[t->natids];
415 t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
416 if (!t->ftid_bmap_array) {
421 t4_os_lock_init(&t->atid_lock);
422 t4_os_lock_init(&t->ftid_lock);
426 rte_atomic32_init(&t->tids_in_use);
427 rte_atomic32_set(&t->tids_in_use, 0);
428 rte_atomic32_init(&t->conns_in_use);
429 rte_atomic32_set(&t->conns_in_use, 0);
431 /* Setup the free list for atid_tab and clear the stid bitmap. */
434 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
435 t->afree = t->atid_tab;
438 t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
448 static inline bool is_x_1g_port(const struct link_config *lc)
450 return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
453 static inline bool is_x_10g_port(const struct link_config *lc)
455 unsigned int speeds, high_speeds;
457 speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
458 high_speeds = speeds &
459 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
461 return high_speeds != 0;
464 inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
465 unsigned int us, unsigned int cnt,
466 unsigned int size, unsigned int iqe_size)
469 cxgb4_set_rspq_intr_params(q, us, cnt);
470 q->iqe_len = iqe_size;
474 int cfg_queue_count(struct rte_eth_dev *eth_dev)
476 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
477 struct adapter *adap = pi->adapter;
478 struct sge *s = &adap->sge;
479 unsigned int max_queues = s->max_ethqsets / adap->params.nports;
481 if ((eth_dev->data->nb_rx_queues < 1) ||
482 (eth_dev->data->nb_tx_queues < 1))
485 if ((eth_dev->data->nb_rx_queues > max_queues) ||
486 (eth_dev->data->nb_tx_queues > max_queues))
489 if (eth_dev->data->nb_rx_queues > pi->rss_size)
492 /* We must configure RSS, since config has changed*/
493 pi->flags &= ~PORT_RSS_DONE;
495 pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
496 pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
501 void cfg_queues(struct rte_eth_dev *eth_dev)
503 struct rte_config *config = rte_eal_get_configuration();
504 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
505 struct adapter *adap = pi->adapter;
506 struct sge *s = &adap->sge;
507 unsigned int i, nb_ports = 0, qidx = 0;
508 unsigned int q_per_port = 0;
510 if (!(adap->flags & CFG_QUEUES)) {
511 for_each_port(adap, i) {
512 struct port_info *tpi = adap2pinfo(adap, i);
514 nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
515 is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
519 * We default up to # of cores queues per 1G/10G port.
522 q_per_port = (s->max_ethqsets -
523 (adap->params.nports - nb_ports)) /
526 if (q_per_port > config->lcore_count)
527 q_per_port = config->lcore_count;
529 for_each_port(adap, i) {
530 struct port_info *pi = adap2pinfo(adap, i);
532 pi->first_qset = qidx;
534 /* Initially n_rx_qsets == n_tx_qsets */
535 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
536 is_x_1g_port(&pi->link_cfg)) ?
538 pi->n_tx_qsets = pi->n_rx_qsets;
540 if (pi->n_rx_qsets > pi->rss_size)
541 pi->n_rx_qsets = pi->rss_size;
543 qidx += pi->n_rx_qsets;
546 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
547 struct sge_eth_rxq *r = &s->ethrxq[i];
549 init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
551 r->fl.size = (r->usembufs ? 1024 : 72);
554 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
555 s->ethtxq[i].q.size = 1024;
557 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
558 adap->flags |= CFG_QUEUES;
562 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
564 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
568 void cxgbe_stats_reset(struct port_info *pi)
570 t4_clr_port_stats(pi->adapter, pi->tx_chan);
573 static void setup_memwin(struct adapter *adap)
577 /* For T5, only relative offset inside the PCIe BAR is passed */
578 mem_win0_base = MEMWIN0_BASE;
581 * Set up memory window for accessing adapter memory ranges. (Read
582 * back MA register to ensure that changes propagate before we attempt
583 * to use the new values.)
586 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
588 mem_win0_base | V_BIR(0) |
589 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
591 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
595 int init_rss(struct adapter *adap)
602 err = t4_init_rss_mode(adap, adap->mbox);
607 for_each_port(adap, i) {
608 struct port_info *pi = adap2pinfo(adap, i);
610 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
614 pi->rss_hf = CXGBE_RSS_HF_ALL;
620 * Dump basic information about the adapter.
622 void print_adapter_info(struct adapter *adap)
625 * Hardware/Firmware/etc. Version/Revision IDs.
627 t4_dump_version_info(adap);
630 void print_port_info(struct adapter *adap)
634 struct rte_pci_addr *loc = &adap->pdev->addr;
636 for_each_port(adap, i) {
637 const struct port_info *pi = adap2pinfo(adap, i);
640 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
641 bufp += sprintf(bufp, "100M/");
642 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
643 bufp += sprintf(bufp, "1G/");
644 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
645 bufp += sprintf(bufp, "10G/");
646 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
647 bufp += sprintf(bufp, "25G/");
648 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
649 bufp += sprintf(bufp, "40G/");
650 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
651 bufp += sprintf(bufp, "50G/");
652 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
653 bufp += sprintf(bufp, "100G/");
656 sprintf(bufp, "BASE-%s",
657 t4_get_port_type_description(
658 (enum fw_port_type)pi->port_type));
661 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
662 loc->domain, loc->bus, loc->devid, loc->function,
663 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
664 (adap->flags & USING_MSIX) ? " MSI-X" :
665 (adap->flags & USING_MSI) ? " MSI" : "");
670 check_devargs_handler(__rte_unused const char *key, const char *value,
671 __rte_unused void *opaque)
673 if (strcmp(value, "1"))
679 int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key)
681 struct rte_kvargs *kvlist;
686 kvlist = rte_kvargs_parse(devargs->args, NULL);
690 if (!rte_kvargs_count(kvlist, key)) {
691 rte_kvargs_free(kvlist);
695 if (rte_kvargs_process(kvlist, key,
696 check_devargs_handler, NULL) < 0) {
697 rte_kvargs_free(kvlist);
700 rte_kvargs_free(kvlist);
705 static void configure_vlan_types(struct adapter *adapter)
707 struct rte_pci_device *pdev = adapter->pdev;
710 for_each_port(adapter, i) {
711 /* OVLAN Type 0x88a8 */
712 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
713 V_OVLAN_MASK(M_OVLAN_MASK) |
714 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
715 V_OVLAN_MASK(M_OVLAN_MASK) |
716 V_OVLAN_ETYPE(0x88a8));
717 /* OVLAN Type 0x9100 */
718 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
719 V_OVLAN_MASK(M_OVLAN_MASK) |
720 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
721 V_OVLAN_MASK(M_OVLAN_MASK) |
722 V_OVLAN_ETYPE(0x9100));
723 /* OVLAN Type 0x8100 */
724 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
725 V_OVLAN_MASK(M_OVLAN_MASK) |
726 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
727 V_OVLAN_MASK(M_OVLAN_MASK) |
728 V_OVLAN_ETYPE(0x8100));
731 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
732 V_IVLAN_ETYPE(M_IVLAN_ETYPE),
733 V_IVLAN_ETYPE(0x8100));
735 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
736 F_OVLAN_EN0 | F_OVLAN_EN1 |
737 F_OVLAN_EN2 | F_IVLAN_EN,
738 F_OVLAN_EN0 | F_OVLAN_EN1 |
739 F_OVLAN_EN2 | F_IVLAN_EN);
742 if (cxgbe_get_devargs(pdev->device.devargs, CXGBE_DEVARG_KEEP_OVLAN))
743 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
744 V_RM_OVLAN(1), V_RM_OVLAN(0));
747 static void configure_pcie_ext_tag(struct adapter *adapter)
750 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
756 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
757 v |= PCI_EXP_DEVCTL_EXT_TAG;
758 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
759 if (is_t6(adapter->params.chip)) {
760 t4_set_reg_field(adapter, A_PCIE_CFG2,
761 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
763 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
764 V_T6_MINTAG(M_T6_MINTAG),
767 t4_set_reg_field(adapter, A_PCIE_CFG2,
768 V_TOTMAXTAG(M_TOTMAXTAG),
770 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
777 /* Figure out how many Queue Sets we can support */
778 void configure_max_ethqsets(struct adapter *adapter)
780 unsigned int ethqsets;
783 * We need to reserve an Ingress Queue for the Asynchronous Firmware
786 * For each Queue Set, we'll need the ability to allocate two Egress
787 * Contexts -- one for the Ingress Queue Free List and one for the TX
790 if (is_pf4(adapter)) {
791 struct pf_resources *pfres = &adapter->params.pfres;
793 ethqsets = pfres->niqflint - 1;
794 if (pfres->neq < ethqsets * 2)
795 ethqsets = pfres->neq / 2;
797 struct vf_resources *vfres = &adapter->params.vfres;
799 ethqsets = vfres->niqflint - 1;
800 if (vfres->nethctrl != ethqsets)
801 ethqsets = min(vfres->nethctrl, ethqsets);
802 if (vfres->neq < ethqsets * 2)
803 ethqsets = vfres->neq / 2;
806 if (ethqsets > MAX_ETH_QSETS)
807 ethqsets = MAX_ETH_QSETS;
808 adapter->sge.max_ethqsets = ethqsets;
812 * Tweak configuration based on system architecture, etc. Most of these have
813 * defaults assigned to them by Firmware Configuration Files (if we're using
814 * them) but need to be explicitly set if we're using hard-coded
815 * initialization. So these are essentially common tweaks/settings for
816 * Configuration Files and hard-coded initialization ...
818 static int adap_init0_tweaks(struct adapter *adapter)
823 * Fix up various Host-Dependent Parameters like Page Size, Cache
824 * Line Size, etc. The firmware default is for a 4KB Page Size and
825 * 64B Cache Line Size ...
827 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
831 * Keep the chip default offset to deliver Ingress packets into our
832 * DMA buffers to zero
835 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
836 V_PKTSHIFT(rx_dma_offset));
838 t4_set_reg_field(adapter, A_SGE_FLM_CFG,
839 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
840 V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
842 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
843 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
845 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
846 V_IDMAARBROUNDROBIN(1U));
849 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
850 * adds the pseudo header itself.
852 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
853 F_CSUM_HAS_PSEUDO_HDR, 0);
859 * Attempt to initialize the adapter via a Firmware Configuration File.
861 static int adap_init0_config(struct adapter *adapter, int reset)
863 struct fw_caps_config_cmd caps_cmd;
864 unsigned long mtype = 0, maddr = 0;
865 u32 finiver, finicsum, cfcsum;
867 int config_issued = 0;
869 char config_name[20];
872 * Reset device if necessary.
875 ret = t4_fw_reset(adapter, adapter->mbox,
876 F_PIORSTMODE | F_PIORST);
878 dev_warn(adapter, "Firmware reset failed, error %d\n",
884 cfg_addr = t4_flash_cfg_addr(adapter);
887 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
892 strcpy(config_name, "On Flash");
893 mtype = FW_MEMTYPE_CF_FLASH;
897 * Issue a Capability Configuration command to the firmware to get it
898 * to parse the Configuration File. We don't use t4_fw_config_file()
899 * because we want the ability to modify various features after we've
900 * processed the configuration file ...
902 memset(&caps_cmd, 0, sizeof(caps_cmd));
903 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
904 F_FW_CMD_REQUEST | F_FW_CMD_READ);
905 caps_cmd.cfvalid_to_len16 =
906 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
907 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
908 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
910 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
913 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
914 * Configuration File in FLASH), our last gasp effort is to use the
915 * Firmware Configuration File which is embedded in the firmware. A
916 * very few early versions of the firmware didn't have one embedded
917 * but we can ignore those.
919 if (ret == -ENOENT) {
920 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
923 memset(&caps_cmd, 0, sizeof(caps_cmd));
924 caps_cmd.op_to_write =
925 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
926 F_FW_CMD_REQUEST | F_FW_CMD_READ);
927 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
928 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
929 sizeof(caps_cmd), &caps_cmd);
930 strcpy(config_name, "Firmware Default");
937 finiver = be32_to_cpu(caps_cmd.finiver);
938 finicsum = be32_to_cpu(caps_cmd.finicsum);
939 cfcsum = be32_to_cpu(caps_cmd.cfcsum);
940 if (finicsum != cfcsum)
941 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
945 * If we're a pure NIC driver then disable all offloading facilities.
946 * This will allow the firmware to optimize aspects of the hardware
947 * configuration which will result in improved performance.
949 caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD);
950 caps_cmd.toecaps = 0;
951 caps_cmd.iscsicaps = 0;
952 caps_cmd.rdmacaps = 0;
953 caps_cmd.fcoecaps = 0;
956 * And now tell the firmware to use the configuration we just loaded.
958 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
959 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
960 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
961 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
964 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
970 * Tweak configuration based on system architecture, etc.
972 ret = adap_init0_tweaks(adapter);
974 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
979 * And finally tell the firmware to initialize itself using the
980 * parameters from the Configuration File.
982 ret = t4_fw_initialize(adapter, adapter->mbox);
984 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
990 * Return successfully and note that we're operating with parameters
991 * not supplied by the driver, rather than from hard-wired
992 * initialization constants buried in the driver.
995 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
996 config_name, finiver, cfcsum);
1001 * Something bad happened. Return the error ... (If the "error"
1002 * is that there's no Configuration File on the adapter we don't
1003 * want to issue a warning since this is fairly common.)
1006 if (config_issued && ret != -ENOENT)
1007 dev_warn(adapter, "\"%s\" configuration file error %d\n",
1010 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
1014 static int adap_init0(struct adapter *adap)
1016 struct fw_caps_config_cmd caps_cmd;
1019 enum dev_state state;
1020 u32 params[7], val[7];
1022 int mbox = adap->mbox;
1025 * Contact FW, advertising Master capability.
1027 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
1029 dev_err(adap, "%s: could not connect to FW, error %d\n",
1034 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
1038 adap->flags |= MASTER_PF;
1040 if (state == DEV_STATE_INIT) {
1042 * Force halt and reset FW because a previous instance may have
1043 * exited abnormally without properly shutting down
1045 ret = t4_fw_halt(adap, adap->mbox, reset);
1047 dev_err(adap, "Failed to halt. Exit.\n");
1051 ret = t4_fw_restart(adap, adap->mbox, reset);
1053 dev_err(adap, "Failed to restart. Exit.\n");
1056 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
1059 t4_get_version_info(adap);
1061 ret = t4_get_core_clock(adap, &adap->params.vpd);
1063 dev_err(adap, "%s: could not get core clock, error %d\n",
1069 * If the firmware is initialized already (and we're not forcing a
1070 * master initialization), note that we're living with existing
1071 * adapter parameters. Otherwise, it's time to try initializing the
1074 if (state == DEV_STATE_INIT) {
1075 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
1076 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
1078 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
1080 ret = adap_init0_config(adap, reset);
1081 if (ret == -ENOENT) {
1083 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
1088 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
1092 /* Now that we've successfully configured and initialized the adapter
1093 * (or found it already initialized), we can ask the Firmware what
1094 * resources it has provisioned for us.
1096 ret = t4_get_pfres(adap);
1098 dev_err(adap->pdev_dev,
1099 "Unable to retrieve resource provisioning info\n");
1103 /* Find out what ports are available to us. */
1104 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1105 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
1106 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
1108 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
1113 adap->params.nports = hweight32(port_vec);
1114 adap->params.portvec = port_vec;
1116 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
1117 adap->params.nports);
1120 * Give the SGE code a chance to pull in anything that it needs ...
1121 * Note that this must be called after we retrieve our VPD parameters
1122 * in order to know how to convert core ticks to seconds, etc.
1124 ret = t4_sge_init(adap);
1126 dev_err(adap, "t4_sge_init failed with error %d\n",
1132 * Grab some of our basic fundamental operating parameters.
1134 #define FW_PARAM_DEV(param) \
1135 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
1136 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
1138 #define FW_PARAM_PFVF(param) \
1139 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
1140 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \
1141 V_FW_PARAMS_PARAM_Y(0) | \
1142 V_FW_PARAMS_PARAM_Z(0))
1144 params[0] = FW_PARAM_PFVF(L2T_START);
1145 params[1] = FW_PARAM_PFVF(L2T_END);
1146 params[2] = FW_PARAM_PFVF(FILTER_START);
1147 params[3] = FW_PARAM_PFVF(FILTER_END);
1148 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val);
1151 adap->l2t_start = val[0];
1152 adap->l2t_end = val[1];
1153 adap->tids.ftid_base = val[2];
1154 adap->tids.nftids = val[3] - val[2] + 1;
1156 params[0] = FW_PARAM_PFVF(CLIP_START);
1157 params[1] = FW_PARAM_PFVF(CLIP_END);
1158 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
1161 adap->clipt_start = val[0];
1162 adap->clipt_end = val[1];
1165 * Get device capabilities so we can determine what resources we need
1168 memset(&caps_cmd, 0, sizeof(caps_cmd));
1169 caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1170 F_FW_CMD_REQUEST | F_FW_CMD_READ);
1171 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
1172 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
1177 if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) &&
1178 is_t6(adap->params.chip)) {
1179 if (init_hash_filter(adap) < 0)
1183 /* query tid-related parameters */
1184 params[0] = FW_PARAM_DEV(NTID);
1185 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
1189 adap->tids.ntids = val[0];
1190 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
1192 /* If we're running on newer firmware, let it know that we're
1193 * prepared to deal with encapsulated CPL messages. Older
1194 * firmware won't understand this and we'll just get
1195 * unencapsulated messages ...
1197 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
1199 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1202 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
1203 * capability. Earlier versions of the firmware didn't have the
1204 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
1205 * permission to use ULPTX MEMWRITE DSGL.
1207 if (is_t4(adap->params.chip)) {
1208 adap->params.ulptx_memwrite_dsgl = false;
1210 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
1211 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1213 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
1217 * The MTU/MSS Table is initialized by now, so load their values. If
1218 * we're initializing the adapter, then we'll make any modifications
1219 * we want to the MTU/MSS Table and also initialize the congestion
1222 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
1223 if (state != DEV_STATE_INIT) {
1227 * The default MTU Table contains values 1492 and 1500.
1228 * However, for TCP, it's better to have two values which are
1229 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
1230 * This allows us to have a TCP Data Payload which is a
1231 * multiple of 8 regardless of what combination of TCP Options
1232 * are in use (always a multiple of 4 bytes) which is
1233 * important for performance reasons. For instance, if no
1234 * options are in use, then we have a 20-byte IP header and a
1235 * 20-byte TCP header. In this case, a 1500-byte MSS would
1236 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
1237 * which is not a multiple of 8. So using an MSS of 1488 in
1238 * this case results in a TCP Data Payload of 1448 bytes which
1239 * is a multiple of 8. On the other hand, if 12-byte TCP Time
1240 * Stamps have been negotiated, then an MTU of 1500 bytes
1241 * results in a TCP Data Payload of 1448 bytes which, as
1242 * above, is a multiple of 8 bytes ...
1244 for (i = 0; i < NMTUS; i++)
1245 if (adap->params.mtus[i] == 1492) {
1246 adap->params.mtus[i] = 1488;
1250 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
1251 adap->params.b_wnd);
1253 t4_init_sge_params(adap);
1254 t4_init_tp_params(adap);
1255 configure_pcie_ext_tag(adap);
1256 configure_vlan_types(adap);
1257 configure_max_ethqsets(adap);
1259 adap->params.drv_memwin = MEMWIN_NIC;
1260 adap->flags |= FW_OK;
1261 dev_debug(adap, "%s: returning zero..\n", __func__);
1265 * Something bad happened. If a command timed out or failed with EIO
1266 * FW does not operate within its spec or something catastrophic
1267 * happened to HW/FW, stop issuing commands.
1270 if (ret != -ETIMEDOUT && ret != -EIO)
1271 t4_fw_bye(adap, adap->mbox);
1276 * t4_os_portmod_changed - handle port module changes
1277 * @adap: the adapter associated with the module change
1278 * @port_id: the port index whose module status has changed
1280 * This is the OS-dependent handler for port module changes. It is
1281 * invoked when a port module is removed or inserted for any OS-specific
1284 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1286 static const char * const mod_str[] = {
1287 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1290 const struct port_info *pi = adap2pinfo(adap, port_id);
1292 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
1293 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1294 else if (pi->mod_type < ARRAY_SIZE(mod_str))
1295 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1296 mod_str[pi->mod_type]);
1297 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1298 dev_info(adap, "Port%d: unsupported port module inserted\n",
1300 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1301 dev_info(adap, "Port%d: unknown port module inserted\n",
1303 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
1304 dev_info(adap, "Port%d: transceiver module error\n",
1307 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1308 pi->port_id, pi->mod_type);
1311 inline bool force_linkup(struct adapter *adap)
1313 struct rte_pci_device *pdev = adap->pdev;
1316 return false; /* force_linkup not required for pf driver*/
1317 if (!cxgbe_get_devargs(pdev->device.devargs,
1318 CXGBE_DEVARG_FORCE_LINK_UP))
1324 * link_start - enable a port
1325 * @dev: the port to enable
1327 * Performs the MAC and PHY actions needed to enable a port.
1329 int link_start(struct port_info *pi)
1331 struct adapter *adapter = pi->adapter;
1335 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1336 (ETHER_HDR_LEN + ETHER_CRC_LEN);
1339 * We do not set address filters and promiscuity here, the stack does
1340 * that step explicitly.
1342 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1,
1345 ret = t4_change_mac(adapter, adapter->mbox, pi->viid,
1347 (u8 *)&pi->eth_dev->data->mac_addrs[0],
1350 pi->xact_addr_filt = ret;
1354 if (ret == 0 && is_pf4(adapter))
1355 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
1359 * Enabling a Virtual Interface can result in an interrupt
1360 * during the processing of the VI Enable command and, in some
1361 * paths, result in an attempt to issue another command in the
1362 * interrupt context. Thus, we disable interrupts during the
1363 * course of the VI Enable command ...
1365 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1369 if (ret == 0 && force_linkup(adapter))
1370 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
1375 * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1377 * @rss_hf: Hash configuration to apply
1379 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1381 struct adapter *adapter = pi->adapter;
1382 const struct sge_eth_rxq *rxq;
1387 /* Should never be called before setting up sge eth rx queues */
1388 if (!(adapter->flags & FULL_INIT_DONE)) {
1389 dev_err(adap, "%s No RXQs available on port %d\n",
1390 __func__, pi->port_id);
1394 /* Don't allow unsupported hash functions */
1395 if (rss_hf & ~CXGBE_RSS_HF_ALL)
1398 if (rss_hf & CXGBE_RSS_HF_IPV4_MASK)
1399 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1401 if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1402 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1404 if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1405 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1406 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1408 if (rss_hf & CXGBE_RSS_HF_IPV6_MASK)
1409 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1411 if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK)
1412 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1413 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1415 if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK)
1416 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1417 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1418 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1420 rxq = &adapter->sge.ethrxq[pi->first_qset];
1421 rss = rxq[0].rspq.abs_id;
1423 /* If Tunnel All Lookup isn't specified in the global RSS
1424 * Configuration, then we need to specify a default Ingress
1425 * Queue for any ingress packets which aren't hashed. We'll
1426 * use our first ingress queue ...
1428 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1434 * cxgbe_write_rss - write the RSS table for a given port
1436 * @queues: array of queue indices for RSS
1438 * Sets up the portion of the HW RSS table for the port's VI to distribute
1439 * packets to the Rx queues in @queues.
1441 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1445 struct adapter *adapter = pi->adapter;
1446 const struct sge_eth_rxq *rxq;
1448 /* Should never be called before setting up sge eth rx queues */
1449 BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1451 rxq = &adapter->sge.ethrxq[pi->first_qset];
1452 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1456 /* map the queue indices to queue ids */
1457 for (i = 0; i < pi->rss_size; i++, queues++)
1458 rss[i] = rxq[*queues].rspq.abs_id;
1460 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1461 pi->rss_size, rss, pi->rss_size);
1467 * setup_rss - configure RSS
1468 * @adapter: the adapter
1470 * Sets up RSS to distribute packets to multiple receive queues. We
1471 * configure the RSS CPU lookup table to distribute to the number of HW
1472 * receive queues, and the response queue lookup table to narrow that
1473 * down to the response queues actually configured for each port.
1474 * We always configure the RSS mapping for all ports since the mapping
1475 * table has plenty of entries.
1477 int setup_rss(struct port_info *pi)
1480 struct adapter *adapter = pi->adapter;
1482 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1483 __func__, pi->rss_size, pi->n_rx_qsets);
1485 if (!(pi->flags & PORT_RSS_DONE)) {
1486 if (adapter->flags & FULL_INIT_DONE) {
1487 /* Fill default values with equal distribution */
1488 for (j = 0; j < pi->rss_size; j++)
1489 pi->rss[j] = j % pi->n_rx_qsets;
1491 err = cxgbe_write_rss(pi, pi->rss);
1495 err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1498 pi->flags |= PORT_RSS_DONE;
1505 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1507 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1509 /* 0-increment GTS to start the timer and enable interrupts */
1510 t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1511 T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1512 V_SEINTARM(q->intr_params) |
1513 V_INGRESSQID(q->cntxt_id));
1516 void cxgbe_enable_rx_queues(struct port_info *pi)
1518 struct adapter *adap = pi->adapter;
1519 struct sge *s = &adap->sge;
1522 for (i = 0; i < pi->n_rx_qsets; i++)
1523 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1527 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1528 * @port_type: Firmware Port Type
1529 * @fw_caps: Firmware Port Capabilities
1530 * @speed_caps: Device Info Speed Capabilities
1532 * Translate a Firmware Port Capabilities specification to Device Info
1533 * Speed Capabilities.
1535 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1536 unsigned int fw_caps,
1539 #define SET_SPEED(__speed_name) \
1541 *speed_caps |= ETH_LINK_ ## __speed_name; \
1544 #define FW_CAPS_TO_SPEED(__fw_name) \
1546 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1547 SET_SPEED(__fw_name); \
1550 switch (port_type) {
1551 case FW_PORT_TYPE_BT_SGMII:
1552 case FW_PORT_TYPE_BT_XFI:
1553 case FW_PORT_TYPE_BT_XAUI:
1554 FW_CAPS_TO_SPEED(SPEED_100M);
1555 FW_CAPS_TO_SPEED(SPEED_1G);
1556 FW_CAPS_TO_SPEED(SPEED_10G);
1559 case FW_PORT_TYPE_KX4:
1560 case FW_PORT_TYPE_KX:
1561 case FW_PORT_TYPE_FIBER_XFI:
1562 case FW_PORT_TYPE_FIBER_XAUI:
1563 case FW_PORT_TYPE_SFP:
1564 case FW_PORT_TYPE_QSFP_10G:
1565 case FW_PORT_TYPE_QSA:
1566 FW_CAPS_TO_SPEED(SPEED_1G);
1567 FW_CAPS_TO_SPEED(SPEED_10G);
1570 case FW_PORT_TYPE_KR:
1571 SET_SPEED(SPEED_10G);
1574 case FW_PORT_TYPE_BP_AP:
1575 case FW_PORT_TYPE_BP4_AP:
1576 SET_SPEED(SPEED_1G);
1577 SET_SPEED(SPEED_10G);
1580 case FW_PORT_TYPE_BP40_BA:
1581 case FW_PORT_TYPE_QSFP:
1582 SET_SPEED(SPEED_40G);
1585 case FW_PORT_TYPE_CR_QSFP:
1586 case FW_PORT_TYPE_SFP28:
1587 case FW_PORT_TYPE_KR_SFP28:
1588 FW_CAPS_TO_SPEED(SPEED_1G);
1589 FW_CAPS_TO_SPEED(SPEED_10G);
1590 FW_CAPS_TO_SPEED(SPEED_25G);
1593 case FW_PORT_TYPE_CR2_QSFP:
1594 SET_SPEED(SPEED_50G);
1597 case FW_PORT_TYPE_KR4_100G:
1598 case FW_PORT_TYPE_CR4_QSFP:
1599 FW_CAPS_TO_SPEED(SPEED_25G);
1600 FW_CAPS_TO_SPEED(SPEED_40G);
1601 FW_CAPS_TO_SPEED(SPEED_50G);
1602 FW_CAPS_TO_SPEED(SPEED_100G);
1609 #undef FW_CAPS_TO_SPEED
1614 * cxgbe_get_speed_caps - Fetch supported speed capabilities
1615 * @pi: Underlying port's info
1616 * @speed_caps: Device Info speed capabilities
1618 * Fetch supported speed capabilities of the underlying port.
1620 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1624 fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1627 if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1628 *speed_caps |= ETH_LINK_SPEED_FIXED;
1632 * cxgbe_set_link_status - Set device link up or down.
1633 * @pi: Underlying port's info
1634 * @status: 0 - down, 1 - up
1636 * Set the device link up or down.
1638 int cxgbe_set_link_status(struct port_info *pi, bool status)
1640 struct adapter *adapter = pi->adapter;
1643 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, status, status);
1645 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1650 t4_reset_link_config(adapter, pi->pidx);
1656 * cxgb_up - enable the adapter
1657 * @adap: adapter being enabled
1659 * Called when the first port is enabled, this function performs the
1660 * actions necessary to make an adapter operational, such as completing
1661 * the initialization of HW modules, and enabling interrupts.
1663 int cxgbe_up(struct adapter *adap)
1665 enable_rx(adap, &adap->sge.fw_evtq);
1666 t4_sge_tx_monitor_start(adap);
1668 t4_intr_enable(adap);
1669 adap->flags |= FULL_INIT_DONE;
1671 /* TODO: deadman watchdog ?? */
1678 int cxgbe_down(struct port_info *pi)
1680 return cxgbe_set_link_status(pi, false);
1684 * Release resources when all the ports have been stopped.
1686 void cxgbe_close(struct adapter *adapter)
1688 struct port_info *pi;
1691 if (adapter->flags & FULL_INIT_DONE) {
1692 tid_free(&adapter->tids);
1693 t4_cleanup_mpstcam(adapter);
1694 t4_cleanup_clip_tbl(adapter);
1695 t4_cleanup_l2t(adapter);
1696 if (is_pf4(adapter))
1697 t4_intr_disable(adapter);
1698 t4_sge_tx_monitor_stop(adapter);
1699 t4_free_sge_resources(adapter);
1700 for_each_port(adapter, i) {
1701 pi = adap2pinfo(adapter, i);
1703 t4_free_vi(adapter, adapter->mbox,
1704 adapter->pf, 0, pi->viid);
1705 rte_free(pi->eth_dev->data->mac_addrs);
1706 /* Skip first port since it'll be freed by DPDK stack */
1708 rte_free(pi->eth_dev->data->dev_private);
1709 rte_eth_dev_release_port(pi->eth_dev);
1712 adapter->flags &= ~FULL_INIT_DONE;
1715 if (is_pf4(adapter) && (adapter->flags & FW_OK))
1716 t4_fw_bye(adapter, adapter->mbox);
1719 int cxgbe_probe(struct adapter *adapter)
1721 struct port_info *pi;
1727 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1728 chip = t4_get_chip_type(adapter,
1729 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1733 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1734 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1736 adapter->mbox = func;
1739 t4_os_lock_init(&adapter->mbox_lock);
1740 TAILQ_INIT(&adapter->mbox_list);
1741 t4_os_lock_init(&adapter->win0_lock);
1743 err = t4_prep_adapter(adapter);
1747 setup_memwin(adapter);
1748 err = adap_init0(adapter);
1750 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1755 if (!is_t4(adapter->params.chip)) {
1757 * The userspace doorbell BAR is split evenly into doorbell
1758 * regions, each associated with an egress queue. If this
1759 * per-queue region is large enough (at least UDBS_SEG_SIZE)
1760 * then it can be used to submit a tx work request with an
1761 * implied doorbell. Enable write combining on the BAR if
1762 * there is room for such work requests.
1764 int s_qpp, qpp, num_seg;
1766 s_qpp = (S_QUEUESPERPAGEPF0 +
1767 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1769 qpp = 1 << ((t4_read_reg(adapter,
1770 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1771 & M_QUEUESPERPAGEPF0);
1772 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1774 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1776 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1777 if (!adapter->bar2) {
1778 dev_err(adapter, "cannot map device bar2 region\n");
1782 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1786 for_each_port(adapter, i) {
1787 const unsigned int numa_node = rte_socket_id();
1788 char name[RTE_ETH_NAME_MAX_LEN];
1789 struct rte_eth_dev *eth_dev;
1791 snprintf(name, sizeof(name), "%s_%d",
1792 adapter->pdev->device.name, i);
1795 /* First port is already allocated by DPDK */
1796 eth_dev = adapter->eth_dev;
1801 * now do all data allocation - for eth_dev structure,
1802 * and internal (private) data for the remaining ports
1805 /* reserve an ethdev entry */
1806 eth_dev = rte_eth_dev_allocate(name);
1810 eth_dev->data->dev_private =
1811 rte_zmalloc_socket(name, sizeof(struct port_info),
1812 RTE_CACHE_LINE_SIZE, numa_node);
1813 if (!eth_dev->data->dev_private)
1817 pi = (struct port_info *)eth_dev->data->dev_private;
1818 adapter->port[i] = pi;
1819 pi->eth_dev = eth_dev;
1820 pi->adapter = adapter;
1821 pi->xact_addr_filt = -1;
1825 pi->eth_dev->device = &adapter->pdev->device;
1826 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1827 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1828 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1830 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1832 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1834 if (!pi->eth_dev->data->mac_addrs) {
1835 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1842 /* First port will be notified by upper layer */
1843 rte_eth_dev_probing_finish(eth_dev);
1847 if (adapter->flags & FW_OK) {
1848 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1850 dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1856 cfg_queues(adapter->eth_dev);
1858 print_adapter_info(adapter);
1859 print_port_info(adapter);
1861 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
1862 adapter->clipt_end);
1863 if (!adapter->clipt) {
1864 /* We tolerate a lack of clip_table, giving up some
1867 dev_warn(adapter, "could not allocate CLIP. Continuing\n");
1870 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
1871 if (!adapter->l2t) {
1872 /* We tolerate a lack of L2T, giving up some functionality */
1873 dev_warn(adapter, "could not allocate L2T. Continuing\n");
1876 if (tid_init(&adapter->tids) < 0) {
1877 /* Disable filtering support */
1878 dev_warn(adapter, "could not allocate TID table, "
1879 "filter support disabled. Continuing\n");
1882 adapter->mpstcam = t4_init_mpstcam(adapter);
1883 if (!adapter->mpstcam)
1884 dev_warn(adapter, "could not allocate mps tcam table."
1887 if (is_hashfilter(adapter)) {
1888 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) {
1889 u32 hash_base, hash_reg;
1891 hash_reg = A_LE_DB_TID_HASHBASE;
1892 hash_base = t4_read_reg(adapter, hash_reg);
1893 adapter->tids.hash_base = hash_base / 4;
1896 /* Disable hash filtering support */
1898 "Maskless filter support disabled. Continuing\n");
1901 err = init_rss(adapter);
1908 for_each_port(adapter, i) {
1909 pi = adap2pinfo(adapter, i);
1911 t4_free_vi(adapter, adapter->mbox, adapter->pf,
1913 /* Skip first port since it'll be de-allocated by DPDK */
1917 if (pi->eth_dev->data->dev_private)
1918 rte_free(pi->eth_dev->data->dev_private);
1919 rte_eth_dev_release_port(pi->eth_dev);
1923 if (adapter->flags & FW_OK)
1924 t4_fw_bye(adapter, adapter->mbox);