1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_branch_prediction.h>
24 #include <rte_memory.h>
25 #include <rte_tailq.h>
27 #include <rte_alarm.h>
28 #include <rte_ether.h>
29 #include <ethdev_driver.h>
30 #include <ethdev_pci.h>
31 #include <rte_random.h>
33 #include <rte_kvargs.h>
35 #include "base/common.h"
36 #include "base/t4_regs.h"
37 #include "base/t4_msg.h"
39 #include "cxgbe_pfvf.h"
45 static const u16 cxgbe_filter_mode_features[] = {
46 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE |
48 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE |
50 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS |
52 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS |
54 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_PORT |
56 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_TOS |
58 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VLAN |
60 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VNIC_ID |
62 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VLAN |
64 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VNIC_ID |
66 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_VLAN | F_PORT |
68 (F_FRAGMENTATION | F_MPSHITTYPE | F_MACMATCH | F_VNIC_ID | F_PORT |
70 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_PROTOCOL | F_TOS |
72 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_PORT),
73 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_FCOE),
74 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_PORT),
75 (F_FRAGMENTATION | F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_FCOE),
76 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_PORT),
77 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_FCOE),
78 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID |
80 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID |
82 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_VLAN | F_PORT |
84 (F_FRAGMENTATION | F_MPSHITTYPE | F_PROTOCOL | F_VNIC_ID | F_PORT |
86 (F_FRAGMENTATION | F_MPSHITTYPE | F_TOS | F_VLAN | F_PORT | F_FCOE),
87 (F_FRAGMENTATION | F_MPSHITTYPE | F_TOS | F_VNIC_ID | F_PORT | F_FCOE),
88 (F_FRAGMENTATION | F_MPSHITTYPE | F_VLAN | F_VNIC_ID | F_FCOE),
89 (F_FRAGMENTATION | F_MACMATCH | F_ETHERTYPE | F_PROTOCOL | F_PORT |
91 (F_FRAGMENTATION | F_MACMATCH | F_ETHERTYPE | F_TOS | F_PORT | F_FCOE),
92 (F_FRAGMENTATION | F_MACMATCH | F_PROTOCOL | F_VLAN | F_PORT | F_FCOE),
93 (F_FRAGMENTATION | F_MACMATCH | F_PROTOCOL | F_VNIC_ID | F_PORT |
95 (F_FRAGMENTATION | F_MACMATCH | F_TOS | F_VLAN | F_PORT | F_FCOE),
96 (F_FRAGMENTATION | F_MACMATCH | F_TOS | F_VNIC_ID | F_PORT | F_FCOE),
97 (F_FRAGMENTATION | F_ETHERTYPE | F_VLAN | F_PORT | F_FCOE),
98 (F_FRAGMENTATION | F_ETHERTYPE | F_VNIC_ID | F_PORT | F_FCOE),
99 (F_FRAGMENTATION | F_PROTOCOL | F_TOS | F_VLAN | F_FCOE),
100 (F_FRAGMENTATION | F_PROTOCOL | F_TOS | F_VNIC_ID | F_FCOE),
101 (F_FRAGMENTATION | F_VLAN | F_VNIC_ID | F_PORT | F_FCOE),
102 (F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_PROTOCOL | F_PORT |
104 (F_MPSHITTYPE | F_MACMATCH | F_ETHERTYPE | F_TOS | F_PORT | F_FCOE),
105 (F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VLAN | F_PORT),
106 (F_MPSHITTYPE | F_MACMATCH | F_PROTOCOL | F_VNIC_ID | F_PORT),
107 (F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VLAN | F_PORT),
108 (F_MPSHITTYPE | F_MACMATCH | F_TOS | F_VNIC_ID | F_PORT),
109 (F_MPSHITTYPE | F_ETHERTYPE | F_VLAN | F_PORT | F_FCOE),
110 (F_MPSHITTYPE | F_ETHERTYPE | F_VNIC_ID | F_PORT | F_FCOE),
111 (F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VLAN | F_PORT | F_FCOE),
112 (F_MPSHITTYPE | F_PROTOCOL | F_TOS | F_VNIC_ID | F_PORT | F_FCOE),
113 (F_MPSHITTYPE | F_VLAN | F_VNIC_ID | F_PORT),
117 * Allocate a chunk of memory. The allocated memory is cleared.
119 void *t4_alloc_mem(size_t size)
121 return rte_zmalloc(NULL, size, 0);
125 * Free memory allocated through t4_alloc_mem().
127 void t4_free_mem(void *addr)
133 * Response queue handler for the FW event queue.
135 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
136 __rte_unused const struct pkt_gl *gl)
138 u8 opcode = ((const struct rss_header *)rsp)->opcode;
140 rsp++; /* skip RSS header */
143 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
145 if (unlikely(opcode == CPL_FW4_MSG &&
146 ((const struct cpl_fw4_msg *)rsp)->type ==
149 opcode = ((const struct rss_header *)rsp)->opcode;
151 if (opcode != CPL_SGE_EGR_UPDATE) {
152 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
158 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
160 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
161 const struct cpl_fw6_msg *msg = (const void *)rsp;
163 t4_handle_fw_rpl(q->adapter, msg->data);
164 } else if (opcode == CPL_ABORT_RPL_RSS) {
165 const struct cpl_abort_rpl_rss *p = (const void *)rsp;
167 cxgbe_hash_del_filter_rpl(q->adapter, p);
168 } else if (opcode == CPL_SET_TCB_RPL) {
169 const struct cpl_set_tcb_rpl *p = (const void *)rsp;
171 cxgbe_filter_rpl(q->adapter, p);
172 } else if (opcode == CPL_ACT_OPEN_RPL) {
173 const struct cpl_act_open_rpl *p = (const void *)rsp;
175 cxgbe_hash_filter_rpl(q->adapter, p);
176 } else if (opcode == CPL_L2T_WRITE_RPL) {
177 const struct cpl_l2t_write_rpl *p = (const void *)rsp;
179 cxgbe_do_l2t_write_rpl(q->adapter, p);
180 } else if (opcode == CPL_SMT_WRITE_RPL) {
181 const struct cpl_smt_write_rpl *p = (const void *)rsp;
183 cxgbe_do_smt_write_rpl(q->adapter, p);
185 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
193 * Setup sge control queues to pass control information.
195 int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter)
197 struct sge *s = &adapter->sge;
200 for_each_port(adapter, i) {
201 struct port_info *pi = adap2pinfo(adapter, i);
202 char name[RTE_ETH_NAME_MAX_LEN];
203 struct sge_ctrl_txq *q = &s->ctrlq[i];
206 err = t4_sge_alloc_ctrl_txq(adapter, q,
211 dev_err(adapter, "Failed to alloc ctrl txq. Err: %d",
215 snprintf(name, sizeof(name), "%s_ctrl_pool_%d",
216 pi->eth_dev->device->driver->name,
217 pi->eth_dev->data->port_id);
218 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
221 RTE_MBUF_DEFAULT_BUF_SIZE,
226 "Can't create ctrl pool for port %d. Err: %d\n",
227 pi->eth_dev->data->port_id, err);
233 t4_free_sge_resources(adapter);
238 * cxgbe_poll_for_completion: Poll rxq for completion
240 * @ms: milliseconds to delay
241 * @cnt: number of times to poll
242 * @c: completion to check for 'done' status
244 * Polls the rxq for reples until completion is done or the count
247 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int ms,
248 unsigned int cnt, struct t4_completion *c)
251 unsigned int work_done, budget = 32;
256 for (i = 0; i < cnt; i++) {
257 cxgbe_poll(q, NULL, budget, &work_done);
258 t4_os_lock(&c->lock);
260 t4_os_unlock(&c->lock);
263 t4_os_unlock(&c->lock);
269 int cxgbe_setup_sge_fwevtq(struct adapter *adapter)
271 struct sge *s = &adapter->sge;
275 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
276 msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
281 static int closest_timer(const struct sge *s, int time)
283 unsigned int i, match = 0;
284 int delta, min_delta = INT_MAX;
286 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
287 delta = time - s->timer_val[i];
290 if (delta < min_delta) {
298 static int closest_thres(const struct sge *s, int thres)
300 unsigned int i, match = 0;
301 int delta, min_delta = INT_MAX;
303 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
304 delta = thres - s->counter_val[i];
307 if (delta < min_delta) {
316 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
318 * @us: the hold-off time in us, or 0 to disable timer
319 * @cnt: the hold-off packet count, or 0 to disable counter
321 * Sets an Rx queue's interrupt hold-off time and packet count. At least
322 * one of the two needs to be enabled for the queue to generate interrupts.
324 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
327 struct adapter *adap = q->adapter;
328 unsigned int timer_val;
334 new_idx = closest_thres(&adap->sge, cnt);
335 if (q->desc && q->pktcnt_idx != new_idx) {
336 /* the queue has already been created, update it */
337 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
339 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
340 V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
341 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
346 q->pktcnt_idx = new_idx;
349 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
350 closest_timer(&adap->sge, us);
353 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
355 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
356 V_QINTR_CNT_EN(cnt > 0);
361 * Allocate an active-open TID and set it to the supplied value.
363 int cxgbe_alloc_atid(struct tid_info *t, void *data)
367 t4_os_lock(&t->atid_lock);
369 union aopen_entry *p = t->afree;
371 atid = p - t->atid_tab;
376 t4_os_unlock(&t->atid_lock);
381 * Release an active-open TID.
383 void cxgbe_free_atid(struct tid_info *t, unsigned int atid)
385 union aopen_entry *p = &t->atid_tab[atid];
387 t4_os_lock(&t->atid_lock);
391 t4_os_unlock(&t->atid_lock);
395 * Populate a TID_RELEASE WR. Caller must properly size the skb.
397 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid)
399 struct cpl_tid_release *req;
401 req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *);
402 INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
406 * Release a TID and inform HW. If we are unable to allocate the release
407 * message we defer to a work queue.
409 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
410 unsigned short family)
412 struct rte_mbuf *mbuf;
413 struct adapter *adap = container_of(t, struct adapter, tids);
415 WARN_ON(tid >= t->ntids);
417 if (t->tid_tab[tid]) {
418 t->tid_tab[tid] = NULL;
419 __atomic_sub_fetch(&t->conns_in_use, 1, __ATOMIC_RELAXED);
420 if (t->hash_base && tid >= t->hash_base) {
421 if (family == FILTER_TYPE_IPV4)
422 __atomic_sub_fetch(&t->hash_tids_in_use, 1,
425 if (family == FILTER_TYPE_IPV4)
426 __atomic_sub_fetch(&t->tids_in_use, 1,
431 mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool);
433 mbuf->data_len = sizeof(struct cpl_tid_release);
434 mbuf->pkt_len = mbuf->data_len;
435 mk_tid_release(mbuf, tid);
436 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf);
443 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid,
444 unsigned short family)
446 t->tid_tab[tid] = data;
447 if (t->hash_base && tid >= t->hash_base) {
448 if (family == FILTER_TYPE_IPV4)
449 __atomic_add_fetch(&t->hash_tids_in_use, 1,
452 if (family == FILTER_TYPE_IPV4)
453 __atomic_add_fetch(&t->tids_in_use, 1,
457 __atomic_add_fetch(&t->conns_in_use, 1, __ATOMIC_RELAXED);
463 static void tid_free(struct tid_info *t)
466 rte_bitmap_free(t->ftid_bmap);
468 if (t->ftid_bmap_array)
469 t4_os_free(t->ftid_bmap_array);
471 t4_os_free(t->tid_tab);
474 memset(t, 0, sizeof(struct tid_info));
478 * Allocate and initialize the TID tables. Returns 0 on success.
480 static int tid_init(struct tid_info *t)
483 unsigned int ftid_bmap_size;
484 unsigned int natids = t->natids;
485 unsigned int max_ftids = t->nftids;
487 ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
488 size = t->ntids * sizeof(*t->tid_tab) +
489 max_ftids * sizeof(*t->ftid_tab) +
490 natids * sizeof(*t->atid_tab);
492 t->tid_tab = t4_os_alloc(size);
496 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
497 t->ftid_tab = (struct filter_entry *)&t->atid_tab[t->natids];
498 t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
499 if (!t->ftid_bmap_array) {
504 t4_os_lock_init(&t->atid_lock);
505 t4_os_lock_init(&t->ftid_lock);
512 /* Setup the free list for atid_tab and clear the stid bitmap. */
515 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
516 t->afree = t->atid_tab;
519 t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
529 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
530 unsigned int us, unsigned int cnt,
531 unsigned int size, unsigned int iqe_size)
534 cxgb4_set_rspq_intr_params(q, us, cnt);
535 q->iqe_len = iqe_size;
539 int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev)
541 struct port_info *temp_pi, *pi = eth_dev->data->dev_private;
542 struct adapter *adap = pi->adapter;
543 u16 first_txq = 0, first_rxq = 0;
544 struct sge *s = &adap->sge;
545 u16 i, max_rxqs, max_txqs;
547 max_rxqs = s->max_ethqsets;
548 max_txqs = s->max_ethqsets;
549 for_each_port(adap, i) {
550 temp_pi = adap2pinfo(adap, i);
551 if (i == pi->port_id)
554 if (max_rxqs <= temp_pi->n_rx_qsets ||
555 max_txqs <= temp_pi->n_tx_qsets)
558 first_rxq += temp_pi->n_rx_qsets;
559 first_txq += temp_pi->n_tx_qsets;
560 max_rxqs -= temp_pi->n_rx_qsets;
561 max_txqs -= temp_pi->n_tx_qsets;
564 if ((eth_dev->data->nb_rx_queues < 1) ||
565 (eth_dev->data->nb_tx_queues < 1))
568 if (eth_dev->data->nb_rx_queues > max_rxqs ||
569 eth_dev->data->nb_tx_queues > max_txqs)
572 /* We must configure RSS, since config has changed*/
573 pi->flags &= ~PORT_RSS_DONE;
575 pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
576 pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
577 pi->first_rxqset = first_rxq;
578 pi->first_txqset = first_txq;
583 void cxgbe_cfg_queues_free(struct adapter *adap)
585 if (adap->sge.ethtxq) {
586 rte_free(adap->sge.ethtxq);
587 adap->sge.ethtxq = NULL;
590 if (adap->sge.ethrxq) {
591 rte_free(adap->sge.ethrxq);
592 adap->sge.ethrxq = NULL;
595 adap->flags &= ~CFG_QUEUES;
598 int cxgbe_cfg_queues(struct rte_eth_dev *eth_dev)
600 struct port_info *pi = eth_dev->data->dev_private;
601 struct adapter *adap = pi->adapter;
602 struct sge *s = &adap->sge;
605 if (!(adap->flags & CFG_QUEUES)) {
606 s->ethrxq = rte_calloc_socket(NULL, s->max_ethqsets,
607 sizeof(struct sge_eth_rxq), 0,
612 s->ethtxq = rte_calloc_socket(NULL, s->max_ethqsets,
613 sizeof(struct sge_eth_txq), 0,
621 for (i = 0; i < s->max_ethqsets; i++) {
622 struct sge_eth_rxq *r = &s->ethrxq[i];
623 struct sge_eth_txq *t = &s->ethtxq[i];
625 init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
631 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
632 adap->flags |= CFG_QUEUES;
638 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
640 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
644 void cxgbe_stats_reset(struct port_info *pi)
646 t4_clr_port_stats(pi->adapter, pi->tx_chan);
649 static void setup_memwin(struct adapter *adap)
653 /* For T5, only relative offset inside the PCIe BAR is passed */
654 mem_win0_base = MEMWIN0_BASE;
657 * Set up memory window for accessing adapter memory ranges. (Read
658 * back MA register to ensure that changes propagate before we attempt
659 * to use the new values.)
662 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
664 mem_win0_base | V_BIR(0) |
665 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
667 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
671 int cxgbe_init_rss(struct adapter *adap)
678 err = t4_init_rss_mode(adap, adap->mbox);
683 for_each_port(adap, i) {
684 struct port_info *pi = adap2pinfo(adap, i);
686 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
690 pi->rss_hf = CXGBE_RSS_HF_ALL;
696 * Dump basic information about the adapter.
698 void cxgbe_print_adapter_info(struct adapter *adap)
701 * Hardware/Firmware/etc. Version/Revision IDs.
703 t4_dump_version_info(adap);
706 void cxgbe_print_port_info(struct adapter *adap)
710 struct rte_pci_addr *loc = &adap->pdev->addr;
712 for_each_port(adap, i) {
713 const struct port_info *pi = adap2pinfo(adap, i);
716 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
717 bufp += sprintf(bufp, "100M/");
718 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
719 bufp += sprintf(bufp, "1G/");
720 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
721 bufp += sprintf(bufp, "10G/");
722 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
723 bufp += sprintf(bufp, "25G/");
724 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
725 bufp += sprintf(bufp, "40G/");
726 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
727 bufp += sprintf(bufp, "50G/");
728 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
729 bufp += sprintf(bufp, "100G/");
732 sprintf(bufp, "BASE-%s",
733 t4_get_port_type_description(
734 (enum fw_port_type)pi->link_cfg.port_type));
737 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
738 loc->domain, loc->bus, loc->devid, loc->function,
739 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
740 (adap->flags & USING_MSIX) ? " MSI-X" :
741 (adap->flags & USING_MSI) ? " MSI" : "");
745 static int check_devargs_handler(const char *key, const char *value, void *p)
747 if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) ||
748 !strncmp(key, CXGBE_DEVARG_CMN_TX_MODE_LATENCY, strlen(key)) ||
749 !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) {
750 if (!strncmp(value, "1", 1)) {
751 bool *dst_val = (bool *)p;
757 if (!strncmp(key, CXGBE_DEVARG_PF_FILTER_MODE, strlen(key)) ||
758 !strncmp(key, CXGBE_DEVARG_PF_FILTER_MASK, strlen(key))) {
759 u32 *dst_val = (u32 *)p;
763 arg_val = strtoul(value, &endptr, 16);
764 if (errno || endptr == value)
773 static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key,
776 struct rte_kvargs *kvlist;
782 kvlist = rte_kvargs_parse(devargs->args, NULL);
786 if (!rte_kvargs_count(kvlist, key))
789 ret = rte_kvargs_process(kvlist, key, check_devargs_handler, p);
792 rte_kvargs_free(kvlist);
797 static void cxgbe_get_devargs_int(struct adapter *adap, bool *dst,
798 const char *key, bool default_value)
800 struct rte_pci_device *pdev = adap->pdev;
802 bool devarg_value = default_value;
804 *dst = default_value;
808 ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value);
815 static void cxgbe_get_devargs_u32(struct adapter *adap, u32 *dst,
816 const char *key, u32 default_value)
818 struct rte_pci_device *pdev = adap->pdev;
819 u32 devarg_value = default_value;
822 *dst = default_value;
826 ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value);
833 void cxgbe_process_devargs(struct adapter *adap)
835 cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan,
836 CXGBE_DEVARG_CMN_KEEP_OVLAN, false);
837 cxgbe_get_devargs_int(adap, &adap->devargs.tx_mode_latency,
838 CXGBE_DEVARG_CMN_TX_MODE_LATENCY, false);
839 cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up,
840 CXGBE_DEVARG_VF_FORCE_LINK_UP, false);
841 cxgbe_get_devargs_u32(adap, &adap->devargs.filtermode,
842 CXGBE_DEVARG_PF_FILTER_MODE, 0);
843 cxgbe_get_devargs_u32(adap, &adap->devargs.filtermask,
844 CXGBE_DEVARG_PF_FILTER_MASK, 0);
847 static void configure_vlan_types(struct adapter *adapter)
851 for_each_port(adapter, i) {
852 /* OVLAN Type 0x88a8 */
853 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
854 V_OVLAN_MASK(M_OVLAN_MASK) |
855 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
856 V_OVLAN_MASK(M_OVLAN_MASK) |
857 V_OVLAN_ETYPE(0x88a8));
858 /* OVLAN Type 0x9100 */
859 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
860 V_OVLAN_MASK(M_OVLAN_MASK) |
861 V_OVLAN_ETYPE(M_OVLAN_ETYPE),
862 V_OVLAN_MASK(M_OVLAN_MASK) |
863 V_OVLAN_ETYPE(0x9100));
866 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
867 V_IVLAN_ETYPE(M_IVLAN_ETYPE),
868 V_IVLAN_ETYPE(0x8100));
870 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
871 F_OVLAN_EN0 | F_OVLAN_EN1 |
873 F_OVLAN_EN0 | F_OVLAN_EN1 |
877 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1),
878 V_RM_OVLAN(!adapter->devargs.keep_ovlan));
881 static int cxgbe_get_filter_vnic_mode_from_devargs(u32 val)
885 vnic_mode = val & (CXGBE_DEVARGS_FILTER_MODE_PF_VF |
886 CXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER);
889 case CXGBE_DEVARGS_FILTER_MODE_VLAN_OUTER:
890 return CXGBE_FILTER_VNIC_MODE_OVLAN;
891 case CXGBE_DEVARGS_FILTER_MODE_PF_VF:
892 return CXGBE_FILTER_VNIC_MODE_PFVF;
898 return CXGBE_FILTER_VNIC_MODE_NONE;
901 static int cxgbe_get_filter_mode_from_devargs(u32 val, bool closest_match)
903 int vnic_mode, fmode = 0;
907 if (val >= CXGBE_DEVARGS_FILTER_MODE_MAX) {
908 pr_err("Unsupported flags set in filter mode. Must be < 0x%x\n",
909 CXGBE_DEVARGS_FILTER_MODE_MAX);
913 vnic_mode = cxgbe_get_filter_vnic_mode_from_devargs(val);
915 pr_err("Unsupported Vnic-mode, more than 1 Vnic-mode selected\n");
921 if (val & CXGBE_DEVARGS_FILTER_MODE_PHYSICAL_PORT)
923 if (val & CXGBE_DEVARGS_FILTER_MODE_ETHERNET_DSTMAC)
925 if (val & CXGBE_DEVARGS_FILTER_MODE_ETHERNET_ETHTYPE)
926 fmode |= F_ETHERTYPE;
927 if (val & CXGBE_DEVARGS_FILTER_MODE_VLAN_INNER)
929 if (val & CXGBE_DEVARGS_FILTER_MODE_IP_TOS)
931 if (val & CXGBE_DEVARGS_FILTER_MODE_IP_PROTOCOL)
934 for (i = 0; i < ARRAY_SIZE(cxgbe_filter_mode_features); i++) {
935 if ((cxgbe_filter_mode_features[i] & fmode) == fmode) {
944 return closest_match ? cxgbe_filter_mode_features[i] : fmode;
947 static int configure_filter_mode_mask(struct adapter *adap)
949 u32 params[2], val[2], nparams = 0;
952 if (!adap->devargs.filtermode && !adap->devargs.filtermask)
955 if (!adap->devargs.filtermode || !adap->devargs.filtermask) {
956 pr_err("Unsupported, Provide both filtermode and filtermask devargs\n");
960 if (adap->devargs.filtermask & ~adap->devargs.filtermode) {
961 pr_err("Unsupported, filtermask (0x%x) must be subset of filtermode (0x%x)\n",
962 adap->devargs.filtermask, adap->devargs.filtermode);
967 params[0] = CXGBE_FW_PARAM_DEV(FILTER) |
968 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK);
970 ret = cxgbe_get_filter_mode_from_devargs(adap->devargs.filtermode,
973 pr_err("Unsupported filtermode devargs combination:0x%x\n",
974 adap->devargs.filtermode);
978 val[0] = V_FW_PARAMS_PARAM_FILTER_MODE(ret);
980 ret = cxgbe_get_filter_mode_from_devargs(adap->devargs.filtermask,
983 pr_err("Unsupported filtermask devargs combination:0x%x\n",
984 adap->devargs.filtermask);
988 val[0] |= V_FW_PARAMS_PARAM_FILTER_MASK(ret);
992 ret = cxgbe_get_filter_vnic_mode_from_devargs(adap->devargs.filtermode);
997 params[1] = CXGBE_FW_PARAM_DEV(FILTER) |
998 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE);
1005 return t4_set_params(adap, adap->mbox, adap->pf, 0, nparams,
1009 static void configure_pcie_ext_tag(struct adapter *adapter)
1012 int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
1018 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
1019 v |= PCI_EXP_DEVCTL_EXT_TAG;
1020 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
1021 if (is_t6(adapter->params.chip)) {
1022 t4_set_reg_field(adapter, A_PCIE_CFG2,
1023 V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
1025 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
1026 V_T6_MINTAG(M_T6_MINTAG),
1029 t4_set_reg_field(adapter, A_PCIE_CFG2,
1030 V_TOTMAXTAG(M_TOTMAXTAG),
1032 t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
1039 /* Figure out how many Queue Sets we can support */
1040 void cxgbe_configure_max_ethqsets(struct adapter *adapter)
1042 unsigned int ethqsets, reserved;
1044 /* We need to reserve an Ingress Queue for the Asynchronous Firmware
1045 * Event Queue and 1 Control Queue per port.
1047 * For each Queue Set, we'll need the ability to allocate two Egress
1048 * Contexts -- one for the Ingress Queue Free List and one for the TX
1051 reserved = max(adapter->params.nports, 1);
1052 if (is_pf4(adapter)) {
1053 struct pf_resources *pfres = &adapter->params.pfres;
1055 ethqsets = min(pfres->niqflint, pfres->nethctrl);
1056 if (ethqsets > (pfres->neq / 2))
1057 ethqsets = pfres->neq / 2;
1059 struct vf_resources *vfres = &adapter->params.vfres;
1061 ethqsets = min(vfres->niqflint, vfres->nethctrl);
1062 if (ethqsets > (vfres->neq / 2))
1063 ethqsets = vfres->neq / 2;
1066 ethqsets -= reserved;
1067 adapter->sge.max_ethqsets = ethqsets;
1071 * Tweak configuration based on system architecture, etc. Most of these have
1072 * defaults assigned to them by Firmware Configuration Files (if we're using
1073 * them) but need to be explicitly set if we're using hard-coded
1074 * initialization. So these are essentially common tweaks/settings for
1075 * Configuration Files and hard-coded initialization ...
1077 static int adap_init0_tweaks(struct adapter *adapter)
1082 * Fix up various Host-Dependent Parameters like Page Size, Cache
1083 * Line Size, etc. The firmware default is for a 4KB Page Size and
1084 * 64B Cache Line Size ...
1086 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
1090 * Keep the chip default offset to deliver Ingress packets into our
1091 * DMA buffers to zero
1094 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
1095 V_PKTSHIFT(rx_dma_offset));
1097 t4_set_reg_field(adapter, A_SGE_FLM_CFG,
1098 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
1099 V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
1101 t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
1102 V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
1104 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
1105 V_IDMAARBROUNDROBIN(1U));
1108 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
1109 * adds the pseudo header itself.
1111 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
1112 F_CSUM_HAS_PSEUDO_HDR, 0);
1118 * Attempt to initialize the adapter via a Firmware Configuration File.
1120 static int adap_init0_config(struct adapter *adapter, int reset)
1122 u32 finiver, finicsum, cfcsum, param, val;
1123 struct fw_caps_config_cmd caps_cmd;
1124 unsigned long mtype = 0, maddr = 0;
1125 u8 config_issued = 0;
1126 char config_name[20];
1130 * Reset device if necessary.
1133 ret = t4_fw_reset(adapter, adapter->mbox,
1134 F_PIORSTMODE | F_PIORST);
1136 dev_warn(adapter, "Firmware reset failed, error %d\n",
1142 cfg_addr = t4_flash_cfg_addr(adapter);
1145 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
1150 strcpy(config_name, "On Flash");
1151 mtype = FW_MEMTYPE_CF_FLASH;
1154 /* Enable HASH filter region when support is available. */
1156 param = CXGBE_FW_PARAM_DEV(HASHFILTER_WITH_OFLD);
1157 t4_set_params(adapter, adapter->mbox, adapter->pf, 0, 1,
1161 * Issue a Capability Configuration command to the firmware to get it
1162 * to parse the Configuration File. We don't use t4_fw_config_file()
1163 * because we want the ability to modify various features after we've
1164 * processed the configuration file ...
1166 memset(&caps_cmd, 0, sizeof(caps_cmd));
1167 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1168 F_FW_CMD_REQUEST | F_FW_CMD_READ);
1169 caps_cmd.cfvalid_to_len16 =
1170 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
1171 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
1172 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
1173 FW_LEN16(caps_cmd));
1174 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
1177 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
1178 * Configuration File in FLASH), our last gasp effort is to use the
1179 * Firmware Configuration File which is embedded in the firmware. A
1180 * very few early versions of the firmware didn't have one embedded
1181 * but we can ignore those.
1183 if (ret == -ENOENT) {
1184 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
1187 memset(&caps_cmd, 0, sizeof(caps_cmd));
1188 caps_cmd.op_to_write =
1189 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1190 F_FW_CMD_REQUEST | F_FW_CMD_READ);
1191 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
1192 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
1193 sizeof(caps_cmd), &caps_cmd);
1194 strcpy(config_name, "Firmware Default");
1201 finiver = be32_to_cpu(caps_cmd.finiver);
1202 finicsum = be32_to_cpu(caps_cmd.finicsum);
1203 cfcsum = be32_to_cpu(caps_cmd.cfcsum);
1204 if (finicsum != cfcsum)
1205 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
1209 * If we're a pure NIC driver then disable all offloading facilities.
1210 * This will allow the firmware to optimize aspects of the hardware
1211 * configuration which will result in improved performance.
1213 caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD);
1214 caps_cmd.toecaps = 0;
1215 caps_cmd.iscsicaps = 0;
1216 caps_cmd.rdmacaps = 0;
1217 caps_cmd.fcoecaps = 0;
1218 caps_cmd.cryptocaps = 0;
1221 * And now tell the firmware to use the configuration we just loaded.
1223 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1224 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
1225 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
1226 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
1229 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
1235 * Tweak configuration based on system architecture, etc.
1237 ret = adap_init0_tweaks(adapter);
1239 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
1244 * And finally tell the firmware to initialize itself using the
1245 * parameters from the Configuration File.
1247 ret = t4_fw_initialize(adapter, adapter->mbox);
1249 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
1255 * Return successfully and note that we're operating with parameters
1256 * not supplied by the driver, rather than from hard-wired
1257 * initialization constants buried in the driver.
1260 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
1261 config_name, finiver, cfcsum);
1266 * Something bad happened. Return the error ... (If the "error"
1267 * is that there's no Configuration File on the adapter we don't
1268 * want to issue a warning since this is fairly common.)
1271 if (config_issued && ret != -ENOENT)
1272 dev_warn(adapter, "\"%s\" configuration file error %d\n",
1275 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
1279 static int adap_init0(struct adapter *adap)
1281 struct fw_caps_config_cmd caps_cmd;
1284 enum dev_state state;
1285 u32 params[7], val[7];
1287 int mbox = adap->mbox;
1290 * Contact FW, advertising Master capability.
1292 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
1294 dev_err(adap, "%s: could not connect to FW, error %d\n",
1299 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
1303 adap->flags |= MASTER_PF;
1305 if (state == DEV_STATE_INIT) {
1307 * Force halt and reset FW because a previous instance may have
1308 * exited abnormally without properly shutting down
1310 ret = t4_fw_halt(adap, adap->mbox, reset);
1312 dev_err(adap, "Failed to halt. Exit.\n");
1316 ret = t4_fw_restart(adap, adap->mbox, reset);
1318 dev_err(adap, "Failed to restart. Exit.\n");
1321 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
1324 t4_get_version_info(adap);
1326 ret = t4_get_core_clock(adap, &adap->params.vpd);
1328 dev_err(adap, "%s: could not get core clock, error %d\n",
1334 * If the firmware is initialized already (and we're not forcing a
1335 * master initialization), note that we're living with existing
1336 * adapter parameters. Otherwise, it's time to try initializing the
1339 if (state == DEV_STATE_INIT) {
1340 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
1341 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
1343 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
1345 ret = adap_init0_config(adap, reset);
1346 if (ret == -ENOENT) {
1348 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
1353 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
1357 /* Now that we've successfully configured and initialized the adapter
1358 * (or found it already initialized), we can ask the Firmware what
1359 * resources it has provisioned for us.
1361 ret = t4_get_pfres(adap);
1363 dev_err(adap->pdev_dev,
1364 "Unable to retrieve resource provisioning info\n");
1368 /* Find out what ports are available to us. */
1369 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1370 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
1371 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
1373 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
1378 adap->params.nports = hweight32(port_vec);
1379 adap->params.portvec = port_vec;
1381 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
1382 adap->params.nports);
1385 * Give the SGE code a chance to pull in anything that it needs ...
1386 * Note that this must be called after we retrieve our VPD parameters
1387 * in order to know how to convert core ticks to seconds, etc.
1389 ret = t4_sge_init(adap);
1391 dev_err(adap, "t4_sge_init failed with error %d\n",
1397 * Grab some of our basic fundamental operating parameters.
1399 params[0] = CXGBE_FW_PARAM_PFVF(L2T_START);
1400 params[1] = CXGBE_FW_PARAM_PFVF(L2T_END);
1401 params[2] = CXGBE_FW_PARAM_PFVF(FILTER_START);
1402 params[3] = CXGBE_FW_PARAM_PFVF(FILTER_END);
1403 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val);
1406 adap->l2t_start = val[0];
1407 adap->l2t_end = val[1];
1408 adap->tids.ftid_base = val[2];
1409 adap->tids.nftids = val[3] - val[2] + 1;
1411 params[0] = CXGBE_FW_PARAM_PFVF(CLIP_START);
1412 params[1] = CXGBE_FW_PARAM_PFVF(CLIP_END);
1413 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
1416 adap->clipt_start = val[0];
1417 adap->clipt_end = val[1];
1420 * Get device capabilities so we can determine what resources we need
1423 memset(&caps_cmd, 0, sizeof(caps_cmd));
1424 caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1425 F_FW_CMD_REQUEST | F_FW_CMD_READ);
1426 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
1427 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
1432 if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) &&
1433 is_t6(adap->params.chip)) {
1434 if (cxgbe_init_hash_filter(adap) < 0)
1438 /* See if FW supports FW_FILTER2 work request */
1439 if (is_t4(adap->params.chip)) {
1440 adap->params.filter2_wr_support = 0;
1442 params[0] = CXGBE_FW_PARAM_DEV(FILTER2_WR);
1443 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1445 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
1448 /* Check if FW supports returning vin.
1449 * If this is not supported, driver will interpret
1450 * these values from viid.
1452 params[0] = CXGBE_FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN);
1453 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1455 adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0);
1457 /* query tid-related parameters */
1458 params[0] = CXGBE_FW_PARAM_DEV(NTID);
1459 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
1463 adap->tids.ntids = val[0];
1464 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
1466 /* If we're running on newer firmware, let it know that we're
1467 * prepared to deal with encapsulated CPL messages. Older
1468 * firmware won't understand this and we'll just get
1469 * unencapsulated messages ...
1471 params[0] = CXGBE_FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
1473 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1476 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
1477 * capability. Earlier versions of the firmware didn't have the
1478 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
1479 * permission to use ULPTX MEMWRITE DSGL.
1481 if (is_t4(adap->params.chip)) {
1482 adap->params.ulptx_memwrite_dsgl = false;
1484 params[0] = CXGBE_FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
1485 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1487 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
1490 /* Query for max number of packets that can be coalesced for Tx */
1491 params[0] = CXGBE_FW_PARAM_PFVF(MAX_PKTS_PER_ETH_TX_PKTS_WR);
1492 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1493 if (!ret && val[0] > 0)
1494 adap->params.max_tx_coalesce_num = val[0];
1496 adap->params.max_tx_coalesce_num = ETH_COALESCE_PKT_NUM;
1498 params[0] = CXGBE_FW_PARAM_DEV(VI_ENABLE_INGRESS_AFTER_LINKUP);
1499 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1500 adap->params.vi_enable_rx = (ret == 0 && val[0] != 0);
1502 /* Read the RAW MPS entries. In T6, the last 2 TCAM entries
1503 * are reserved for RAW MAC addresses (rawf = 2, one per port).
1505 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
1506 params[0] = CXGBE_FW_PARAM_PFVF(RAWF_START);
1507 params[1] = CXGBE_FW_PARAM_PFVF(RAWF_END);
1508 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
1511 adap->params.rawf_start = val[0];
1512 adap->params.rawf_size = val[1] - val[0] + 1;
1517 * The MTU/MSS Table is initialized by now, so load their values. If
1518 * we're initializing the adapter, then we'll make any modifications
1519 * we want to the MTU/MSS Table and also initialize the congestion
1522 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
1523 if (state != DEV_STATE_INIT) {
1527 * The default MTU Table contains values 1492 and 1500.
1528 * However, for TCP, it's better to have two values which are
1529 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
1530 * This allows us to have a TCP Data Payload which is a
1531 * multiple of 8 regardless of what combination of TCP Options
1532 * are in use (always a multiple of 4 bytes) which is
1533 * important for performance reasons. For instance, if no
1534 * options are in use, then we have a 20-byte IP header and a
1535 * 20-byte TCP header. In this case, a 1500-byte MSS would
1536 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
1537 * which is not a multiple of 8. So using an MSS of 1488 in
1538 * this case results in a TCP Data Payload of 1448 bytes which
1539 * is a multiple of 8. On the other hand, if 12-byte TCP Time
1540 * Stamps have been negotiated, then an MTU of 1500 bytes
1541 * results in a TCP Data Payload of 1448 bytes which, as
1542 * above, is a multiple of 8 bytes ...
1544 for (i = 0; i < NMTUS; i++)
1545 if (adap->params.mtus[i] == 1492) {
1546 adap->params.mtus[i] = 1488;
1550 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
1551 adap->params.b_wnd);
1553 t4_init_sge_params(adap);
1554 ret = configure_filter_mode_mask(adap);
1557 t4_init_tp_params(adap);
1558 configure_pcie_ext_tag(adap);
1559 configure_vlan_types(adap);
1560 cxgbe_configure_max_ethqsets(adap);
1562 adap->params.drv_memwin = MEMWIN_NIC;
1563 adap->flags |= FW_OK;
1564 dev_debug(adap, "%s: returning zero..\n", __func__);
1568 * Something bad happened. If a command timed out or failed with EIO
1569 * FW does not operate within its spec or something catastrophic
1570 * happened to HW/FW, stop issuing commands.
1573 if (ret != -ETIMEDOUT && ret != -EIO)
1574 t4_fw_bye(adap, adap->mbox);
1579 * t4_os_portmod_changed - handle port module changes
1580 * @adap: the adapter associated with the module change
1581 * @port_id: the port index whose module status has changed
1583 * This is the OS-dependent handler for port module changes. It is
1584 * invoked when a port module is removed or inserted for any OS-specific
1587 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1589 static const char * const mod_str[] = {
1590 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1593 const struct port_info *pi = adap2pinfo(adap, port_id);
1595 if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_NONE)
1596 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1597 else if (pi->link_cfg.mod_type < ARRAY_SIZE(mod_str))
1598 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1599 mod_str[pi->link_cfg.mod_type]);
1600 else if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1601 dev_info(adap, "Port%d: unsupported port module inserted\n",
1603 else if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1604 dev_info(adap, "Port%d: unknown port module inserted\n",
1606 else if (pi->link_cfg.mod_type == FW_PORT_MOD_TYPE_ERROR)
1607 dev_info(adap, "Port%d: transceiver module error\n",
1610 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1611 pi->port_id, pi->link_cfg.mod_type);
1614 void t4_os_link_changed(struct adapter *adap, int port_id)
1616 struct port_info *pi = adap2pinfo(adap, port_id);
1618 /* If link status has not changed or if firmware doesn't
1619 * support enabling/disabling VI's Rx path during runtime,
1622 if (adap->params.vi_enable_rx == 0 ||
1623 pi->vi_en_rx == pi->link_cfg.link_ok)
1626 /* Don't enable VI Rx path, if link has been administratively
1629 if (pi->vi_en_tx == 0 && pi->vi_en_rx == 0)
1632 /* When link goes down, disable the port's Rx path to drop
1633 * Rx traffic closer to the wire, instead of processing it
1634 * further in the Rx pipeline. The Rx path will be re-enabled
1635 * once the link up message comes in firmware event queue.
1637 pi->vi_en_rx = pi->link_cfg.link_ok;
1638 t4_enable_vi(adap, adap->mbox, pi->viid, pi->vi_en_rx, pi->vi_en_tx);
1641 bool cxgbe_force_linkup(struct adapter *adap)
1644 return false; /* force_linkup not required for pf driver */
1646 return adap->devargs.force_link_up;
1650 * link_start - enable a port
1651 * @dev: the port to enable
1653 * Performs the MAC and PHY actions needed to enable a port.
1655 int cxgbe_link_start(struct port_info *pi)
1657 struct adapter *adapter = pi->adapter;
1662 mtu = pi->eth_dev->data->mtu;
1664 conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads;
1667 * We do not set address filters and promiscuity here, the stack does
1668 * that step explicitly.
1670 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1,
1671 !!(conf_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP),
1674 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt,
1675 (u8 *)&pi->eth_dev->data->mac_addrs[0]);
1677 pi->xact_addr_filt = ret;
1681 if (ret == 0 && is_pf4(adapter))
1682 ret = t4_link_l1cfg(pi, pi->link_cfg.admin_caps);
1684 /* Disable VI Rx until link up message is received in
1685 * firmware event queue, if firmware supports enabling/
1686 * disabling VI Rx at runtime.
1688 pi->vi_en_rx = adapter->params.vi_enable_rx ? 0 : 1;
1690 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1691 pi->vi_en_rx, pi->vi_en_tx, false);
1694 if (ret == 0 && cxgbe_force_linkup(adapter))
1695 pi->eth_dev->data->dev_link.link_status = RTE_ETH_LINK_UP;
1700 * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1702 * @rss_hf: Hash configuration to apply
1704 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1706 struct adapter *adapter = pi->adapter;
1707 const struct sge_eth_rxq *rxq;
1712 /* Should never be called before setting up sge eth rx queues */
1713 if (!(adapter->flags & FULL_INIT_DONE)) {
1714 dev_err(adap, "%s No RXQs available on port %d\n",
1715 __func__, pi->port_id);
1719 /* Don't allow unsupported hash functions */
1720 if (rss_hf & ~CXGBE_RSS_HF_ALL)
1723 if (rss_hf & CXGBE_RSS_HF_IPV4_MASK)
1724 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1726 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP)
1727 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1729 if (rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP)
1730 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1731 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1733 if (rss_hf & CXGBE_RSS_HF_IPV6_MASK)
1734 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1736 if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK)
1737 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1738 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1740 if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK)
1741 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1742 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1743 F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1745 rxq = &adapter->sge.ethrxq[pi->first_rxqset];
1746 rss = rxq[0].rspq.abs_id;
1748 /* If Tunnel All Lookup isn't specified in the global RSS
1749 * Configuration, then we need to specify a default Ingress
1750 * Queue for any ingress packets which aren't hashed. We'll
1751 * use our first ingress queue ...
1753 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1759 * cxgbe_write_rss - write the RSS table for a given port
1761 * @queues: array of queue indices for RSS
1763 * Sets up the portion of the HW RSS table for the port's VI to distribute
1764 * packets to the Rx queues in @queues.
1766 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1770 struct adapter *adapter = pi->adapter;
1771 const struct sge_eth_rxq *rxq;
1773 /* Should never be called before setting up sge eth rx queues */
1774 BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1776 rxq = &adapter->sge.ethrxq[pi->first_rxqset];
1777 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1781 /* map the queue indices to queue ids */
1782 for (i = 0; i < pi->rss_size; i++, queues++)
1783 rss[i] = rxq[*queues].rspq.abs_id;
1785 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1786 pi->rss_size, rss, pi->rss_size);
1792 * setup_rss - configure RSS
1793 * @adapter: the adapter
1795 * Sets up RSS to distribute packets to multiple receive queues. We
1796 * configure the RSS CPU lookup table to distribute to the number of HW
1797 * receive queues, and the response queue lookup table to narrow that
1798 * down to the response queues actually configured for each port.
1799 * We always configure the RSS mapping for all ports since the mapping
1800 * table has plenty of entries.
1802 int cxgbe_setup_rss(struct port_info *pi)
1805 struct adapter *adapter = pi->adapter;
1807 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1808 __func__, pi->rss_size, pi->n_rx_qsets);
1810 if (!(pi->flags & PORT_RSS_DONE)) {
1811 if (adapter->flags & FULL_INIT_DONE) {
1812 /* Fill default values with equal distribution */
1813 for (j = 0; j < pi->rss_size; j++)
1814 pi->rss[j] = j % pi->n_rx_qsets;
1816 err = cxgbe_write_rss(pi, pi->rss);
1820 err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1823 pi->flags |= PORT_RSS_DONE;
1830 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1832 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1834 /* 0-increment GTS to start the timer and enable interrupts */
1835 t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1836 T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1837 V_SEINTARM(q->intr_params) |
1838 V_INGRESSQID(q->cntxt_id));
1841 void cxgbe_enable_rx_queues(struct port_info *pi)
1843 struct adapter *adap = pi->adapter;
1844 struct sge *s = &adap->sge;
1847 for (i = 0; i < pi->n_rx_qsets; i++)
1848 enable_rx(adap, &s->ethrxq[pi->first_rxqset + i].rspq);
1852 * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1853 * @port_type: Firmware Port Type
1854 * @fw_caps: Firmware Port Capabilities
1855 * @speed_caps: Device Info Speed Capabilities
1857 * Translate a Firmware Port Capabilities specification to Device Info
1858 * Speed Capabilities.
1860 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1861 unsigned int fw_caps,
1864 #define SET_SPEED(__speed_name) \
1866 *speed_caps |= RTE_ETH_LINK_ ## __speed_name; \
1869 #define FW_CAPS_TO_SPEED(__fw_name) \
1871 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1872 SET_SPEED(__fw_name); \
1875 switch (port_type) {
1876 case FW_PORT_TYPE_BT_SGMII:
1877 case FW_PORT_TYPE_BT_XFI:
1878 case FW_PORT_TYPE_BT_XAUI:
1879 FW_CAPS_TO_SPEED(SPEED_100M);
1880 FW_CAPS_TO_SPEED(SPEED_1G);
1881 FW_CAPS_TO_SPEED(SPEED_10G);
1884 case FW_PORT_TYPE_KX4:
1885 case FW_PORT_TYPE_KX:
1886 case FW_PORT_TYPE_FIBER_XFI:
1887 case FW_PORT_TYPE_FIBER_XAUI:
1888 case FW_PORT_TYPE_SFP:
1889 case FW_PORT_TYPE_QSFP_10G:
1890 case FW_PORT_TYPE_QSA:
1891 FW_CAPS_TO_SPEED(SPEED_1G);
1892 FW_CAPS_TO_SPEED(SPEED_10G);
1895 case FW_PORT_TYPE_KR:
1896 SET_SPEED(SPEED_10G);
1899 case FW_PORT_TYPE_BP_AP:
1900 case FW_PORT_TYPE_BP4_AP:
1901 SET_SPEED(SPEED_1G);
1902 SET_SPEED(SPEED_10G);
1905 case FW_PORT_TYPE_BP40_BA:
1906 case FW_PORT_TYPE_QSFP:
1907 SET_SPEED(SPEED_40G);
1910 case FW_PORT_TYPE_CR_QSFP:
1911 case FW_PORT_TYPE_SFP28:
1912 case FW_PORT_TYPE_KR_SFP28:
1913 FW_CAPS_TO_SPEED(SPEED_1G);
1914 FW_CAPS_TO_SPEED(SPEED_10G);
1915 FW_CAPS_TO_SPEED(SPEED_25G);
1918 case FW_PORT_TYPE_CR2_QSFP:
1919 SET_SPEED(SPEED_50G);
1922 case FW_PORT_TYPE_KR4_100G:
1923 case FW_PORT_TYPE_CR4_QSFP:
1924 FW_CAPS_TO_SPEED(SPEED_25G);
1925 FW_CAPS_TO_SPEED(SPEED_40G);
1926 FW_CAPS_TO_SPEED(SPEED_50G);
1927 FW_CAPS_TO_SPEED(SPEED_100G);
1934 #undef FW_CAPS_TO_SPEED
1939 * cxgbe_get_speed_caps - Fetch supported speed capabilities
1940 * @pi: Underlying port's info
1941 * @speed_caps: Device Info speed capabilities
1943 * Fetch supported speed capabilities of the underlying port.
1945 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1949 fw_caps_to_speed_caps(pi->link_cfg.port_type, pi->link_cfg.pcaps,
1952 if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1953 *speed_caps |= RTE_ETH_LINK_SPEED_FIXED;
1957 * cxgbe_set_link_status - Set device link up or down.
1958 * @pi: Underlying port's info
1959 * @status: 0 - down, 1 - up
1961 * Set the device link up or down.
1963 int cxgbe_set_link_status(struct port_info *pi, bool status)
1965 struct adapter *adapter = pi->adapter;
1968 /* Wait for link up message from firmware to enable Rx path,
1969 * if firmware supports enabling/disabling VI Rx at runtime.
1971 pi->vi_en_rx = adapter->params.vi_enable_rx ? 0 : status;
1972 pi->vi_en_tx = status;
1973 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, pi->vi_en_rx,
1976 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1981 t4_reset_link_config(adapter, pi->pidx);
1987 * cxgb_up - enable the adapter
1988 * @adap: adapter being enabled
1990 * Called when the first port is enabled, this function performs the
1991 * actions necessary to make an adapter operational, such as completing
1992 * the initialization of HW modules, and enabling interrupts.
1994 int cxgbe_up(struct adapter *adap)
1996 enable_rx(adap, &adap->sge.fw_evtq);
1997 t4_sge_tx_monitor_start(adap);
1999 t4_intr_enable(adap);
2000 adap->flags |= FULL_INIT_DONE;
2002 /* TODO: deadman watchdog ?? */
2009 int cxgbe_down(struct port_info *pi)
2011 return cxgbe_set_link_status(pi, false);
2015 * Release resources when all the ports have been stopped.
2017 void cxgbe_close(struct adapter *adapter)
2019 if (adapter->flags & FULL_INIT_DONE) {
2020 tid_free(&adapter->tids);
2021 t4_cleanup_mpstcam(adapter);
2022 t4_cleanup_clip_tbl(adapter);
2023 t4_cleanup_l2t(adapter);
2024 t4_cleanup_smt(adapter);
2025 if (is_pf4(adapter))
2026 t4_intr_disable(adapter);
2027 t4_sge_tx_monitor_stop(adapter);
2028 t4_free_sge_resources(adapter);
2029 adapter->flags &= ~FULL_INIT_DONE;
2032 cxgbe_cfg_queues_free(adapter);
2034 if (is_pf4(adapter) && (adapter->flags & FW_OK))
2035 t4_fw_bye(adapter, adapter->mbox);
2038 static void adap_smt_index(struct adapter *adapter, u32 *smt_start_idx,
2041 u32 params[2], smt_val[2];
2044 params[0] = CXGBE_FW_PARAM_PFVF(GET_SMT_START);
2045 params[1] = CXGBE_FW_PARAM_PFVF(GET_SMT_SIZE);
2047 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2048 2, params, smt_val);
2050 /* if FW doesn't recognize this command then set it to default setting
2051 * which is start index as 0 and size as 256.
2055 *smt_size = SMT_SIZE;
2057 *smt_start_idx = smt_val[0];
2058 /* smt size can be zero, if nsmt is not yet configured in
2059 * the config file or set as zero, then configure all the
2060 * remaining entries to this PF itself.
2063 *smt_size = SMT_SIZE - *smt_start_idx;
2065 *smt_size = smt_val[1];
2069 int cxgbe_probe(struct adapter *adapter)
2071 u32 smt_start_idx, smt_size;
2072 struct port_info *pi;
2078 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
2079 chip = t4_get_chip_type(adapter,
2080 CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
2084 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
2085 G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
2087 adapter->mbox = func;
2090 t4_os_lock_init(&adapter->mbox_lock);
2091 TAILQ_INIT(&adapter->mbox_list);
2092 t4_os_lock_init(&adapter->win0_lock);
2094 err = t4_prep_adapter(adapter);
2098 setup_memwin(adapter);
2099 err = adap_init0(adapter);
2101 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
2106 if (!is_t4(adapter->params.chip)) {
2108 * The userspace doorbell BAR is split evenly into doorbell
2109 * regions, each associated with an egress queue. If this
2110 * per-queue region is large enough (at least UDBS_SEG_SIZE)
2111 * then it can be used to submit a tx work request with an
2112 * implied doorbell. Enable write combining on the BAR if
2113 * there is room for such work requests.
2115 int s_qpp, qpp, num_seg;
2117 s_qpp = (S_QUEUESPERPAGEPF0 +
2118 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
2120 qpp = 1 << ((t4_read_reg(adapter,
2121 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
2122 & M_QUEUESPERPAGEPF0);
2123 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
2125 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
2127 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
2128 if (!adapter->bar2) {
2129 dev_err(adapter, "cannot map device bar2 region\n");
2133 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
2137 for_each_port(adapter, i) {
2138 const unsigned int numa_node = rte_socket_id();
2139 char name[RTE_ETH_NAME_MAX_LEN];
2140 struct rte_eth_dev *eth_dev;
2142 snprintf(name, sizeof(name), "%s_%d",
2143 adapter->pdev->device.name, i);
2146 /* First port is already allocated by DPDK */
2147 eth_dev = adapter->eth_dev;
2152 * now do all data allocation - for eth_dev structure,
2153 * and internal (private) data for the remaining ports
2156 /* reserve an ethdev entry */
2157 eth_dev = rte_eth_dev_allocate(name);
2161 eth_dev->data->dev_private =
2162 rte_zmalloc_socket(name, sizeof(struct port_info),
2163 RTE_CACHE_LINE_SIZE, numa_node);
2164 if (!eth_dev->data->dev_private)
2168 pi = eth_dev->data->dev_private;
2169 adapter->port[i] = pi;
2170 pi->eth_dev = eth_dev;
2171 pi->adapter = adapter;
2172 pi->xact_addr_filt = -1;
2176 pi->eth_dev->device = &adapter->pdev->device;
2177 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
2178 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
2179 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
2181 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
2183 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
2184 RTE_ETHER_ADDR_LEN, 0);
2185 if (!pi->eth_dev->data->mac_addrs) {
2186 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
2193 /* First port will be notified by upper layer */
2194 rte_eth_dev_probing_finish(eth_dev);
2198 if (adapter->flags & FW_OK) {
2199 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
2201 dev_err(adapter, "%s: t4_port_init failed with err %d\n",
2207 err = cxgbe_cfg_queues(adapter->eth_dev);
2211 cxgbe_print_adapter_info(adapter);
2212 cxgbe_print_port_info(adapter);
2214 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
2215 adapter->clipt_end);
2216 if (!adapter->clipt) {
2217 /* We tolerate a lack of clip_table, giving up some
2220 dev_warn(adapter, "could not allocate CLIP. Continuing\n");
2223 adap_smt_index(adapter, &smt_start_idx, &smt_size);
2224 adapter->smt = t4_init_smt(smt_start_idx, smt_size);
2226 dev_warn(adapter, "could not allocate SMT, continuing\n");
2228 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
2229 if (!adapter->l2t) {
2230 /* We tolerate a lack of L2T, giving up some functionality */
2231 dev_warn(adapter, "could not allocate L2T. Continuing\n");
2234 if (tid_init(&adapter->tids) < 0) {
2235 /* Disable filtering support */
2236 dev_warn(adapter, "could not allocate TID table, "
2237 "filter support disabled. Continuing\n");
2240 t4_os_lock_init(&adapter->flow_lock);
2242 adapter->mpstcam = t4_init_mpstcam(adapter);
2243 if (!adapter->mpstcam)
2244 dev_warn(adapter, "could not allocate mps tcam table."
2247 if (is_hashfilter(adapter)) {
2248 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) {
2249 u32 hash_base, hash_reg;
2251 hash_reg = A_LE_DB_TID_HASHBASE;
2252 hash_base = t4_read_reg(adapter, hash_reg);
2253 adapter->tids.hash_base = hash_base / 4;
2256 /* Disable hash filtering support */
2258 "Maskless filter support disabled. Continuing\n");
2261 err = cxgbe_init_rss(adapter);
2268 cxgbe_cfg_queues_free(adapter);
2270 for_each_port(adapter, i) {
2271 pi = adap2pinfo(adapter, i);
2273 t4_free_vi(adapter, adapter->mbox, adapter->pf,
2275 rte_eth_dev_release_port(pi->eth_dev);
2278 if (adapter->flags & FW_OK)
2279 t4_fw_bye(adapter, adapter->mbox);