drivers/net/cxgbe/cxgbe_main.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2014-2018 Chelsio Communications.
   3  * All rights reserved.
   4  */
   5
   6 #include <sys/queue.h>
   7 #include <stdio.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15
  16 #include <rte_byteorder.h>
  17 #include <rte_common.h>
  18 #include <rte_cycles.h>
  19 #include <rte_interrupts.h>
  20 #include <rte_log.h>
  21 #include <rte_debug.h>
  22 #include <rte_pci.h>
  23 #include <rte_atomic.h>
  24 #include <rte_branch_prediction.h>
  25 #include <rte_memory.h>
  26 #include <rte_tailq.h>
  27 #include <rte_eal.h>
  28 #include <rte_alarm.h>
  29 #include <rte_ether.h>
  30 #include <rte_ethdev_driver.h>
  31 #include <rte_ethdev_pci.h>
  32 #include <rte_random.h>
  33 #include <rte_dev.h>
  34 #include <rte_kvargs.h>
  35
  36 #include "base/common.h"
  37 #include "base/t4_regs.h"
  38 #include "base/t4_msg.h"
  39 #include "cxgbe.h"
  40 #include "clip_tbl.h"
  41 #include "l2t.h"
  42 #include "mps_tcam.h"
  43
  44 /**
  45  * Allocate a chunk of memory. The allocated memory is cleared.
  46  */
  47 void *t4_alloc_mem(size_t size)
  48 {
  49         return rte_zmalloc(NULL, size, 0);
  50 }
  51
  52 /**
  53  * Free memory allocated through t4_alloc_mem().
  54  */
  55 void t4_free_mem(void *addr)
  56 {
  57         rte_free(addr);
  58 }
  59
  60 /*
  61  * Response queue handler for the FW event queue.
  62  */
  63 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
  64                           __rte_unused const struct pkt_gl *gl)
  65 {
  66         u8 opcode = ((const struct rss_header *)rsp)->opcode;
  67
  68         rsp++;                                          /* skip RSS header */
  69
  70         /*
  71          * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
  72          */
  73         if (unlikely(opcode == CPL_FW4_MSG &&
  74                      ((const struct cpl_fw4_msg *)rsp)->type ==
  75                       FW_TYPE_RSSCPL)) {
  76                 rsp++;
  77                 opcode = ((const struct rss_header *)rsp)->opcode;
  78                 rsp++;
  79                 if (opcode != CPL_SGE_EGR_UPDATE) {
  80                         dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n",
  81                                 opcode);
  82                         goto out;
  83                 }
  84         }
  85
  86         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
  87                 /* do nothing */
  88         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
  89                 const struct cpl_fw6_msg *msg = (const void *)rsp;
  90
  91                 t4_handle_fw_rpl(q->adapter, msg->data);
  92         } else if (opcode == CPL_ABORT_RPL_RSS) {
  93                 const struct cpl_abort_rpl_rss *p = (const void *)rsp;
  94
  95                 cxgbe_hash_del_filter_rpl(q->adapter, p);
  96         } else if (opcode == CPL_SET_TCB_RPL) {
  97                 const struct cpl_set_tcb_rpl *p = (const void *)rsp;
  98
  99                 cxgbe_filter_rpl(q->adapter, p);
 100         } else if (opcode == CPL_ACT_OPEN_RPL) {
 101                 const struct cpl_act_open_rpl *p = (const void *)rsp;
 102
 103                 cxgbe_hash_filter_rpl(q->adapter, p);
 104         } else if (opcode == CPL_L2T_WRITE_RPL) {
 105                 const struct cpl_l2t_write_rpl *p = (const void *)rsp;
 106
 107                 cxgbe_do_l2t_write_rpl(q->adapter, p);
 108         } else {
 109                 dev_err(adapter, "unexpected CPL %#x on FW event queue\n",
 110                         opcode);
 111         }
 112 out:
 113         return 0;
 114 }
 115
 116 /**
 117  * Setup sge control queues to pass control information.
 118  */
 119 int cxgbe_setup_sge_ctrl_txq(struct adapter *adapter)
 120 {
 121         struct sge *s = &adapter->sge;
 122         int err = 0, i = 0;
 123
 124         for_each_port(adapter, i) {
 125                 struct port_info *pi = adap2pinfo(adapter, i);
 126                 char name[RTE_ETH_NAME_MAX_LEN];
 127                 struct sge_ctrl_txq *q = &s->ctrlq[i];
 128
 129                 q->q.size = 1024;
 130                 err = t4_sge_alloc_ctrl_txq(adapter, q,
 131                                             adapter->eth_dev,  i,
 132                                             s->fw_evtq.cntxt_id,
 133                                             rte_socket_id());
 134                 if (err) {
 135                         dev_err(adapter, "Failed to alloc ctrl txq. Err: %d",
 136                                 err);
 137                         goto out;
 138                 }
 139                 snprintf(name, sizeof(name), "%s_ctrl_pool_%d",
 140                          pi->eth_dev->device->driver->name,
 141                          pi->eth_dev->data->port_id);
 142                 q->mb_pool = rte_pktmbuf_pool_create(name, s->ctrlq[i].q.size,
 143                                                      RTE_CACHE_LINE_SIZE,
 144                                                      RTE_MBUF_PRIV_ALIGN,
 145                                                      RTE_MBUF_DEFAULT_BUF_SIZE,
 146                                                      SOCKET_ID_ANY);
 147                 if (!q->mb_pool) {
 148                         err = -rte_errno;
 149                         dev_err(adapter,
 150                                 "Can't create ctrl pool for port %d. Err: %d\n",
 151                                 pi->eth_dev->data->port_id, err);
 152                         goto out;
 153                 }
 154         }
 155         return 0;
 156 out:
 157         t4_free_sge_resources(adapter);
 158         return err;
 159 }
 160
 161 /**
 162  * cxgbe_poll_for_completion: Poll rxq for completion
 163  * @q: rxq to poll
 164  * @ms: milliseconds to delay
 165  * @cnt: number of times to poll
 166  * @c: completion to check for 'done' status
 167  *
 168  * Polls the rxq for reples until completion is done or the count
 169  * expires.
 170  */
 171 int cxgbe_poll_for_completion(struct sge_rspq *q, unsigned int ms,
 172                               unsigned int cnt, struct t4_completion *c)
 173 {
 174         unsigned int i;
 175         unsigned int work_done, budget = 32;
 176
 177         if (!c)
 178                 return -EINVAL;
 179
 180         for (i = 0; i < cnt; i++) {
 181                 cxgbe_poll(q, NULL, budget, &work_done);
 182                 t4_os_lock(&c->lock);
 183                 if (c->done) {
 184                         t4_os_unlock(&c->lock);
 185                         return 0;
 186                 }
 187                 t4_os_unlock(&c->lock);
 188                 rte_delay_ms(ms);
 189         }
 190         return -ETIMEDOUT;
 191 }
 192
 193 int cxgbe_setup_sge_fwevtq(struct adapter *adapter)
 194 {
 195         struct sge *s = &adapter->sge;
 196         int err = 0;
 197         int msi_idx = 0;
 198
 199         err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev,
 200                                msi_idx, NULL, fwevtq_handler, -1, NULL, 0,
 201                                rte_socket_id());
 202         return err;
 203 }
 204
 205 static int closest_timer(const struct sge *s, int time)
 206 {
 207         unsigned int i, match = 0;
 208         int delta, min_delta = INT_MAX;
 209
 210         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
 211                 delta = time - s->timer_val[i];
 212                 if (delta < 0)
 213                         delta = -delta;
 214                 if (delta < min_delta) {
 215                         min_delta = delta;
 216                         match = i;
 217                 }
 218         }
 219         return match;
 220 }
 221
 222 static int closest_thres(const struct sge *s, int thres)
 223 {
 224         unsigned int i, match = 0;
 225         int delta, min_delta = INT_MAX;
 226
 227         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
 228                 delta = thres - s->counter_val[i];
 229                 if (delta < 0)
 230                         delta = -delta;
 231                 if (delta < min_delta) {
 232                         min_delta = delta;
 233                         match = i;
 234                 }
 235         }
 236         return match;
 237 }
 238
 239 /**
 240  * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
 241  * @q: the Rx queue
 242  * @us: the hold-off time in us, or 0 to disable timer
 243  * @cnt: the hold-off packet count, or 0 to disable counter
 244  *
 245  * Sets an Rx queue's interrupt hold-off time and packet count.  At least
 246  * one of the two needs to be enabled for the queue to generate interrupts.
 247  */
 248 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
 249                                unsigned int cnt)
 250 {
 251         struct adapter *adap = q->adapter;
 252         unsigned int timer_val;
 253
 254         if (cnt) {
 255                 int err;
 256                 u32 v, new_idx;
 257
 258                 new_idx = closest_thres(&adap->sge, cnt);
 259                 if (q->desc && q->pktcnt_idx != new_idx) {
 260                         /* the queue has already been created, update it */
 261                         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 262                             V_FW_PARAMS_PARAM_X(
 263                             FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
 264                             V_FW_PARAMS_PARAM_YZ(q->cntxt_id);
 265                         err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
 266                                             &v, &new_idx);
 267                         if (err)
 268                                 return err;
 269                 }
 270                 q->pktcnt_idx = new_idx;
 271         }
 272
 273         timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER :
 274                                 closest_timer(&adap->sge, us);
 275
 276         if ((us | cnt) == 0)
 277                 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX);
 278         else
 279                 q->intr_params = V_QINTR_TIMER_IDX(timer_val) |
 280                                  V_QINTR_CNT_EN(cnt > 0);
 281         return 0;
 282 }
 283
 284 /**
 285  * Allocate an active-open TID and set it to the supplied value.
 286  */
 287 int cxgbe_alloc_atid(struct tid_info *t, void *data)
 288 {
 289         int atid = -1;
 290
 291         t4_os_lock(&t->atid_lock);
 292         if (t->afree) {
 293                 union aopen_entry *p = t->afree;
 294
 295                 atid = p - t->atid_tab;
 296                 t->afree = p->next;
 297                 p->data = data;
 298                 t->atids_in_use++;
 299         }
 300         t4_os_unlock(&t->atid_lock);
 301         return atid;
 302 }
 303
 304 /**
 305  * Release an active-open TID.
 306  */
 307 void cxgbe_free_atid(struct tid_info *t, unsigned int atid)
 308 {
 309         union aopen_entry *p = &t->atid_tab[atid];
 310
 311         t4_os_lock(&t->atid_lock);
 312         p->next = t->afree;
 313         t->afree = p;
 314         t->atids_in_use--;
 315         t4_os_unlock(&t->atid_lock);
 316 }
 317
 318 /**
 319  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
 320  */
 321 static void mk_tid_release(struct rte_mbuf *mbuf, unsigned int tid)
 322 {
 323         struct cpl_tid_release *req;
 324
 325         req = rte_pktmbuf_mtod(mbuf, struct cpl_tid_release *);
 326         INIT_TP_WR_MIT_CPL(req, CPL_TID_RELEASE, tid);
 327 }
 328
 329 /**
 330  * Release a TID and inform HW.  If we are unable to allocate the release
 331  * message we defer to a work queue.
 332  */
 333 void cxgbe_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid,
 334                       unsigned short family)
 335 {
 336         struct rte_mbuf *mbuf;
 337         struct adapter *adap = container_of(t, struct adapter, tids);
 338
 339         WARN_ON(tid >= t->ntids);
 340
 341         if (t->tid_tab[tid]) {
 342                 t->tid_tab[tid] = NULL;
 343                 rte_atomic32_dec(&t->conns_in_use);
 344                 if (t->hash_base && tid >= t->hash_base) {
 345                         if (family == FILTER_TYPE_IPV4)
 346                                 rte_atomic32_dec(&t->hash_tids_in_use);
 347                 } else {
 348                         if (family == FILTER_TYPE_IPV4)
 349                                 rte_atomic32_dec(&t->tids_in_use);
 350                 }
 351         }
 352
 353         mbuf = rte_pktmbuf_alloc((&adap->sge.ctrlq[chan])->mb_pool);
 354         if (mbuf) {
 355                 mbuf->data_len = sizeof(struct cpl_tid_release);
 356                 mbuf->pkt_len = mbuf->data_len;
 357                 mk_tid_release(mbuf, tid);
 358                 t4_mgmt_tx(&adap->sge.ctrlq[chan], mbuf);
 359         }
 360 }
 361
 362 /**
 363  * Insert a TID.
 364  */
 365 void cxgbe_insert_tid(struct tid_info *t, void *data, unsigned int tid,
 366                       unsigned short family)
 367 {
 368         t->tid_tab[tid] = data;
 369         if (t->hash_base && tid >= t->hash_base) {
 370                 if (family == FILTER_TYPE_IPV4)
 371                         rte_atomic32_inc(&t->hash_tids_in_use);
 372         } else {
 373                 if (family == FILTER_TYPE_IPV4)
 374                         rte_atomic32_inc(&t->tids_in_use);
 375         }
 376
 377         rte_atomic32_inc(&t->conns_in_use);
 378 }
 379
 380 /**
 381  * Free TID tables.
 382  */
 383 static void tid_free(struct tid_info *t)
 384 {
 385         if (t->tid_tab) {
 386                 if (t->ftid_bmap)
 387                         rte_bitmap_free(t->ftid_bmap);
 388
 389                 if (t->ftid_bmap_array)
 390                         t4_os_free(t->ftid_bmap_array);
 391
 392                 t4_os_free(t->tid_tab);
 393         }
 394
 395         memset(t, 0, sizeof(struct tid_info));
 396 }
 397
 398 /**
 399  * Allocate and initialize the TID tables.  Returns 0 on success.
 400  */
 401 static int tid_init(struct tid_info *t)
 402 {
 403         size_t size;
 404         unsigned int ftid_bmap_size;
 405         unsigned int natids = t->natids;
 406         unsigned int max_ftids = t->nftids;
 407
 408         ftid_bmap_size = rte_bitmap_get_memory_footprint(t->nftids);
 409         size = t->ntids * sizeof(*t->tid_tab) +
 410                 max_ftids * sizeof(*t->ftid_tab) +
 411                 natids * sizeof(*t->atid_tab);
 412
 413         t->tid_tab = t4_os_alloc(size);
 414         if (!t->tid_tab)
 415                 return -ENOMEM;
 416
 417         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
 418         t->ftid_tab = (struct filter_entry *)&t->atid_tab[t->natids];
 419         t->ftid_bmap_array = t4_os_alloc(ftid_bmap_size);
 420         if (!t->ftid_bmap_array) {
 421                 tid_free(t);
 422                 return -ENOMEM;
 423         }
 424
 425         t4_os_lock_init(&t->atid_lock);
 426         t4_os_lock_init(&t->ftid_lock);
 427
 428         t->afree = NULL;
 429         t->atids_in_use = 0;
 430         rte_atomic32_init(&t->tids_in_use);
 431         rte_atomic32_set(&t->tids_in_use, 0);
 432         rte_atomic32_init(&t->conns_in_use);
 433         rte_atomic32_set(&t->conns_in_use, 0);
 434
 435         /* Setup the free list for atid_tab and clear the stid bitmap. */
 436         if (natids) {
 437                 while (--natids)
 438                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
 439                 t->afree = t->atid_tab;
 440         }
 441
 442         t->ftid_bmap = rte_bitmap_init(t->nftids, t->ftid_bmap_array,
 443                                        ftid_bmap_size);
 444         if (!t->ftid_bmap) {
 445                 tid_free(t);
 446                 return -ENOMEM;
 447         }
 448
 449         return 0;
 450 }
 451
 452 static inline bool is_x_1g_port(const struct link_config *lc)
 453 {
 454         return (lc->pcaps & FW_PORT_CAP32_SPEED_1G) != 0;
 455 }
 456
 457 static inline bool is_x_10g_port(const struct link_config *lc)
 458 {
 459         unsigned int speeds, high_speeds;
 460
 461         speeds = V_FW_PORT_CAP32_SPEED(G_FW_PORT_CAP32_SPEED(lc->pcaps));
 462         high_speeds = speeds &
 463                       ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G);
 464
 465         return high_speeds != 0;
 466 }
 467
 468 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
 469                       unsigned int us, unsigned int cnt,
 470                       unsigned int size, unsigned int iqe_size)
 471 {
 472         q->adapter = adap;
 473         cxgb4_set_rspq_intr_params(q, us, cnt);
 474         q->iqe_len = iqe_size;
 475         q->size = size;
 476 }
 477
 478 int cxgbe_cfg_queue_count(struct rte_eth_dev *eth_dev)
 479 {
 480         struct port_info *pi = eth_dev->data->dev_private;
 481         struct adapter *adap = pi->adapter;
 482         struct sge *s = &adap->sge;
 483         unsigned int max_queues = s->max_ethqsets / adap->params.nports;
 484
 485         if ((eth_dev->data->nb_rx_queues < 1) ||
 486             (eth_dev->data->nb_tx_queues < 1))
 487                 return -EINVAL;
 488
 489         if ((eth_dev->data->nb_rx_queues > max_queues) ||
 490             (eth_dev->data->nb_tx_queues > max_queues))
 491                 return -EINVAL;
 492
 493         if (eth_dev->data->nb_rx_queues > pi->rss_size)
 494                 return -EINVAL;
 495
 496         /* We must configure RSS, since config has changed*/
 497         pi->flags &= ~PORT_RSS_DONE;
 498
 499         pi->n_rx_qsets = eth_dev->data->nb_rx_queues;
 500         pi->n_tx_qsets = eth_dev->data->nb_tx_queues;
 501
 502         return 0;
 503 }
 504
 505 void cxgbe_cfg_queues(struct rte_eth_dev *eth_dev)
 506 {
 507         struct port_info *pi = eth_dev->data->dev_private;
 508         struct adapter *adap = pi->adapter;
 509         struct sge *s = &adap->sge;
 510         unsigned int i, nb_ports = 0, qidx = 0;
 511         unsigned int q_per_port = 0;
 512
 513         if (!(adap->flags & CFG_QUEUES)) {
 514                 for_each_port(adap, i) {
 515                         struct port_info *tpi = adap2pinfo(adap, i);
 516
 517                         nb_ports += (is_x_10g_port(&tpi->link_cfg)) ||
 518                                      is_x_1g_port(&tpi->link_cfg) ? 1 : 0;
 519                 }
 520
 521                 /*
 522                  * We default up to # of cores queues per 1G/10G port.
 523                  */
 524                 if (nb_ports)
 525                         q_per_port = (s->max_ethqsets -
 526                                      (adap->params.nports - nb_ports)) /
 527                                      nb_ports;
 528
 529                 if (q_per_port > rte_lcore_count())
 530                         q_per_port = rte_lcore_count();
 531
 532                 for_each_port(adap, i) {
 533                         struct port_info *pi = adap2pinfo(adap, i);
 534
 535                         pi->first_qset = qidx;
 536
 537                         /* Initially n_rx_qsets == n_tx_qsets */
 538                         pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) ||
 539                                           is_x_1g_port(&pi->link_cfg)) ?
 540                                           q_per_port : 1;
 541                         pi->n_tx_qsets = pi->n_rx_qsets;
 542
 543                         if (pi->n_rx_qsets > pi->rss_size)
 544                                 pi->n_rx_qsets = pi->rss_size;
 545
 546                         qidx += pi->n_rx_qsets;
 547                 }
 548
 549                 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
 550                         struct sge_eth_rxq *r = &s->ethrxq[i];
 551
 552                         init_rspq(adap, &r->rspq, 5, 32, 1024, 64);
 553                         r->usembufs = 1;
 554                         r->fl.size = (r->usembufs ? 1024 : 72);
 555                 }
 556
 557                 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
 558                         s->ethtxq[i].q.size = 1024;
 559
 560                 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64);
 561                 adap->flags |= CFG_QUEUES;
 562         }
 563 }
 564
 565 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats)
 566 {
 567         t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats,
 568                                  &pi->stats_base);
 569 }
 570
 571 void cxgbe_stats_reset(struct port_info *pi)
 572 {
 573         t4_clr_port_stats(pi->adapter, pi->tx_chan);
 574 }
 575
 576 static void setup_memwin(struct adapter *adap)
 577 {
 578         u32 mem_win0_base;
 579
 580         /* For T5, only relative offset inside the PCIe BAR is passed */
 581         mem_win0_base = MEMWIN0_BASE;
 582
 583         /*
 584          * Set up memory window for accessing adapter memory ranges.  (Read
 585          * back MA register to ensure that changes propagate before we attempt
 586          * to use the new values.)
 587          */
 588         t4_write_reg(adap,
 589                      PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 590                                          MEMWIN_NIC),
 591                      mem_win0_base | V_BIR(0) |
 592                      V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT));
 593         t4_read_reg(adap,
 594                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN,
 595                                         MEMWIN_NIC));
 596 }
 597
 598 int cxgbe_init_rss(struct adapter *adap)
 599 {
 600         unsigned int i;
 601
 602         if (is_pf4(adap)) {
 603                 int err;
 604
 605                 err = t4_init_rss_mode(adap, adap->mbox);
 606                 if (err)
 607                         return err;
 608         }
 609
 610         for_each_port(adap, i) {
 611                 struct port_info *pi = adap2pinfo(adap, i);
 612
 613                 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
 614                 if (!pi->rss)
 615                         return -ENOMEM;
 616
 617                 pi->rss_hf = CXGBE_RSS_HF_ALL;
 618         }
 619         return 0;
 620 }
 621
 622 /**
 623  * Dump basic information about the adapter.
 624  */
 625 void cxgbe_print_adapter_info(struct adapter *adap)
 626 {
 627         /**
 628          * Hardware/Firmware/etc. Version/Revision IDs.
 629          */
 630         t4_dump_version_info(adap);
 631 }
 632
 633 void cxgbe_print_port_info(struct adapter *adap)
 634 {
 635         int i;
 636         char buf[80];
 637         struct rte_pci_addr *loc = &adap->pdev->addr;
 638
 639         for_each_port(adap, i) {
 640                 const struct port_info *pi = adap2pinfo(adap, i);
 641                 char *bufp = buf;
 642
 643                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M)
 644                         bufp += sprintf(bufp, "100M/");
 645                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G)
 646                         bufp += sprintf(bufp, "1G/");
 647                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G)
 648                         bufp += sprintf(bufp, "10G/");
 649                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G)
 650                         bufp += sprintf(bufp, "25G/");
 651                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G)
 652                         bufp += sprintf(bufp, "40G/");
 653                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G)
 654                         bufp += sprintf(bufp, "50G/");
 655                 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G)
 656                         bufp += sprintf(bufp, "100G/");
 657                 if (bufp != buf)
 658                         --bufp;
 659                 sprintf(bufp, "BASE-%s",
 660                         t4_get_port_type_description(
 661                                         (enum fw_port_type)pi->port_type));
 662
 663                 dev_info(adap,
 664                          " " PCI_PRI_FMT " Chelsio rev %d %s %s\n",
 665                          loc->domain, loc->bus, loc->devid, loc->function,
 666                          CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
 667                          (adap->flags & USING_MSIX) ? " MSI-X" :
 668                          (adap->flags & USING_MSI) ? " MSI" : "");
 669         }
 670 }
 671
 672 static int check_devargs_handler(const char *key, const char *value, void *p)
 673 {
 674         if (!strncmp(key, CXGBE_DEVARG_CMN_KEEP_OVLAN, strlen(key)) ||
 675             !strncmp(key, CXGBE_DEVARG_VF_FORCE_LINK_UP, strlen(key))) {
 676                 if (!strncmp(value, "1", 1)) {
 677                         bool *dst_val = (bool *)p;
 678
 679                         *dst_val = true;
 680                 }
 681         }
 682
 683         return 0;
 684 }
 685
 686 static int cxgbe_get_devargs(struct rte_devargs *devargs, const char *key,
 687                              void *p)
 688 {
 689         struct rte_kvargs *kvlist;
 690         int ret = 0;
 691
 692         if (!devargs)
 693                 return 0;
 694
 695         kvlist = rte_kvargs_parse(devargs->args, NULL);
 696         if (!kvlist)
 697                 return 0;
 698
 699         if (!rte_kvargs_count(kvlist, key))
 700                 goto out;
 701
 702         ret = rte_kvargs_process(kvlist, key, check_devargs_handler, p);
 703
 704 out:
 705         rte_kvargs_free(kvlist);
 706
 707         return ret;
 708 }
 709
 710 static void cxgbe_get_devargs_int(struct adapter *adap, int *dst,
 711                                   const char *key, int default_value)
 712 {
 713         struct rte_pci_device *pdev = adap->pdev;
 714         int ret, devarg_value = default_value;
 715
 716         *dst = default_value;
 717         if (!pdev)
 718                 return;
 719
 720         ret = cxgbe_get_devargs(pdev->device.devargs, key, &devarg_value);
 721         if (ret)
 722                 return;
 723
 724         *dst = devarg_value;
 725 }
 726
 727 void cxgbe_process_devargs(struct adapter *adap)
 728 {
 729         cxgbe_get_devargs_int(adap, &adap->devargs.keep_ovlan,
 730                               CXGBE_DEVARG_CMN_KEEP_OVLAN, 0);
 731         cxgbe_get_devargs_int(adap, &adap->devargs.force_link_up,
 732                               CXGBE_DEVARG_VF_FORCE_LINK_UP, 0);
 733 }
 734
 735 static void configure_vlan_types(struct adapter *adapter)
 736 {
 737         int i;
 738
 739         for_each_port(adapter, i) {
 740                 /* OVLAN Type 0x88a8 */
 741                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN0),
 742                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 743                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 744                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 745                                  V_OVLAN_ETYPE(0x88a8));
 746                 /* OVLAN Type 0x9100 */
 747                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN1),
 748                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 749                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 750                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 751                                  V_OVLAN_ETYPE(0x9100));
 752                 /* OVLAN Type 0x8100 */
 753                 t4_set_reg_field(adapter, MPS_PORT_RX_OVLAN_REG(i, A_RX_OVLAN2),
 754                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 755                                  V_OVLAN_ETYPE(M_OVLAN_ETYPE),
 756                                  V_OVLAN_MASK(M_OVLAN_MASK) |
 757                                  V_OVLAN_ETYPE(0x8100));
 758
 759                 /* IVLAN 0X8100 */
 760                 t4_set_reg_field(adapter, MPS_PORT_RX_IVLAN(i),
 761                                  V_IVLAN_ETYPE(M_IVLAN_ETYPE),
 762                                  V_IVLAN_ETYPE(0x8100));
 763
 764                 t4_set_reg_field(adapter, MPS_PORT_RX_CTL(i),
 765                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 766                                  F_OVLAN_EN2 | F_IVLAN_EN,
 767                                  F_OVLAN_EN0 | F_OVLAN_EN1 |
 768                                  F_OVLAN_EN2 | F_IVLAN_EN);
 769         }
 770
 771         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, V_RM_OVLAN(1),
 772                                V_RM_OVLAN(!adapter->devargs.keep_ovlan));
 773 }
 774
 775 static void configure_pcie_ext_tag(struct adapter *adapter)
 776 {
 777         u16 v;
 778         int pos = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
 779
 780         if (!pos)
 781                 return;
 782
 783         if (pos > 0) {
 784                 t4_os_pci_read_cfg2(adapter, pos + PCI_EXP_DEVCTL, &v);
 785                 v |= PCI_EXP_DEVCTL_EXT_TAG;
 786                 t4_os_pci_write_cfg2(adapter, pos + PCI_EXP_DEVCTL, v);
 787                 if (is_t6(adapter->params.chip)) {
 788                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 789                                          V_T6_TOTMAXTAG(M_T6_TOTMAXTAG),
 790                                          V_T6_TOTMAXTAG(7));
 791                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 792                                          V_T6_MINTAG(M_T6_MINTAG),
 793                                          V_T6_MINTAG(8));
 794                 } else {
 795                         t4_set_reg_field(adapter, A_PCIE_CFG2,
 796                                          V_TOTMAXTAG(M_TOTMAXTAG),
 797                                          V_TOTMAXTAG(3));
 798                         t4_set_reg_field(adapter, A_PCIE_CMD_CFG,
 799                                          V_MINTAG(M_MINTAG),
 800                                          V_MINTAG(8));
 801                 }
 802         }
 803 }
 804
 805 /* Figure out how many Queue Sets we can support */
 806 void cxgbe_configure_max_ethqsets(struct adapter *adapter)
 807 {
 808         unsigned int ethqsets;
 809
 810         /*
 811          * We need to reserve an Ingress Queue for the Asynchronous Firmware
 812          * Event Queue.
 813          *
 814          * For each Queue Set, we'll need the ability to allocate two Egress
 815          * Contexts -- one for the Ingress Queue Free List and one for the TX
 816          * Ethernet Queue.
 817          */
 818         if (is_pf4(adapter)) {
 819                 struct pf_resources *pfres = &adapter->params.pfres;
 820
 821                 ethqsets = pfres->niqflint - 1;
 822                 if (pfres->neq < ethqsets * 2)
 823                         ethqsets = pfres->neq / 2;
 824         } else {
 825                 struct vf_resources *vfres = &adapter->params.vfres;
 826
 827                 ethqsets = vfres->niqflint - 1;
 828                 if (vfres->nethctrl != ethqsets)
 829                         ethqsets = min(vfres->nethctrl, ethqsets);
 830                 if (vfres->neq < ethqsets * 2)
 831                         ethqsets = vfres->neq / 2;
 832         }
 833
 834         if (ethqsets > MAX_ETH_QSETS)
 835                 ethqsets = MAX_ETH_QSETS;
 836         adapter->sge.max_ethqsets = ethqsets;
 837 }
 838
 839 /*
 840  * Tweak configuration based on system architecture, etc.  Most of these have
 841  * defaults assigned to them by Firmware Configuration Files (if we're using
 842  * them) but need to be explicitly set if we're using hard-coded
 843  * initialization. So these are essentially common tweaks/settings for
 844  * Configuration Files and hard-coded initialization ...
 845  */
 846 static int adap_init0_tweaks(struct adapter *adapter)
 847 {
 848         u8 rx_dma_offset;
 849
 850         /*
 851          * Fix up various Host-Dependent Parameters like Page Size, Cache
 852          * Line Size, etc.  The firmware default is for a 4KB Page Size and
 853          * 64B Cache Line Size ...
 854          */
 855         t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES,
 856                                     T5_LAST_REV);
 857
 858         /*
 859          * Keep the chip default offset to deliver Ingress packets into our
 860          * DMA buffers to zero
 861          */
 862         rx_dma_offset = 0;
 863         t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT),
 864                          V_PKTSHIFT(rx_dma_offset));
 865
 866         t4_set_reg_field(adapter, A_SGE_FLM_CFG,
 867                          V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING,
 868                          V_CREDITCNT(3) | V_CREDITCNTPACKING(1));
 869
 870         t4_set_reg_field(adapter, A_SGE_INGRESS_RX_THRESHOLD,
 871                          V_THRESHOLD_3(M_THRESHOLD_3), V_THRESHOLD_3(32U));
 872
 873         t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U),
 874                          V_IDMAARBROUNDROBIN(1U));
 875
 876         /*
 877          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
 878          * adds the pseudo header itself.
 879          */
 880         t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG,
 881                                F_CSUM_HAS_PSEUDO_HDR, 0);
 882
 883         return 0;
 884 }
 885
 886 /*
 887  * Attempt to initialize the adapter via a Firmware Configuration File.
 888  */
 889 static int adap_init0_config(struct adapter *adapter, int reset)
 890 {
 891         struct fw_caps_config_cmd caps_cmd;
 892         unsigned long mtype = 0, maddr = 0;
 893         u32 finiver, finicsum, cfcsum;
 894         int ret;
 895         int config_issued = 0;
 896         int cfg_addr;
 897         char config_name[20];
 898
 899         /*
 900          * Reset device if necessary.
 901          */
 902         if (reset) {
 903                 ret = t4_fw_reset(adapter, adapter->mbox,
 904                                   F_PIORSTMODE | F_PIORST);
 905                 if (ret < 0) {
 906                         dev_warn(adapter, "Firmware reset failed, error %d\n",
 907                                  -ret);
 908                         goto bye;
 909                 }
 910         }
 911
 912         cfg_addr = t4_flash_cfg_addr(adapter);
 913         if (cfg_addr < 0) {
 914                 ret = cfg_addr;
 915                 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n",
 916                          -ret);
 917                 goto bye;
 918         }
 919
 920         strcpy(config_name, "On Flash");
 921         mtype = FW_MEMTYPE_CF_FLASH;
 922         maddr = cfg_addr;
 923
 924         /*
 925          * Issue a Capability Configuration command to the firmware to get it
 926          * to parse the Configuration File.  We don't use t4_fw_config_file()
 927          * because we want the ability to modify various features after we've
 928          * processed the configuration file ...
 929          */
 930         memset(&caps_cmd, 0, sizeof(caps_cmd));
 931         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 932                                            F_FW_CMD_REQUEST | F_FW_CMD_READ);
 933         caps_cmd.cfvalid_to_len16 =
 934                 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID |
 935                             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
 936                             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
 937                             FW_LEN16(caps_cmd));
 938         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 939                          &caps_cmd);
 940         /*
 941          * If the CAPS_CONFIG failed with an ENOENT (for a Firmware
 942          * Configuration File in FLASH), our last gasp effort is to use the
 943          * Firmware Configuration File which is embedded in the firmware.  A
 944          * very few early versions of the firmware didn't have one embedded
 945          * but we can ignore those.
 946          */
 947         if (ret == -ENOENT) {
 948                 dev_info(adapter, "%s: Going for embedded config in firmware..\n",
 949                          __func__);
 950
 951                 memset(&caps_cmd, 0, sizeof(caps_cmd));
 952                 caps_cmd.op_to_write =
 953                         cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 954                                     F_FW_CMD_REQUEST | F_FW_CMD_READ);
 955                 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd));
 956                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
 957                                  sizeof(caps_cmd), &caps_cmd);
 958                 strcpy(config_name, "Firmware Default");
 959         }
 960
 961         config_issued = 1;
 962         if (ret < 0)
 963                 goto bye;
 964
 965         finiver = be32_to_cpu(caps_cmd.finiver);
 966         finicsum = be32_to_cpu(caps_cmd.finicsum);
 967         cfcsum = be32_to_cpu(caps_cmd.cfcsum);
 968         if (finicsum != cfcsum)
 969                 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n",
 970                          finicsum, cfcsum);
 971
 972         /*
 973          * If we're a pure NIC driver then disable all offloading facilities.
 974          * This will allow the firmware to optimize aspects of the hardware
 975          * configuration which will result in improved performance.
 976          */
 977         caps_cmd.niccaps &= cpu_to_be16(~FW_CAPS_CONFIG_NIC_ETHOFLD);
 978         caps_cmd.toecaps = 0;
 979         caps_cmd.iscsicaps = 0;
 980         caps_cmd.rdmacaps = 0;
 981         caps_cmd.fcoecaps = 0;
 982
 983         /*
 984          * And now tell the firmware to use the configuration we just loaded.
 985          */
 986         caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
 987                                            F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
 988         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
 989         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
 990                          NULL);
 991         if (ret < 0) {
 992                 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n",
 993                          -ret);
 994                 goto bye;
 995         }
 996
 997         /*
 998          * Tweak configuration based on system architecture, etc.
 999          */
1000         ret = adap_init0_tweaks(adapter);
1001         if (ret < 0) {
1002                 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret);
1003                 goto bye;
1004         }
1005
1006         /*
1007          * And finally tell the firmware to initialize itself using the
1008          * parameters from the Configuration File.
1009          */
1010         ret = t4_fw_initialize(adapter, adapter->mbox);
1011         if (ret < 0) {
1012                 dev_warn(adapter, "Initializing Firmware failed, error %d\n",
1013                          -ret);
1014                 goto bye;
1015         }
1016
1017         /*
1018          * Return successfully and note that we're operating with parameters
1019          * not supplied by the driver, rather than from hard-wired
1020          * initialization constants buried in the driver.
1021          */
1022         dev_info(adapter,
1023                  "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n",
1024                  config_name, finiver, cfcsum);
1025
1026         return 0;
1027
1028         /*
1029          * Something bad happened.  Return the error ...  (If the "error"
1030          * is that there's no Configuration File on the adapter we don't
1031          * want to issue a warning since this is fairly common.)
1032          */
1033 bye:
1034         if (config_issued && ret != -ENOENT)
1035                 dev_warn(adapter, "\"%s\" configuration file error %d\n",
1036                          config_name, -ret);
1037
1038         dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret);
1039         return ret;
1040 }
1041
1042 static int adap_init0(struct adapter *adap)
1043 {
1044         struct fw_caps_config_cmd caps_cmd;
1045         int ret = 0;
1046         u32 v, port_vec;
1047         enum dev_state state;
1048         u32 params[7], val[7];
1049         int reset = 1;
1050         int mbox = adap->mbox;
1051
1052         /*
1053          * Contact FW, advertising Master capability.
1054          */
1055         ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
1056         if (ret < 0) {
1057                 dev_err(adap, "%s: could not connect to FW, error %d\n",
1058                         __func__, -ret);
1059                 goto bye;
1060         }
1061
1062         CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__,
1063                          adap->mbox, ret);
1064
1065         if (ret == mbox)
1066                 adap->flags |= MASTER_PF;
1067
1068         if (state == DEV_STATE_INIT) {
1069                 /*
1070                  * Force halt and reset FW because a previous instance may have
1071                  * exited abnormally without properly shutting down
1072                  */
1073                 ret = t4_fw_halt(adap, adap->mbox, reset);
1074                 if (ret < 0) {
1075                         dev_err(adap, "Failed to halt. Exit.\n");
1076                         goto bye;
1077                 }
1078
1079                 ret = t4_fw_restart(adap, adap->mbox, reset);
1080                 if (ret < 0) {
1081                         dev_err(adap, "Failed to restart. Exit.\n");
1082                         goto bye;
1083                 }
1084                 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT);
1085         }
1086
1087         t4_get_version_info(adap);
1088
1089         ret = t4_get_core_clock(adap, &adap->params.vpd);
1090         if (ret < 0) {
1091                 dev_err(adap, "%s: could not get core clock, error %d\n",
1092                         __func__, -ret);
1093                 goto bye;
1094         }
1095
1096         /*
1097          * If the firmware is initialized already (and we're not forcing a
1098          * master initialization), note that we're living with existing
1099          * adapter parameters.  Otherwise, it's time to try initializing the
1100          * adapter ...
1101          */
1102         if (state == DEV_STATE_INIT) {
1103                 dev_info(adap, "Coming up as %s: Adapter already initialized\n",
1104                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
1105         } else {
1106                 dev_info(adap, "Coming up as MASTER: Initializing adapter\n");
1107
1108                 ret = adap_init0_config(adap, reset);
1109                 if (ret == -ENOENT) {
1110                         dev_err(adap,
1111                                 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n");
1112                         goto bye;
1113                 }
1114         }
1115         if (ret < 0) {
1116                 dev_err(adap, "could not initialize adapter, error %d\n", -ret);
1117                 goto bye;
1118         }
1119
1120         /* Now that we've successfully configured and initialized the adapter
1121          * (or found it already initialized), we can ask the Firmware what
1122          * resources it has provisioned for us.
1123          */
1124         ret = t4_get_pfres(adap);
1125         if (ret) {
1126                 dev_err(adap->pdev_dev,
1127                         "Unable to retrieve resource provisioning info\n");
1128                 goto bye;
1129         }
1130
1131         /* Find out what ports are available to us. */
1132         v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1133             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
1134         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
1135         if (ret < 0) {
1136                 dev_err(adap, "%s: failure in t4_query_params; error = %d\n",
1137                         __func__, ret);
1138                 goto bye;
1139         }
1140
1141         adap->params.nports = hweight32(port_vec);
1142         adap->params.portvec = port_vec;
1143
1144         dev_debug(adap, "%s: adap->params.nports = %u\n", __func__,
1145                   adap->params.nports);
1146
1147         /*
1148          * Give the SGE code a chance to pull in anything that it needs ...
1149          * Note that this must be called after we retrieve our VPD parameters
1150          * in order to know how to convert core ticks to seconds, etc.
1151          */
1152         ret = t4_sge_init(adap);
1153         if (ret < 0) {
1154                 dev_err(adap, "t4_sge_init failed with error %d\n",
1155                         -ret);
1156                 goto bye;
1157         }
1158
1159         /*
1160          * Grab some of our basic fundamental operating parameters.
1161          */
1162 #define FW_PARAM_DEV(param) \
1163         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
1164          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
1165
1166 #define FW_PARAM_PFVF(param) \
1167         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
1168          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) |  \
1169          V_FW_PARAMS_PARAM_Y(0) | \
1170          V_FW_PARAMS_PARAM_Z(0))
1171
1172         params[0] = FW_PARAM_PFVF(L2T_START);
1173         params[1] = FW_PARAM_PFVF(L2T_END);
1174         params[2] = FW_PARAM_PFVF(FILTER_START);
1175         params[3] = FW_PARAM_PFVF(FILTER_END);
1176         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4, params, val);
1177         if (ret < 0)
1178                 goto bye;
1179         adap->l2t_start = val[0];
1180         adap->l2t_end = val[1];
1181         adap->tids.ftid_base = val[2];
1182         adap->tids.nftids = val[3] - val[2] + 1;
1183
1184         params[0] = FW_PARAM_PFVF(CLIP_START);
1185         params[1] = FW_PARAM_PFVF(CLIP_END);
1186         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
1187         if (ret < 0)
1188                 goto bye;
1189         adap->clipt_start = val[0];
1190         adap->clipt_end = val[1];
1191
1192         /*
1193          * Get device capabilities so we can determine what resources we need
1194          * to manage.
1195          */
1196         memset(&caps_cmd, 0, sizeof(caps_cmd));
1197         caps_cmd.op_to_write = htonl(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
1198                                      F_FW_CMD_REQUEST | F_FW_CMD_READ);
1199         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
1200         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
1201                          &caps_cmd);
1202         if (ret < 0)
1203                 goto bye;
1204
1205         if ((caps_cmd.niccaps & cpu_to_be16(FW_CAPS_CONFIG_NIC_HASHFILTER)) &&
1206             is_t6(adap->params.chip)) {
1207                 if (cxgbe_init_hash_filter(adap) < 0)
1208                         goto bye;
1209         }
1210
1211         /* See if FW supports FW_FILTER2 work request */
1212         if (is_t4(adap->params.chip)) {
1213                 adap->params.filter2_wr_support = 0;
1214         } else {
1215                 params[0] = FW_PARAM_DEV(FILTER2_WR);
1216                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1217                                       1, params, val);
1218                 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0);
1219         }
1220
1221         /* query tid-related parameters */
1222         params[0] = FW_PARAM_DEV(NTID);
1223         ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
1224                               params, val);
1225         if (ret < 0)
1226                 goto bye;
1227         adap->tids.ntids = val[0];
1228         adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
1229
1230         /* If we're running on newer firmware, let it know that we're
1231          * prepared to deal with encapsulated CPL messages.  Older
1232          * firmware won't understand this and we'll just get
1233          * unencapsulated messages ...
1234          */
1235         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
1236         val[0] = 1;
1237         (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
1238
1239         /*
1240          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
1241          * capability.  Earlier versions of the firmware didn't have the
1242          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
1243          * permission to use ULPTX MEMWRITE DSGL.
1244          */
1245         if (is_t4(adap->params.chip)) {
1246                 adap->params.ulptx_memwrite_dsgl = false;
1247         } else {
1248                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
1249                 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
1250                                       1, params, val);
1251                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
1252         }
1253
1254         /*
1255          * The MTU/MSS Table is initialized by now, so load their values.  If
1256          * we're initializing the adapter, then we'll make any modifications
1257          * we want to the MTU/MSS Table and also initialize the congestion
1258          * parameters.
1259          */
1260         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
1261         if (state != DEV_STATE_INIT) {
1262                 int i;
1263
1264                 /*
1265                  * The default MTU Table contains values 1492 and 1500.
1266                  * However, for TCP, it's better to have two values which are
1267                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
1268                  * This allows us to have a TCP Data Payload which is a
1269                  * multiple of 8 regardless of what combination of TCP Options
1270                  * are in use (always a multiple of 4 bytes) which is
1271                  * important for performance reasons.  For instance, if no
1272                  * options are in use, then we have a 20-byte IP header and a
1273                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
1274                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
1275                  * which is not a multiple of 8.  So using an MSS of 1488 in
1276                  * this case results in a TCP Data Payload of 1448 bytes which
1277                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
1278                  * Stamps have been negotiated, then an MTU of 1500 bytes
1279                  * results in a TCP Data Payload of 1448 bytes which, as
1280                  * above, is a multiple of 8 bytes ...
1281                  */
1282                 for (i = 0; i < NMTUS; i++)
1283                         if (adap->params.mtus[i] == 1492) {
1284                                 adap->params.mtus[i] = 1488;
1285                                 break;
1286                         }
1287
1288                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
1289                              adap->params.b_wnd);
1290         }
1291         t4_init_sge_params(adap);
1292         t4_init_tp_params(adap);
1293         configure_pcie_ext_tag(adap);
1294         configure_vlan_types(adap);
1295         cxgbe_configure_max_ethqsets(adap);
1296
1297         adap->params.drv_memwin = MEMWIN_NIC;
1298         adap->flags |= FW_OK;
1299         dev_debug(adap, "%s: returning zero..\n", __func__);
1300         return 0;
1301
1302         /*
1303          * Something bad happened.  If a command timed out or failed with EIO
1304          * FW does not operate within its spec or something catastrophic
1305          * happened to HW/FW, stop issuing commands.
1306          */
1307 bye:
1308         if (ret != -ETIMEDOUT && ret != -EIO)
1309                 t4_fw_bye(adap, adap->mbox);
1310         return ret;
1311 }
1312
1313 /**
1314  * t4_os_portmod_changed - handle port module changes
1315  * @adap: the adapter associated with the module change
1316  * @port_id: the port index whose module status has changed
1317  *
1318  * This is the OS-dependent handler for port module changes.  It is
1319  * invoked when a port module is removed or inserted for any OS-specific
1320  * processing.
1321  */
1322 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
1323 {
1324         static const char * const mod_str[] = {
1325                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
1326         };
1327
1328         const struct port_info *pi = adap2pinfo(adap, port_id);
1329
1330         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
1331                 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id);
1332         else if (pi->mod_type < ARRAY_SIZE(mod_str))
1333                 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id,
1334                          mod_str[pi->mod_type]);
1335         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
1336                 dev_info(adap, "Port%d: unsupported port module inserted\n",
1337                          pi->port_id);
1338         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
1339                 dev_info(adap, "Port%d: unknown port module inserted\n",
1340                          pi->port_id);
1341         else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
1342                 dev_info(adap, "Port%d: transceiver module error\n",
1343                          pi->port_id);
1344         else
1345                 dev_info(adap, "Port%d: unknown module type %d inserted\n",
1346                          pi->port_id, pi->mod_type);
1347 }
1348
1349 bool cxgbe_force_linkup(struct adapter *adap)
1350 {
1351         if (is_pf4(adap))
1352                 return false;   /* force_linkup not required for pf driver */
1353
1354         return adap->devargs.force_link_up;
1355 }
1356
1357 /**
1358  * link_start - enable a port
1359  * @dev: the port to enable
1360  *
1361  * Performs the MAC and PHY actions needed to enable a port.
1362  */
1363 int cxgbe_link_start(struct port_info *pi)
1364 {
1365         struct adapter *adapter = pi->adapter;
1366         u64 conf_offloads;
1367         unsigned int mtu;
1368         int ret;
1369
1370         mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1371               (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN);
1372
1373         conf_offloads = pi->eth_dev->data->dev_conf.rxmode.offloads;
1374
1375         /*
1376          * We do not set address filters and promiscuity here, the stack does
1377          * that step explicitly.
1378          */
1379         ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, -1,
1380                             !!(conf_offloads & DEV_RX_OFFLOAD_VLAN_STRIP),
1381                             true);
1382         if (ret == 0) {
1383                 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt,
1384                                 (u8 *)&pi->eth_dev->data->mac_addrs[0]);
1385                 if (ret >= 0) {
1386                         pi->xact_addr_filt = ret;
1387                         ret = 0;
1388                 }
1389         }
1390         if (ret == 0 && is_pf4(adapter))
1391                 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan,
1392                                     &pi->link_cfg);
1393         if (ret == 0) {
1394                 /*
1395                  * Enabling a Virtual Interface can result in an interrupt
1396                  * during the processing of the VI Enable command and, in some
1397                  * paths, result in an attempt to issue another command in the
1398                  * interrupt context.  Thus, we disable interrupts during the
1399                  * course of the VI Enable command ...
1400                  */
1401                 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid,
1402                                           true, true, false);
1403         }
1404
1405         if (ret == 0 && cxgbe_force_linkup(adapter))
1406                 pi->eth_dev->data->dev_link.link_status = ETH_LINK_UP;
1407         return ret;
1408 }
1409
1410 /**
1411  * cxgbe_write_rss_conf - flash the RSS configuration for a given port
1412  * @pi: the port
1413  * @rss_hf: Hash configuration to apply
1414  */
1415 int cxgbe_write_rss_conf(const struct port_info *pi, uint64_t rss_hf)
1416 {
1417         struct adapter *adapter = pi->adapter;
1418         const struct sge_eth_rxq *rxq;
1419         u64 flags = 0;
1420         u16 rss;
1421         int err;
1422
1423         /*  Should never be called before setting up sge eth rx queues */
1424         if (!(adapter->flags & FULL_INIT_DONE)) {
1425                 dev_err(adap, "%s No RXQs available on port %d\n",
1426                         __func__, pi->port_id);
1427                 return -EINVAL;
1428         }
1429
1430         /* Don't allow unsupported hash functions */
1431         if (rss_hf & ~CXGBE_RSS_HF_ALL)
1432                 return -EINVAL;
1433
1434         if (rss_hf & CXGBE_RSS_HF_IPV4_MASK)
1435                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
1436
1437         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
1438                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
1439
1440         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
1441                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
1442                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1443
1444         if (rss_hf & CXGBE_RSS_HF_IPV6_MASK)
1445                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
1446
1447         if (rss_hf & CXGBE_RSS_HF_TCP_IPV6_MASK)
1448                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1449                          F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
1450
1451         if (rss_hf & CXGBE_RSS_HF_UDP_IPV6_MASK)
1452                 flags |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
1453                          F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
1454                          F_FW_RSS_VI_CONFIG_CMD_UDPEN;
1455
1456         rxq = &adapter->sge.ethrxq[pi->first_qset];
1457         rss = rxq[0].rspq.abs_id;
1458
1459         /* If Tunnel All Lookup isn't specified in the global RSS
1460          * Configuration, then we need to specify a default Ingress
1461          * Queue for any ingress packets which aren't hashed.  We'll
1462          * use our first ingress queue ...
1463          */
1464         err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
1465                                flags, rss);
1466         return err;
1467 }
1468
1469 /**
1470  * cxgbe_write_rss - write the RSS table for a given port
1471  * @pi: the port
1472  * @queues: array of queue indices for RSS
1473  *
1474  * Sets up the portion of the HW RSS table for the port's VI to distribute
1475  * packets to the Rx queues in @queues.
1476  */
1477 int cxgbe_write_rss(const struct port_info *pi, const u16 *queues)
1478 {
1479         u16 *rss;
1480         int i, err;
1481         struct adapter *adapter = pi->adapter;
1482         const struct sge_eth_rxq *rxq;
1483
1484         /*  Should never be called before setting up sge eth rx queues */
1485         BUG_ON(!(adapter->flags & FULL_INIT_DONE));
1486
1487         rxq = &adapter->sge.ethrxq[pi->first_qset];
1488         rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0);
1489         if (!rss)
1490                 return -ENOMEM;
1491
1492         /* map the queue indices to queue ids */
1493         for (i = 0; i < pi->rss_size; i++, queues++)
1494                 rss[i] = rxq[*queues].rspq.abs_id;
1495
1496         err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
1497                                   pi->rss_size, rss, pi->rss_size);
1498         rte_free(rss);
1499         return err;
1500 }
1501
1502 /**
1503  * setup_rss - configure RSS
1504  * @adapter: the adapter
1505  *
1506  * Sets up RSS to distribute packets to multiple receive queues.  We
1507  * configure the RSS CPU lookup table to distribute to the number of HW
1508  * receive queues, and the response queue lookup table to narrow that
1509  * down to the response queues actually configured for each port.
1510  * We always configure the RSS mapping for all ports since the mapping
1511  * table has plenty of entries.
1512  */
1513 int cxgbe_setup_rss(struct port_info *pi)
1514 {
1515         int j, err;
1516         struct adapter *adapter = pi->adapter;
1517
1518         dev_debug(adapter, "%s:  pi->rss_size = %u; pi->n_rx_qsets = %u\n",
1519                   __func__, pi->rss_size, pi->n_rx_qsets);
1520
1521         if (!(pi->flags & PORT_RSS_DONE)) {
1522                 if (adapter->flags & FULL_INIT_DONE) {
1523                         /* Fill default values with equal distribution */
1524                         for (j = 0; j < pi->rss_size; j++)
1525                                 pi->rss[j] = j % pi->n_rx_qsets;
1526
1527                         err = cxgbe_write_rss(pi, pi->rss);
1528                         if (err)
1529                                 return err;
1530
1531                         err = cxgbe_write_rss_conf(pi, pi->rss_hf);
1532                         if (err)
1533                                 return err;
1534                         pi->flags |= PORT_RSS_DONE;
1535                 }
1536         }
1537         return 0;
1538 }
1539
1540 /*
1541  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1542  */
1543 static void enable_rx(struct adapter *adap, struct sge_rspq *q)
1544 {
1545         /* 0-increment GTS to start the timer and enable interrupts */
1546         t4_write_reg(adap, is_pf4(adap) ? MYPF_REG(A_SGE_PF_GTS) :
1547                                           T4VF_SGE_BASE_ADDR + A_SGE_VF_GTS,
1548                      V_SEINTARM(q->intr_params) |
1549                      V_INGRESSQID(q->cntxt_id));
1550 }
1551
1552 void cxgbe_enable_rx_queues(struct port_info *pi)
1553 {
1554         struct adapter *adap = pi->adapter;
1555         struct sge *s = &adap->sge;
1556         unsigned int i;
1557
1558         for (i = 0; i < pi->n_rx_qsets; i++)
1559                 enable_rx(adap, &s->ethrxq[pi->first_qset + i].rspq);
1560 }
1561
1562 /**
1563  * fw_caps_to_speed_caps - translate Firmware Port Caps to Speed Caps.
1564  * @port_type: Firmware Port Type
1565  * @fw_caps: Firmware Port Capabilities
1566  * @speed_caps: Device Info Speed Capabilities
1567  *
1568  * Translate a Firmware Port Capabilities specification to Device Info
1569  * Speed Capabilities.
1570  */
1571 static void fw_caps_to_speed_caps(enum fw_port_type port_type,
1572                                   unsigned int fw_caps,
1573                                   u32 *speed_caps)
1574 {
1575 #define SET_SPEED(__speed_name) \
1576         do { \
1577                 *speed_caps |= ETH_LINK_ ## __speed_name; \
1578         } while (0)
1579
1580 #define FW_CAPS_TO_SPEED(__fw_name) \
1581         do { \
1582                 if (fw_caps & FW_PORT_CAP32_ ## __fw_name) \
1583                         SET_SPEED(__fw_name); \
1584         } while (0)
1585
1586         switch (port_type) {
1587         case FW_PORT_TYPE_BT_SGMII:
1588         case FW_PORT_TYPE_BT_XFI:
1589         case FW_PORT_TYPE_BT_XAUI:
1590                 FW_CAPS_TO_SPEED(SPEED_100M);
1591                 FW_CAPS_TO_SPEED(SPEED_1G);
1592                 FW_CAPS_TO_SPEED(SPEED_10G);
1593                 break;
1594
1595         case FW_PORT_TYPE_KX4:
1596         case FW_PORT_TYPE_KX:
1597         case FW_PORT_TYPE_FIBER_XFI:
1598         case FW_PORT_TYPE_FIBER_XAUI:
1599         case FW_PORT_TYPE_SFP:
1600         case FW_PORT_TYPE_QSFP_10G:
1601         case FW_PORT_TYPE_QSA:
1602                 FW_CAPS_TO_SPEED(SPEED_1G);
1603                 FW_CAPS_TO_SPEED(SPEED_10G);
1604                 break;
1605
1606         case FW_PORT_TYPE_KR:
1607                 SET_SPEED(SPEED_10G);
1608                 break;
1609
1610         case FW_PORT_TYPE_BP_AP:
1611         case FW_PORT_TYPE_BP4_AP:
1612                 SET_SPEED(SPEED_1G);
1613                 SET_SPEED(SPEED_10G);
1614                 break;
1615
1616         case FW_PORT_TYPE_BP40_BA:
1617         case FW_PORT_TYPE_QSFP:
1618                 SET_SPEED(SPEED_40G);
1619                 break;
1620
1621         case FW_PORT_TYPE_CR_QSFP:
1622         case FW_PORT_TYPE_SFP28:
1623         case FW_PORT_TYPE_KR_SFP28:
1624                 FW_CAPS_TO_SPEED(SPEED_1G);
1625                 FW_CAPS_TO_SPEED(SPEED_10G);
1626                 FW_CAPS_TO_SPEED(SPEED_25G);
1627                 break;
1628
1629         case FW_PORT_TYPE_CR2_QSFP:
1630                 SET_SPEED(SPEED_50G);
1631                 break;
1632
1633         case FW_PORT_TYPE_KR4_100G:
1634         case FW_PORT_TYPE_CR4_QSFP:
1635                 FW_CAPS_TO_SPEED(SPEED_25G);
1636                 FW_CAPS_TO_SPEED(SPEED_40G);
1637                 FW_CAPS_TO_SPEED(SPEED_50G);
1638                 FW_CAPS_TO_SPEED(SPEED_100G);
1639                 break;
1640
1641         default:
1642                 break;
1643         }
1644
1645 #undef FW_CAPS_TO_SPEED
1646 #undef SET_SPEED
1647 }
1648
1649 /**
1650  * cxgbe_get_speed_caps - Fetch supported speed capabilities
1651  * @pi: Underlying port's info
1652  * @speed_caps: Device Info speed capabilities
1653  *
1654  * Fetch supported speed capabilities of the underlying port.
1655  */
1656 void cxgbe_get_speed_caps(struct port_info *pi, u32 *speed_caps)
1657 {
1658         *speed_caps = 0;
1659
1660         fw_caps_to_speed_caps(pi->port_type, pi->link_cfg.pcaps,
1661                               speed_caps);
1662
1663         if (!(pi->link_cfg.pcaps & FW_PORT_CAP32_ANEG))
1664                 *speed_caps |= ETH_LINK_SPEED_FIXED;
1665 }
1666
1667 /**
1668  * cxgbe_set_link_status - Set device link up or down.
1669  * @pi: Underlying port's info
1670  * @status: 0 - down, 1 - up
1671  *
1672  * Set the device link up or down.
1673  */
1674 int cxgbe_set_link_status(struct port_info *pi, bool status)
1675 {
1676         struct adapter *adapter = pi->adapter;
1677         int err = 0;
1678
1679         err = t4_enable_vi(adapter, adapter->mbox, pi->viid, status, status);
1680         if (err) {
1681                 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err);
1682                 return err;
1683         }
1684
1685         if (!status)
1686                 t4_reset_link_config(adapter, pi->pidx);
1687
1688         return 0;
1689 }
1690
1691 /**
1692  * cxgb_up - enable the adapter
1693  * @adap: adapter being enabled
1694  *
1695  * Called when the first port is enabled, this function performs the
1696  * actions necessary to make an adapter operational, such as completing
1697  * the initialization of HW modules, and enabling interrupts.
1698  */
1699 int cxgbe_up(struct adapter *adap)
1700 {
1701         enable_rx(adap, &adap->sge.fw_evtq);
1702         t4_sge_tx_monitor_start(adap);
1703         if (is_pf4(adap))
1704                 t4_intr_enable(adap);
1705         adap->flags |= FULL_INIT_DONE;
1706
1707         /* TODO: deadman watchdog ?? */
1708         return 0;
1709 }
1710
1711 /*
1712  * Close the port
1713  */
1714 int cxgbe_down(struct port_info *pi)
1715 {
1716         return cxgbe_set_link_status(pi, false);
1717 }
1718
1719 /*
1720  * Release resources when all the ports have been stopped.
1721  */
1722 void cxgbe_close(struct adapter *adapter)
1723 {
1724         struct port_info *pi;
1725         int i;
1726
1727         if (adapter->flags & FULL_INIT_DONE) {
1728                 tid_free(&adapter->tids);
1729                 t4_cleanup_mpstcam(adapter);
1730                 t4_cleanup_clip_tbl(adapter);
1731                 t4_cleanup_l2t(adapter);
1732                 if (is_pf4(adapter))
1733                         t4_intr_disable(adapter);
1734                 t4_sge_tx_monitor_stop(adapter);
1735                 t4_free_sge_resources(adapter);
1736                 for_each_port(adapter, i) {
1737                         pi = adap2pinfo(adapter, i);
1738                         if (pi->viid != 0)
1739                                 t4_free_vi(adapter, adapter->mbox,
1740                                            adapter->pf, 0, pi->viid);
1741                         rte_eth_dev_release_port(pi->eth_dev);
1742                 }
1743                 adapter->flags &= ~FULL_INIT_DONE;
1744         }
1745
1746         if (is_pf4(adapter) && (adapter->flags & FW_OK))
1747                 t4_fw_bye(adapter, adapter->mbox);
1748 }
1749
1750 int cxgbe_probe(struct adapter *adapter)
1751 {
1752         struct port_info *pi;
1753         int chip;
1754         int func, i;
1755         int err = 0;
1756         u32 whoami;
1757
1758         whoami = t4_read_reg(adapter, A_PL_WHOAMI);
1759         chip = t4_get_chip_type(adapter,
1760                         CHELSIO_PCI_ID_VER(adapter->pdev->id.device_id));
1761         if (chip < 0)
1762                 return chip;
1763
1764         func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
1765                G_SOURCEPF(whoami) : G_T6_SOURCEPF(whoami);
1766
1767         adapter->mbox = func;
1768         adapter->pf = func;
1769
1770         t4_os_lock_init(&adapter->mbox_lock);
1771         TAILQ_INIT(&adapter->mbox_list);
1772         t4_os_lock_init(&adapter->win0_lock);
1773
1774         err = t4_prep_adapter(adapter);
1775         if (err)
1776                 return err;
1777
1778         setup_memwin(adapter);
1779         err = adap_init0(adapter);
1780         if (err) {
1781                 dev_err(adapter, "%s: Adapter initialization failed, error %d\n",
1782                         __func__, err);
1783                 goto out_free;
1784         }
1785
1786         if (!is_t4(adapter->params.chip)) {
1787                 /*
1788                  * The userspace doorbell BAR is split evenly into doorbell
1789                  * regions, each associated with an egress queue.  If this
1790                  * per-queue region is large enough (at least UDBS_SEG_SIZE)
1791                  * then it can be used to submit a tx work request with an
1792                  * implied doorbell.  Enable write combining on the BAR if
1793                  * there is room for such work requests.
1794                  */
1795                 int s_qpp, qpp, num_seg;
1796
1797                 s_qpp = (S_QUEUESPERPAGEPF0 +
1798                         (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) *
1799                         adapter->pf);
1800                 qpp = 1 << ((t4_read_reg(adapter,
1801                                 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp)
1802                                 & M_QUEUESPERPAGEPF0);
1803                 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE;
1804                 if (qpp > num_seg)
1805                         dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n");
1806
1807                 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr;
1808                 if (!adapter->bar2) {
1809                         dev_err(adapter, "cannot map device bar2 region\n");
1810                         err = -ENOMEM;
1811                         goto out_free;
1812                 }
1813                 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) |
1814                              V_STATMODE(0));
1815         }
1816
1817         for_each_port(adapter, i) {
1818                 const unsigned int numa_node = rte_socket_id();
1819                 char name[RTE_ETH_NAME_MAX_LEN];
1820                 struct rte_eth_dev *eth_dev;
1821
1822                 snprintf(name, sizeof(name), "%s_%d",
1823                          adapter->pdev->device.name, i);
1824
1825                 if (i == 0) {
1826                         /* First port is already allocated by DPDK */
1827                         eth_dev = adapter->eth_dev;
1828                         goto allocate_mac;
1829                 }
1830
1831                 /*
1832                  * now do all data allocation - for eth_dev structure,
1833                  * and internal (private) data for the remaining ports
1834                  */
1835
1836                 /* reserve an ethdev entry */
1837                 eth_dev = rte_eth_dev_allocate(name);
1838                 if (!eth_dev)
1839                         goto out_free;
1840
1841                 eth_dev->data->dev_private =
1842                         rte_zmalloc_socket(name, sizeof(struct port_info),
1843                                            RTE_CACHE_LINE_SIZE, numa_node);
1844                 if (!eth_dev->data->dev_private)
1845                         goto out_free;
1846
1847 allocate_mac:
1848                 pi = eth_dev->data->dev_private;
1849                 adapter->port[i] = pi;
1850                 pi->eth_dev = eth_dev;
1851                 pi->adapter = adapter;
1852                 pi->xact_addr_filt = -1;
1853                 pi->port_id = i;
1854                 pi->pidx = i;
1855
1856                 pi->eth_dev->device = &adapter->pdev->device;
1857                 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops;
1858                 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst;
1859                 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst;
1860
1861                 rte_eth_copy_pci_info(pi->eth_dev, adapter->pdev);
1862
1863                 pi->eth_dev->data->mac_addrs = rte_zmalloc(name,
1864                                                         RTE_ETHER_ADDR_LEN, 0);
1865                 if (!pi->eth_dev->data->mac_addrs) {
1866                         dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n",
1867                                 __func__);
1868                         err = -1;
1869                         goto out_free;
1870                 }
1871
1872                 if (i > 0) {
1873                         /* First port will be notified by upper layer */
1874                         rte_eth_dev_probing_finish(eth_dev);
1875                 }
1876         }
1877
1878         if (adapter->flags & FW_OK) {
1879                 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0);
1880                 if (err) {
1881                         dev_err(adapter, "%s: t4_port_init failed with err %d\n",
1882                                 __func__, err);
1883                         goto out_free;
1884                 }
1885         }
1886
1887         cxgbe_cfg_queues(adapter->eth_dev);
1888
1889         cxgbe_print_adapter_info(adapter);
1890         cxgbe_print_port_info(adapter);
1891
1892         adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
1893                                           adapter->clipt_end);
1894         if (!adapter->clipt) {
1895                 /* We tolerate a lack of clip_table, giving up some
1896                  * functionality
1897                  */
1898                 dev_warn(adapter, "could not allocate CLIP. Continuing\n");
1899         }
1900
1901         adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
1902         if (!adapter->l2t) {
1903                 /* We tolerate a lack of L2T, giving up some functionality */
1904                 dev_warn(adapter, "could not allocate L2T. Continuing\n");
1905         }
1906
1907         if (tid_init(&adapter->tids) < 0) {
1908                 /* Disable filtering support */
1909                 dev_warn(adapter, "could not allocate TID table, "
1910                          "filter support disabled. Continuing\n");
1911         }
1912
1913         adapter->mpstcam = t4_init_mpstcam(adapter);
1914         if (!adapter->mpstcam)
1915                 dev_warn(adapter, "could not allocate mps tcam table."
1916                          " Continuing\n");
1917
1918         if (is_hashfilter(adapter)) {
1919                 if (t4_read_reg(adapter, A_LE_DB_CONFIG) & F_HASHEN) {
1920                         u32 hash_base, hash_reg;
1921
1922                         hash_reg = A_LE_DB_TID_HASHBASE;
1923                         hash_base = t4_read_reg(adapter, hash_reg);
1924                         adapter->tids.hash_base = hash_base / 4;
1925                 }
1926         } else {
1927                 /* Disable hash filtering support */
1928                 dev_warn(adapter,
1929                          "Maskless filter support disabled. Continuing\n");
1930         }
1931
1932         err = cxgbe_init_rss(adapter);
1933         if (err)
1934                 goto out_free;
1935
1936         return 0;
1937
1938 out_free:
1939         for_each_port(adapter, i) {
1940                 pi = adap2pinfo(adapter, i);
1941                 if (pi->viid != 0)
1942                         t4_free_vi(adapter, adapter->mbox, adapter->pf,
1943                                    0, pi->viid);
1944                 rte_eth_dev_release_port(pi->eth_dev);
1945         }
1946
1947         if (adapter->flags & FW_OK)
1948                 t4_fw_bye(adapter, adapter->mbox);
1949         return -err;
1950 }