1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Chelsio Communications.
8 #include "base/t4_msg.h"
11 L2T_SIZE = 4096 /* # of L2T entries */
15 L2T_STATE_VALID, /* entry is up to date */
16 L2T_STATE_SYNC_WRITE, /* synchronous write of entry underway */
18 /* when state is one of the below the entry is not hashed */
19 L2T_STATE_SWITCHING, /* entry is being used by a switching filter */
20 L2T_STATE_UNUSED /* entry not in use */
24 * State for the corresponding entry of the HW L2 table.
27 u16 state; /* entry state */
28 u16 idx; /* entry index within in-memory table */
29 u16 vlan; /* VLAN TCI (id: bits 0-11, prio: 13-15 */
30 u8 lport; /* destination port */
31 u8 dmac[RTE_ETHER_ADDR_LEN]; /* destination MAC address */
32 rte_spinlock_t lock; /* entry lock */
33 rte_atomic32_t refcnt; /* entry reference count */
37 unsigned int l2t_start; /* start index of our piece of the L2T */
38 unsigned int l2t_size; /* number of entries in l2tab */
39 rte_rwlock_t lock; /* table rw lock */
40 struct l2t_entry l2tab[0]; /* MUST BE LAST */
44 #define L2T_ARPMISS true
46 /* identifies sync vs async L2T_WRITE_REQs */
48 #define V_SYNC_WR(x) ((x) << S_SYNC_WR)
49 #define F_SYNC_WR V_SYNC_WR(1)
51 struct l2t_data *t4_init_l2t(unsigned int l2t_start, unsigned int l2t_end);
52 void t4_cleanup_l2t(struct adapter *adap);
53 struct l2t_entry *cxgbe_l2t_alloc_switching(struct rte_eth_dev *dev, u16 vlan,
55 void cxgbe_l2t_release(struct l2t_entry *e);
56 void cxgbe_do_l2t_write_rpl(struct adapter *p,
57 const struct cpl_l2t_write_rpl *rpl);
58 #endif /* _CXGBE_L2T_H_ */