1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2014-2018 Chelsio Communications.
14 #include <netinet/in.h>
16 #include <rte_byteorder.h>
17 #include <rte_common.h>
18 #include <rte_cycles.h>
19 #include <rte_interrupts.h>
21 #include <rte_debug.h>
23 #include <rte_atomic.h>
24 #include <rte_branch_prediction.h>
25 #include <rte_memory.h>
26 #include <rte_memzone.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_malloc.h>
33 #include <rte_random.h>
41 static inline void ship_tx_pkt_coalesce_wr(struct adapter *adap,
42 struct sge_eth_txq *txq);
45 * Max number of Rx buffers we replenish at a time.
47 #define MAX_RX_REFILL 64U
49 #define NOMEM_TMR_IDX (SGE_NTIMERS - 1)
52 * Max Tx descriptor space we allow for an Ethernet packet to be inlined
55 #define MAX_IMM_TX_PKT_LEN 256
58 * Max size of a WR sent through a control Tx queue.
60 #define MAX_CTRL_WR_LEN SGE_MAX_WR_LEN
63 * Rx buffer sizes for "usembufs" Free List buffers (one ingress packet
64 * per mbuf buffer). We currently only support two sizes for 1500- and
65 * 9000-byte MTUs. We could easily support more but there doesn't seem to be
66 * much need for that ...
68 #define FL_MTU_SMALL 1500
69 #define FL_MTU_LARGE 9000
71 static inline unsigned int fl_mtu_bufsize(struct adapter *adapter,
74 struct sge *s = &adapter->sge;
76 return CXGBE_ALIGN(s->pktshift + ETHER_HDR_LEN + VLAN_HLEN + mtu,
80 #define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL)
81 #define FL_MTU_LARGE_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_LARGE)
84 * Bits 0..3 of rx_sw_desc.dma_addr have special meaning. The hardware uses
85 * these to specify the buffer size as an index into the SGE Free List Buffer
86 * Size register array. We also use bit 4, when the buffer has been unmapped
87 * for DMA, but this is of course never sent to the hardware and is only used
88 * to prevent double unmappings. All of the above requires that the Free List
89 * Buffers which we allocate have the bottom 5 bits free (0) -- i.e. are
90 * 32-byte or or a power of 2 greater in alignment. Since the SGE's minimal
91 * Free List Buffer alignment is 32 bytes, this works out for us ...
94 RX_BUF_FLAGS = 0x1f, /* bottom five bits are special */
95 RX_BUF_SIZE = 0x0f, /* bottom three bits are for buf sizes */
96 RX_UNMAPPED_BUF = 0x10, /* buffer is not mapped */
99 * XXX We shouldn't depend on being able to use these indices.
100 * XXX Especially when some other Master PF has initialized the
101 * XXX adapter or we use the Firmware Configuration File. We
102 * XXX should really search through the Host Buffer Size register
103 * XXX array for the appropriately sized buffer indices.
105 RX_SMALL_PG_BUF = 0x0, /* small (PAGE_SIZE) page buffer */
106 RX_LARGE_PG_BUF = 0x1, /* buffer large page buffer */
108 RX_SMALL_MTU_BUF = 0x2, /* small MTU buffer */
109 RX_LARGE_MTU_BUF = 0x3, /* large MTU buffer */
113 * txq_avail - return the number of available slots in a Tx queue
116 * Returns the number of descriptors in a Tx queue available to write new
119 static inline unsigned int txq_avail(const struct sge_txq *q)
121 return q->size - 1 - q->in_use;
124 static int map_mbuf(struct rte_mbuf *mbuf, dma_addr_t *addr)
126 struct rte_mbuf *m = mbuf;
128 for (; m; m = m->next, addr++) {
129 *addr = m->buf_iova + rte_pktmbuf_headroom(m);
140 * free_tx_desc - reclaims Tx descriptors and their buffers
141 * @q: the Tx queue to reclaim descriptors from
142 * @n: the number of descriptors to reclaim
144 * Reclaims Tx descriptors from an SGE Tx queue and frees the associated
145 * Tx buffers. Called with the Tx queue lock held.
147 static void free_tx_desc(struct sge_txq *q, unsigned int n)
149 struct tx_sw_desc *d;
150 unsigned int cidx = 0;
154 if (d->mbuf) { /* an SGL is present */
155 rte_pktmbuf_free(d->mbuf);
158 if (d->coalesce.idx) {
161 for (i = 0; i < d->coalesce.idx; i++) {
162 rte_pktmbuf_free(d->coalesce.mbuf[i]);
163 d->coalesce.mbuf[i] = NULL;
168 if (++cidx == q->size) {
172 RTE_MBUF_PREFETCH_TO_FREE(&q->sdesc->mbuf->pool);
176 static void reclaim_tx_desc(struct sge_txq *q, unsigned int n)
178 struct tx_sw_desc *d;
179 unsigned int cidx = q->cidx;
183 if (d->mbuf) { /* an SGL is present */
184 rte_pktmbuf_free(d->mbuf);
188 if (++cidx == q->size) {
197 * fl_cap - return the capacity of a free-buffer list
200 * Returns the capacity of a free-buffer list. The capacity is less than
201 * the size because one descriptor needs to be left unpopulated, otherwise
202 * HW will think the FL is empty.
204 static inline unsigned int fl_cap(const struct sge_fl *fl)
206 return fl->size - 8; /* 1 descriptor = 8 buffers */
210 * fl_starving - return whether a Free List is starving.
211 * @adapter: pointer to the adapter
214 * Tests specified Free List to see whether the number of buffers
215 * available to the hardware has falled below our "starvation"
218 static inline bool fl_starving(const struct adapter *adapter,
219 const struct sge_fl *fl)
221 const struct sge *s = &adapter->sge;
223 return fl->avail - fl->pend_cred <= s->fl_starve_thres;
226 static inline unsigned int get_buf_size(struct adapter *adapter,
227 const struct rx_sw_desc *d)
229 unsigned int rx_buf_size_idx = d->dma_addr & RX_BUF_SIZE;
230 unsigned int buf_size = 0;
232 switch (rx_buf_size_idx) {
233 case RX_SMALL_MTU_BUF:
234 buf_size = FL_MTU_SMALL_BUFSIZE(adapter);
237 case RX_LARGE_MTU_BUF:
238 buf_size = FL_MTU_LARGE_BUFSIZE(adapter);
250 * free_rx_bufs - free the Rx buffers on an SGE free list
251 * @q: the SGE free list to free buffers from
252 * @n: how many buffers to free
254 * Release the next @n buffers on an SGE free-buffer Rx queue. The
255 * buffers must be made inaccessible to HW before calling this function.
257 static void free_rx_bufs(struct sge_fl *q, int n)
259 unsigned int cidx = q->cidx;
260 struct rx_sw_desc *d;
265 rte_pktmbuf_free(d->buf);
269 if (++cidx == q->size) {
279 * unmap_rx_buf - unmap the current Rx buffer on an SGE free list
280 * @q: the SGE free list
282 * Unmap the current buffer on an SGE free-buffer Rx queue. The
283 * buffer must be made inaccessible to HW before calling this function.
285 * This is similar to @free_rx_bufs above but does not free the buffer.
286 * Do note that the FL still loses any further access to the buffer.
288 static void unmap_rx_buf(struct sge_fl *q)
290 if (++q->cidx == q->size)
295 static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
297 if (q->pend_cred >= 64) {
298 u32 val = adap->params.arch.sge_fl_db;
300 if (is_t4(adap->params.chip))
301 val |= V_PIDX(q->pend_cred / 8);
303 val |= V_PIDX_T5(q->pend_cred / 8);
306 * Make sure all memory writes to the Free List queue are
307 * committed before we tell the hardware about them.
312 * If we don't have access to the new User Doorbell (T5+), use
313 * the old doorbell mechanism; otherwise use the new BAR2
316 if (unlikely(!q->bar2_addr)) {
317 u32 reg = is_pf4(adap) ? MYPF_REG(A_SGE_PF_KDOORBELL) :
321 t4_write_reg_relaxed(adap, reg,
322 val | V_QID(q->cntxt_id));
324 writel_relaxed(val | V_QID(q->bar2_qid),
325 (void *)((uintptr_t)q->bar2_addr +
329 * This Write memory Barrier will force the write to
330 * the User Doorbell area to be flushed.
338 static inline void set_rx_sw_desc(struct rx_sw_desc *sd, void *buf,
342 sd->dma_addr = mapping; /* includes size low bits */
346 * refill_fl_usembufs - refill an SGE Rx buffer ring with mbufs
348 * @q: the ring to refill
349 * @n: the number of new buffers to allocate
351 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
352 * allocated with the supplied gfp flags. The caller must assure that
353 * @n does not exceed the queue's capacity. If afterwards the queue is
354 * found critically low mark it as starving in the bitmap of starving FLs.
356 * Returns the number of buffers allocated.
358 static unsigned int refill_fl_usembufs(struct adapter *adap, struct sge_fl *q,
361 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, fl);
362 unsigned int cred = q->avail;
363 __be64 *d = &q->desc[q->pidx];
364 struct rx_sw_desc *sd = &q->sdesc[q->pidx];
365 unsigned int buf_size_idx = RX_SMALL_MTU_BUF;
366 struct rte_mbuf *buf_bulk[n];
368 struct rte_pktmbuf_pool_private *mbp_priv;
369 u8 jumbo_en = rxq->rspq.eth_dev->data->dev_conf.rxmode.offloads &
370 DEV_RX_OFFLOAD_JUMBO_FRAME;
372 /* Use jumbo mtu buffers if mbuf data room size can fit jumbo data. */
373 mbp_priv = rte_mempool_get_priv(rxq->rspq.mb_pool);
375 ((mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM) >= 9000))
376 buf_size_idx = RX_LARGE_MTU_BUF;
378 ret = rte_mempool_get_bulk(rxq->rspq.mb_pool, (void *)buf_bulk, n);
379 if (unlikely(ret != 0)) {
380 dev_debug(adap, "%s: failed to allocated fl entries in bulk ..\n",
383 rxq->rspq.eth_dev->data->rx_mbuf_alloc_failed++;
387 for (i = 0; i < n; i++) {
388 struct rte_mbuf *mbuf = buf_bulk[i];
392 dev_debug(adap, "%s: mbuf alloc failed\n", __func__);
394 rxq->rspq.eth_dev->data->rx_mbuf_alloc_failed++;
398 rte_mbuf_refcnt_set(mbuf, 1);
400 (uint16_t)(RTE_PTR_ALIGN((char *)mbuf->buf_addr +
401 RTE_PKTMBUF_HEADROOM,
402 adap->sge.fl_align) -
403 (char *)mbuf->buf_addr);
406 mbuf->port = rxq->rspq.port_id;
408 mapping = (dma_addr_t)RTE_ALIGN(mbuf->buf_iova +
411 mapping |= buf_size_idx;
412 *d++ = cpu_to_be64(mapping);
413 set_rx_sw_desc(sd, mbuf, mapping);
417 if (++q->pidx == q->size) {
424 out: cred = q->avail - cred;
425 q->pend_cred += cred;
428 if (unlikely(fl_starving(adap, q))) {
430 * Make sure data has been written to free list
440 * refill_fl - refill an SGE Rx buffer ring with mbufs
442 * @q: the ring to refill
443 * @n: the number of new buffers to allocate
445 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
446 * allocated with the supplied gfp flags. The caller must assure that
447 * @n does not exceed the queue's capacity. Returns the number of buffers
450 static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n)
452 return refill_fl_usembufs(adap, q, n);
455 static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
457 refill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail));
461 * Return the number of reclaimable descriptors in a Tx queue.
463 static inline int reclaimable(const struct sge_txq *q)
465 int hw_cidx = ntohs(q->stat->cidx);
469 return hw_cidx + q->size;
474 * reclaim_completed_tx - reclaims completed Tx descriptors
475 * @q: the Tx queue to reclaim completed descriptors from
477 * Reclaims Tx descriptors that the SGE has indicated it has processed.
479 void reclaim_completed_tx(struct sge_txq *q)
481 unsigned int avail = reclaimable(q);
484 /* reclaim as much as possible */
485 reclaim_tx_desc(q, avail);
487 avail = reclaimable(q);
492 * sgl_len - calculates the size of an SGL of the given capacity
493 * @n: the number of SGL entries
495 * Calculates the number of flits needed for a scatter/gather list that
496 * can hold the given number of entries.
498 static inline unsigned int sgl_len(unsigned int n)
501 * A Direct Scatter Gather List uses 32-bit lengths and 64-bit PCI DMA
502 * addresses. The DSGL Work Request starts off with a 32-bit DSGL
503 * ULPTX header, then Length0, then Address0, then, for 1 <= i <= N,
504 * repeated sequences of { Length[i], Length[i+1], Address[i],
505 * Address[i+1] } (this ensures that all addresses are on 64-bit
506 * boundaries). If N is even, then Length[N+1] should be set to 0 and
507 * Address[N+1] is omitted.
509 * The following calculation incorporates all of the above. It's
510 * somewhat hard to follow but, briefly: the "+2" accounts for the
511 * first two flits which include the DSGL header, Length0 and
512 * Address0; the "(3*(n-1))/2" covers the main body of list entries (3
513 * flits for every pair of the remaining N) +1 if (n-1) is odd; and
514 * finally the "+((n-1)&1)" adds the one remaining flit needed if
518 return (3 * n) / 2 + (n & 1) + 2;
522 * flits_to_desc - returns the num of Tx descriptors for the given flits
523 * @n: the number of flits
525 * Returns the number of Tx descriptors needed for the supplied number
528 static inline unsigned int flits_to_desc(unsigned int n)
530 return DIV_ROUND_UP(n, 8);
534 * is_eth_imm - can an Ethernet packet be sent as immediate data?
537 * Returns whether an Ethernet packet is small enough to fit as
538 * immediate data. Return value corresponds to the headroom required.
540 static inline int is_eth_imm(const struct rte_mbuf *m)
542 unsigned int hdrlen = (m->ol_flags & PKT_TX_TCP_SEG) ?
543 sizeof(struct cpl_tx_pkt_lso_core) : 0;
545 hdrlen += sizeof(struct cpl_tx_pkt);
546 if (m->pkt_len <= MAX_IMM_TX_PKT_LEN - hdrlen)
553 * calc_tx_flits - calculate the number of flits for a packet Tx WR
555 * @adap: adapter structure pointer
557 * Returns the number of flits needed for a Tx WR for the given Ethernet
558 * packet, including the needed WR and CPL headers.
560 static inline unsigned int calc_tx_flits(const struct rte_mbuf *m,
561 struct adapter *adap)
563 size_t wr_size = is_pf4(adap) ? sizeof(struct fw_eth_tx_pkt_wr) :
564 sizeof(struct fw_eth_tx_pkt_vm_wr);
569 * If the mbuf is small enough, we can pump it out as a work request
570 * with only immediate data. In that case we just have to have the
571 * TX Packet header plus the mbuf data in the Work Request.
574 hdrlen = is_eth_imm(m);
576 return DIV_ROUND_UP(m->pkt_len + hdrlen, sizeof(__be64));
579 * Otherwise, we're going to have to construct a Scatter gather list
580 * of the mbuf body and fragments. We also include the flits necessary
581 * for the TX Packet Work Request and CPL. We always have a firmware
582 * Write Header (incorporated as part of the cpl_tx_pkt_lso and
583 * cpl_tx_pkt structures), followed by either a TX Packet Write CPL
584 * message or, if we're doing a Large Send Offload, an LSO CPL message
585 * with an embedded TX Packet Write CPL message.
587 flits = sgl_len(m->nb_segs);
589 flits += (wr_size + sizeof(struct cpl_tx_pkt_lso_core) +
590 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
593 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
598 * write_sgl - populate a scatter/gather list for a packet
600 * @q: the Tx queue we are writing into
601 * @sgl: starting location for writing the SGL
602 * @end: points right after the end of the SGL
603 * @start: start offset into mbuf main-body data to include in the SGL
604 * @addr: address of mapped region
606 * Generates a scatter/gather list for the buffers that make up a packet.
607 * The caller must provide adequate space for the SGL that will be written.
608 * The SGL includes all of the packet's page fragments and the data in its
609 * main body except for the first @start bytes. @sgl must be 16-byte
610 * aligned and within a Tx descriptor with available space. @end points
611 * write after the end of the SGL but does not account for any potential
612 * wrap around, i.e., @end > @sgl.
614 static void write_sgl(struct rte_mbuf *mbuf, struct sge_txq *q,
615 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
616 const dma_addr_t *addr)
619 struct ulptx_sge_pair *to;
620 struct rte_mbuf *m = mbuf;
621 unsigned int nfrags = m->nb_segs;
622 struct ulptx_sge_pair buf[nfrags / 2];
624 len = m->data_len - start;
625 sgl->len0 = htonl(len);
626 sgl->addr0 = rte_cpu_to_be_64(addr[0]);
628 sgl->cmd_nsge = htonl(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
629 V_ULPTX_NSGE(nfrags));
630 if (likely(--nfrags == 0))
633 * Most of the complexity below deals with the possibility we hit the
634 * end of the queue in the middle of writing the SGL. For this case
635 * only we create the SGL in a temporary buffer and then copy it.
637 to = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge;
639 for (i = 0; nfrags >= 2; nfrags -= 2, to++) {
641 to->len[0] = rte_cpu_to_be_32(m->data_len);
642 to->addr[0] = rte_cpu_to_be_64(addr[++i]);
644 to->len[1] = rte_cpu_to_be_32(m->data_len);
645 to->addr[1] = rte_cpu_to_be_64(addr[++i]);
649 to->len[0] = rte_cpu_to_be_32(m->data_len);
650 to->len[1] = rte_cpu_to_be_32(0);
651 to->addr[0] = rte_cpu_to_be_64(addr[i + 1]);
653 if (unlikely((u8 *)end > (u8 *)q->stat)) {
654 unsigned int part0 = RTE_PTR_DIFF((u8 *)q->stat,
659 memcpy(sgl->sge, buf, part0);
660 part1 = RTE_PTR_DIFF((u8 *)end, (u8 *)q->stat);
661 rte_memcpy(q->desc, RTE_PTR_ADD((u8 *)buf, part0), part1);
662 end = RTE_PTR_ADD((void *)q->desc, part1);
664 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */
668 #define IDXDIFF(head, tail, wrap) \
669 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
671 #define Q_IDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->size)
672 #define R_IDXDIFF(q, idx) IDXDIFF((q)->cidx, (q)->idx, (q)->size)
674 #define PIDXDIFF(head, tail, wrap) \
675 ((tail) >= (head) ? (tail) - (head) : (wrap) - (head) + (tail))
676 #define P_IDXDIFF(q, idx) PIDXDIFF((q)->cidx, idx, (q)->size)
679 * ring_tx_db - ring a Tx queue's doorbell
682 * @n: number of new descriptors to give to HW
684 * Ring the doorbel for a Tx queue.
686 static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q)
688 int n = Q_IDXDIFF(q, dbidx);
691 * Make sure that all writes to the TX Descriptors are committed
692 * before we tell the hardware about them.
697 * If we don't have access to the new User Doorbell (T5+), use the old
698 * doorbell mechanism; otherwise use the new BAR2 mechanism.
700 if (unlikely(!q->bar2_addr)) {
704 * For T4 we need to participate in the Doorbell Recovery
708 t4_write_reg(adap, MYPF_REG(A_SGE_PF_KDOORBELL),
709 V_QID(q->cntxt_id) | val);
712 q->db_pidx = q->pidx;
714 u32 val = V_PIDX_T5(n);
717 * T4 and later chips share the same PIDX field offset within
718 * the doorbell, but T5 and later shrank the field in order to
719 * gain a bit for Doorbell Priority. The field was absurdly
720 * large in the first place (14 bits) so we just use the T5
721 * and later limits and warn if a Queue ID is too large.
723 WARN_ON(val & F_DBPRIO);
725 writel(val | V_QID(q->bar2_qid),
726 (void *)((uintptr_t)q->bar2_addr + SGE_UDB_KDOORBELL));
729 * This Write Memory Barrier will force the write to the User
730 * Doorbell area to be flushed. This is needed to prevent
731 * writes on different CPUs for the same queue from hitting
732 * the adapter out of order. This is required when some Work
733 * Requests take the Write Combine Gather Buffer path (user
734 * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some
735 * take the traditional path where we simply increment the
736 * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the
737 * hardware DMA read the actual Work Request.
745 * Figure out what HW csum a packet wants and return the appropriate control
748 static u64 hwcsum(enum chip_type chip, const struct rte_mbuf *m)
752 if (m->ol_flags & PKT_TX_IP_CKSUM) {
753 switch (m->ol_flags & PKT_TX_L4_MASK) {
754 case PKT_TX_TCP_CKSUM:
755 csum_type = TX_CSUM_TCPIP;
757 case PKT_TX_UDP_CKSUM:
758 csum_type = TX_CSUM_UDPIP;
767 if (likely(csum_type >= TX_CSUM_TCPIP)) {
768 u64 hdr_len = V_TXPKT_IPHDR_LEN(m->l3_len);
769 int eth_hdr_len = m->l2_len;
771 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
772 hdr_len |= V_TXPKT_ETHHDR_LEN(eth_hdr_len);
774 hdr_len |= V_T6_TXPKT_ETHHDR_LEN(eth_hdr_len);
775 return V_TXPKT_CSUM_TYPE(csum_type) | hdr_len;
779 * unknown protocol, disable HW csum
780 * and hope a bad packet is detected
782 return F_TXPKT_L4CSUM_DIS;
785 static inline void txq_advance(struct sge_txq *q, unsigned int n)
789 if (q->pidx >= q->size)
793 #define MAX_COALESCE_LEN 64000
795 static inline int wraps_around(struct sge_txq *q, int ndesc)
797 return (q->pidx + ndesc) > q->size ? 1 : 0;
800 static void tx_timer_cb(void *data)
802 struct adapter *adap = (struct adapter *)data;
803 struct sge_eth_txq *txq = &adap->sge.ethtxq[0];
805 unsigned int coal_idx;
807 /* monitor any pending tx */
808 for (i = 0; i < adap->sge.max_ethqsets; i++, txq++) {
809 if (t4_os_trylock(&txq->txq_lock)) {
810 coal_idx = txq->q.coalesce.idx;
812 if (coal_idx == txq->q.last_coal_idx &&
813 txq->q.pidx == txq->q.last_pidx) {
814 ship_tx_pkt_coalesce_wr(adap, txq);
816 txq->q.last_coal_idx = coal_idx;
817 txq->q.last_pidx = txq->q.pidx;
820 t4_os_unlock(&txq->txq_lock);
823 rte_eal_alarm_set(50, tx_timer_cb, (void *)adap);
827 * ship_tx_pkt_coalesce_wr - finalizes and ships a coalesce WR
828 * @ adap: adapter structure
831 * writes the different fields of the pkts WR and sends it.
833 static inline void ship_tx_pkt_coalesce_wr(struct adapter *adap,
834 struct sge_eth_txq *txq)
836 struct fw_eth_tx_pkts_vm_wr *vmwr;
837 const size_t fw_hdr_copy_len = (sizeof(vmwr->ethmacdst) +
838 sizeof(vmwr->ethmacsrc) +
839 sizeof(vmwr->ethtype) +
840 sizeof(vmwr->vlantci));
841 struct fw_eth_tx_pkts_wr *wr;
842 struct sge_txq *q = &txq->q;
846 /* fill the pkts WR header */
847 wr = (void *)&q->desc[q->pidx];
848 wr->op_pkd = htonl(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR));
849 vmwr = (void *)&q->desc[q->pidx];
851 wr_mid = V_FW_WR_LEN16(DIV_ROUND_UP(q->coalesce.flits, 2));
852 ndesc = flits_to_desc(q->coalesce.flits);
853 wr->equiq_to_len16 = htonl(wr_mid);
854 wr->plen = cpu_to_be16(q->coalesce.len);
855 wr->npkt = q->coalesce.idx;
858 wr->op_pkd = htonl(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR));
859 wr->type = q->coalesce.type;
861 wr->op_pkd = htonl(V_FW_WR_OP(FW_ETH_TX_PKTS_VM_WR));
863 memcpy((void *)vmwr->ethmacdst, (void *)q->coalesce.ethmacdst,
867 /* zero out coalesce structure members */
868 memset((void *)&q->coalesce, 0, sizeof(struct eth_coalesce));
870 txq_advance(q, ndesc);
871 txq->stats.coal_wr++;
872 txq->stats.coal_pkts += wr->npkt;
874 if (Q_IDXDIFF(q, equeidx) >= q->size / 2) {
875 q->equeidx = q->pidx;
876 wr_mid |= F_FW_WR_EQUEQ;
877 wr->equiq_to_len16 = htonl(wr_mid);
883 * should_tx_packet_coalesce - decides wether to coalesce an mbuf or not
884 * @txq: tx queue where the mbuf is sent
885 * @mbuf: mbuf to be sent
886 * @nflits: return value for number of flits needed
887 * @adap: adapter structure
889 * This function decides if a packet should be coalesced or not.
891 static inline int should_tx_packet_coalesce(struct sge_eth_txq *txq,
892 struct rte_mbuf *mbuf,
893 unsigned int *nflits,
894 struct adapter *adap)
896 struct fw_eth_tx_pkts_vm_wr *wr;
897 const size_t fw_hdr_copy_len = (sizeof(wr->ethmacdst) +
898 sizeof(wr->ethmacsrc) +
899 sizeof(wr->ethtype) +
900 sizeof(wr->vlantci));
901 struct sge_txq *q = &txq->q;
902 unsigned int flits, ndesc;
903 unsigned char type = 0;
904 int credits, wr_size;
906 /* use coal WR type 1 when no frags are present */
907 type = (mbuf->nb_segs == 1) ? 1 : 0;
912 if (q->coalesce.idx && memcmp((void *)q->coalesce.ethmacdst,
913 rte_pktmbuf_mtod(mbuf, void *),
915 ship_tx_pkt_coalesce_wr(adap, txq);
918 if (unlikely(type != q->coalesce.type && q->coalesce.idx))
919 ship_tx_pkt_coalesce_wr(adap, txq);
921 /* calculate the number of flits required for coalescing this packet
922 * without the 2 flits of the WR header. These are added further down
923 * if we are just starting in new PKTS WR. sgl_len doesn't account for
924 * the possible 16 bytes alignment ULP TX commands so we do it here.
926 flits = (sgl_len(mbuf->nb_segs) + 1) & ~1U;
928 flits += (sizeof(struct ulp_txpkt) +
929 sizeof(struct ulptx_idata)) / sizeof(__be64);
930 flits += sizeof(struct cpl_tx_pkt_core) / sizeof(__be64);
933 /* If coalescing is on, the mbuf is added to a pkts WR */
934 if (q->coalesce.idx) {
935 ndesc = DIV_ROUND_UP(q->coalesce.flits + flits, 8);
936 credits = txq_avail(q) - ndesc;
938 /* If we are wrapping or this is last mbuf then, send the
939 * already coalesced mbufs and let the non-coalesce pass
942 if (unlikely(credits < 0 || wraps_around(q, ndesc))) {
943 ship_tx_pkt_coalesce_wr(adap, txq);
947 /* If the max coalesce len or the max WR len is reached
948 * ship the WR and keep coalescing on.
950 if (unlikely((q->coalesce.len + mbuf->pkt_len >
952 (q->coalesce.flits + flits >
954 ship_tx_pkt_coalesce_wr(adap, txq);
961 /* start a new pkts WR, the WR header is not filled below */
962 wr_size = is_pf4(adap) ? sizeof(struct fw_eth_tx_pkts_wr) :
963 sizeof(struct fw_eth_tx_pkts_vm_wr);
964 flits += wr_size / sizeof(__be64);
965 ndesc = flits_to_desc(q->coalesce.flits + flits);
966 credits = txq_avail(q) - ndesc;
968 if (unlikely(credits < 0 || wraps_around(q, ndesc)))
970 q->coalesce.flits += wr_size / sizeof(__be64);
971 q->coalesce.type = type;
972 q->coalesce.ptr = (unsigned char *)&q->desc[q->pidx] +
973 q->coalesce.flits * sizeof(__be64);
975 memcpy((void *)q->coalesce.ethmacdst,
976 rte_pktmbuf_mtod(mbuf, void *), fw_hdr_copy_len);
981 * tx_do_packet_coalesce - add an mbuf to a coalesce WR
982 * @txq: sge_eth_txq used send the mbuf
983 * @mbuf: mbuf to be sent
984 * @flits: flits needed for this mbuf
985 * @adap: adapter structure
986 * @pi: port_info structure
987 * @addr: mapped address of the mbuf
989 * Adds an mbuf to be sent as part of a coalesce WR by filling a
990 * ulp_tx_pkt command, ulp_tx_sc_imm command, cpl message and
991 * ulp_tx_sc_dsgl command.
993 static inline int tx_do_packet_coalesce(struct sge_eth_txq *txq,
994 struct rte_mbuf *mbuf,
995 int flits, struct adapter *adap,
996 const struct port_info *pi,
997 dma_addr_t *addr, uint16_t nb_pkts)
1000 struct sge_txq *q = &txq->q;
1001 struct ulp_txpkt *mc;
1002 struct ulptx_idata *sc_imm;
1003 struct cpl_tx_pkt_core *cpl;
1004 struct tx_sw_desc *sd;
1005 unsigned int idx = q->coalesce.idx, len = mbuf->pkt_len;
1006 unsigned int max_coal_pkt_num = is_pf4(adap) ? ETH_COALESCE_PKT_NUM :
1007 ETH_COALESCE_VF_PKT_NUM;
1009 #ifdef RTE_LIBRTE_CXGBE_TPUT
1010 RTE_SET_USED(nb_pkts);
1013 if (q->coalesce.type == 0) {
1014 mc = (struct ulp_txpkt *)q->coalesce.ptr;
1015 mc->cmd_dest = htonl(V_ULPTX_CMD(4) | V_ULP_TXPKT_DEST(0) |
1016 V_ULP_TXPKT_FID(adap->sge.fw_evtq.cntxt_id) |
1018 mc->len = htonl(DIV_ROUND_UP(flits, 2));
1019 sc_imm = (struct ulptx_idata *)(mc + 1);
1020 sc_imm->cmd_more = htonl(V_ULPTX_CMD(ULP_TX_SC_IMM) |
1022 sc_imm->len = htonl(sizeof(*cpl));
1023 end = (u64 *)mc + flits;
1024 cpl = (struct cpl_tx_pkt_core *)(sc_imm + 1);
1026 end = (u64 *)q->coalesce.ptr + flits;
1027 cpl = (struct cpl_tx_pkt_core *)q->coalesce.ptr;
1030 /* update coalesce structure for this txq */
1031 q->coalesce.flits += flits;
1032 q->coalesce.ptr += flits * sizeof(__be64);
1033 q->coalesce.len += mbuf->pkt_len;
1035 /* fill the cpl message, same as in t4_eth_xmit, this should be kept
1036 * similar to t4_eth_xmit
1038 if (mbuf->ol_flags & PKT_TX_IP_CKSUM) {
1039 cntrl = hwcsum(adap->params.chip, mbuf) |
1041 txq->stats.tx_cso++;
1043 cntrl = F_TXPKT_L4CSUM_DIS | F_TXPKT_IPCSUM_DIS;
1046 if (mbuf->ol_flags & PKT_TX_VLAN_PKT) {
1047 txq->stats.vlan_ins++;
1048 cntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(mbuf->vlan_tci);
1051 cpl->ctrl0 = htonl(V_TXPKT_OPCODE(CPL_TX_PKT_XT));
1053 cpl->ctrl0 |= htonl(V_TXPKT_INTF(pi->tx_chan) |
1054 V_TXPKT_PF(adap->pf));
1056 cpl->ctrl0 |= htonl(V_TXPKT_INTF(pi->port_id));
1057 cpl->pack = htons(0);
1058 cpl->len = htons(len);
1059 cpl->ctrl1 = cpu_to_be64(cntrl);
1060 write_sgl(mbuf, q, (struct ulptx_sgl *)(cpl + 1), end, 0, addr);
1062 txq->stats.tx_bytes += len;
1064 sd = &q->sdesc[q->pidx + (idx >> 1)];
1066 if (sd->coalesce.idx) {
1069 for (i = 0; i < sd->coalesce.idx; i++) {
1070 rte_pktmbuf_free(sd->coalesce.mbuf[i]);
1071 sd->coalesce.mbuf[i] = NULL;
1076 /* store pointers to the mbuf and the sgl used in free_tx_desc.
1077 * each tx desc can hold two pointers corresponding to the value
1078 * of ETH_COALESCE_PKT_PER_DESC
1080 sd->coalesce.mbuf[idx & 1] = mbuf;
1081 sd->coalesce.sgl[idx & 1] = (struct ulptx_sgl *)(cpl + 1);
1082 sd->coalesce.idx = (idx & 1) + 1;
1084 /* send the coaelsced work request if max reached */
1085 if (++q->coalesce.idx == max_coal_pkt_num
1086 #ifndef RTE_LIBRTE_CXGBE_TPUT
1087 || q->coalesce.idx >= nb_pkts
1090 ship_tx_pkt_coalesce_wr(adap, txq);
1095 * t4_eth_xmit - add a packet to an Ethernet Tx queue
1096 * @txq: the egress queue
1099 * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled.
1101 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
1104 const struct port_info *pi;
1105 struct cpl_tx_pkt_lso_core *lso;
1106 struct adapter *adap;
1107 struct rte_mbuf *m = mbuf;
1108 struct fw_eth_tx_pkt_wr *wr;
1109 struct fw_eth_tx_pkt_vm_wr *vmwr;
1110 struct cpl_tx_pkt_core *cpl;
1111 struct tx_sw_desc *d;
1112 dma_addr_t addr[m->nb_segs];
1113 unsigned int flits, ndesc, cflits;
1114 int l3hdr_len, l4hdr_len, eth_xtra_len;
1120 u32 max_pkt_len = txq->data->dev_conf.rxmode.max_rx_pkt_len;
1122 /* Reject xmit if queue is stopped */
1123 if (unlikely(txq->flags & EQ_STOPPED))
1127 * The chip min packet length is 10 octets but play safe and reject
1128 * anything shorter than an Ethernet header.
1130 if (unlikely(m->pkt_len < ETHER_HDR_LEN)) {
1132 rte_pktmbuf_free(m);
1136 if ((!(m->ol_flags & PKT_TX_TCP_SEG)) &&
1137 (unlikely(m->pkt_len > max_pkt_len)))
1140 pi = (struct port_info *)txq->data->dev_private;
1143 cntrl = F_TXPKT_L4CSUM_DIS | F_TXPKT_IPCSUM_DIS;
1144 /* align the end of coalesce WR to a 512 byte boundary */
1145 txq->q.coalesce.max = (8 - (txq->q.pidx & 7)) * 8;
1147 if (!((m->ol_flags & PKT_TX_TCP_SEG) || (m->pkt_len > ETHER_MAX_LEN))) {
1148 if (should_tx_packet_coalesce(txq, mbuf, &cflits, adap)) {
1149 if (unlikely(map_mbuf(mbuf, addr) < 0)) {
1150 dev_warn(adap, "%s: mapping err for coalesce\n",
1152 txq->stats.mapping_err++;
1155 rte_prefetch0((volatile void *)addr);
1156 return tx_do_packet_coalesce(txq, mbuf, cflits, adap,
1163 if (txq->q.coalesce.idx)
1164 ship_tx_pkt_coalesce_wr(adap, txq);
1166 flits = calc_tx_flits(m, adap);
1167 ndesc = flits_to_desc(flits);
1168 credits = txq_avail(&txq->q) - ndesc;
1170 if (unlikely(credits < 0)) {
1171 dev_debug(adap, "%s: Tx ring %u full; credits = %d\n",
1172 __func__, txq->q.cntxt_id, credits);
1176 if (unlikely(map_mbuf(m, addr) < 0)) {
1177 txq->stats.mapping_err++;
1181 wr_mid = V_FW_WR_LEN16(DIV_ROUND_UP(flits, 2));
1182 if (Q_IDXDIFF(&txq->q, equeidx) >= 64) {
1183 txq->q.equeidx = txq->q.pidx;
1184 wr_mid |= F_FW_WR_EQUEQ;
1187 wr = (void *)&txq->q.desc[txq->q.pidx];
1188 vmwr = (void *)&txq->q.desc[txq->q.pidx];
1189 wr->equiq_to_len16 = htonl(wr_mid);
1191 wr->r3 = rte_cpu_to_be_64(0);
1192 end = (u64 *)wr + flits;
1194 const size_t fw_hdr_copy_len = (sizeof(vmwr->ethmacdst) +
1195 sizeof(vmwr->ethmacsrc) +
1196 sizeof(vmwr->ethtype) +
1197 sizeof(vmwr->vlantci));
1199 vmwr->r3[0] = rte_cpu_to_be_32(0);
1200 vmwr->r3[1] = rte_cpu_to_be_32(0);
1201 memcpy((void *)vmwr->ethmacdst, rte_pktmbuf_mtod(m, void *),
1203 end = (u64 *)vmwr + flits;
1207 len += sizeof(*cpl);
1209 /* Coalescing skipped and we send through normal path */
1210 if (!(m->ol_flags & PKT_TX_TCP_SEG)) {
1211 wr->op_immdlen = htonl(V_FW_WR_OP(is_pf4(adap) ?
1213 FW_ETH_TX_PKT_VM_WR) |
1214 V_FW_WR_IMMDLEN(len));
1216 cpl = (void *)(wr + 1);
1218 cpl = (void *)(vmwr + 1);
1219 if (m->ol_flags & PKT_TX_IP_CKSUM) {
1220 cntrl = hwcsum(adap->params.chip, m) |
1222 txq->stats.tx_cso++;
1226 lso = (void *)(wr + 1);
1228 lso = (void *)(vmwr + 1);
1229 v6 = (m->ol_flags & PKT_TX_IPV6) != 0;
1230 l3hdr_len = m->l3_len;
1231 l4hdr_len = m->l4_len;
1232 eth_xtra_len = m->l2_len - ETHER_HDR_LEN;
1233 len += sizeof(*lso);
1234 wr->op_immdlen = htonl(V_FW_WR_OP(is_pf4(adap) ?
1236 FW_ETH_TX_PKT_VM_WR) |
1237 V_FW_WR_IMMDLEN(len));
1238 lso->lso_ctrl = htonl(V_LSO_OPCODE(CPL_TX_PKT_LSO) |
1239 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
1241 V_LSO_ETHHDR_LEN(eth_xtra_len / 4) |
1242 V_LSO_IPHDR_LEN(l3hdr_len / 4) |
1243 V_LSO_TCPHDR_LEN(l4hdr_len / 4));
1244 lso->ipid_ofst = htons(0);
1245 lso->mss = htons(m->tso_segsz);
1246 lso->seqno_offset = htonl(0);
1247 if (is_t4(adap->params.chip))
1248 lso->len = htonl(m->pkt_len);
1250 lso->len = htonl(V_LSO_T5_XFER_SIZE(m->pkt_len));
1251 cpl = (void *)(lso + 1);
1253 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1254 cntrl = V_TXPKT_ETHHDR_LEN(eth_xtra_len);
1256 cntrl = V_T6_TXPKT_ETHHDR_LEN(eth_xtra_len);
1258 cntrl |= V_TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 :
1260 V_TXPKT_IPHDR_LEN(l3hdr_len);
1262 txq->stats.tx_cso += m->tso_segsz;
1265 if (m->ol_flags & PKT_TX_VLAN_PKT) {
1266 txq->stats.vlan_ins++;
1267 cntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->vlan_tci);
1270 cpl->ctrl0 = htonl(V_TXPKT_OPCODE(CPL_TX_PKT_XT));
1272 cpl->ctrl0 |= htonl(V_TXPKT_INTF(pi->tx_chan) |
1273 V_TXPKT_PF(adap->pf));
1275 cpl->ctrl0 |= htonl(V_TXPKT_INTF(pi->port_id) |
1278 cpl->pack = htons(0);
1279 cpl->len = htons(m->pkt_len);
1280 cpl->ctrl1 = cpu_to_be64(cntrl);
1283 txq->stats.tx_bytes += m->pkt_len;
1284 last_desc = txq->q.pidx + ndesc - 1;
1285 if (last_desc >= (int)txq->q.size)
1286 last_desc -= txq->q.size;
1288 d = &txq->q.sdesc[last_desc];
1289 if (d->coalesce.idx) {
1292 for (i = 0; i < d->coalesce.idx; i++) {
1293 rte_pktmbuf_free(d->coalesce.mbuf[i]);
1294 d->coalesce.mbuf[i] = NULL;
1296 d->coalesce.idx = 0;
1298 write_sgl(m, &txq->q, (struct ulptx_sgl *)(cpl + 1), end, 0,
1300 txq->q.sdesc[last_desc].mbuf = m;
1301 txq->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)(cpl + 1);
1302 txq_advance(&txq->q, ndesc);
1303 ring_tx_db(adap, &txq->q);
1308 * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs
1309 * @q: the SGE control Tx queue
1311 * This is a variant of reclaim_completed_tx() that is used for Tx queues
1312 * that send only immediate data (presently just the control queues) and
1313 * thus do not have any mbufs to release.
1315 static inline void reclaim_completed_tx_imm(struct sge_txq *q)
1317 int hw_cidx = ntohs(q->stat->cidx);
1318 int reclaim = hw_cidx - q->cidx;
1323 q->in_use -= reclaim;
1328 * is_imm - check whether a packet can be sent as immediate data
1331 * Returns true if a packet can be sent as a WR with immediate data.
1333 static inline int is_imm(const struct rte_mbuf *mbuf)
1335 return mbuf->pkt_len <= MAX_CTRL_WR_LEN;
1339 * inline_tx_mbuf: inline a packet's data into TX descriptors
1340 * @q: the TX queue where the packet will be inlined
1341 * @from: pointer to data portion of packet
1342 * @to: pointer after cpl where data has to be inlined
1343 * @len: length of data to inline
1345 * Inline a packet's contents directly to TX descriptors, starting at
1346 * the given position within the TX DMA ring.
1347 * Most of the complexity of this operation is dealing with wrap arounds
1348 * in the middle of the packet we want to inline.
1350 static void inline_tx_mbuf(const struct sge_txq *q, caddr_t from, caddr_t *to,
1353 int left = RTE_PTR_DIFF(q->stat, *to);
1355 if (likely((uintptr_t)*to + len <= (uintptr_t)q->stat)) {
1356 rte_memcpy(*to, from, len);
1357 *to = RTE_PTR_ADD(*to, len);
1359 rte_memcpy(*to, from, left);
1360 from = RTE_PTR_ADD(from, left);
1362 rte_memcpy((void *)q->desc, from, left);
1363 *to = RTE_PTR_ADD((void *)q->desc, left);
1368 * ctrl_xmit - send a packet through an SGE control Tx queue
1369 * @q: the control queue
1372 * Send a packet through an SGE control Tx queue. Packets sent through
1373 * a control queue must fit entirely as immediate data.
1375 static int ctrl_xmit(struct sge_ctrl_txq *q, struct rte_mbuf *mbuf)
1378 struct fw_wr_hdr *wr;
1381 if (unlikely(!is_imm(mbuf))) {
1383 rte_pktmbuf_free(mbuf);
1387 reclaim_completed_tx_imm(&q->q);
1388 ndesc = DIV_ROUND_UP(mbuf->pkt_len, sizeof(struct tx_desc));
1389 t4_os_lock(&q->ctrlq_lock);
1391 q->full = txq_avail(&q->q) < ndesc ? 1 : 0;
1392 if (unlikely(q->full)) {
1393 t4_os_unlock(&q->ctrlq_lock);
1397 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx];
1399 inline_tx_mbuf(&q->q, rte_pktmbuf_mtod(mbuf, caddr_t),
1400 &dst, mbuf->data_len);
1402 txq_advance(&q->q, ndesc);
1403 if (unlikely(txq_avail(&q->q) < 64))
1404 wr->lo |= htonl(F_FW_WR_EQUEQ);
1408 ring_tx_db(q->adapter, &q->q);
1409 t4_os_unlock(&q->ctrlq_lock);
1411 rte_pktmbuf_free(mbuf);
1416 * t4_mgmt_tx - send a management message
1417 * @q: the control queue
1418 * @mbuf: the packet containing the management message
1420 * Send a management message through control queue.
1422 int t4_mgmt_tx(struct sge_ctrl_txq *q, struct rte_mbuf *mbuf)
1424 return ctrl_xmit(q, mbuf);
1428 * alloc_ring - allocate resources for an SGE descriptor ring
1429 * @dev: the PCI device's core device
1430 * @nelem: the number of descriptors
1431 * @elem_size: the size of each descriptor
1432 * @sw_size: the size of the SW state associated with each ring element
1433 * @phys: the physical address of the allocated ring
1434 * @metadata: address of the array holding the SW state for the ring
1435 * @stat_size: extra space in HW ring for status information
1436 * @node: preferred node for memory allocations
1438 * Allocates resources for an SGE descriptor ring, such as Tx queues,
1439 * free buffer lists, or response queues. Each SGE ring requires
1440 * space for its HW descriptors plus, optionally, space for the SW state
1441 * associated with each HW entry (the metadata). The function returns
1442 * three values: the virtual address for the HW ring (the return value
1443 * of the function), the bus address of the HW ring, and the address
1446 static void *alloc_ring(size_t nelem, size_t elem_size,
1447 size_t sw_size, dma_addr_t *phys, void *metadata,
1448 size_t stat_size, __rte_unused uint16_t queue_id,
1449 int socket_id, const char *z_name,
1450 const char *z_name_sw)
1452 size_t len = CXGBE_MAX_RING_DESC_SIZE * elem_size + stat_size;
1453 const struct rte_memzone *tz;
1456 dev_debug(adapter, "%s: nelem = %zu; elem_size = %zu; sw_size = %zu; "
1457 "stat_size = %zu; queue_id = %u; socket_id = %d; z_name = %s;"
1458 " z_name_sw = %s\n", __func__, nelem, elem_size, sw_size,
1459 stat_size, queue_id, socket_id, z_name, z_name_sw);
1461 tz = rte_memzone_lookup(z_name);
1463 dev_debug(adapter, "%s: tz exists...returning existing..\n",
1469 * Allocate TX/RX ring hardware descriptors. A memzone large enough to
1470 * handle the maximum ring size is allocated in order to allow for
1471 * resizing in later calls to the queue setup function.
1473 tz = rte_memzone_reserve_aligned(z_name, len, socket_id,
1474 RTE_MEMZONE_IOVA_CONTIG, 4096);
1479 memset(tz->addr, 0, len);
1481 s = rte_zmalloc_socket(z_name_sw, nelem * sw_size,
1482 RTE_CACHE_LINE_SIZE, socket_id);
1485 dev_err(adapter, "%s: failed to get sw_ring memory\n",
1491 *(void **)metadata = s;
1493 *phys = (uint64_t)tz->iova;
1498 * t4_pktgl_to_mbuf_usembufs - build an mbuf from a packet gather list
1499 * @gl: the gather list
1501 * Builds an mbuf from the given packet gather list. Returns the mbuf or
1502 * %NULL if mbuf allocation failed.
1504 static struct rte_mbuf *t4_pktgl_to_mbuf_usembufs(const struct pkt_gl *gl)
1507 * If there's only one mbuf fragment, just return that.
1509 if (likely(gl->nfrags == 1))
1510 return gl->mbufs[0];
1516 * t4_pktgl_to_mbuf - build an mbuf from a packet gather list
1517 * @gl: the gather list
1519 * Builds an mbuf from the given packet gather list. Returns the mbuf or
1520 * %NULL if mbuf allocation failed.
1522 static struct rte_mbuf *t4_pktgl_to_mbuf(const struct pkt_gl *gl)
1524 return t4_pktgl_to_mbuf_usembufs(gl);
1528 * t4_ethrx_handler - process an ingress ethernet packet
1529 * @q: the response queue that received the packet
1530 * @rsp: the response queue descriptor holding the RX_PKT message
1531 * @si: the gather list of packet fragments
1533 * Process an ingress ethernet packet and deliver it to the stack.
1535 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1536 const struct pkt_gl *si)
1538 struct rte_mbuf *mbuf;
1539 const struct cpl_rx_pkt *pkt;
1540 const struct rss_header *rss_hdr;
1542 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1545 rss_hdr = (const void *)rsp;
1546 pkt = (const void *)&rsp[1];
1547 /* Compressed error vector is enabled for T6 only */
1548 if (q->adapter->params.tp.rx_pkt_encap)
1549 err_vec = G_T6_COMPR_RXERR_VEC(ntohs(pkt->err_vec));
1551 err_vec = ntohs(pkt->err_vec);
1552 csum_ok = pkt->csum_calc && !err_vec;
1554 mbuf = t4_pktgl_to_mbuf(si);
1555 if (unlikely(!mbuf)) {
1556 rxq->stats.rx_drops++;
1560 mbuf->port = pkt->iff;
1561 if (pkt->l2info & htonl(F_RXF_IP)) {
1562 mbuf->packet_type = RTE_PTYPE_L3_IPV4;
1563 if (unlikely(!csum_ok))
1564 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1566 if ((pkt->l2info & htonl(F_RXF_UDP | F_RXF_TCP)) && !csum_ok)
1567 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1568 } else if (pkt->l2info & htonl(F_RXF_IP6)) {
1569 mbuf->packet_type = RTE_PTYPE_L3_IPV6;
1572 mbuf->port = pkt->iff;
1574 if (!rss_hdr->filter_tid && rss_hdr->hash_type) {
1575 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1576 mbuf->hash.rss = ntohl(rss_hdr->hash_val);
1580 mbuf->ol_flags |= PKT_RX_VLAN;
1581 mbuf->vlan_tci = ntohs(pkt->vlan);
1584 rxq->stats.rx_bytes += mbuf->pkt_len;
1589 #define CXGB4_MSG_AN ((void *)1)
1592 * rspq_next - advance to the next entry in a response queue
1595 * Updates the state of a response queue to advance it to the next entry.
1597 static inline void rspq_next(struct sge_rspq *q)
1599 q->cur_desc = (const __be64 *)((const char *)q->cur_desc + q->iqe_len);
1600 if (unlikely(++q->cidx == q->size)) {
1603 q->cur_desc = q->desc;
1608 * process_responses - process responses from an SGE response queue
1609 * @q: the ingress queue to process
1610 * @budget: how many responses can be processed in this round
1611 * @rx_pkts: mbuf to put the pkts
1613 * Process responses from an SGE response queue up to the supplied budget.
1614 * Responses include received packets as well as control messages from FW
1617 * Additionally choose the interrupt holdoff time for the next interrupt
1618 * on this queue. If the system is under memory shortage use a fairly
1619 * long delay to help recovery.
1621 static int process_responses(struct sge_rspq *q, int budget,
1622 struct rte_mbuf **rx_pkts)
1624 int ret = 0, rsp_type;
1625 int budget_left = budget;
1626 const struct rsp_ctrl *rc;
1627 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1629 while (likely(budget_left)) {
1630 if (q->cidx == ntohs(q->stat->pidx))
1633 rc = (const struct rsp_ctrl *)
1634 ((const char *)q->cur_desc + (q->iqe_len - sizeof(*rc)));
1637 * Ensure response has been read
1640 rsp_type = G_RSPD_TYPE(rc->u.type_gen);
1642 if (likely(rsp_type == X_RSPD_TYPE_FLBUF)) {
1643 struct sge *s = &q->adapter->sge;
1644 unsigned int stat_pidx;
1647 stat_pidx = ntohs(q->stat->pidx);
1648 stat_pidx_diff = P_IDXDIFF(q, stat_pidx);
1649 while (stat_pidx_diff && budget_left) {
1650 const struct rx_sw_desc *rsd =
1651 &rxq->fl.sdesc[rxq->fl.cidx];
1652 const struct rss_header *rss_hdr =
1653 (const void *)q->cur_desc;
1654 const struct cpl_rx_pkt *cpl =
1655 (const void *)&q->cur_desc[1];
1656 struct rte_mbuf *pkt, *npkt;
1661 rc = (const struct rsp_ctrl *)
1662 ((const char *)q->cur_desc +
1663 (q->iqe_len - sizeof(*rc)));
1665 rsp_type = G_RSPD_TYPE(rc->u.type_gen);
1666 if (unlikely(rsp_type != X_RSPD_TYPE_FLBUF))
1669 len = ntohl(rc->pldbuflen_qid);
1670 BUG_ON(!(len & F_RSPD_NEWBUF));
1673 len = G_RSPD_LEN(len);
1676 /* Compressed error vector is enabled for
1679 if (q->adapter->params.tp.rx_pkt_encap)
1680 err_vec = G_T6_COMPR_RXERR_VEC(
1681 ntohs(cpl->err_vec));
1683 err_vec = ntohs(cpl->err_vec);
1684 csum_ok = cpl->csum_calc && !err_vec;
1686 /* Chain mbufs into len if necessary */
1688 struct rte_mbuf *new_pkt = rsd->buf;
1690 bufsz = min(get_buf_size(q->adapter,
1692 new_pkt->data_len = bufsz;
1693 unmap_rx_buf(&rxq->fl);
1695 npkt->next = new_pkt;
1698 rsd = &rxq->fl.sdesc[rxq->fl.cidx];
1703 if (cpl->l2info & htonl(F_RXF_IP)) {
1704 pkt->packet_type = RTE_PTYPE_L3_IPV4;
1705 if (unlikely(!csum_ok))
1707 PKT_RX_IP_CKSUM_BAD;
1710 htonl(F_RXF_UDP | F_RXF_TCP)) &&
1713 PKT_RX_L4_CKSUM_BAD;
1714 } else if (cpl->l2info & htonl(F_RXF_IP6)) {
1715 pkt->packet_type = RTE_PTYPE_L3_IPV6;
1718 if (!rss_hdr->filter_tid &&
1719 rss_hdr->hash_type) {
1720 pkt->ol_flags |= PKT_RX_RSS_HASH;
1722 ntohl(rss_hdr->hash_val);
1726 pkt->ol_flags |= PKT_RX_VLAN |
1727 PKT_RX_VLAN_STRIPPED;
1728 pkt->vlan_tci = ntohs(cpl->vlan);
1731 rte_pktmbuf_adj(pkt, s->pktshift);
1733 rxq->stats.rx_bytes += pkt->pkt_len;
1734 rx_pkts[budget - budget_left] = pkt;
1741 } else if (likely(rsp_type == X_RSPD_TYPE_CPL)) {
1742 ret = q->handler(q, q->cur_desc, NULL);
1744 ret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN);
1747 if (unlikely(ret)) {
1748 /* couldn't process descriptor, back off for recovery */
1749 q->next_intr_params = V_QINTR_TIMER_IDX(NOMEM_TMR_IDX);
1758 * If this is a Response Queue with an associated Free List and
1759 * there's room for another chunk of new Free List buffer pointers,
1760 * refill the Free List.
1763 if (q->offset >= 0 && fl_cap(&rxq->fl) - rxq->fl.avail >= 64)
1764 __refill_fl(q->adapter, &rxq->fl);
1766 return budget - budget_left;
1769 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
1770 unsigned int budget, unsigned int *work_done)
1772 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1773 unsigned int cidx_inc;
1774 unsigned int params;
1777 *work_done = process_responses(q, budget, rx_pkts);
1780 cidx_inc = R_IDXDIFF(q, gts_idx);
1782 if (q->offset >= 0 && fl_cap(&rxq->fl) - rxq->fl.avail >= 64)
1783 __refill_fl(q->adapter, &rxq->fl);
1785 params = q->intr_params;
1786 q->next_intr_params = params;
1787 val = V_CIDXINC(cidx_inc) | V_SEINTARM(params);
1789 if (unlikely(!q->bar2_addr)) {
1790 u32 reg = is_pf4(q->adapter) ? MYPF_REG(A_SGE_PF_GTS) :
1791 T4VF_SGE_BASE_ADDR +
1794 t4_write_reg(q->adapter, reg,
1795 val | V_INGRESSQID((u32)q->cntxt_id));
1797 writel(val | V_INGRESSQID(q->bar2_qid),
1798 (void *)((uintptr_t)q->bar2_addr + SGE_UDB_GTS));
1799 /* This Write memory Barrier will force the
1800 * write to the User Doorbell area to be
1805 q->gts_idx = q->cidx;
1811 * bar2_address - return the BAR2 address for an SGE Queue's Registers
1812 * @adapter: the adapter
1813 * @qid: the SGE Queue ID
1814 * @qtype: the SGE Queue Type (Egress or Ingress)
1815 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
1817 * Returns the BAR2 address for the SGE Queue Registers associated with
1818 * @qid. If BAR2 SGE Registers aren't available, returns NULL. Also
1819 * returns the BAR2 Queue ID to be used with writes to the BAR2 SGE
1820 * Queue Registers. If the BAR2 Queue ID is 0, then "Inferred Queue ID"
1821 * Registers are supported (e.g. the Write Combining Doorbell Buffer).
1823 static void __iomem *bar2_address(struct adapter *adapter, unsigned int qid,
1824 enum t4_bar2_qtype qtype,
1825 unsigned int *pbar2_qid)
1830 ret = t4_bar2_sge_qregs(adapter, qid, qtype, &bar2_qoffset, pbar2_qid);
1834 return adapter->bar2 + bar2_qoffset;
1837 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq)
1839 struct sge_eth_rxq *rxq = container_of(rq, struct sge_eth_rxq, rspq);
1840 unsigned int fl_id = rxq->fl.size ? rxq->fl.cntxt_id : 0xffff;
1842 return t4_iq_start_stop(adap, adap->mbox, true, adap->pf, 0,
1843 rq->cntxt_id, fl_id, 0xffff);
1846 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq)
1848 struct sge_eth_rxq *rxq = container_of(rq, struct sge_eth_rxq, rspq);
1849 unsigned int fl_id = rxq->fl.size ? rxq->fl.cntxt_id : 0xffff;
1851 return t4_iq_start_stop(adap, adap->mbox, false, adap->pf, 0,
1852 rq->cntxt_id, fl_id, 0xffff);
1856 * @intr_idx: MSI/MSI-X vector if >=0, -(absolute qid + 1) if < 0
1857 * @cong: < 0 -> no congestion feedback, >= 0 -> congestion channel map
1859 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1860 struct rte_eth_dev *eth_dev, int intr_idx,
1861 struct sge_fl *fl, rspq_handler_t hnd, int cong,
1862 struct rte_mempool *mp, int queue_id, int socket_id)
1866 struct sge *s = &adap->sge;
1867 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1868 char z_name[RTE_MEMZONE_NAMESIZE];
1869 char z_name_sw[RTE_MEMZONE_NAMESIZE];
1870 unsigned int nb_refill;
1873 /* Size needs to be multiple of 16, including status entry. */
1874 iq->size = cxgbe_roundup(iq->size, 16);
1876 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1877 eth_dev->device->driver->name,
1878 fwevtq ? "fwq_ring" : "rx_ring",
1879 eth_dev->data->port_id, queue_id);
1880 snprintf(z_name_sw, sizeof(z_name_sw), "%s_sw_ring", z_name);
1882 iq->desc = alloc_ring(iq->size, iq->iqe_len, 0, &iq->phys_addr, NULL, 0,
1883 queue_id, socket_id, z_name, z_name_sw);
1887 memset(&c, 0, sizeof(c));
1888 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
1889 F_FW_CMD_WRITE | F_FW_CMD_EXEC);
1892 pciechan = cong > 0 ? cxgbe_ffs(cong) - 1 : pi->tx_chan;
1893 c.op_to_vfn |= htonl(V_FW_IQ_CMD_PFN(adap->pf) |
1894 V_FW_IQ_CMD_VFN(0));
1896 c.iqns_to_fl0congen = htonl(F_FW_IQ_CMD_IQFLINTCONGEN |
1899 pciechan = pi->port_id;
1902 c.alloc_to_len16 = htonl(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
1904 c.type_to_iqandstindex =
1905 htonl(V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
1906 V_FW_IQ_CMD_IQASYNCH(fwevtq) |
1907 V_FW_IQ_CMD_VIID(pi->viid) |
1908 V_FW_IQ_CMD_IQANDST(intr_idx < 0) |
1909 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_STATUS_PAGE) |
1910 V_FW_IQ_CMD_IQANDSTINDEX(intr_idx >= 0 ? intr_idx :
1912 c.iqdroprss_to_iqesize =
1913 htons(V_FW_IQ_CMD_IQPCIECH(pciechan) |
1914 F_FW_IQ_CMD_IQGTSMODE |
1915 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->pktcnt_idx) |
1916 V_FW_IQ_CMD_IQESIZE(ilog2(iq->iqe_len) - 4));
1917 c.iqsize = htons(iq->size);
1918 c.iqaddr = cpu_to_be64(iq->phys_addr);
1921 struct sge_eth_rxq *rxq = container_of(fl, struct sge_eth_rxq,
1923 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
1926 * Allocate the ring for the hardware free list (with space
1927 * for its status page) along with the associated software
1928 * descriptor ring. The free list size needs to be a multiple
1929 * of the Egress Queue Unit and at least 2 Egress Units larger
1930 * than the SGE's Egress Congrestion Threshold
1931 * (fl_starve_thres - 1).
1933 if (fl->size < s->fl_starve_thres - 1 + 2 * 8)
1934 fl->size = s->fl_starve_thres - 1 + 2 * 8;
1935 fl->size = cxgbe_roundup(fl->size, 8);
1937 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1938 eth_dev->device->driver->name,
1939 fwevtq ? "fwq_ring" : "fl_ring",
1940 eth_dev->data->port_id, queue_id);
1941 snprintf(z_name_sw, sizeof(z_name_sw), "%s_sw_ring", z_name);
1943 fl->desc = alloc_ring(fl->size, sizeof(__be64),
1944 sizeof(struct rx_sw_desc),
1945 &fl->addr, &fl->sdesc, s->stat_len,
1946 queue_id, socket_id, z_name, z_name_sw);
1951 flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
1952 c.iqns_to_fl0congen |=
1953 htonl(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
1954 (unlikely(rxq->usembufs) ?
1955 0 : F_FW_IQ_CMD_FL0PACKEN) |
1956 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
1957 F_FW_IQ_CMD_FL0PADEN);
1958 if (is_pf4(adap) && cong >= 0)
1959 c.iqns_to_fl0congen |=
1960 htonl(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
1961 F_FW_IQ_CMD_FL0CONGCIF |
1962 F_FW_IQ_CMD_FL0CONGEN);
1964 /* In T6, for egress queue type FL there is internal overhead
1965 * of 16B for header going into FLM module.
1966 * Hence maximum allowed burst size will be 448 bytes.
1968 c.fl0dcaen_to_fl0cidxfthresh =
1969 htons(V_FW_IQ_CMD_FL0FBMIN(chip_ver <= CHELSIO_T5 ?
1970 X_FETCHBURSTMIN_128B :
1971 X_FETCHBURSTMIN_64B) |
1972 V_FW_IQ_CMD_FL0FBMAX(chip_ver <= CHELSIO_T5 ?
1973 X_FETCHBURSTMAX_512B :
1974 X_FETCHBURSTMAX_256B));
1975 c.fl0size = htons(flsz);
1976 c.fl0addr = cpu_to_be64(fl->addr);
1980 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
1982 ret = t4vf_wr_mbox(adap, &c, sizeof(c), &c);
1986 iq->cur_desc = iq->desc;
1990 iq->next_intr_params = iq->intr_params;
1991 iq->cntxt_id = ntohs(c.iqid);
1992 iq->abs_id = ntohs(c.physiqid);
1993 iq->bar2_addr = bar2_address(adap, iq->cntxt_id, T4_BAR2_QTYPE_INGRESS,
1995 iq->size--; /* subtract status entry */
1996 iq->stat = (void *)&iq->desc[iq->size * 8];
1997 iq->eth_dev = eth_dev;
1999 iq->port_id = pi->pidx;
2002 /* set offset to -1 to distinguish ingress queues without FL */
2003 iq->offset = fl ? 0 : -1;
2006 fl->cntxt_id = ntohs(c.fl0id);
2011 fl->alloc_failed = 0;
2014 * Note, we must initialize the BAR2 Free List User Doorbell
2015 * information before refilling the Free List!
2017 fl->bar2_addr = bar2_address(adap, fl->cntxt_id,
2018 T4_BAR2_QTYPE_EGRESS,
2021 nb_refill = refill_fl(adap, fl, fl_cap(fl));
2022 if (nb_refill != fl_cap(fl)) {
2024 dev_err(adap, "%s: mbuf alloc failed with error: %d\n",
2031 * For T5 and later we attempt to set up the Congestion Manager values
2032 * of the new RX Ethernet Queue. This should really be handled by
2033 * firmware because it's more complex than any host driver wants to
2034 * get involved with and it's different per chip and this is almost
2035 * certainly wrong. Formware would be wrong as well, but it would be
2036 * a lot easier to fix in one place ... For now we do something very
2037 * simple (and hopefully less wrong).
2039 if (is_pf4(adap) && !is_t4(adap->params.chip) && cong >= 0) {
2043 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2044 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2045 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id));
2047 val = V_CONMCTXT_CNGTPMODE(X_CONMCTXT_CNGTPMODE_QUEUE);
2049 val = V_CONMCTXT_CNGTPMODE(
2050 X_CONMCTXT_CNGTPMODE_CHANNEL);
2051 for (i = 0; i < 4; i++) {
2052 if (cong & (1 << i))
2053 val |= V_CONMCTXT_CNGCHMAP(1 <<
2057 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
2060 dev_warn(adap->pdev_dev, "Failed to set Congestion Manager Context for Ingress Queue %d: %d\n",
2061 iq->cntxt_id, -ret);
2067 t4_iq_free(adap, adap->mbox, adap->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
2068 iq->cntxt_id, fl->cntxt_id, 0xffff);
2077 if (fl && fl->desc) {
2078 rte_free(fl->sdesc);
2086 static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id,
2087 unsigned int abs_id)
2091 q->bar2_addr = bar2_address(adap, q->cntxt_id, T4_BAR2_QTYPE_EGRESS,
2098 q->coalesce.idx = 0;
2099 q->coalesce.len = 0;
2100 q->coalesce.flits = 0;
2101 q->last_coal_idx = 0;
2103 q->stat = (void *)&q->desc[q->size];
2106 int t4_sge_eth_txq_start(struct sge_eth_txq *txq)
2109 * TODO: For flow-control, queue may be stopped waiting to reclaim
2111 * Ensure queue is in EQ_STOPPED state before starting it.
2113 if (!(txq->flags & EQ_STOPPED))
2116 txq->flags &= ~EQ_STOPPED;
2121 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq)
2123 txq->flags |= EQ_STOPPED;
2128 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
2129 struct rte_eth_dev *eth_dev, uint16_t queue_id,
2130 unsigned int iqid, int socket_id)
2133 struct fw_eq_eth_cmd c;
2134 struct sge *s = &adap->sge;
2135 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
2136 char z_name[RTE_MEMZONE_NAMESIZE];
2137 char z_name_sw[RTE_MEMZONE_NAMESIZE];
2140 /* Add status entries */
2141 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2143 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2144 eth_dev->device->driver->name, "tx_ring",
2145 eth_dev->data->port_id, queue_id);
2146 snprintf(z_name_sw, sizeof(z_name_sw), "%s_sw_ring", z_name);
2148 txq->q.desc = alloc_ring(txq->q.size, sizeof(struct tx_desc),
2149 sizeof(struct tx_sw_desc), &txq->q.phys_addr,
2150 &txq->q.sdesc, s->stat_len, queue_id,
2151 socket_id, z_name, z_name_sw);
2155 memset(&c, 0, sizeof(c));
2156 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
2157 F_FW_CMD_WRITE | F_FW_CMD_EXEC);
2159 pciechan = pi->tx_chan;
2160 c.op_to_vfn |= htonl(V_FW_EQ_ETH_CMD_PFN(adap->pf) |
2161 V_FW_EQ_ETH_CMD_VFN(0));
2163 pciechan = pi->port_id;
2166 c.alloc_to_len16 = htonl(F_FW_EQ_ETH_CMD_ALLOC |
2167 F_FW_EQ_ETH_CMD_EQSTART | (sizeof(c) / 16));
2168 c.autoequiqe_to_viid = htonl(F_FW_EQ_ETH_CMD_AUTOEQUEQE |
2169 V_FW_EQ_ETH_CMD_VIID(pi->viid));
2170 c.fetchszm_to_iqid =
2171 htonl(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
2172 V_FW_EQ_ETH_CMD_PCIECHN(pciechan) |
2173 F_FW_EQ_ETH_CMD_FETCHRO | V_FW_EQ_ETH_CMD_IQID(iqid));
2175 htonl(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
2176 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
2177 V_FW_EQ_ETH_CMD_EQSIZE(nentries));
2178 c.eqaddr = rte_cpu_to_be_64(txq->q.phys_addr);
2181 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2183 ret = t4vf_wr_mbox(adap, &c, sizeof(c), &c);
2185 rte_free(txq->q.sdesc);
2186 txq->q.sdesc = NULL;
2191 init_txq(adap, &txq->q, G_FW_EQ_ETH_CMD_EQID(ntohl(c.eqid_pkd)),
2192 G_FW_EQ_ETH_CMD_PHYSEQID(ntohl(c.physeqid_pkd)));
2194 txq->stats.pkts = 0;
2195 txq->stats.tx_cso = 0;
2196 txq->stats.coal_wr = 0;
2197 txq->stats.vlan_ins = 0;
2198 txq->stats.tx_bytes = 0;
2199 txq->stats.coal_pkts = 0;
2200 txq->stats.mapping_err = 0;
2201 txq->flags |= EQ_STOPPED;
2202 txq->eth_dev = eth_dev;
2203 txq->data = eth_dev->data;
2204 t4_os_lock_init(&txq->txq_lock);
2208 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
2209 struct rte_eth_dev *eth_dev, uint16_t queue_id,
2210 unsigned int iqid, int socket_id)
2213 struct fw_eq_ctrl_cmd c;
2214 struct sge *s = &adap->sge;
2215 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
2216 char z_name[RTE_MEMZONE_NAMESIZE];
2217 char z_name_sw[RTE_MEMZONE_NAMESIZE];
2219 /* Add status entries */
2220 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2222 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2223 eth_dev->device->driver->name, "ctrl_tx_ring",
2224 eth_dev->data->port_id, queue_id);
2225 snprintf(z_name_sw, sizeof(z_name_sw), "%s_sw_ring", z_name);
2227 txq->q.desc = alloc_ring(txq->q.size, sizeof(struct tx_desc),
2228 0, &txq->q.phys_addr,
2230 socket_id, z_name, z_name_sw);
2234 memset(&c, 0, sizeof(c));
2235 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
2236 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
2237 V_FW_EQ_CTRL_CMD_PFN(adap->pf) |
2238 V_FW_EQ_CTRL_CMD_VFN(0));
2239 c.alloc_to_len16 = htonl(F_FW_EQ_CTRL_CMD_ALLOC |
2240 F_FW_EQ_CTRL_CMD_EQSTART | (sizeof(c) / 16));
2241 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(0));
2242 c.physeqid_pkd = htonl(0);
2243 c.fetchszm_to_iqid =
2244 htonl(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
2245 V_FW_EQ_CTRL_CMD_PCIECHN(pi->tx_chan) |
2246 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(iqid));
2248 htonl(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
2249 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
2250 V_FW_EQ_CTRL_CMD_EQSIZE(nentries));
2251 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2253 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
2259 init_txq(adap, &txq->q, G_FW_EQ_CTRL_CMD_EQID(ntohl(c.cmpliqid_eqid)),
2260 G_FW_EQ_CTRL_CMD_EQID(ntohl(c. physeqid_pkd)));
2261 txq->adapter = adap;
2266 static void free_txq(struct sge_txq *q)
2273 static void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq,
2276 unsigned int fl_id = fl ? fl->cntxt_id : 0xffff;
2278 t4_iq_free(adap, adap->mbox, adap->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
2279 rq->cntxt_id, fl_id, 0xffff);
2285 free_rx_bufs(fl, fl->avail);
2286 rte_free(fl->sdesc);
2294 * Clear all queues of the port
2296 * Note: This function must only be called after rx and tx path
2297 * of the port have been disabled.
2299 void t4_sge_eth_clear_queues(struct port_info *pi)
2302 struct adapter *adap = pi->adapter;
2303 struct sge_eth_rxq *rxq = &adap->sge.ethrxq[pi->first_qset];
2304 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
2306 for (i = 0; i < pi->n_rx_qsets; i++, rxq++) {
2308 t4_sge_eth_rxq_stop(adap, &rxq->rspq);
2310 for (i = 0; i < pi->n_tx_qsets; i++, txq++) {
2312 struct sge_txq *q = &txq->q;
2314 t4_sge_eth_txq_stop(txq);
2315 reclaim_completed_tx(q);
2316 free_tx_desc(q, q->size);
2317 q->equeidx = q->pidx;
2322 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq)
2324 if (rxq->rspq.desc) {
2325 t4_sge_eth_rxq_stop(adap, &rxq->rspq);
2326 free_rspq_fl(adap, &rxq->rspq, rxq->fl.size ? &rxq->fl : NULL);
2330 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq)
2333 t4_sge_eth_txq_stop(txq);
2334 reclaim_completed_tx(&txq->q);
2335 t4_eth_eq_free(adap, adap->mbox, adap->pf, 0, txq->q.cntxt_id);
2336 free_tx_desc(&txq->q, txq->q.size);
2337 rte_free(txq->q.sdesc);
2342 void t4_sge_tx_monitor_start(struct adapter *adap)
2344 rte_eal_alarm_set(50, tx_timer_cb, (void *)adap);
2347 void t4_sge_tx_monitor_stop(struct adapter *adap)
2349 rte_eal_alarm_cancel(tx_timer_cb, (void *)adap);
2353 * t4_free_sge_resources - free SGE resources
2354 * @adap: the adapter
2356 * Frees resources used by the SGE queue sets.
2358 void t4_free_sge_resources(struct adapter *adap)
2361 struct sge_eth_rxq *rxq = &adap->sge.ethrxq[0];
2362 struct sge_eth_txq *txq = &adap->sge.ethtxq[0];
2364 /* clean up Ethernet Tx/Rx queues */
2365 for (i = 0; i < adap->sge.max_ethqsets; i++, rxq++, txq++) {
2366 /* Free only the queues allocated */
2367 if (rxq->rspq.desc) {
2368 t4_sge_eth_rxq_release(adap, rxq);
2369 rxq->rspq.eth_dev = NULL;
2372 t4_sge_eth_txq_release(adap, txq);
2373 txq->eth_dev = NULL;
2377 /* clean up control Tx queues */
2378 for (i = 0; i < ARRAY_SIZE(adap->sge.ctrlq); i++) {
2379 struct sge_ctrl_txq *cq = &adap->sge.ctrlq[i];
2382 reclaim_completed_tx_imm(&cq->q);
2383 t4_ctrl_eq_free(adap, adap->mbox, adap->pf, 0,
2389 if (adap->sge.fw_evtq.desc)
2390 free_rspq_fl(adap, &adap->sge.fw_evtq, NULL);
2394 * t4_sge_init - initialize SGE
2395 * @adap: the adapter
2397 * Performs SGE initialization needed every time after a chip reset.
2398 * We do not initialize any of the queues here, instead the driver
2399 * top-level must request those individually.
2401 * Called in two different modes:
2403 * 1. Perform actual hardware initialization and record hard-coded
2404 * parameters which were used. This gets used when we're the
2405 * Master PF and the Firmware Configuration File support didn't
2406 * work for some reason.
2408 * 2. We're not the Master PF or initialization was performed with
2409 * a Firmware Configuration File. In this case we need to grab
2410 * any of the SGE operating parameters that we need to have in
2411 * order to do our job and make sure we can live with them ...
2413 static int t4_sge_init_soft(struct adapter *adap)
2415 struct sge *s = &adap->sge;
2416 u32 fl_small_pg, fl_large_pg, fl_small_mtu, fl_large_mtu;
2417 u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5;
2418 u32 ingress_rx_threshold;
2421 * Verify that CPL messages are going to the Ingress Queue for
2422 * process_responses() and that only packet data is going to the
2425 if ((t4_read_reg(adap, A_SGE_CONTROL) & F_RXPKTCPLMODE) !=
2426 V_RXPKTCPLMODE(X_RXPKTCPLMODE_SPLIT)) {
2427 dev_err(adap, "bad SGE CPL MODE\n");
2432 * Validate the Host Buffer Register Array indices that we want to
2435 * XXX Note that we should really read through the Host Buffer Size
2436 * XXX register array and find the indices of the Buffer Sizes which
2437 * XXX meet our needs!
2439 #define READ_FL_BUF(x) \
2440 t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE0 + (x) * sizeof(u32))
2442 fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF);
2443 fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF);
2444 fl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF);
2445 fl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF);
2448 * We only bother using the Large Page logic if the Large Page Buffer
2449 * is larger than our Page Size Buffer.
2451 if (fl_large_pg <= fl_small_pg)
2457 * The Page Size Buffer must be exactly equal to our Page Size and the
2458 * Large Page Size Buffer should be 0 (per above) or a power of 2.
2460 if (fl_small_pg != CXGBE_PAGE_SIZE ||
2461 (fl_large_pg & (fl_large_pg - 1)) != 0) {
2462 dev_err(adap, "bad SGE FL page buffer sizes [%d, %d]\n",
2463 fl_small_pg, fl_large_pg);
2467 s->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT;
2469 if (adap->use_unpacked_mode) {
2472 if (fl_small_mtu < FL_MTU_SMALL_BUFSIZE(adap)) {
2473 dev_err(adap, "bad SGE FL small MTU %d\n",
2477 if (fl_large_mtu < FL_MTU_LARGE_BUFSIZE(adap)) {
2478 dev_err(adap, "bad SGE FL large MTU %d\n",
2487 * Retrieve our RX interrupt holdoff timer values and counter
2488 * threshold values from the SGE parameters.
2490 timer_value_0_and_1 = t4_read_reg(adap, A_SGE_TIMER_VALUE_0_AND_1);
2491 timer_value_2_and_3 = t4_read_reg(adap, A_SGE_TIMER_VALUE_2_AND_3);
2492 timer_value_4_and_5 = t4_read_reg(adap, A_SGE_TIMER_VALUE_4_AND_5);
2493 s->timer_val[0] = core_ticks_to_us(adap,
2494 G_TIMERVALUE0(timer_value_0_and_1));
2495 s->timer_val[1] = core_ticks_to_us(adap,
2496 G_TIMERVALUE1(timer_value_0_and_1));
2497 s->timer_val[2] = core_ticks_to_us(adap,
2498 G_TIMERVALUE2(timer_value_2_and_3));
2499 s->timer_val[3] = core_ticks_to_us(adap,
2500 G_TIMERVALUE3(timer_value_2_and_3));
2501 s->timer_val[4] = core_ticks_to_us(adap,
2502 G_TIMERVALUE4(timer_value_4_and_5));
2503 s->timer_val[5] = core_ticks_to_us(adap,
2504 G_TIMERVALUE5(timer_value_4_and_5));
2506 ingress_rx_threshold = t4_read_reg(adap, A_SGE_INGRESS_RX_THRESHOLD);
2507 s->counter_val[0] = G_THRESHOLD_0(ingress_rx_threshold);
2508 s->counter_val[1] = G_THRESHOLD_1(ingress_rx_threshold);
2509 s->counter_val[2] = G_THRESHOLD_2(ingress_rx_threshold);
2510 s->counter_val[3] = G_THRESHOLD_3(ingress_rx_threshold);
2515 int t4_sge_init(struct adapter *adap)
2517 struct sge *s = &adap->sge;
2518 u32 sge_control, sge_conm_ctrl;
2519 int ret, egress_threshold;
2522 * Ingress Padding Boundary and Egress Status Page Size are set up by
2523 * t4_fixup_host_params().
2525 sge_control = t4_read_reg(adap, A_SGE_CONTROL);
2526 s->pktshift = G_PKTSHIFT(sge_control);
2527 s->stat_len = (sge_control & F_EGRSTATUSPAGESIZE) ? 128 : 64;
2528 s->fl_align = t4_fl_pkt_align(adap);
2529 ret = t4_sge_init_soft(adap);
2531 dev_err(adap, "%s: t4_sge_init_soft failed, error %d\n",
2537 * A FL with <= fl_starve_thres buffers is starving and a periodic
2538 * timer will attempt to refill it. This needs to be larger than the
2539 * SGE's Egress Congestion Threshold. If it isn't, then we can get
2540 * stuck waiting for new packets while the SGE is waiting for us to
2541 * give it more Free List entries. (Note that the SGE's Egress
2542 * Congestion Threshold is in units of 2 Free List pointers.) For T4,
2543 * there was only a single field to control this. For T5 there's the
2544 * original field which now only applies to Unpacked Mode Free List
2545 * buffers and a new field which only applies to Packed Mode Free List
2548 sge_conm_ctrl = t4_read_reg(adap, A_SGE_CONM_CTRL);
2549 if (is_t4(adap->params.chip) || adap->use_unpacked_mode)
2550 egress_threshold = G_EGRTHRESHOLD(sge_conm_ctrl);
2552 egress_threshold = G_EGRTHRESHOLDPACKING(sge_conm_ctrl);
2553 s->fl_starve_thres = 2 * egress_threshold + 1;
2558 int t4vf_sge_init(struct adapter *adap)
2560 struct sge_params *sge_params = &adap->params.sge;
2561 u32 sge_ingress_queues_per_page;
2562 u32 sge_egress_queues_per_page;
2563 u32 sge_control, sge_control2;
2564 u32 fl_small_pg, fl_large_pg;
2565 u32 sge_ingress_rx_threshold;
2566 u32 sge_timer_value_0_and_1;
2567 u32 sge_timer_value_2_and_3;
2568 u32 sge_timer_value_4_and_5;
2569 u32 sge_congestion_control;
2570 struct sge *s = &adap->sge;
2571 unsigned int s_hps, s_qpp;
2572 u32 sge_host_page_size;
2573 u32 params[7], vals[7];
2576 /* query basic params from fw */
2577 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
2578 V_FW_PARAMS_PARAM_XYZ(A_SGE_CONTROL));
2579 params[1] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
2580 V_FW_PARAMS_PARAM_XYZ(A_SGE_HOST_PAGE_SIZE));
2581 params[2] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
2582 V_FW_PARAMS_PARAM_XYZ(A_SGE_FL_BUFFER_SIZE0));
2583 params[3] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
2584 V_FW_PARAMS_PARAM_XYZ(A_SGE_FL_BUFFER_SIZE1));
2585 params[4] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
2586 V_FW_PARAMS_PARAM_XYZ(A_SGE_TIMER_VALUE_0_AND_1));
2587 params[5] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
2588 V_FW_PARAMS_PARAM_XYZ(A_SGE_TIMER_VALUE_2_AND_3));
2589 params[6] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
2590 V_FW_PARAMS_PARAM_XYZ(A_SGE_TIMER_VALUE_4_AND_5));
2591 v = t4vf_query_params(adap, 7, params, vals);
2592 if (v != FW_SUCCESS)
2595 sge_control = vals[0];
2596 sge_host_page_size = vals[1];
2597 fl_small_pg = vals[2];
2598 fl_large_pg = vals[3];
2599 sge_timer_value_0_and_1 = vals[4];
2600 sge_timer_value_2_and_3 = vals[5];
2601 sge_timer_value_4_and_5 = vals[6];
2604 * Start by vetting the basic SGE parameters which have been set up by
2605 * the Physical Function Driver.
2608 /* We only bother using the Large Page logic if the Large Page Buffer
2609 * is larger than our Page Size Buffer.
2611 if (fl_large_pg <= fl_small_pg)
2614 /* The Page Size Buffer must be exactly equal to our Page Size and the
2615 * Large Page Size Buffer should be 0 (per above) or a power of 2.
2617 if (fl_small_pg != CXGBE_PAGE_SIZE ||
2618 (fl_large_pg & (fl_large_pg - 1)) != 0) {
2619 dev_err(adapter->pdev_dev, "bad SGE FL buffer sizes [%d, %d]\n",
2620 fl_small_pg, fl_large_pg);
2624 if ((sge_control & F_RXPKTCPLMODE) !=
2625 V_RXPKTCPLMODE(X_RXPKTCPLMODE_SPLIT)) {
2626 dev_err(adapter->pdev_dev, "bad SGE CPL MODE\n");
2631 /* Grab ingress packing boundary from SGE_CONTROL2 for */
2632 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
2633 V_FW_PARAMS_PARAM_XYZ(A_SGE_CONTROL2));
2634 v = t4vf_query_params(adap, 1, params, vals);
2635 if (v != FW_SUCCESS) {
2636 dev_err(adapter, "Unable to get SGE Control2; "
2637 "probably old firmware.\n");
2640 sge_control2 = vals[0];
2642 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
2643 V_FW_PARAMS_PARAM_XYZ(A_SGE_INGRESS_RX_THRESHOLD));
2644 params[1] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
2645 V_FW_PARAMS_PARAM_XYZ(A_SGE_CONM_CTRL));
2646 v = t4vf_query_params(adap, 2, params, vals);
2647 if (v != FW_SUCCESS)
2649 sge_ingress_rx_threshold = vals[0];
2650 sge_congestion_control = vals[1];
2651 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
2652 V_FW_PARAMS_PARAM_XYZ(A_SGE_EGRESS_QUEUES_PER_PAGE_VF));
2653 params[1] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_REG) |
2654 V_FW_PARAMS_PARAM_XYZ(A_SGE_INGRESS_QUEUES_PER_PAGE_VF));
2655 v = t4vf_query_params(adap, 2, params, vals);
2656 if (v != FW_SUCCESS) {
2657 dev_warn(adap, "Unable to get VF SGE Queues/Page; "
2658 "probably old firmware.\n");
2661 sge_egress_queues_per_page = vals[0];
2662 sge_ingress_queues_per_page = vals[1];
2665 * We need the Queues/Page for our VF. This is based on the
2666 * PF from which we're instantiated and is indexed in the
2667 * register we just read.
2669 s_hps = (S_HOSTPAGESIZEPF0 +
2670 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adap->pf);
2672 ((sge_host_page_size >> s_hps) & M_HOSTPAGESIZEPF0);
2674 s_qpp = (S_QUEUESPERPAGEPF0 +
2675 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adap->pf);
2676 sge_params->eq_qpp =
2677 ((sge_egress_queues_per_page >> s_qpp)
2678 & M_QUEUESPERPAGEPF0);
2679 sge_params->iq_qpp =
2680 ((sge_ingress_queues_per_page >> s_qpp)
2681 & M_QUEUESPERPAGEPF0);
2684 * Now translate the queried parameters into our internal forms.
2687 s->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT;
2688 s->stat_len = ((sge_control & F_EGRSTATUSPAGESIZE)
2690 s->pktshift = G_PKTSHIFT(sge_control);
2691 s->fl_align = t4vf_fl_pkt_align(adap, sge_control, sge_control2);
2694 * A FL with <= fl_starve_thres buffers is starving and a periodic
2695 * timer will attempt to refill it. This needs to be larger than the
2696 * SGE's Egress Congestion Threshold. If it isn't, then we can get
2697 * stuck waiting for new packets while the SGE is waiting for us to
2698 * give it more Free List entries. (Note that the SGE's Egress
2699 * Congestion Threshold is in units of 2 Free List pointers.)
2701 switch (CHELSIO_CHIP_VERSION(adap->params.chip)) {
2703 s->fl_starve_thres =
2704 G_EGRTHRESHOLDPACKING(sge_congestion_control);
2708 s->fl_starve_thres =
2709 G_T6_EGRTHRESHOLDPACKING(sge_congestion_control);
2712 s->fl_starve_thres = s->fl_starve_thres * 2 + 1;
2715 * Save RX interrupt holdoff timer values and counter
2716 * threshold values from the SGE parameters.
2718 s->timer_val[0] = core_ticks_to_us(adap,
2719 G_TIMERVALUE0(sge_timer_value_0_and_1));
2720 s->timer_val[1] = core_ticks_to_us(adap,
2721 G_TIMERVALUE1(sge_timer_value_0_and_1));
2722 s->timer_val[2] = core_ticks_to_us(adap,
2723 G_TIMERVALUE2(sge_timer_value_2_and_3));
2724 s->timer_val[3] = core_ticks_to_us(adap,
2725 G_TIMERVALUE3(sge_timer_value_2_and_3));
2726 s->timer_val[4] = core_ticks_to_us(adap,
2727 G_TIMERVALUE4(sge_timer_value_4_and_5));
2728 s->timer_val[5] = core_ticks_to_us(adap,
2729 G_TIMERVALUE5(sge_timer_value_4_and_5));
2730 s->counter_val[0] = G_THRESHOLD_0(sge_ingress_rx_threshold);
2731 s->counter_val[1] = G_THRESHOLD_1(sge_ingress_rx_threshold);
2732 s->counter_val[2] = G_THRESHOLD_2(sge_ingress_rx_threshold);
2733 s->counter_val[3] = G_THRESHOLD_3(sge_ingress_rx_threshold);