4 * Copyright(c) 2014-2015 Chelsio Communications.
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34 #include <sys/queue.h>
42 #include <netinet/in.h>
44 #include <rte_byteorder.h>
45 #include <rte_common.h>
46 #include <rte_cycles.h>
47 #include <rte_interrupts.h>
49 #include <rte_debug.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
55 #include <rte_tailq.h>
57 #include <rte_alarm.h>
58 #include <rte_ether.h>
59 #include <rte_ethdev.h>
60 #include <rte_atomic.h>
61 #include <rte_malloc.h>
62 #include <rte_random.h>
70 static inline void ship_tx_pkt_coalesce_wr(struct adapter *adap,
71 struct sge_eth_txq *txq);
74 * Max number of Rx buffers we replenish at a time.
76 #define MAX_RX_REFILL 64U
78 #define NOMEM_TMR_IDX (SGE_NTIMERS - 1)
81 * Max Tx descriptor space we allow for an Ethernet packet to be inlined
84 #define MAX_IMM_TX_PKT_LEN 256
87 * Rx buffer sizes for "usembufs" Free List buffers (one ingress packet
88 * per mbuf buffer). We currently only support two sizes for 1500- and
89 * 9000-byte MTUs. We could easily support more but there doesn't seem to be
90 * much need for that ...
92 #define FL_MTU_SMALL 1500
93 #define FL_MTU_LARGE 9000
95 static inline unsigned int fl_mtu_bufsize(struct adapter *adapter,
98 struct sge *s = &adapter->sge;
100 return CXGBE_ALIGN(s->pktshift + ETHER_HDR_LEN + VLAN_HLEN + mtu,
104 #define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL)
105 #define FL_MTU_LARGE_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_LARGE)
108 * Bits 0..3 of rx_sw_desc.dma_addr have special meaning. The hardware uses
109 * these to specify the buffer size as an index into the SGE Free List Buffer
110 * Size register array. We also use bit 4, when the buffer has been unmapped
111 * for DMA, but this is of course never sent to the hardware and is only used
112 * to prevent double unmappings. All of the above requires that the Free List
113 * Buffers which we allocate have the bottom 5 bits free (0) -- i.e. are
114 * 32-byte or or a power of 2 greater in alignment. Since the SGE's minimal
115 * Free List Buffer alignment is 32 bytes, this works out for us ...
118 RX_BUF_FLAGS = 0x1f, /* bottom five bits are special */
119 RX_BUF_SIZE = 0x0f, /* bottom three bits are for buf sizes */
120 RX_UNMAPPED_BUF = 0x10, /* buffer is not mapped */
123 * XXX We shouldn't depend on being able to use these indices.
124 * XXX Especially when some other Master PF has initialized the
125 * XXX adapter or we use the Firmware Configuration File. We
126 * XXX should really search through the Host Buffer Size register
127 * XXX array for the appropriately sized buffer indices.
129 RX_SMALL_PG_BUF = 0x0, /* small (PAGE_SIZE) page buffer */
130 RX_LARGE_PG_BUF = 0x1, /* buffer large page buffer */
132 RX_SMALL_MTU_BUF = 0x2, /* small MTU buffer */
133 RX_LARGE_MTU_BUF = 0x3, /* large MTU buffer */
137 * txq_avail - return the number of available slots in a Tx queue
140 * Returns the number of descriptors in a Tx queue available to write new
143 static inline unsigned int txq_avail(const struct sge_txq *q)
145 return q->size - 1 - q->in_use;
148 static int map_mbuf(struct rte_mbuf *mbuf, dma_addr_t *addr)
150 struct rte_mbuf *m = mbuf;
152 for (; m; m = m->next, addr++) {
153 *addr = m->buf_physaddr + rte_pktmbuf_headroom(m);
164 * free_tx_desc - reclaims Tx descriptors and their buffers
165 * @q: the Tx queue to reclaim descriptors from
166 * @n: the number of descriptors to reclaim
168 * Reclaims Tx descriptors from an SGE Tx queue and frees the associated
169 * Tx buffers. Called with the Tx queue lock held.
171 static void free_tx_desc(struct sge_txq *q, unsigned int n)
173 struct tx_sw_desc *d;
174 unsigned int cidx = 0;
178 if (d->mbuf) { /* an SGL is present */
179 rte_pktmbuf_free(d->mbuf);
182 if (d->coalesce.idx) {
185 for (i = 0; i < d->coalesce.idx; i++) {
186 rte_pktmbuf_free(d->coalesce.mbuf[i]);
187 d->coalesce.mbuf[i] = NULL;
192 if (++cidx == q->size) {
196 RTE_MBUF_PREFETCH_TO_FREE(&q->sdesc->mbuf->pool);
200 static void reclaim_tx_desc(struct sge_txq *q, unsigned int n)
202 struct tx_sw_desc *d;
203 unsigned int cidx = q->cidx;
207 if (d->mbuf) { /* an SGL is present */
208 rte_pktmbuf_free(d->mbuf);
212 if (++cidx == q->size) {
221 * fl_cap - return the capacity of a free-buffer list
224 * Returns the capacity of a free-buffer list. The capacity is less than
225 * the size because one descriptor needs to be left unpopulated, otherwise
226 * HW will think the FL is empty.
228 static inline unsigned int fl_cap(const struct sge_fl *fl)
230 return fl->size - 8; /* 1 descriptor = 8 buffers */
234 * fl_starving - return whether a Free List is starving.
235 * @adapter: pointer to the adapter
238 * Tests specified Free List to see whether the number of buffers
239 * available to the hardware has falled below our "starvation"
242 static inline bool fl_starving(const struct adapter *adapter,
243 const struct sge_fl *fl)
245 const struct sge *s = &adapter->sge;
247 return fl->avail - fl->pend_cred <= s->fl_starve_thres;
250 static inline unsigned int get_buf_size(struct adapter *adapter,
251 const struct rx_sw_desc *d)
253 unsigned int rx_buf_size_idx = d->dma_addr & RX_BUF_SIZE;
254 unsigned int buf_size = 0;
256 switch (rx_buf_size_idx) {
257 case RX_SMALL_MTU_BUF:
258 buf_size = FL_MTU_SMALL_BUFSIZE(adapter);
261 case RX_LARGE_MTU_BUF:
262 buf_size = FL_MTU_LARGE_BUFSIZE(adapter);
274 * free_rx_bufs - free the Rx buffers on an SGE free list
275 * @q: the SGE free list to free buffers from
276 * @n: how many buffers to free
278 * Release the next @n buffers on an SGE free-buffer Rx queue. The
279 * buffers must be made inaccessible to HW before calling this function.
281 static void free_rx_bufs(struct sge_fl *q, int n)
283 unsigned int cidx = q->cidx;
284 struct rx_sw_desc *d;
289 rte_pktmbuf_free(d->buf);
293 if (++cidx == q->size) {
303 * unmap_rx_buf - unmap the current Rx buffer on an SGE free list
304 * @q: the SGE free list
306 * Unmap the current buffer on an SGE free-buffer Rx queue. The
307 * buffer must be made inaccessible to HW before calling this function.
309 * This is similar to @free_rx_bufs above but does not free the buffer.
310 * Do note that the FL still loses any further access to the buffer.
312 static void unmap_rx_buf(struct sge_fl *q)
314 if (++q->cidx == q->size)
319 static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
321 if (q->pend_cred >= 64) {
322 u32 val = adap->params.arch.sge_fl_db;
324 if (is_t4(adap->params.chip))
325 val |= V_PIDX(q->pend_cred / 8);
327 val |= V_PIDX_T5(q->pend_cred / 8);
330 * Make sure all memory writes to the Free List queue are
331 * committed before we tell the hardware about them.
336 * If we don't have access to the new User Doorbell (T5+), use
337 * the old doorbell mechanism; otherwise use the new BAR2
340 if (unlikely(!q->bar2_addr)) {
341 t4_write_reg_relaxed(adap, MYPF_REG(A_SGE_PF_KDOORBELL),
342 val | V_QID(q->cntxt_id));
344 writel_relaxed(val | V_QID(q->bar2_qid),
345 (void *)((uintptr_t)q->bar2_addr +
349 * This Write memory Barrier will force the write to
350 * the User Doorbell area to be flushed.
358 static inline void set_rx_sw_desc(struct rx_sw_desc *sd, void *buf,
362 sd->dma_addr = mapping; /* includes size low bits */
366 * refill_fl_usembufs - refill an SGE Rx buffer ring with mbufs
368 * @q: the ring to refill
369 * @n: the number of new buffers to allocate
371 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
372 * allocated with the supplied gfp flags. The caller must assure that
373 * @n does not exceed the queue's capacity. If afterwards the queue is
374 * found critically low mark it as starving in the bitmap of starving FLs.
376 * Returns the number of buffers allocated.
378 static unsigned int refill_fl_usembufs(struct adapter *adap, struct sge_fl *q,
381 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, fl);
382 unsigned int cred = q->avail;
383 __be64 *d = &q->desc[q->pidx];
384 struct rx_sw_desc *sd = &q->sdesc[q->pidx];
385 unsigned int buf_size_idx = RX_SMALL_MTU_BUF;
386 struct rte_mbuf *buf_bulk[n];
388 struct rte_pktmbuf_pool_private *mbp_priv;
389 u8 jumbo_en = rxq->rspq.eth_dev->data->dev_conf.rxmode.jumbo_frame;
391 /* Use jumbo mtu buffers iff mbuf data room size can fit jumbo data. */
392 mbp_priv = rte_mempool_get_priv(rxq->rspq.mb_pool);
394 ((mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM) >= 9000))
395 buf_size_idx = RX_LARGE_MTU_BUF;
397 ret = rte_mempool_get_bulk(rxq->rspq.mb_pool, (void *)buf_bulk, n);
398 if (unlikely(ret != 0)) {
399 dev_debug(adap, "%s: failed to allocated fl entries in bulk ..\n",
402 rxq->rspq.eth_dev->data->rx_mbuf_alloc_failed++;
406 for (i = 0; i < n; i++) {
407 struct rte_mbuf *mbuf = buf_bulk[i];
411 dev_debug(adap, "%s: mbuf alloc failed\n", __func__);
413 rxq->rspq.eth_dev->data->rx_mbuf_alloc_failed++;
417 rte_mbuf_refcnt_set(mbuf, 1);
418 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
421 mbuf->port = rxq->rspq.port_id;
423 mapping = (dma_addr_t)RTE_ALIGN(mbuf->buf_physaddr +
426 mapping |= buf_size_idx;
427 *d++ = cpu_to_be64(mapping);
428 set_rx_sw_desc(sd, mbuf, mapping);
432 if (++q->pidx == q->size) {
439 out: cred = q->avail - cred;
440 q->pend_cred += cred;
443 if (unlikely(fl_starving(adap, q))) {
445 * Make sure data has been written to free list
455 * refill_fl - refill an SGE Rx buffer ring with mbufs
457 * @q: the ring to refill
458 * @n: the number of new buffers to allocate
460 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
461 * allocated with the supplied gfp flags. The caller must assure that
462 * @n does not exceed the queue's capacity. Returns the number of buffers
465 static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n)
467 return refill_fl_usembufs(adap, q, n);
470 static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
472 refill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail));
476 * Return the number of reclaimable descriptors in a Tx queue.
478 static inline int reclaimable(const struct sge_txq *q)
480 int hw_cidx = ntohs(q->stat->cidx);
484 return hw_cidx + q->size;
489 * reclaim_completed_tx - reclaims completed Tx descriptors
490 * @q: the Tx queue to reclaim completed descriptors from
492 * Reclaims Tx descriptors that the SGE has indicated it has processed.
494 void reclaim_completed_tx(struct sge_txq *q)
496 unsigned int avail = reclaimable(q);
499 /* reclaim as much as possible */
500 reclaim_tx_desc(q, avail);
502 avail = reclaimable(q);
507 * sgl_len - calculates the size of an SGL of the given capacity
508 * @n: the number of SGL entries
510 * Calculates the number of flits needed for a scatter/gather list that
511 * can hold the given number of entries.
513 static inline unsigned int sgl_len(unsigned int n)
516 * A Direct Scatter Gather List uses 32-bit lengths and 64-bit PCI DMA
517 * addresses. The DSGL Work Request starts off with a 32-bit DSGL
518 * ULPTX header, then Length0, then Address0, then, for 1 <= i <= N,
519 * repeated sequences of { Length[i], Length[i+1], Address[i],
520 * Address[i+1] } (this ensures that all addresses are on 64-bit
521 * boundaries). If N is even, then Length[N+1] should be set to 0 and
522 * Address[N+1] is omitted.
524 * The following calculation incorporates all of the above. It's
525 * somewhat hard to follow but, briefly: the "+2" accounts for the
526 * first two flits which include the DSGL header, Length0 and
527 * Address0; the "(3*(n-1))/2" covers the main body of list entries (3
528 * flits for every pair of the remaining N) +1 if (n-1) is odd; and
529 * finally the "+((n-1)&1)" adds the one remaining flit needed if
533 return (3 * n) / 2 + (n & 1) + 2;
537 * flits_to_desc - returns the num of Tx descriptors for the given flits
538 * @n: the number of flits
540 * Returns the number of Tx descriptors needed for the supplied number
543 static inline unsigned int flits_to_desc(unsigned int n)
545 return DIV_ROUND_UP(n, 8);
549 * is_eth_imm - can an Ethernet packet be sent as immediate data?
552 * Returns whether an Ethernet packet is small enough to fit as
553 * immediate data. Return value corresponds to the headroom required.
555 static inline int is_eth_imm(const struct rte_mbuf *m)
557 unsigned int hdrlen = (m->ol_flags & PKT_TX_TCP_SEG) ?
558 sizeof(struct cpl_tx_pkt_lso_core) : 0;
560 hdrlen += sizeof(struct cpl_tx_pkt);
561 if (m->pkt_len <= MAX_IMM_TX_PKT_LEN - hdrlen)
568 * calc_tx_flits - calculate the number of flits for a packet Tx WR
571 * Returns the number of flits needed for a Tx WR for the given Ethernet
572 * packet, including the needed WR and CPL headers.
574 static inline unsigned int calc_tx_flits(const struct rte_mbuf *m)
580 * If the mbuf is small enough, we can pump it out as a work request
581 * with only immediate data. In that case we just have to have the
582 * TX Packet header plus the mbuf data in the Work Request.
585 hdrlen = is_eth_imm(m);
587 return DIV_ROUND_UP(m->pkt_len + hdrlen, sizeof(__be64));
590 * Otherwise, we're going to have to construct a Scatter gather list
591 * of the mbuf body and fragments. We also include the flits necessary
592 * for the TX Packet Work Request and CPL. We always have a firmware
593 * Write Header (incorporated as part of the cpl_tx_pkt_lso and
594 * cpl_tx_pkt structures), followed by either a TX Packet Write CPL
595 * message or, if we're doing a Large Send Offload, an LSO CPL message
596 * with an embeded TX Packet Write CPL message.
598 flits = sgl_len(m->nb_segs);
600 flits += (sizeof(struct fw_eth_tx_pkt_wr) +
601 sizeof(struct cpl_tx_pkt_lso_core) +
602 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
604 flits += (sizeof(struct fw_eth_tx_pkt_wr) +
605 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
610 * write_sgl - populate a scatter/gather list for a packet
612 * @q: the Tx queue we are writing into
613 * @sgl: starting location for writing the SGL
614 * @end: points right after the end of the SGL
615 * @start: start offset into mbuf main-body data to include in the SGL
616 * @addr: address of mapped region
618 * Generates a scatter/gather list for the buffers that make up a packet.
619 * The caller must provide adequate space for the SGL that will be written.
620 * The SGL includes all of the packet's page fragments and the data in its
621 * main body except for the first @start bytes. @sgl must be 16-byte
622 * aligned and within a Tx descriptor with available space. @end points
623 * write after the end of the SGL but does not account for any potential
624 * wrap around, i.e., @end > @sgl.
626 static void write_sgl(struct rte_mbuf *mbuf, struct sge_txq *q,
627 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
628 const dma_addr_t *addr)
631 struct ulptx_sge_pair *to;
632 struct rte_mbuf *m = mbuf;
633 unsigned int nfrags = m->nb_segs;
634 struct ulptx_sge_pair buf[nfrags / 2];
636 len = m->data_len - start;
637 sgl->len0 = htonl(len);
638 sgl->addr0 = rte_cpu_to_be_64(addr[0]);
640 sgl->cmd_nsge = htonl(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
641 V_ULPTX_NSGE(nfrags));
642 if (likely(--nfrags == 0))
645 * Most of the complexity below deals with the possibility we hit the
646 * end of the queue in the middle of writing the SGL. For this case
647 * only we create the SGL in a temporary buffer and then copy it.
649 to = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge;
651 for (i = 0; nfrags >= 2; nfrags -= 2, to++) {
653 to->len[0] = rte_cpu_to_be_32(m->data_len);
654 to->addr[0] = rte_cpu_to_be_64(addr[++i]);
656 to->len[1] = rte_cpu_to_be_32(m->data_len);
657 to->addr[1] = rte_cpu_to_be_64(addr[++i]);
661 to->len[0] = rte_cpu_to_be_32(m->data_len);
662 to->len[1] = rte_cpu_to_be_32(0);
663 to->addr[0] = rte_cpu_to_be_64(addr[i + 1]);
665 if (unlikely((u8 *)end > (u8 *)q->stat)) {
666 unsigned int part0 = RTE_PTR_DIFF((u8 *)q->stat,
671 memcpy(sgl->sge, buf, part0);
672 part1 = RTE_PTR_DIFF((u8 *)end, (u8 *)q->stat);
673 rte_memcpy(q->desc, RTE_PTR_ADD((u8 *)buf, part0), part1);
674 end = RTE_PTR_ADD((void *)q->desc, part1);
676 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */
680 #define IDXDIFF(head, tail, wrap) \
681 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
683 #define Q_IDXDIFF(q, idx) IDXDIFF((q)->pidx, (q)->idx, (q)->size)
684 #define R_IDXDIFF(q, idx) IDXDIFF((q)->cidx, (q)->idx, (q)->size)
687 * ring_tx_db - ring a Tx queue's doorbell
690 * @n: number of new descriptors to give to HW
692 * Ring the doorbel for a Tx queue.
694 static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q)
696 int n = Q_IDXDIFF(q, dbidx);
699 * Make sure that all writes to the TX Descriptors are committed
700 * before we tell the hardware about them.
705 * If we don't have access to the new User Doorbell (T5+), use the old
706 * doorbell mechanism; otherwise use the new BAR2 mechanism.
708 if (unlikely(!q->bar2_addr)) {
712 * For T4 we need to participate in the Doorbell Recovery
716 t4_write_reg(adap, MYPF_REG(A_SGE_PF_KDOORBELL),
717 V_QID(q->cntxt_id) | val);
720 q->db_pidx = q->pidx;
722 u32 val = V_PIDX_T5(n);
725 * T4 and later chips share the same PIDX field offset within
726 * the doorbell, but T5 and later shrank the field in order to
727 * gain a bit for Doorbell Priority. The field was absurdly
728 * large in the first place (14 bits) so we just use the T5
729 * and later limits and warn if a Queue ID is too large.
731 WARN_ON(val & F_DBPRIO);
733 writel(val | V_QID(q->bar2_qid),
734 (void *)((uintptr_t)q->bar2_addr + SGE_UDB_KDOORBELL));
737 * This Write Memory Barrier will force the write to the User
738 * Doorbell area to be flushed. This is needed to prevent
739 * writes on different CPUs for the same queue from hitting
740 * the adapter out of order. This is required when some Work
741 * Requests take the Write Combine Gather Buffer path (user
742 * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some
743 * take the traditional path where we simply increment the
744 * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the
745 * hardware DMA read the actual Work Request.
753 * Figure out what HW csum a packet wants and return the appropriate control
756 static u64 hwcsum(enum chip_type chip, const struct rte_mbuf *m)
760 if (m->ol_flags & PKT_TX_IP_CKSUM) {
761 switch (m->ol_flags & PKT_TX_L4_MASK) {
762 case PKT_TX_TCP_CKSUM:
763 csum_type = TX_CSUM_TCPIP;
765 case PKT_TX_UDP_CKSUM:
766 csum_type = TX_CSUM_UDPIP;
775 if (likely(csum_type >= TX_CSUM_TCPIP)) {
776 u64 hdr_len = V_TXPKT_IPHDR_LEN(m->l3_len);
777 int eth_hdr_len = m->l2_len;
779 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
780 hdr_len |= V_TXPKT_ETHHDR_LEN(eth_hdr_len);
782 hdr_len |= V_T6_TXPKT_ETHHDR_LEN(eth_hdr_len);
783 return V_TXPKT_CSUM_TYPE(csum_type) | hdr_len;
787 * unknown protocol, disable HW csum
788 * and hope a bad packet is detected
790 return F_TXPKT_L4CSUM_DIS;
793 static inline void txq_advance(struct sge_txq *q, unsigned int n)
797 if (q->pidx >= q->size)
801 #define MAX_COALESCE_LEN 64000
803 static inline int wraps_around(struct sge_txq *q, int ndesc)
805 return (q->pidx + ndesc) > q->size ? 1 : 0;
808 static void tx_timer_cb(void *data)
810 struct adapter *adap = (struct adapter *)data;
811 struct sge_eth_txq *txq = &adap->sge.ethtxq[0];
813 unsigned int coal_idx;
815 /* monitor any pending tx */
816 for (i = 0; i < adap->sge.max_ethqsets; i++, txq++) {
817 if (t4_os_trylock(&txq->txq_lock)) {
818 coal_idx = txq->q.coalesce.idx;
820 if (coal_idx == txq->q.last_coal_idx &&
821 txq->q.pidx == txq->q.last_pidx) {
822 ship_tx_pkt_coalesce_wr(adap, txq);
824 txq->q.last_coal_idx = coal_idx;
825 txq->q.last_pidx = txq->q.pidx;
828 t4_os_unlock(&txq->txq_lock);
831 rte_eal_alarm_set(50, tx_timer_cb, (void *)adap);
835 * ship_tx_pkt_coalesce_wr - finalizes and ships a coalesce WR
836 * @ adap: adapter structure
839 * writes the different fields of the pkts WR and sends it.
841 static inline void ship_tx_pkt_coalesce_wr(struct adapter *adap,
842 struct sge_eth_txq *txq)
845 struct sge_txq *q = &txq->q;
846 struct fw_eth_tx_pkts_wr *wr;
849 /* fill the pkts WR header */
850 wr = (void *)&q->desc[q->pidx];
851 wr->op_pkd = htonl(V_FW_WR_OP(FW_ETH_TX_PKTS2_WR));
853 wr_mid = V_FW_WR_LEN16(DIV_ROUND_UP(q->coalesce.flits, 2));
854 ndesc = flits_to_desc(q->coalesce.flits);
855 wr->equiq_to_len16 = htonl(wr_mid);
856 wr->plen = cpu_to_be16(q->coalesce.len);
857 wr->npkt = q->coalesce.idx;
859 wr->type = q->coalesce.type;
861 /* zero out coalesce structure members */
863 q->coalesce.flits = 0;
866 txq_advance(q, ndesc);
867 txq->stats.coal_wr++;
868 txq->stats.coal_pkts += wr->npkt;
870 if (Q_IDXDIFF(q, equeidx) >= q->size / 2) {
871 q->equeidx = q->pidx;
872 wr_mid |= F_FW_WR_EQUEQ;
873 wr->equiq_to_len16 = htonl(wr_mid);
879 * should_tx_packet_coalesce - decides wether to coalesce an mbuf or not
880 * @txq: tx queue where the mbuf is sent
881 * @mbuf: mbuf to be sent
882 * @nflits: return value for number of flits needed
883 * @adap: adapter structure
885 * This function decides if a packet should be coalesced or not.
887 static inline int should_tx_packet_coalesce(struct sge_eth_txq *txq,
888 struct rte_mbuf *mbuf,
889 unsigned int *nflits,
890 struct adapter *adap)
892 struct sge_txq *q = &txq->q;
893 unsigned int flits, ndesc;
894 unsigned char type = 0;
897 /* use coal WR type 1 when no frags are present */
898 type = (mbuf->nb_segs == 1) ? 1 : 0;
900 if (unlikely(type != q->coalesce.type && q->coalesce.idx))
901 ship_tx_pkt_coalesce_wr(adap, txq);
903 /* calculate the number of flits required for coalescing this packet
904 * without the 2 flits of the WR header. These are added further down
905 * if we are just starting in new PKTS WR. sgl_len doesn't account for
906 * the possible 16 bytes alignment ULP TX commands so we do it here.
908 flits = (sgl_len(mbuf->nb_segs) + 1) & ~1U;
910 flits += (sizeof(struct ulp_txpkt) +
911 sizeof(struct ulptx_idata)) / sizeof(__be64);
912 flits += sizeof(struct cpl_tx_pkt_core) / sizeof(__be64);
915 /* If coalescing is on, the mbuf is added to a pkts WR */
916 if (q->coalesce.idx) {
917 ndesc = DIV_ROUND_UP(q->coalesce.flits + flits, 8);
918 credits = txq_avail(q) - ndesc;
920 /* If we are wrapping or this is last mbuf then, send the
921 * already coalesced mbufs and let the non-coalesce pass
924 if (unlikely(credits < 0 || wraps_around(q, ndesc))) {
925 ship_tx_pkt_coalesce_wr(adap, txq);
929 /* If the max coalesce len or the max WR len is reached
930 * ship the WR and keep coalescing on.
932 if (unlikely((q->coalesce.len + mbuf->pkt_len >
934 (q->coalesce.flits + flits >
936 ship_tx_pkt_coalesce_wr(adap, txq);
943 /* start a new pkts WR, the WR header is not filled below */
944 flits += sizeof(struct fw_eth_tx_pkts_wr) / sizeof(__be64);
945 ndesc = flits_to_desc(q->coalesce.flits + flits);
946 credits = txq_avail(q) - ndesc;
948 if (unlikely(credits < 0 || wraps_around(q, ndesc)))
950 q->coalesce.flits += 2;
951 q->coalesce.type = type;
952 q->coalesce.ptr = (unsigned char *)&q->desc[q->pidx] +
958 * tx_do_packet_coalesce - add an mbuf to a coalesce WR
959 * @txq: sge_eth_txq used send the mbuf
960 * @mbuf: mbuf to be sent
961 * @flits: flits needed for this mbuf
962 * @adap: adapter structure
963 * @pi: port_info structure
964 * @addr: mapped address of the mbuf
966 * Adds an mbuf to be sent as part of a coalesce WR by filling a
967 * ulp_tx_pkt command, ulp_tx_sc_imm command, cpl message and
968 * ulp_tx_sc_dsgl command.
970 static inline int tx_do_packet_coalesce(struct sge_eth_txq *txq,
971 struct rte_mbuf *mbuf,
972 int flits, struct adapter *adap,
973 const struct port_info *pi,
974 dma_addr_t *addr, uint16_t nb_pkts)
977 struct sge_txq *q = &txq->q;
978 struct ulp_txpkt *mc;
979 struct ulptx_idata *sc_imm;
980 struct cpl_tx_pkt_core *cpl;
981 struct tx_sw_desc *sd;
982 unsigned int idx = q->coalesce.idx, len = mbuf->pkt_len;
984 #ifdef RTE_LIBRTE_CXGBE_TPUT
985 RTE_SET_USED(nb_pkts);
988 if (q->coalesce.type == 0) {
989 mc = (struct ulp_txpkt *)q->coalesce.ptr;
990 mc->cmd_dest = htonl(V_ULPTX_CMD(4) | V_ULP_TXPKT_DEST(0) |
991 V_ULP_TXPKT_FID(adap->sge.fw_evtq.cntxt_id) |
993 mc->len = htonl(DIV_ROUND_UP(flits, 2));
994 sc_imm = (struct ulptx_idata *)(mc + 1);
995 sc_imm->cmd_more = htonl(V_ULPTX_CMD(ULP_TX_SC_IMM) |
997 sc_imm->len = htonl(sizeof(*cpl));
998 end = (u64 *)mc + flits;
999 cpl = (struct cpl_tx_pkt_core *)(sc_imm + 1);
1001 end = (u64 *)q->coalesce.ptr + flits;
1002 cpl = (struct cpl_tx_pkt_core *)q->coalesce.ptr;
1005 /* update coalesce structure for this txq */
1006 q->coalesce.flits += flits;
1007 q->coalesce.ptr += flits * sizeof(__be64);
1008 q->coalesce.len += mbuf->pkt_len;
1010 /* fill the cpl message, same as in t4_eth_xmit, this should be kept
1011 * similar to t4_eth_xmit
1013 if (mbuf->ol_flags & PKT_TX_IP_CKSUM) {
1014 cntrl = hwcsum(adap->params.chip, mbuf) |
1016 txq->stats.tx_cso++;
1018 cntrl = F_TXPKT_L4CSUM_DIS | F_TXPKT_IPCSUM_DIS;
1021 if (mbuf->ol_flags & PKT_TX_VLAN_PKT) {
1022 txq->stats.vlan_ins++;
1023 cntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(mbuf->vlan_tci);
1026 cpl->ctrl0 = htonl(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
1027 V_TXPKT_INTF(pi->tx_chan) |
1028 V_TXPKT_PF(adap->pf));
1029 cpl->pack = htons(0);
1030 cpl->len = htons(len);
1031 cpl->ctrl1 = cpu_to_be64(cntrl);
1032 write_sgl(mbuf, q, (struct ulptx_sgl *)(cpl + 1), end, 0, addr);
1034 txq->stats.tx_bytes += len;
1036 sd = &q->sdesc[q->pidx + (idx >> 1)];
1038 if (sd->coalesce.idx) {
1041 for (i = 0; i < sd->coalesce.idx; i++) {
1042 rte_pktmbuf_free(sd->coalesce.mbuf[i]);
1043 sd->coalesce.mbuf[i] = NULL;
1048 /* store pointers to the mbuf and the sgl used in free_tx_desc.
1049 * each tx desc can hold two pointers corresponding to the value
1050 * of ETH_COALESCE_PKT_PER_DESC
1052 sd->coalesce.mbuf[idx & 1] = mbuf;
1053 sd->coalesce.sgl[idx & 1] = (struct ulptx_sgl *)(cpl + 1);
1054 sd->coalesce.idx = (idx & 1) + 1;
1056 /* send the coaelsced work request if max reached */
1057 if (++q->coalesce.idx == ETH_COALESCE_PKT_NUM
1058 #ifndef RTE_LIBRTE_CXGBE_TPUT
1059 || q->coalesce.idx >= nb_pkts
1062 ship_tx_pkt_coalesce_wr(adap, txq);
1067 * t4_eth_xmit - add a packet to an Ethernet Tx queue
1068 * @txq: the egress queue
1071 * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled.
1073 int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf,
1076 const struct port_info *pi;
1077 struct cpl_tx_pkt_lso_core *lso;
1078 struct adapter *adap;
1079 struct rte_mbuf *m = mbuf;
1080 struct fw_eth_tx_pkt_wr *wr;
1081 struct cpl_tx_pkt_core *cpl;
1082 struct tx_sw_desc *d;
1083 dma_addr_t addr[m->nb_segs];
1084 unsigned int flits, ndesc, cflits;
1085 int l3hdr_len, l4hdr_len, eth_xtra_len;
1091 u32 max_pkt_len = txq->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len;
1093 /* Reject xmit if queue is stopped */
1094 if (unlikely(txq->flags & EQ_STOPPED))
1098 * The chip min packet length is 10 octets but play safe and reject
1099 * anything shorter than an Ethernet header.
1101 if (unlikely(m->pkt_len < ETHER_HDR_LEN)) {
1103 rte_pktmbuf_free(m);
1107 if ((!(m->ol_flags & PKT_TX_TCP_SEG)) &&
1108 (unlikely(m->pkt_len > max_pkt_len)))
1111 pi = (struct port_info *)txq->eth_dev->data->dev_private;
1114 cntrl = F_TXPKT_L4CSUM_DIS | F_TXPKT_IPCSUM_DIS;
1115 /* align the end of coalesce WR to a 512 byte boundary */
1116 txq->q.coalesce.max = (8 - (txq->q.pidx & 7)) * 8;
1118 if (!((m->ol_flags & PKT_TX_TCP_SEG) || (m->pkt_len > ETHER_MAX_LEN))) {
1119 if (should_tx_packet_coalesce(txq, mbuf, &cflits, adap)) {
1120 if (unlikely(map_mbuf(mbuf, addr) < 0)) {
1121 dev_warn(adap, "%s: mapping err for coalesce\n",
1123 txq->stats.mapping_err++;
1126 rte_prefetch0((volatile void *)addr);
1127 return tx_do_packet_coalesce(txq, mbuf, cflits, adap,
1134 if (txq->q.coalesce.idx)
1135 ship_tx_pkt_coalesce_wr(adap, txq);
1137 flits = calc_tx_flits(m);
1138 ndesc = flits_to_desc(flits);
1139 credits = txq_avail(&txq->q) - ndesc;
1141 if (unlikely(credits < 0)) {
1142 dev_debug(adap, "%s: Tx ring %u full; credits = %d\n",
1143 __func__, txq->q.cntxt_id, credits);
1147 if (unlikely(map_mbuf(m, addr) < 0)) {
1148 txq->stats.mapping_err++;
1152 wr_mid = V_FW_WR_LEN16(DIV_ROUND_UP(flits, 2));
1153 if (Q_IDXDIFF(&txq->q, equeidx) >= 64) {
1154 txq->q.equeidx = txq->q.pidx;
1155 wr_mid |= F_FW_WR_EQUEQ;
1158 wr = (void *)&txq->q.desc[txq->q.pidx];
1159 wr->equiq_to_len16 = htonl(wr_mid);
1160 wr->r3 = rte_cpu_to_be_64(0);
1161 end = (u64 *)wr + flits;
1164 len += sizeof(*cpl);
1166 /* Coalescing skipped and we send through normal path */
1167 if (!(m->ol_flags & PKT_TX_TCP_SEG)) {
1168 wr->op_immdlen = htonl(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
1169 V_FW_WR_IMMDLEN(len));
1170 cpl = (void *)(wr + 1);
1171 if (m->ol_flags & PKT_TX_IP_CKSUM) {
1172 cntrl = hwcsum(adap->params.chip, m) |
1174 txq->stats.tx_cso++;
1177 lso = (void *)(wr + 1);
1178 v6 = (m->ol_flags & PKT_TX_IPV6) != 0;
1179 l3hdr_len = m->l3_len;
1180 l4hdr_len = m->l4_len;
1181 eth_xtra_len = m->l2_len - ETHER_HDR_LEN;
1182 len += sizeof(*lso);
1183 wr->op_immdlen = htonl(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
1184 V_FW_WR_IMMDLEN(len));
1185 lso->lso_ctrl = htonl(V_LSO_OPCODE(CPL_TX_PKT_LSO) |
1186 F_LSO_FIRST_SLICE | F_LSO_LAST_SLICE |
1188 V_LSO_ETHHDR_LEN(eth_xtra_len / 4) |
1189 V_LSO_IPHDR_LEN(l3hdr_len / 4) |
1190 V_LSO_TCPHDR_LEN(l4hdr_len / 4));
1191 lso->ipid_ofst = htons(0);
1192 lso->mss = htons(m->tso_segsz);
1193 lso->seqno_offset = htonl(0);
1194 if (is_t4(adap->params.chip))
1195 lso->len = htonl(m->pkt_len);
1197 lso->len = htonl(V_LSO_T5_XFER_SIZE(m->pkt_len));
1198 cpl = (void *)(lso + 1);
1200 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
1201 cntrl = V_TXPKT_ETHHDR_LEN(eth_xtra_len);
1203 cntrl = V_T6_TXPKT_ETHHDR_LEN(eth_xtra_len);
1205 cntrl |= V_TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 :
1207 V_TXPKT_IPHDR_LEN(l3hdr_len);
1209 txq->stats.tx_cso += m->tso_segsz;
1212 if (m->ol_flags & PKT_TX_VLAN_PKT) {
1213 txq->stats.vlan_ins++;
1214 cntrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->vlan_tci);
1217 cpl->ctrl0 = htonl(V_TXPKT_OPCODE(CPL_TX_PKT_XT) |
1218 V_TXPKT_INTF(pi->tx_chan) |
1219 V_TXPKT_PF(adap->pf));
1220 cpl->pack = htons(0);
1221 cpl->len = htons(m->pkt_len);
1222 cpl->ctrl1 = cpu_to_be64(cntrl);
1225 txq->stats.tx_bytes += m->pkt_len;
1226 last_desc = txq->q.pidx + ndesc - 1;
1227 if (last_desc >= (int)txq->q.size)
1228 last_desc -= txq->q.size;
1230 d = &txq->q.sdesc[last_desc];
1231 if (d->coalesce.idx) {
1234 for (i = 0; i < d->coalesce.idx; i++) {
1235 rte_pktmbuf_free(d->coalesce.mbuf[i]);
1236 d->coalesce.mbuf[i] = NULL;
1238 d->coalesce.idx = 0;
1240 write_sgl(m, &txq->q, (struct ulptx_sgl *)(cpl + 1), end, 0,
1242 txq->q.sdesc[last_desc].mbuf = m;
1243 txq->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)(cpl + 1);
1244 txq_advance(&txq->q, ndesc);
1245 ring_tx_db(adap, &txq->q);
1250 * alloc_ring - allocate resources for an SGE descriptor ring
1251 * @dev: the PCI device's core device
1252 * @nelem: the number of descriptors
1253 * @elem_size: the size of each descriptor
1254 * @sw_size: the size of the SW state associated with each ring element
1255 * @phys: the physical address of the allocated ring
1256 * @metadata: address of the array holding the SW state for the ring
1257 * @stat_size: extra space in HW ring for status information
1258 * @node: preferred node for memory allocations
1260 * Allocates resources for an SGE descriptor ring, such as Tx queues,
1261 * free buffer lists, or response queues. Each SGE ring requires
1262 * space for its HW descriptors plus, optionally, space for the SW state
1263 * associated with each HW entry (the metadata). The function returns
1264 * three values: the virtual address for the HW ring (the return value
1265 * of the function), the bus address of the HW ring, and the address
1268 static void *alloc_ring(size_t nelem, size_t elem_size,
1269 size_t sw_size, dma_addr_t *phys, void *metadata,
1270 size_t stat_size, __rte_unused uint16_t queue_id,
1271 int socket_id, const char *z_name,
1272 const char *z_name_sw)
1274 size_t len = CXGBE_MAX_RING_DESC_SIZE * elem_size + stat_size;
1275 const struct rte_memzone *tz;
1278 dev_debug(adapter, "%s: nelem = %zu; elem_size = %zu; sw_size = %zu; "
1279 "stat_size = %zu; queue_id = %u; socket_id = %d; z_name = %s;"
1280 " z_name_sw = %s\n", __func__, nelem, elem_size, sw_size,
1281 stat_size, queue_id, socket_id, z_name, z_name_sw);
1283 tz = rte_memzone_lookup(z_name);
1285 dev_debug(adapter, "%s: tz exists...returning existing..\n",
1291 * Allocate TX/RX ring hardware descriptors. A memzone large enough to
1292 * handle the maximum ring size is allocated in order to allow for
1293 * resizing in later calls to the queue setup function.
1295 tz = rte_memzone_reserve_aligned(z_name, len, socket_id, 0, 4096);
1300 memset(tz->addr, 0, len);
1302 s = rte_zmalloc_socket(z_name_sw, nelem * sw_size,
1303 RTE_CACHE_LINE_SIZE, socket_id);
1306 dev_err(adapter, "%s: failed to get sw_ring memory\n",
1312 *(void **)metadata = s;
1314 *phys = (uint64_t)tz->phys_addr;
1319 * t4_pktgl_to_mbuf_usembufs - build an mbuf from a packet gather list
1320 * @gl: the gather list
1322 * Builds an mbuf from the given packet gather list. Returns the mbuf or
1323 * %NULL if mbuf allocation failed.
1325 static struct rte_mbuf *t4_pktgl_to_mbuf_usembufs(const struct pkt_gl *gl)
1328 * If there's only one mbuf fragment, just return that.
1330 if (likely(gl->nfrags == 1))
1331 return gl->mbufs[0];
1337 * t4_pktgl_to_mbuf - build an mbuf from a packet gather list
1338 * @gl: the gather list
1340 * Builds an mbuf from the given packet gather list. Returns the mbuf or
1341 * %NULL if mbuf allocation failed.
1343 static struct rte_mbuf *t4_pktgl_to_mbuf(const struct pkt_gl *gl)
1345 return t4_pktgl_to_mbuf_usembufs(gl);
1349 * t4_ethrx_handler - process an ingress ethernet packet
1350 * @q: the response queue that received the packet
1351 * @rsp: the response queue descriptor holding the RX_PKT message
1352 * @si: the gather list of packet fragments
1354 * Process an ingress ethernet packet and deliver it to the stack.
1356 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1357 const struct pkt_gl *si)
1359 struct rte_mbuf *mbuf;
1360 const struct cpl_rx_pkt *pkt;
1361 const struct rss_header *rss_hdr;
1363 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1366 rss_hdr = (const void *)rsp;
1367 pkt = (const void *)&rsp[1];
1368 /* Compressed error vector is enabled for T6 only */
1369 if (q->adapter->params.tp.rx_pkt_encap)
1370 err_vec = G_T6_COMPR_RXERR_VEC(ntohs(pkt->err_vec));
1372 err_vec = ntohs(pkt->err_vec);
1373 csum_ok = pkt->csum_calc && !err_vec;
1375 mbuf = t4_pktgl_to_mbuf(si);
1376 if (unlikely(!mbuf)) {
1377 rxq->stats.rx_drops++;
1381 mbuf->port = pkt->iff;
1382 if (pkt->l2info & htonl(F_RXF_IP)) {
1383 mbuf->packet_type = RTE_PTYPE_L3_IPV4;
1384 if (unlikely(!csum_ok))
1385 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1387 if ((pkt->l2info & htonl(F_RXF_UDP | F_RXF_TCP)) && !csum_ok)
1388 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1389 } else if (pkt->l2info & htonl(F_RXF_IP6)) {
1390 mbuf->packet_type = RTE_PTYPE_L3_IPV6;
1393 mbuf->port = pkt->iff;
1395 if (!rss_hdr->filter_tid && rss_hdr->hash_type) {
1396 mbuf->ol_flags |= PKT_RX_RSS_HASH;
1397 mbuf->hash.rss = ntohl(rss_hdr->hash_val);
1401 mbuf->ol_flags |= PKT_RX_VLAN_PKT;
1402 mbuf->vlan_tci = ntohs(pkt->vlan);
1405 rxq->stats.rx_bytes += mbuf->pkt_len;
1410 #define CXGB4_MSG_AN ((void *)1)
1413 * rspq_next - advance to the next entry in a response queue
1416 * Updates the state of a response queue to advance it to the next entry.
1418 static inline void rspq_next(struct sge_rspq *q)
1420 q->cur_desc = (const __be64 *)((const char *)q->cur_desc + q->iqe_len);
1421 if (unlikely(++q->cidx == q->size)) {
1424 q->cur_desc = q->desc;
1429 * process_responses - process responses from an SGE response queue
1430 * @q: the ingress queue to process
1431 * @budget: how many responses can be processed in this round
1432 * @rx_pkts: mbuf to put the pkts
1434 * Process responses from an SGE response queue up to the supplied budget.
1435 * Responses include received packets as well as control messages from FW
1438 * Additionally choose the interrupt holdoff time for the next interrupt
1439 * on this queue. If the system is under memory shortage use a fairly
1440 * long delay to help recovery.
1442 static int process_responses(struct sge_rspq *q, int budget,
1443 struct rte_mbuf **rx_pkts)
1445 int ret = 0, rsp_type;
1446 int budget_left = budget;
1447 const struct rsp_ctrl *rc;
1448 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1450 while (likely(budget_left)) {
1451 if (q->cidx == ntohs(q->stat->pidx))
1454 rc = (const struct rsp_ctrl *)
1455 ((const char *)q->cur_desc + (q->iqe_len - sizeof(*rc)));
1458 * Ensure response has been read
1461 rsp_type = G_RSPD_TYPE(rc->u.type_gen);
1463 if (likely(rsp_type == X_RSPD_TYPE_FLBUF)) {
1464 const struct rx_sw_desc *rsd =
1465 &rxq->fl.sdesc[rxq->fl.cidx];
1466 const struct rss_header *rss_hdr =
1467 (const void *)q->cur_desc;
1468 const struct cpl_rx_pkt *cpl =
1469 (const void *)&q->cur_desc[1];
1470 struct rte_mbuf *pkt, *npkt;
1475 len = ntohl(rc->pldbuflen_qid);
1476 BUG_ON(!(len & F_RSPD_NEWBUF));
1479 len = G_RSPD_LEN(len);
1482 /* Compressed error vector is enabled for
1485 if (q->adapter->params.tp.rx_pkt_encap)
1486 err_vec = G_T6_COMPR_RXERR_VEC(
1487 ntohs(cpl->err_vec));
1489 err_vec = ntohs(cpl->err_vec);
1490 csum_ok = cpl->csum_calc && !err_vec;
1492 /* Chain mbufs into len if necessary */
1494 struct rte_mbuf *new_pkt = rsd->buf;
1496 bufsz = min(get_buf_size(q->adapter, rsd), len);
1497 new_pkt->data_len = bufsz;
1498 unmap_rx_buf(&rxq->fl);
1500 npkt->next = new_pkt;
1503 rsd = &rxq->fl.sdesc[rxq->fl.cidx];
1508 if (cpl->l2info & htonl(F_RXF_IP)) {
1509 pkt->packet_type = RTE_PTYPE_L3_IPV4;
1510 if (unlikely(!csum_ok))
1511 pkt->ol_flags |= PKT_RX_IP_CKSUM_BAD;
1514 htonl(F_RXF_UDP | F_RXF_TCP)) && !csum_ok)
1515 pkt->ol_flags |= PKT_RX_L4_CKSUM_BAD;
1516 } else if (cpl->l2info & htonl(F_RXF_IP6)) {
1517 pkt->packet_type = RTE_PTYPE_L3_IPV6;
1520 if (!rss_hdr->filter_tid && rss_hdr->hash_type) {
1521 pkt->ol_flags |= PKT_RX_RSS_HASH;
1522 pkt->hash.rss = ntohl(rss_hdr->hash_val);
1526 pkt->ol_flags |= PKT_RX_VLAN_PKT;
1527 pkt->vlan_tci = ntohs(cpl->vlan);
1530 rxq->stats.rx_bytes += pkt->pkt_len;
1531 rx_pkts[budget - budget_left] = pkt;
1532 } else if (likely(rsp_type == X_RSPD_TYPE_CPL)) {
1533 ret = q->handler(q, q->cur_desc, NULL);
1535 ret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN);
1538 if (unlikely(ret)) {
1539 /* couldn't process descriptor, back off for recovery */
1540 q->next_intr_params = V_QINTR_TIMER_IDX(NOMEM_TMR_IDX);
1549 * If this is a Response Queue with an associated Free List and
1550 * there's room for another chunk of new Free List buffer pointers,
1551 * refill the Free List.
1554 if (q->offset >= 0 && fl_cap(&rxq->fl) - rxq->fl.avail >= 64)
1555 __refill_fl(q->adapter, &rxq->fl);
1557 return budget - budget_left;
1560 int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
1561 unsigned int budget, unsigned int *work_done)
1563 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1564 unsigned int cidx_inc;
1565 unsigned int params;
1568 *work_done = process_responses(q, budget, rx_pkts);
1571 cidx_inc = R_IDXDIFF(q, gts_idx);
1573 if (q->offset >= 0 && fl_cap(&rxq->fl) - rxq->fl.avail >= 64)
1574 __refill_fl(q->adapter, &rxq->fl);
1576 params = q->intr_params;
1577 q->next_intr_params = params;
1578 val = V_CIDXINC(cidx_inc) | V_SEINTARM(params);
1580 if (unlikely(!q->bar2_addr)) {
1581 t4_write_reg(q->adapter, MYPF_REG(A_SGE_PF_GTS),
1582 val | V_INGRESSQID((u32)q->cntxt_id));
1584 writel(val | V_INGRESSQID(q->bar2_qid),
1585 (void *)((uintptr_t)q->bar2_addr + SGE_UDB_GTS));
1586 /* This Write memory Barrier will force the
1587 * write to the User Doorbell area to be
1592 q->gts_idx = q->cidx;
1598 * bar2_address - return the BAR2 address for an SGE Queue's Registers
1599 * @adapter: the adapter
1600 * @qid: the SGE Queue ID
1601 * @qtype: the SGE Queue Type (Egress or Ingress)
1602 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
1604 * Returns the BAR2 address for the SGE Queue Registers associated with
1605 * @qid. If BAR2 SGE Registers aren't available, returns NULL. Also
1606 * returns the BAR2 Queue ID to be used with writes to the BAR2 SGE
1607 * Queue Registers. If the BAR2 Queue ID is 0, then "Inferred Queue ID"
1608 * Registers are supported (e.g. the Write Combining Doorbell Buffer).
1610 static void __iomem *bar2_address(struct adapter *adapter, unsigned int qid,
1611 enum t4_bar2_qtype qtype,
1612 unsigned int *pbar2_qid)
1617 ret = t4_bar2_sge_qregs(adapter, qid, qtype, &bar2_qoffset, pbar2_qid);
1621 return adapter->bar2 + bar2_qoffset;
1624 int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq)
1626 struct sge_eth_rxq *rxq = container_of(rq, struct sge_eth_rxq, rspq);
1627 unsigned int fl_id = rxq->fl.size ? rxq->fl.cntxt_id : 0xffff;
1629 return t4_iq_start_stop(adap, adap->mbox, true, adap->pf, 0,
1630 rq->cntxt_id, fl_id, 0xffff);
1633 int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq)
1635 struct sge_eth_rxq *rxq = container_of(rq, struct sge_eth_rxq, rspq);
1636 unsigned int fl_id = rxq->fl.size ? rxq->fl.cntxt_id : 0xffff;
1638 return t4_iq_start_stop(adap, adap->mbox, false, adap->pf, 0,
1639 rq->cntxt_id, fl_id, 0xffff);
1643 * @intr_idx: MSI/MSI-X vector if >=0, -(absolute qid + 1) if < 0
1644 * @cong: < 0 -> no congestion feedback, >= 0 -> congestion channel map
1646 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1647 struct rte_eth_dev *eth_dev, int intr_idx,
1648 struct sge_fl *fl, rspq_handler_t hnd, int cong,
1649 struct rte_mempool *mp, int queue_id, int socket_id)
1653 struct sge *s = &adap->sge;
1654 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1655 char z_name[RTE_MEMZONE_NAMESIZE];
1656 char z_name_sw[RTE_MEMZONE_NAMESIZE];
1657 unsigned int nb_refill;
1659 /* Size needs to be multiple of 16, including status entry. */
1660 iq->size = cxgbe_roundup(iq->size, 16);
1662 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1663 eth_dev->data->drv_name,
1664 fwevtq ? "fwq_ring" : "rx_ring",
1665 eth_dev->data->port_id, queue_id);
1666 snprintf(z_name_sw, sizeof(z_name_sw), "%s_sw_ring", z_name);
1668 iq->desc = alloc_ring(iq->size, iq->iqe_len, 0, &iq->phys_addr, NULL, 0,
1669 queue_id, socket_id, z_name, z_name_sw);
1673 memset(&c, 0, sizeof(c));
1674 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
1675 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
1676 V_FW_IQ_CMD_PFN(adap->pf) | V_FW_IQ_CMD_VFN(0));
1677 c.alloc_to_len16 = htonl(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
1679 c.type_to_iqandstindex =
1680 htonl(V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
1681 V_FW_IQ_CMD_IQASYNCH(fwevtq) |
1682 V_FW_IQ_CMD_VIID(pi->viid) |
1683 V_FW_IQ_CMD_IQANDST(intr_idx < 0) |
1684 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_STATUS_PAGE) |
1685 V_FW_IQ_CMD_IQANDSTINDEX(intr_idx >= 0 ? intr_idx :
1687 c.iqdroprss_to_iqesize =
1688 htons(V_FW_IQ_CMD_IQPCIECH(cong > 0 ? cxgbe_ffs(cong) - 1 :
1690 F_FW_IQ_CMD_IQGTSMODE |
1691 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->pktcnt_idx) |
1692 V_FW_IQ_CMD_IQESIZE(ilog2(iq->iqe_len) - 4));
1693 c.iqsize = htons(iq->size);
1694 c.iqaddr = cpu_to_be64(iq->phys_addr);
1696 c.iqns_to_fl0congen = htonl(F_FW_IQ_CMD_IQFLINTCONGEN |
1700 struct sge_eth_rxq *rxq = container_of(fl, struct sge_eth_rxq,
1702 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adap->params.chip);
1705 * Allocate the ring for the hardware free list (with space
1706 * for its status page) along with the associated software
1707 * descriptor ring. The free list size needs to be a multiple
1708 * of the Egress Queue Unit and at least 2 Egress Units larger
1709 * than the SGE's Egress Congrestion Threshold
1710 * (fl_starve_thres - 1).
1712 if (fl->size < s->fl_starve_thres - 1 + 2 * 8)
1713 fl->size = s->fl_starve_thres - 1 + 2 * 8;
1714 fl->size = cxgbe_roundup(fl->size, 8);
1716 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1717 eth_dev->data->drv_name,
1718 fwevtq ? "fwq_ring" : "fl_ring",
1719 eth_dev->data->port_id, queue_id);
1720 snprintf(z_name_sw, sizeof(z_name_sw), "%s_sw_ring", z_name);
1722 fl->desc = alloc_ring(fl->size, sizeof(__be64),
1723 sizeof(struct rx_sw_desc),
1724 &fl->addr, &fl->sdesc, s->stat_len,
1725 queue_id, socket_id, z_name, z_name_sw);
1730 flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
1731 c.iqns_to_fl0congen |=
1732 htonl(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
1733 (unlikely(rxq->usembufs) ?
1734 0 : F_FW_IQ_CMD_FL0PACKEN) |
1735 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
1736 F_FW_IQ_CMD_FL0PADEN);
1738 c.iqns_to_fl0congen |=
1739 htonl(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
1740 F_FW_IQ_CMD_FL0CONGCIF |
1741 F_FW_IQ_CMD_FL0CONGEN);
1743 /* In T6, for egress queue type FL there is internal overhead
1744 * of 16B for header going into FLM module.
1745 * Hence maximum allowed burst size will be 448 bytes.
1747 c.fl0dcaen_to_fl0cidxfthresh =
1748 htons(V_FW_IQ_CMD_FL0FBMIN(chip_ver <= CHELSIO_T5 ?
1749 X_FETCHBURSTMIN_128B :
1750 X_FETCHBURSTMIN_64B) |
1751 V_FW_IQ_CMD_FL0FBMAX(chip_ver <= CHELSIO_T5 ?
1752 X_FETCHBURSTMAX_512B :
1753 X_FETCHBURSTMAX_256B));
1754 c.fl0size = htons(flsz);
1755 c.fl0addr = cpu_to_be64(fl->addr);
1758 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
1762 iq->cur_desc = iq->desc;
1766 iq->next_intr_params = iq->intr_params;
1767 iq->cntxt_id = ntohs(c.iqid);
1768 iq->abs_id = ntohs(c.physiqid);
1769 iq->bar2_addr = bar2_address(adap, iq->cntxt_id, T4_BAR2_QTYPE_INGRESS,
1771 iq->size--; /* subtract status entry */
1772 iq->stat = (void *)&iq->desc[iq->size * 8];
1773 iq->eth_dev = eth_dev;
1775 iq->port_id = pi->port_id;
1778 /* set offset to -1 to distinguish ingress queues without FL */
1779 iq->offset = fl ? 0 : -1;
1782 fl->cntxt_id = ntohs(c.fl0id);
1787 fl->alloc_failed = 0;
1790 * Note, we must initialize the BAR2 Free List User Doorbell
1791 * information before refilling the Free List!
1793 fl->bar2_addr = bar2_address(adap, fl->cntxt_id,
1794 T4_BAR2_QTYPE_EGRESS,
1797 nb_refill = refill_fl(adap, fl, fl_cap(fl));
1798 if (nb_refill != fl_cap(fl)) {
1800 dev_err(adap, "%s: mbuf alloc failed with error: %d\n",
1807 * For T5 and later we attempt to set up the Congestion Manager values
1808 * of the new RX Ethernet Queue. This should really be handled by
1809 * firmware because it's more complex than any host driver wants to
1810 * get involved with and it's different per chip and this is almost
1811 * certainly wrong. Formware would be wrong as well, but it would be
1812 * a lot easier to fix in one place ... For now we do something very
1813 * simple (and hopefully less wrong).
1815 if (!is_t4(adap->params.chip) && cong >= 0) {
1819 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
1820 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
1821 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id));
1823 val = V_CONMCTXT_CNGTPMODE(X_CONMCTXT_CNGTPMODE_QUEUE);
1825 val = V_CONMCTXT_CNGTPMODE(
1826 X_CONMCTXT_CNGTPMODE_CHANNEL);
1827 for (i = 0; i < 4; i++) {
1828 if (cong & (1 << i))
1829 val |= V_CONMCTXT_CNGCHMAP(1 <<
1833 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1836 dev_warn(adap->pdev_dev, "Failed to set Congestion Manager Context for Ingress Queue %d: %d\n",
1837 iq->cntxt_id, -ret);
1843 t4_iq_free(adap, adap->mbox, adap->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
1844 iq->cntxt_id, fl->cntxt_id, 0xffff);
1853 if (fl && fl->desc) {
1854 rte_free(fl->sdesc);
1862 static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id)
1865 q->bar2_addr = bar2_address(adap, q->cntxt_id, T4_BAR2_QTYPE_EGRESS,
1872 q->coalesce.idx = 0;
1873 q->coalesce.len = 0;
1874 q->coalesce.flits = 0;
1875 q->last_coal_idx = 0;
1877 q->stat = (void *)&q->desc[q->size];
1880 int t4_sge_eth_txq_start(struct sge_eth_txq *txq)
1883 * TODO: For flow-control, queue may be stopped waiting to reclaim
1885 * Ensure queue is in EQ_STOPPED state before starting it.
1887 if (!(txq->flags & EQ_STOPPED))
1890 txq->flags &= ~EQ_STOPPED;
1895 int t4_sge_eth_txq_stop(struct sge_eth_txq *txq)
1897 txq->flags |= EQ_STOPPED;
1902 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1903 struct rte_eth_dev *eth_dev, uint16_t queue_id,
1904 unsigned int iqid, int socket_id)
1907 struct fw_eq_eth_cmd c;
1908 struct sge *s = &adap->sge;
1909 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private);
1910 char z_name[RTE_MEMZONE_NAMESIZE];
1911 char z_name_sw[RTE_MEMZONE_NAMESIZE];
1913 /* Add status entries */
1914 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
1916 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1917 eth_dev->data->drv_name, "tx_ring",
1918 eth_dev->data->port_id, queue_id);
1919 snprintf(z_name_sw, sizeof(z_name_sw), "%s_sw_ring", z_name);
1921 txq->q.desc = alloc_ring(txq->q.size, sizeof(struct tx_desc),
1922 sizeof(struct tx_sw_desc), &txq->q.phys_addr,
1923 &txq->q.sdesc, s->stat_len, queue_id,
1924 socket_id, z_name, z_name_sw);
1928 memset(&c, 0, sizeof(c));
1929 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
1930 F_FW_CMD_WRITE | F_FW_CMD_EXEC |
1931 V_FW_EQ_ETH_CMD_PFN(adap->pf) |
1932 V_FW_EQ_ETH_CMD_VFN(0));
1933 c.alloc_to_len16 = htonl(F_FW_EQ_ETH_CMD_ALLOC |
1934 F_FW_EQ_ETH_CMD_EQSTART | (sizeof(c) / 16));
1935 c.autoequiqe_to_viid = htonl(F_FW_EQ_ETH_CMD_AUTOEQUEQE |
1936 V_FW_EQ_ETH_CMD_VIID(pi->viid));
1937 c.fetchszm_to_iqid =
1938 htonl(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
1939 V_FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) |
1940 F_FW_EQ_ETH_CMD_FETCHRO | V_FW_EQ_ETH_CMD_IQID(iqid));
1942 htonl(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
1943 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
1944 V_FW_EQ_ETH_CMD_EQSIZE(nentries));
1945 c.eqaddr = rte_cpu_to_be_64(txq->q.phys_addr);
1947 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
1949 rte_free(txq->q.sdesc);
1950 txq->q.sdesc = NULL;
1955 init_txq(adap, &txq->q, G_FW_EQ_ETH_CMD_EQID(ntohl(c.eqid_pkd)));
1957 txq->stats.pkts = 0;
1958 txq->stats.tx_cso = 0;
1959 txq->stats.coal_wr = 0;
1960 txq->stats.vlan_ins = 0;
1961 txq->stats.tx_bytes = 0;
1962 txq->stats.coal_pkts = 0;
1963 txq->stats.mapping_err = 0;
1964 txq->flags |= EQ_STOPPED;
1965 txq->eth_dev = eth_dev;
1966 t4_os_lock_init(&txq->txq_lock);
1970 static void free_txq(struct sge_txq *q)
1977 static void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq,
1980 unsigned int fl_id = fl ? fl->cntxt_id : 0xffff;
1982 t4_iq_free(adap, adap->mbox, adap->pf, 0, FW_IQ_TYPE_FL_INT_CAP,
1983 rq->cntxt_id, fl_id, 0xffff);
1989 free_rx_bufs(fl, fl->avail);
1990 rte_free(fl->sdesc);
1998 * Clear all queues of the port
2000 * Note: This function must only be called after rx and tx path
2001 * of the port have been disabled.
2003 void t4_sge_eth_clear_queues(struct port_info *pi)
2006 struct adapter *adap = pi->adapter;
2007 struct sge_eth_rxq *rxq = &adap->sge.ethrxq[pi->first_qset];
2008 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
2010 for (i = 0; i < pi->n_rx_qsets; i++, rxq++) {
2012 t4_sge_eth_rxq_stop(adap, &rxq->rspq);
2014 for (i = 0; i < pi->n_tx_qsets; i++, txq++) {
2016 struct sge_txq *q = &txq->q;
2018 t4_sge_eth_txq_stop(txq);
2019 reclaim_completed_tx(q);
2020 free_tx_desc(q, q->size);
2021 q->equeidx = q->pidx;
2026 void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq)
2028 if (rxq->rspq.desc) {
2029 t4_sge_eth_rxq_stop(adap, &rxq->rspq);
2030 free_rspq_fl(adap, &rxq->rspq, rxq->fl.size ? &rxq->fl : NULL);
2034 void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq)
2037 t4_sge_eth_txq_stop(txq);
2038 reclaim_completed_tx(&txq->q);
2039 t4_eth_eq_free(adap, adap->mbox, adap->pf, 0, txq->q.cntxt_id);
2040 free_tx_desc(&txq->q, txq->q.size);
2041 rte_free(txq->q.sdesc);
2046 void t4_sge_tx_monitor_start(struct adapter *adap)
2048 rte_eal_alarm_set(50, tx_timer_cb, (void *)adap);
2051 void t4_sge_tx_monitor_stop(struct adapter *adap)
2053 rte_eal_alarm_cancel(tx_timer_cb, (void *)adap);
2057 * t4_free_sge_resources - free SGE resources
2058 * @adap: the adapter
2060 * Frees resources used by the SGE queue sets.
2062 void t4_free_sge_resources(struct adapter *adap)
2065 struct sge_eth_rxq *rxq = &adap->sge.ethrxq[0];
2066 struct sge_eth_txq *txq = &adap->sge.ethtxq[0];
2068 /* clean up Ethernet Tx/Rx queues */
2069 for (i = 0; i < adap->sge.max_ethqsets; i++, rxq++, txq++) {
2070 /* Free only the queues allocated */
2071 if (rxq->rspq.desc) {
2072 t4_sge_eth_rxq_release(adap, rxq);
2073 rxq->rspq.eth_dev = NULL;
2076 t4_sge_eth_txq_release(adap, txq);
2077 txq->eth_dev = NULL;
2081 if (adap->sge.fw_evtq.desc)
2082 free_rspq_fl(adap, &adap->sge.fw_evtq, NULL);
2086 * t4_sge_init - initialize SGE
2087 * @adap: the adapter
2089 * Performs SGE initialization needed every time after a chip reset.
2090 * We do not initialize any of the queues here, instead the driver
2091 * top-level must request those individually.
2093 * Called in two different modes:
2095 * 1. Perform actual hardware initialization and record hard-coded
2096 * parameters which were used. This gets used when we're the
2097 * Master PF and the Firmware Configuration File support didn't
2098 * work for some reason.
2100 * 2. We're not the Master PF or initialization was performed with
2101 * a Firmware Configuration File. In this case we need to grab
2102 * any of the SGE operating parameters that we need to have in
2103 * order to do our job and make sure we can live with them ...
2105 static int t4_sge_init_soft(struct adapter *adap)
2107 struct sge *s = &adap->sge;
2108 u32 fl_small_pg, fl_large_pg, fl_small_mtu, fl_large_mtu;
2109 u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5;
2110 u32 ingress_rx_threshold;
2113 * Verify that CPL messages are going to the Ingress Queue for
2114 * process_responses() and that only packet data is going to the
2117 if ((t4_read_reg(adap, A_SGE_CONTROL) & F_RXPKTCPLMODE) !=
2118 V_RXPKTCPLMODE(X_RXPKTCPLMODE_SPLIT)) {
2119 dev_err(adap, "bad SGE CPL MODE\n");
2124 * Validate the Host Buffer Register Array indices that we want to
2127 * XXX Note that we should really read through the Host Buffer Size
2128 * XXX register array and find the indices of the Buffer Sizes which
2129 * XXX meet our needs!
2131 #define READ_FL_BUF(x) \
2132 t4_read_reg(adap, A_SGE_FL_BUFFER_SIZE0 + (x) * sizeof(u32))
2134 fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF);
2135 fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF);
2136 fl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF);
2137 fl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF);
2140 * We only bother using the Large Page logic if the Large Page Buffer
2141 * is larger than our Page Size Buffer.
2143 if (fl_large_pg <= fl_small_pg)
2149 * The Page Size Buffer must be exactly equal to our Page Size and the
2150 * Large Page Size Buffer should be 0 (per above) or a power of 2.
2152 if (fl_small_pg != CXGBE_PAGE_SIZE ||
2153 (fl_large_pg & (fl_large_pg - 1)) != 0) {
2154 dev_err(adap, "bad SGE FL page buffer sizes [%d, %d]\n",
2155 fl_small_pg, fl_large_pg);
2159 s->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT;
2161 if (adap->use_unpacked_mode) {
2164 if (fl_small_mtu < FL_MTU_SMALL_BUFSIZE(adap)) {
2165 dev_err(adap, "bad SGE FL small MTU %d\n",
2169 if (fl_large_mtu < FL_MTU_LARGE_BUFSIZE(adap)) {
2170 dev_err(adap, "bad SGE FL large MTU %d\n",
2179 * Retrieve our RX interrupt holdoff timer values and counter
2180 * threshold values from the SGE parameters.
2182 timer_value_0_and_1 = t4_read_reg(adap, A_SGE_TIMER_VALUE_0_AND_1);
2183 timer_value_2_and_3 = t4_read_reg(adap, A_SGE_TIMER_VALUE_2_AND_3);
2184 timer_value_4_and_5 = t4_read_reg(adap, A_SGE_TIMER_VALUE_4_AND_5);
2185 s->timer_val[0] = core_ticks_to_us(adap,
2186 G_TIMERVALUE0(timer_value_0_and_1));
2187 s->timer_val[1] = core_ticks_to_us(adap,
2188 G_TIMERVALUE1(timer_value_0_and_1));
2189 s->timer_val[2] = core_ticks_to_us(adap,
2190 G_TIMERVALUE2(timer_value_2_and_3));
2191 s->timer_val[3] = core_ticks_to_us(adap,
2192 G_TIMERVALUE3(timer_value_2_and_3));
2193 s->timer_val[4] = core_ticks_to_us(adap,
2194 G_TIMERVALUE4(timer_value_4_and_5));
2195 s->timer_val[5] = core_ticks_to_us(adap,
2196 G_TIMERVALUE5(timer_value_4_and_5));
2198 ingress_rx_threshold = t4_read_reg(adap, A_SGE_INGRESS_RX_THRESHOLD);
2199 s->counter_val[0] = G_THRESHOLD_0(ingress_rx_threshold);
2200 s->counter_val[1] = G_THRESHOLD_1(ingress_rx_threshold);
2201 s->counter_val[2] = G_THRESHOLD_2(ingress_rx_threshold);
2202 s->counter_val[3] = G_THRESHOLD_3(ingress_rx_threshold);
2207 int t4_sge_init(struct adapter *adap)
2209 struct sge *s = &adap->sge;
2210 u32 sge_control, sge_conm_ctrl;
2211 int ret, egress_threshold;
2214 * Ingress Padding Boundary and Egress Status Page Size are set up by
2215 * t4_fixup_host_params().
2217 sge_control = t4_read_reg(adap, A_SGE_CONTROL);
2218 s->pktshift = G_PKTSHIFT(sge_control);
2219 s->stat_len = (sge_control & F_EGRSTATUSPAGESIZE) ? 128 : 64;
2220 s->fl_align = t4_fl_pkt_align(adap);
2221 ret = t4_sge_init_soft(adap);
2223 dev_err(adap, "%s: t4_sge_init_soft failed, error %d\n",
2229 * A FL with <= fl_starve_thres buffers is starving and a periodic
2230 * timer will attempt to refill it. This needs to be larger than the
2231 * SGE's Egress Congestion Threshold. If it isn't, then we can get
2232 * stuck waiting for new packets while the SGE is waiting for us to
2233 * give it more Free List entries. (Note that the SGE's Egress
2234 * Congestion Threshold is in units of 2 Free List pointers.) For T4,
2235 * there was only a single field to control this. For T5 there's the
2236 * original field which now only applies to Unpacked Mode Free List
2237 * buffers and a new field which only applies to Packed Mode Free List
2240 sge_conm_ctrl = t4_read_reg(adap, A_SGE_CONM_CTRL);
2241 if (is_t4(adap->params.chip) || adap->use_unpacked_mode)
2242 egress_threshold = G_EGRTHRESHOLD(sge_conm_ctrl);
2244 egress_threshold = G_EGRTHRESHOLDPACKING(sge_conm_ctrl);
2245 s->fl_starve_thres = 2 * egress_threshold + 1;