drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <dpaa_flow.h>
  43 #include <rte_pmd_dpaa.h>
  44
  45 #include <fsl_usd.h>
  46 #include <fsl_qman.h>
  47 #include <fsl_bman.h>
  48 #include <fsl_fman.h>
  49 #include <process.h>
  50
  51 /* Supported Rx offloads */
  52 static uint64_t dev_rx_offloads_sup =
  53                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  54                 DEV_RX_OFFLOAD_SCATTER;
  55
  56 /* Rx offloads which cannot be disabled */
  57 static uint64_t dev_rx_offloads_nodis =
  58                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  59                 DEV_RX_OFFLOAD_UDP_CKSUM |
  60                 DEV_RX_OFFLOAD_TCP_CKSUM |
  61                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  62                 DEV_RX_OFFLOAD_RSS_HASH;
  63
  64 /* Supported Tx offloads */
  65 static uint64_t dev_tx_offloads_sup =
  66                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  67                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  68
  69 /* Tx offloads which cannot be disabled */
  70 static uint64_t dev_tx_offloads_nodis =
  71                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  72                 DEV_TX_OFFLOAD_UDP_CKSUM |
  73                 DEV_TX_OFFLOAD_TCP_CKSUM |
  74                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  75                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  76                 DEV_TX_OFFLOAD_MULTI_SEGS;
  77
  78 /* Keep track of whether QMAN and BMAN have been globally initialized */
  79 static int is_global_init;
  80 static int fmc_q = 1;   /* Indicates the use of static fmc for distribution */
  81 static int default_q;   /* use default queue - FMC is not executed*/
  82 /* At present we only allow up to 4 push mode queues as default - as each of
  83  * this queue need dedicated portal and we are short of portals.
  84  */
  85 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  86 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  87
  88 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  89 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  90
  91
  92 /* Per RX FQ Taildrop in frame count */
  93 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  94
  95 /* Per TX FQ Taildrop in frame count, disabled by default */
  96 static unsigned int td_tx_threshold;
  97
  98 struct rte_dpaa_xstats_name_off {
  99         char name[RTE_ETH_XSTATS_NAME_SIZE];
 100         uint32_t offset;
 101 };
 102
 103 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 104         {"rx_align_err",
 105                 offsetof(struct dpaa_if_stats, raln)},
 106         {"rx_valid_pause",
 107                 offsetof(struct dpaa_if_stats, rxpf)},
 108         {"rx_fcs_err",
 109                 offsetof(struct dpaa_if_stats, rfcs)},
 110         {"rx_vlan_frame",
 111                 offsetof(struct dpaa_if_stats, rvlan)},
 112         {"rx_frame_err",
 113                 offsetof(struct dpaa_if_stats, rerr)},
 114         {"rx_drop_err",
 115                 offsetof(struct dpaa_if_stats, rdrp)},
 116         {"rx_undersized",
 117                 offsetof(struct dpaa_if_stats, rund)},
 118         {"rx_oversize_err",
 119                 offsetof(struct dpaa_if_stats, rovr)},
 120         {"rx_fragment_pkt",
 121                 offsetof(struct dpaa_if_stats, rfrg)},
 122         {"tx_valid_pause",
 123                 offsetof(struct dpaa_if_stats, txpf)},
 124         {"tx_fcs_err",
 125                 offsetof(struct dpaa_if_stats, terr)},
 126         {"tx_vlan_frame",
 127                 offsetof(struct dpaa_if_stats, tvlan)},
 128         {"rx_undersized",
 129                 offsetof(struct dpaa_if_stats, tund)},
 130 };
 131
 132 static struct rte_dpaa_driver rte_dpaa_pmd;
 133
 134 static int
 135 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 136
 137 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 138                                 int wait_to_complete __rte_unused);
 139
 140 static void dpaa_interrupt_handler(void *param);
 141
 142 static inline void
 143 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 144 {
 145         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 146         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 147         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 148                            QM_FQCTRL_PREFERINCACHE;
 149         opts->fqd.context_a.stashing.exclusive = 0;
 150         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 151                 opts->fqd.context_a.stashing.annotation_cl =
 152                                                 DPAA_IF_RX_ANNOTATION_STASH;
 153         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 154         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 155 }
 156
 157 static int
 158 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 159 {
 160         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 161                                 + VLAN_TAG_SIZE;
 162         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 163
 164         PMD_INIT_FUNC_TRACE();
 165
 166         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 167                 return -EINVAL;
 168         /*
 169          * Refuse mtu that requires the support of scattered packets
 170          * when this feature has not been enabled before.
 171          */
 172         if (dev->data->min_rx_buf_size &&
 173                 !dev->data->scattered_rx && frame_size > buffsz) {
 174                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 175                 return -EINVAL;
 176         }
 177
 178         /* check <seg size> * <max_seg>  >= max_frame */
 179         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 180                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 181                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 182                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 183                 return -EINVAL;
 184         }
 185
 186         if (frame_size > RTE_ETHER_MAX_LEN)
 187                 dev->data->dev_conf.rxmode.offloads |=
 188                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 189         else
 190                 dev->data->dev_conf.rxmode.offloads &=
 191                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 192
 193         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 194
 195         fman_if_set_maxfrm(dev->process_private, frame_size);
 196
 197         return 0;
 198 }
 199
 200 static int
 201 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 202 {
 203         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 204         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 205         uint64_t tx_offloads = eth_conf->txmode.offloads;
 206         struct rte_device *rdev = dev->device;
 207         struct rte_dpaa_device *dpaa_dev;
 208         struct fman_if *fif = dev->process_private;
 209         struct __fman_if *__fif;
 210         struct rte_intr_handle *intr_handle;
 211         int ret;
 212
 213         PMD_INIT_FUNC_TRACE();
 214
 215         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 216         intr_handle = &dpaa_dev->intr_handle;
 217         __fif = container_of(fif, struct __fman_if, __if);
 218
 219         /* Rx offloads which are enabled by default */
 220         if (dev_rx_offloads_nodis & ~rx_offloads) {
 221                 DPAA_PMD_INFO(
 222                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 223                 " fixed are 0x%" PRIx64,
 224                 rx_offloads, dev_rx_offloads_nodis);
 225         }
 226
 227         /* Tx offloads which are enabled by default */
 228         if (dev_tx_offloads_nodis & ~tx_offloads) {
 229                 DPAA_PMD_INFO(
 230                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 231                 " fixed are 0x%" PRIx64,
 232                 tx_offloads, dev_tx_offloads_nodis);
 233         }
 234
 235         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 236                 uint32_t max_len;
 237
 238                 DPAA_PMD_DEBUG("enabling jumbo");
 239
 240                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 241                     DPAA_MAX_RX_PKT_LEN)
 242                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 243                 else {
 244                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 245                                 "supported is %d",
 246                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 247                                 DPAA_MAX_RX_PKT_LEN);
 248                         max_len = DPAA_MAX_RX_PKT_LEN;
 249                 }
 250
 251                 fman_if_set_maxfrm(dev->process_private, max_len);
 252                 dev->data->mtu = max_len
 253                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 254         }
 255
 256         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 257                 DPAA_PMD_DEBUG("enabling scatter mode");
 258                 fman_if_set_sg(dev->process_private, 1);
 259                 dev->data->scattered_rx = 1;
 260         }
 261
 262         if (!(default_q || fmc_q)) {
 263                 if (dpaa_fm_config(dev,
 264                         eth_conf->rx_adv_conf.rss_conf.rss_hf)) {
 265                         dpaa_write_fm_config_to_file();
 266                         DPAA_PMD_ERR("FM port configuration: Failed\n");
 267                         return -1;
 268                 }
 269                 dpaa_write_fm_config_to_file();
 270         }
 271
 272         /* if the interrupts were configured on this devices*/
 273         if (intr_handle && intr_handle->fd) {
 274                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 275                         rte_intr_callback_register(intr_handle,
 276                                            dpaa_interrupt_handler,
 277                                            (void *)dev);
 278
 279                 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
 280                 if (ret) {
 281                         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 282                                 rte_intr_callback_unregister(intr_handle,
 283                                         dpaa_interrupt_handler,
 284                                         (void *)dev);
 285                                 if (ret == EINVAL)
 286                                         printf("Failed to enable interrupt: Not Supported\n");
 287                                 else
 288                                         printf("Failed to enable interrupt\n");
 289                         }
 290                         dev->data->dev_conf.intr_conf.lsc = 0;
 291                         dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 292                 }
 293         }
 294         return 0;
 295 }
 296
 297 static const uint32_t *
 298 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 299 {
 300         static const uint32_t ptypes[] = {
 301                 RTE_PTYPE_L2_ETHER,
 302                 RTE_PTYPE_L2_ETHER_VLAN,
 303                 RTE_PTYPE_L2_ETHER_ARP,
 304                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 305                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 306                 RTE_PTYPE_L4_ICMP,
 307                 RTE_PTYPE_L4_TCP,
 308                 RTE_PTYPE_L4_UDP,
 309                 RTE_PTYPE_L4_FRAG,
 310                 RTE_PTYPE_L4_TCP,
 311                 RTE_PTYPE_L4_UDP,
 312                 RTE_PTYPE_L4_SCTP
 313         };
 314
 315         PMD_INIT_FUNC_TRACE();
 316
 317         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 318                 return ptypes;
 319         return NULL;
 320 }
 321
 322 static void dpaa_interrupt_handler(void *param)
 323 {
 324         struct rte_eth_dev *dev = param;
 325         struct rte_device *rdev = dev->device;
 326         struct rte_dpaa_device *dpaa_dev;
 327         struct rte_intr_handle *intr_handle;
 328         uint64_t buf;
 329         int bytes_read;
 330
 331         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 332         intr_handle = &dpaa_dev->intr_handle;
 333
 334         bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
 335         if (bytes_read < 0)
 336                 DPAA_PMD_ERR("Error reading eventfd\n");
 337         dpaa_eth_link_update(dev, 0);
 338         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 339 }
 340
 341 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 342 {
 343         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 344
 345         PMD_INIT_FUNC_TRACE();
 346
 347         if (!(default_q || fmc_q))
 348                 dpaa_write_fm_config_to_file();
 349
 350         /* Change tx callback to the real one */
 351         if (dpaa_intf->cgr_tx)
 352                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 353         else
 354                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 355
 356         fman_if_enable_rx(dev->process_private);
 357
 358         return 0;
 359 }
 360
 361 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 362 {
 363         struct fman_if *fif = dev->process_private;
 364
 365         PMD_INIT_FUNC_TRACE();
 366
 367         if (!fif->is_shared_mac)
 368                 fman_if_disable_rx(fif);
 369         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 370 }
 371
 372 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 373 {
 374         struct fman_if *fif = dev->process_private;
 375         struct __fman_if *__fif;
 376         struct rte_device *rdev = dev->device;
 377         struct rte_dpaa_device *dpaa_dev;
 378         struct rte_intr_handle *intr_handle;
 379
 380         PMD_INIT_FUNC_TRACE();
 381
 382         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 383         intr_handle = &dpaa_dev->intr_handle;
 384         __fif = container_of(fif, struct __fman_if, __if);
 385
 386         dpaa_eth_dev_stop(dev);
 387
 388         if (intr_handle && intr_handle->fd &&
 389             dev->data->dev_conf.intr_conf.lsc != 0) {
 390                 dpaa_intr_disable(__fif->node_name);
 391                 rte_intr_callback_unregister(intr_handle,
 392                                              dpaa_interrupt_handler,
 393                                              (void *)dev);
 394         }
 395 }
 396
 397 static int
 398 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 399                      char *fw_version,
 400                      size_t fw_size)
 401 {
 402         int ret;
 403         FILE *svr_file = NULL;
 404         unsigned int svr_ver = 0;
 405
 406         PMD_INIT_FUNC_TRACE();
 407
 408         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 409         if (!svr_file) {
 410                 DPAA_PMD_ERR("Unable to open SoC device");
 411                 return -ENOTSUP; /* Not supported on this infra */
 412         }
 413         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 414                 dpaa_svr_family = svr_ver & SVR_MASK;
 415         else
 416                 DPAA_PMD_ERR("Unable to read SoC device");
 417
 418         fclose(svr_file);
 419
 420         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 421                        svr_ver, fman_ip_rev);
 422         ret += 1; /* add the size of '\0' */
 423
 424         if (fw_size < (uint32_t)ret)
 425                 return ret;
 426         else
 427                 return 0;
 428 }
 429
 430 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 431                              struct rte_eth_dev_info *dev_info)
 432 {
 433         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 434         struct fman_if *fif = dev->process_private;
 435
 436         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 437
 438         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 439         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 440         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 441         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 442         dev_info->max_hash_mac_addrs = 0;
 443         dev_info->max_vfs = 0;
 444         dev_info->max_vmdq_pools = ETH_16_POOLS;
 445         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 446
 447         if (fif->mac_type == fman_mac_1g) {
 448                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 449         } else if (fif->mac_type == fman_mac_2_5g) {
 450                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 451                                         | ETH_LINK_SPEED_2_5G;
 452         } else if (fif->mac_type == fman_mac_10g) {
 453                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 454                                         | ETH_LINK_SPEED_2_5G
 455                                         | ETH_LINK_SPEED_10G;
 456         } else {
 457                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 458                              dpaa_intf->name, fif->mac_type);
 459                 return -EINVAL;
 460         }
 461
 462         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 463                                         dev_rx_offloads_nodis;
 464         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 465                                         dev_tx_offloads_nodis;
 466         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 467         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 468         dev_info->default_rxportconf.nb_queues = 1;
 469         dev_info->default_txportconf.nb_queues = 1;
 470         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 471         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 472
 473         return 0;
 474 }
 475
 476 static int
 477 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 478                         __rte_unused uint16_t queue_id,
 479                         struct rte_eth_burst_mode *mode)
 480 {
 481         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 482         int ret = -EINVAL;
 483         unsigned int i;
 484         const struct burst_info {
 485                 uint64_t flags;
 486                 const char *output;
 487         } rx_offload_map[] = {
 488                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 489                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"},
 490                         {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 491                         {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 492                         {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 493                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 494                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}
 495         };
 496
 497         /* Update Rx offload info */
 498         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 499                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 500                         snprintf(mode->info, sizeof(mode->info), "%s",
 501                                 rx_offload_map[i].output);
 502                         ret = 0;
 503                         break;
 504                 }
 505         }
 506         return ret;
 507 }
 508
 509 static int
 510 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 511                         __rte_unused uint16_t queue_id,
 512                         struct rte_eth_burst_mode *mode)
 513 {
 514         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 515         int ret = -EINVAL;
 516         unsigned int i;
 517         const struct burst_info {
 518                 uint64_t flags;
 519                 const char *output;
 520         } tx_offload_map[] = {
 521                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 522                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 523                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 524                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 525                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 526                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 527                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 528                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 529         };
 530
 531         /* Update Tx offload info */
 532         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 533                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 534                         snprintf(mode->info, sizeof(mode->info), "%s",
 535                                 tx_offload_map[i].output);
 536                         ret = 0;
 537                         break;
 538                 }
 539         }
 540         return ret;
 541 }
 542
 543 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 544                                 int wait_to_complete __rte_unused)
 545 {
 546         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 547         struct rte_eth_link *link = &dev->data->dev_link;
 548         struct fman_if *fif = dev->process_private;
 549         struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
 550         int ret;
 551
 552         PMD_INIT_FUNC_TRACE();
 553
 554         if (fif->mac_type == fman_mac_1g)
 555                 link->link_speed = ETH_SPEED_NUM_1G;
 556         else if (fif->mac_type == fman_mac_2_5g)
 557                 link->link_speed = ETH_SPEED_NUM_2_5G;
 558         else if (fif->mac_type == fman_mac_10g)
 559                 link->link_speed = ETH_SPEED_NUM_10G;
 560         else
 561                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 562                              dpaa_intf->name, fif->mac_type);
 563
 564         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
 565                 ret = dpaa_get_link_status(__fif->node_name);
 566                 if (ret < 0)
 567                         return ret;
 568                 link->link_status = ret;
 569         } else {
 570                 link->link_status = dpaa_intf->valid;
 571         }
 572
 573         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 574         link->link_autoneg = ETH_LINK_AUTONEG;
 575
 576         DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
 577                       link->link_status ? "Up" : "Down");
 578         return 0;
 579 }
 580
 581 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 582                                struct rte_eth_stats *stats)
 583 {
 584         PMD_INIT_FUNC_TRACE();
 585
 586         fman_if_stats_get(dev->process_private, stats);
 587         return 0;
 588 }
 589
 590 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 591 {
 592         PMD_INIT_FUNC_TRACE();
 593
 594         fman_if_stats_reset(dev->process_private);
 595
 596         return 0;
 597 }
 598
 599 static int
 600 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 601                     unsigned int n)
 602 {
 603         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 604         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 605
 606         if (n < num)
 607                 return num;
 608
 609         if (xstats == NULL)
 610                 return 0;
 611
 612         fman_if_stats_get_all(dev->process_private, values,
 613                               sizeof(struct dpaa_if_stats) / 8);
 614
 615         for (i = 0; i < num; i++) {
 616                 xstats[i].id = i;
 617                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 618         }
 619         return i;
 620 }
 621
 622 static int
 623 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 624                       struct rte_eth_xstat_name *xstats_names,
 625                       unsigned int limit)
 626 {
 627         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 628
 629         if (limit < stat_cnt)
 630                 return stat_cnt;
 631
 632         if (xstats_names != NULL)
 633                 for (i = 0; i < stat_cnt; i++)
 634                         strlcpy(xstats_names[i].name,
 635                                 dpaa_xstats_strings[i].name,
 636                                 sizeof(xstats_names[i].name));
 637
 638         return stat_cnt;
 639 }
 640
 641 static int
 642 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 643                       uint64_t *values, unsigned int n)
 644 {
 645         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 646         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 647
 648         if (!ids) {
 649                 if (n < stat_cnt)
 650                         return stat_cnt;
 651
 652                 if (!values)
 653                         return 0;
 654
 655                 fman_if_stats_get_all(dev->process_private, values_copy,
 656                                       sizeof(struct dpaa_if_stats) / 8);
 657
 658                 for (i = 0; i < stat_cnt; i++)
 659                         values[i] =
 660                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 661
 662                 return stat_cnt;
 663         }
 664
 665         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 666
 667         for (i = 0; i < n; i++) {
 668                 if (ids[i] >= stat_cnt) {
 669                         DPAA_PMD_ERR("id value isn't valid");
 670                         return -1;
 671                 }
 672                 values[i] = values_copy[ids[i]];
 673         }
 674         return n;
 675 }
 676
 677 static int
 678 dpaa_xstats_get_names_by_id(
 679         struct rte_eth_dev *dev,
 680         struct rte_eth_xstat_name *xstats_names,
 681         const uint64_t *ids,
 682         unsigned int limit)
 683 {
 684         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 685         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 686
 687         if (!ids)
 688                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 689
 690         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 691
 692         for (i = 0; i < limit; i++) {
 693                 if (ids[i] >= stat_cnt) {
 694                         DPAA_PMD_ERR("id value isn't valid");
 695                         return -1;
 696                 }
 697                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 698         }
 699         return limit;
 700 }
 701
 702 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 703 {
 704         PMD_INIT_FUNC_TRACE();
 705
 706         fman_if_promiscuous_enable(dev->process_private);
 707
 708         return 0;
 709 }
 710
 711 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 712 {
 713         PMD_INIT_FUNC_TRACE();
 714
 715         fman_if_promiscuous_disable(dev->process_private);
 716
 717         return 0;
 718 }
 719
 720 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 721 {
 722         PMD_INIT_FUNC_TRACE();
 723
 724         fman_if_set_mcast_filter_table(dev->process_private);
 725
 726         return 0;
 727 }
 728
 729 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 730 {
 731         PMD_INIT_FUNC_TRACE();
 732
 733         fman_if_reset_mcast_filter_table(dev->process_private);
 734
 735         return 0;
 736 }
 737
 738 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev)
 739 {
 740         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 741         struct fman_if_ic_params icp;
 742         uint32_t fd_offset;
 743         uint32_t bp_size;
 744
 745         memset(&icp, 0, sizeof(icp));
 746         /* set ICEOF for to the default value , which is 0*/
 747         icp.iciof = DEFAULT_ICIOF;
 748         icp.iceof = DEFAULT_RX_ICEOF;
 749         icp.icsz = DEFAULT_ICSZ;
 750         fman_if_set_ic_params(dev->process_private, &icp);
 751
 752         fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 753         fman_if_set_fdoff(dev->process_private, fd_offset);
 754
 755         /* Buffer pool size should be equal to Dataroom Size*/
 756         bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp);
 757
 758         fman_if_set_bp(dev->process_private,
 759                        dpaa_intf->bp_info->mp->size,
 760                        dpaa_intf->bp_info->bpid, bp_size);
 761 }
 762
 763 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev,
 764                                              int8_t vsp_id, uint32_t bpid)
 765 {
 766         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 767         struct fman_if *fif = dev->process_private;
 768
 769         if (fif->num_profiles) {
 770                 if (vsp_id < 0)
 771                         vsp_id = fif->base_profile_id;
 772         } else {
 773                 if (vsp_id < 0)
 774                         vsp_id = 0;
 775         }
 776
 777         if (dpaa_intf->vsp_bpid[vsp_id] &&
 778                 bpid != dpaa_intf->vsp_bpid[vsp_id]) {
 779                 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP");
 780
 781                 return -1;
 782         }
 783
 784         return 0;
 785 }
 786
 787 static
 788 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 789                             uint16_t nb_desc,
 790                             unsigned int socket_id __rte_unused,
 791                             const struct rte_eth_rxconf *rx_conf,
 792                             struct rte_mempool *mp)
 793 {
 794         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 795         struct fman_if *fif = dev->process_private;
 796         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 797         struct qm_mcc_initfq opts = {0};
 798         u32 flags = 0;
 799         int ret;
 800         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 801
 802         PMD_INIT_FUNC_TRACE();
 803
 804         if (queue_idx >= dev->data->nb_rx_queues) {
 805                 rte_errno = EOVERFLOW;
 806                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 807                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 808                 return -rte_errno;
 809         }
 810
 811         /* Rx deferred start is not supported */
 812         if (rx_conf->rx_deferred_start) {
 813                 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
 814                 return -EINVAL;
 815         }
 816         rxq->nb_desc = UINT16_MAX;
 817         rxq->offloads = rx_conf->offloads;
 818
 819         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 820                         queue_idx, rxq->fqid);
 821
 822         if (!fif->num_profiles) {
 823                 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
 824                         dpaa_intf->bp_info->mp != mp) {
 825                         DPAA_PMD_WARN("Multiple pools on same interface not"
 826                                       " supported");
 827                         return -EINVAL;
 828                 }
 829         } else {
 830                 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id,
 831                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) {
 832                         return -EINVAL;
 833                 }
 834         }
 835
 836         /* Max packet can fit in single buffer */
 837         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 838                 ;
 839         } else if (dev->data->dev_conf.rxmode.offloads &
 840                         DEV_RX_OFFLOAD_SCATTER) {
 841                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 842                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 843                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 844                                 "MaxSGlist %d",
 845                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 846                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 847                         rte_errno = EOVERFLOW;
 848                         return -rte_errno;
 849                 }
 850         } else {
 851                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 852                      " larger than a single mbuf (%u) and scattered"
 853                      " mode has not been requested",
 854                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 855                      buffsz - RTE_PKTMBUF_HEADROOM);
 856         }
 857
 858         dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 859
 860         /* For shared interface, it's done in kernel, skip.*/
 861         if (!fif->is_shared_mac)
 862                 dpaa_fman_if_pool_setup(dev);
 863
 864         if (fif->num_profiles) {
 865                 int8_t vsp_id = rxq->vsp_id;
 866
 867                 if (vsp_id >= 0) {
 868                         ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id,
 869                                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid,
 870                                         fif);
 871                         if (ret) {
 872                                 DPAA_PMD_ERR("dpaa_port_vsp_update failed");
 873                                 return ret;
 874                         }
 875                 } else {
 876                         DPAA_PMD_INFO("Base profile is associated to"
 877                                 " RXQ fqid:%d\r\n", rxq->fqid);
 878                         if (fif->is_shared_mac) {
 879                                 DPAA_PMD_ERR("Fatal: Base profile is associated"
 880                                              " to shared interface on DPDK.");
 881                                 return -EINVAL;
 882                         }
 883                         dpaa_intf->vsp_bpid[fif->base_profile_id] =
 884                                 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
 885                 }
 886         } else {
 887                 dpaa_intf->vsp_bpid[0] =
 888                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
 889         }
 890
 891         dpaa_intf->valid = 1;
 892         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 893                 fman_if_get_sg_enable(fif),
 894                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 895         /* checking if push mode only, no error check for now */
 896         if (!rxq->is_static &&
 897             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 898                 struct qman_portal *qp;
 899                 int q_fd;
 900
 901                 dpaa_push_queue_idx++;
 902                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 903                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 904                                    QM_FQCTRL_CTXASTASHING |
 905                                    QM_FQCTRL_PREFERINCACHE;
 906                 opts.fqd.context_a.stashing.exclusive = 0;
 907                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 908                  * So do not enable stashing in this case
 909                  */
 910                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 911                         opts.fqd.context_a.stashing.annotation_cl =
 912                                                 DPAA_IF_RX_ANNOTATION_STASH;
 913                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 914                 opts.fqd.context_a.stashing.context_cl =
 915                                                 DPAA_IF_RX_CONTEXT_STASH;
 916
 917                 /*Create a channel and associate given queue with the channel*/
 918                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 919                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 920                 opts.fqd.dest.channel = rxq->ch_id;
 921                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 922                 flags = QMAN_INITFQ_FLAG_SCHED;
 923
 924                 /* Configure tail drop */
 925                 if (dpaa_intf->cgr_rx) {
 926                         opts.we_mask |= QM_INITFQ_WE_CGID;
 927                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 928                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 929                 }
 930                 ret = qman_init_fq(rxq, flags, &opts);
 931                 if (ret) {
 932                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 933                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 934                         return ret;
 935                 }
 936                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 937                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 938                 } else {
 939                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 940                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 941                 }
 942
 943                 rxq->is_static = true;
 944
 945                 /* Allocate qman specific portals */
 946                 qp = fsl_qman_fq_portal_create(&q_fd);
 947                 if (!qp) {
 948                         DPAA_PMD_ERR("Unable to alloc fq portal");
 949                         return -1;
 950                 }
 951                 rxq->qp = qp;
 952
 953                 /* Set up the device interrupt handler */
 954                 if (!dev->intr_handle) {
 955                         struct rte_dpaa_device *dpaa_dev;
 956                         struct rte_device *rdev = dev->device;
 957
 958                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
 959                                                 device);
 960                         dev->intr_handle = &dpaa_dev->intr_handle;
 961                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
 962                                         dpaa_push_mode_max_queue, 0);
 963                         if (!dev->intr_handle->intr_vec) {
 964                                 DPAA_PMD_ERR("intr_vec alloc failed");
 965                                 return -ENOMEM;
 966                         }
 967                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
 968                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
 969                 }
 970
 971                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
 972                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
 973                 dev->intr_handle->efds[queue_idx] = q_fd;
 974                 rxq->q_fd = q_fd;
 975         }
 976         rxq->bp_array = rte_dpaa_bpid_info;
 977         dev->data->rx_queues[queue_idx] = rxq;
 978
 979         /* configure the CGR size as per the desc size */
 980         if (dpaa_intf->cgr_rx) {
 981                 struct qm_mcc_initcgr cgr_opts = {0};
 982
 983                 rxq->nb_desc = nb_desc;
 984                 /* Enable tail drop with cgr on this queue */
 985                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 986                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 987                 if (ret) {
 988                         DPAA_PMD_WARN(
 989                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 990                                 rxq->fqid, ret);
 991                 }
 992         }
 993
 994         return 0;
 995 }
 996
 997 int
 998 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 999                 int eth_rx_queue_id,
1000                 u16 ch_id,
1001                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1002 {
1003         int ret;
1004         u32 flags = 0;
1005         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1006         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1007         struct qm_mcc_initfq opts = {0};
1008
1009         if (dpaa_push_mode_max_queue)
1010                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
1011                               "PUSH mode already enabled for first %d queues.\n"
1012                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
1013                               dpaa_push_mode_max_queue);
1014
1015         dpaa_poll_queue_default_config(&opts);
1016
1017         switch (queue_conf->ev.sched_type) {
1018         case RTE_SCHED_TYPE_ATOMIC:
1019                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
1020                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
1021                  * configuration with HOLD_ACTIVE setting
1022                  */
1023                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
1024                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
1025                 break;
1026         case RTE_SCHED_TYPE_ORDERED:
1027                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
1028                 return -1;
1029         default:
1030                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
1031                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
1032                 break;
1033         }
1034
1035         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1036         opts.fqd.dest.channel = ch_id;
1037         opts.fqd.dest.wq = queue_conf->ev.priority;
1038
1039         if (dpaa_intf->cgr_rx) {
1040                 opts.we_mask |= QM_INITFQ_WE_CGID;
1041                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1042                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1043         }
1044
1045         flags = QMAN_INITFQ_FLAG_SCHED;
1046
1047         ret = qman_init_fq(rxq, flags, &opts);
1048         if (ret) {
1049                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
1050                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1051                 return ret;
1052         }
1053
1054         /* copy configuration which needs to be filled during dequeue */
1055         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
1056         dev->data->rx_queues[eth_rx_queue_id] = rxq;
1057
1058         return ret;
1059 }
1060
1061 int
1062 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1063                 int eth_rx_queue_id)
1064 {
1065         struct qm_mcc_initfq opts;
1066         int ret;
1067         u32 flags = 0;
1068         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1069         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1070
1071         dpaa_poll_queue_default_config(&opts);
1072
1073         if (dpaa_intf->cgr_rx) {
1074                 opts.we_mask |= QM_INITFQ_WE_CGID;
1075                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1076                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1077         }
1078
1079         ret = qman_init_fq(rxq, flags, &opts);
1080         if (ret) {
1081                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1082                              rxq->fqid, ret);
1083         }
1084
1085         rxq->cb.dqrr_dpdk_cb = NULL;
1086         dev->data->rx_queues[eth_rx_queue_id] = NULL;
1087
1088         return 0;
1089 }
1090
1091 static
1092 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
1093 {
1094         PMD_INIT_FUNC_TRACE();
1095 }
1096
1097 static
1098 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1099                             uint16_t nb_desc __rte_unused,
1100                 unsigned int socket_id __rte_unused,
1101                 const struct rte_eth_txconf *tx_conf)
1102 {
1103         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1104         struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1105
1106         PMD_INIT_FUNC_TRACE();
1107
1108         /* Tx deferred start is not supported */
1109         if (tx_conf->tx_deferred_start) {
1110                 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1111                 return -EINVAL;
1112         }
1113         txq->nb_desc = UINT16_MAX;
1114         txq->offloads = tx_conf->offloads;
1115
1116         if (queue_idx >= dev->data->nb_tx_queues) {
1117                 rte_errno = EOVERFLOW;
1118                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1119                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
1120                 return -rte_errno;
1121         }
1122
1123         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1124                         queue_idx, txq->fqid);
1125         dev->data->tx_queues[queue_idx] = txq;
1126
1127         return 0;
1128 }
1129
1130 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
1131 {
1132         PMD_INIT_FUNC_TRACE();
1133 }
1134
1135 static uint32_t
1136 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1137 {
1138         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1139         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
1140         u32 frm_cnt = 0;
1141
1142         PMD_INIT_FUNC_TRACE();
1143
1144         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1145                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
1146                                rx_queue_id, frm_cnt);
1147         }
1148         return frm_cnt;
1149 }
1150
1151 static int dpaa_link_down(struct rte_eth_dev *dev)
1152 {
1153         struct fman_if *fif = dev->process_private;
1154         struct __fman_if *__fif;
1155
1156         PMD_INIT_FUNC_TRACE();
1157
1158         __fif = container_of(fif, struct __fman_if, __if);
1159
1160         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1161                 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN);
1162         else
1163                 dpaa_eth_dev_stop(dev);
1164         return 0;
1165 }
1166
1167 static int dpaa_link_up(struct rte_eth_dev *dev)
1168 {
1169         struct fman_if *fif = dev->process_private;
1170         struct __fman_if *__fif;
1171
1172         PMD_INIT_FUNC_TRACE();
1173
1174         __fif = container_of(fif, struct __fman_if, __if);
1175
1176         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1177                 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP);
1178         else
1179                 dpaa_eth_dev_start(dev);
1180         return 0;
1181 }
1182
1183 static int
1184 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1185                    struct rte_eth_fc_conf *fc_conf)
1186 {
1187         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1188         struct rte_eth_fc_conf *net_fc;
1189
1190         PMD_INIT_FUNC_TRACE();
1191
1192         if (!(dpaa_intf->fc_conf)) {
1193                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1194                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1195                 if (!dpaa_intf->fc_conf) {
1196                         DPAA_PMD_ERR("unable to save flow control info");
1197                         return -ENOMEM;
1198                 }
1199         }
1200         net_fc = dpaa_intf->fc_conf;
1201
1202         if (fc_conf->high_water < fc_conf->low_water) {
1203                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1204                 return -EINVAL;
1205         }
1206
1207         if (fc_conf->mode == RTE_FC_NONE) {
1208                 return 0;
1209         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1210                  fc_conf->mode == RTE_FC_FULL) {
1211                 fman_if_set_fc_threshold(dev->process_private,
1212                                          fc_conf->high_water,
1213                                          fc_conf->low_water,
1214                                          dpaa_intf->bp_info->bpid);
1215                 if (fc_conf->pause_time)
1216                         fman_if_set_fc_quanta(dev->process_private,
1217                                               fc_conf->pause_time);
1218         }
1219
1220         /* Save the information in dpaa device */
1221         net_fc->pause_time = fc_conf->pause_time;
1222         net_fc->high_water = fc_conf->high_water;
1223         net_fc->low_water = fc_conf->low_water;
1224         net_fc->send_xon = fc_conf->send_xon;
1225         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1226         net_fc->mode = fc_conf->mode;
1227         net_fc->autoneg = fc_conf->autoneg;
1228
1229         return 0;
1230 }
1231
1232 static int
1233 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1234                    struct rte_eth_fc_conf *fc_conf)
1235 {
1236         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1237         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1238         int ret;
1239
1240         PMD_INIT_FUNC_TRACE();
1241
1242         if (net_fc) {
1243                 fc_conf->pause_time = net_fc->pause_time;
1244                 fc_conf->high_water = net_fc->high_water;
1245                 fc_conf->low_water = net_fc->low_water;
1246                 fc_conf->send_xon = net_fc->send_xon;
1247                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1248                 fc_conf->mode = net_fc->mode;
1249                 fc_conf->autoneg = net_fc->autoneg;
1250                 return 0;
1251         }
1252         ret = fman_if_get_fc_threshold(dev->process_private);
1253         if (ret) {
1254                 fc_conf->mode = RTE_FC_TX_PAUSE;
1255                 fc_conf->pause_time =
1256                         fman_if_get_fc_quanta(dev->process_private);
1257         } else {
1258                 fc_conf->mode = RTE_FC_NONE;
1259         }
1260
1261         return 0;
1262 }
1263
1264 static int
1265 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1266                              struct rte_ether_addr *addr,
1267                              uint32_t index,
1268                              __rte_unused uint32_t pool)
1269 {
1270         int ret;
1271
1272         PMD_INIT_FUNC_TRACE();
1273
1274         ret = fman_if_add_mac_addr(dev->process_private,
1275                                    addr->addr_bytes, index);
1276
1277         if (ret)
1278                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1279         return 0;
1280 }
1281
1282 static void
1283 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1284                           uint32_t index)
1285 {
1286         PMD_INIT_FUNC_TRACE();
1287
1288         fman_if_clear_mac_addr(dev->process_private, index);
1289 }
1290
1291 static int
1292 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1293                        struct rte_ether_addr *addr)
1294 {
1295         int ret;
1296
1297         PMD_INIT_FUNC_TRACE();
1298
1299         ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1300         if (ret)
1301                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1302
1303         return ret;
1304 }
1305
1306 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1307                                       uint16_t queue_id)
1308 {
1309         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1310         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1311
1312         if (!rxq->is_static)
1313                 return -EINVAL;
1314
1315         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1316 }
1317
1318 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1319                                        uint16_t queue_id)
1320 {
1321         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1322         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1323         uint32_t temp;
1324         ssize_t temp1;
1325
1326         if (!rxq->is_static)
1327                 return -EINVAL;
1328
1329         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1330
1331         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1332         if (temp1 != sizeof(temp))
1333                 DPAA_PMD_ERR("irq read error");
1334
1335         qman_fq_portal_thread_irq(rxq->qp);
1336
1337         return 0;
1338 }
1339
1340 static void
1341 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1342         struct rte_eth_rxq_info *qinfo)
1343 {
1344         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1345         struct qman_fq *rxq;
1346
1347         rxq = dev->data->rx_queues[queue_id];
1348
1349         qinfo->mp = dpaa_intf->bp_info->mp;
1350         qinfo->scattered_rx = dev->data->scattered_rx;
1351         qinfo->nb_desc = rxq->nb_desc;
1352         qinfo->conf.rx_free_thresh = 1;
1353         qinfo->conf.rx_drop_en = 1;
1354         qinfo->conf.rx_deferred_start = 0;
1355         qinfo->conf.offloads = rxq->offloads;
1356 }
1357
1358 static void
1359 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1360         struct rte_eth_txq_info *qinfo)
1361 {
1362         struct qman_fq *txq;
1363
1364         txq = dev->data->tx_queues[queue_id];
1365
1366         qinfo->nb_desc = txq->nb_desc;
1367         qinfo->conf.tx_thresh.pthresh = 0;
1368         qinfo->conf.tx_thresh.hthresh = 0;
1369         qinfo->conf.tx_thresh.wthresh = 0;
1370
1371         qinfo->conf.tx_free_thresh = 0;
1372         qinfo->conf.tx_rs_thresh = 0;
1373         qinfo->conf.offloads = txq->offloads;
1374         qinfo->conf.tx_deferred_start = 0;
1375 }
1376
1377 static struct eth_dev_ops dpaa_devops = {
1378         .dev_configure            = dpaa_eth_dev_configure,
1379         .dev_start                = dpaa_eth_dev_start,
1380         .dev_stop                 = dpaa_eth_dev_stop,
1381         .dev_close                = dpaa_eth_dev_close,
1382         .dev_infos_get            = dpaa_eth_dev_info,
1383         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1384
1385         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1386         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1387         .rx_queue_release         = dpaa_eth_rx_queue_release,
1388         .tx_queue_release         = dpaa_eth_tx_queue_release,
1389         .rx_queue_count           = dpaa_dev_rx_queue_count,
1390         .rx_burst_mode_get        = dpaa_dev_rx_burst_mode_get,
1391         .tx_burst_mode_get        = dpaa_dev_tx_burst_mode_get,
1392         .rxq_info_get             = dpaa_rxq_info_get,
1393         .txq_info_get             = dpaa_txq_info_get,
1394
1395         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1396         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1397
1398         .link_update              = dpaa_eth_link_update,
1399         .stats_get                = dpaa_eth_stats_get,
1400         .xstats_get               = dpaa_dev_xstats_get,
1401         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1402         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1403         .xstats_get_names         = dpaa_xstats_get_names,
1404         .xstats_reset             = dpaa_eth_stats_reset,
1405         .stats_reset              = dpaa_eth_stats_reset,
1406         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1407         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1408         .allmulticast_enable      = dpaa_eth_multicast_enable,
1409         .allmulticast_disable     = dpaa_eth_multicast_disable,
1410         .mtu_set                  = dpaa_mtu_set,
1411         .dev_set_link_down        = dpaa_link_down,
1412         .dev_set_link_up          = dpaa_link_up,
1413         .mac_addr_add             = dpaa_dev_add_mac_addr,
1414         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1415         .mac_addr_set             = dpaa_dev_set_mac_addr,
1416
1417         .fw_version_get           = dpaa_fw_version_get,
1418
1419         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1420         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1421 };
1422
1423 static bool
1424 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1425 {
1426         if (strcmp(dev->device->driver->name,
1427                    drv->driver.name))
1428                 return false;
1429
1430         return true;
1431 }
1432
1433 static bool
1434 is_dpaa_supported(struct rte_eth_dev *dev)
1435 {
1436         return is_device_supported(dev, &rte_dpaa_pmd);
1437 }
1438
1439 int
1440 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1441 {
1442         struct rte_eth_dev *dev;
1443
1444         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1445
1446         dev = &rte_eth_devices[port];
1447
1448         if (!is_dpaa_supported(dev))
1449                 return -ENOTSUP;
1450
1451         if (on)
1452                 fman_if_loopback_enable(dev->process_private);
1453         else
1454                 fman_if_loopback_disable(dev->process_private);
1455
1456         return 0;
1457 }
1458
1459 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1460                                struct fman_if *fman_intf)
1461 {
1462         struct rte_eth_fc_conf *fc_conf;
1463         int ret;
1464
1465         PMD_INIT_FUNC_TRACE();
1466
1467         if (!(dpaa_intf->fc_conf)) {
1468                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1469                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1470                 if (!dpaa_intf->fc_conf) {
1471                         DPAA_PMD_ERR("unable to save flow control info");
1472                         return -ENOMEM;
1473                 }
1474         }
1475         fc_conf = dpaa_intf->fc_conf;
1476         ret = fman_if_get_fc_threshold(fman_intf);
1477         if (ret) {
1478                 fc_conf->mode = RTE_FC_TX_PAUSE;
1479                 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1480         } else {
1481                 fc_conf->mode = RTE_FC_NONE;
1482         }
1483
1484         return 0;
1485 }
1486
1487 /* Initialise an Rx FQ */
1488 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1489                               uint32_t fqid)
1490 {
1491         struct qm_mcc_initfq opts = {0};
1492         int ret;
1493         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1494         struct qm_mcc_initcgr cgr_opts = {
1495                 .we_mask = QM_CGR_WE_CS_THRES |
1496                                 QM_CGR_WE_CSTD_EN |
1497                                 QM_CGR_WE_MODE,
1498                 .cgr = {
1499                         .cstd_en = QM_CGR_EN,
1500                         .mode = QMAN_CGR_MODE_FRAME
1501                 }
1502         };
1503
1504         if (fmc_q || default_q) {
1505                 ret = qman_reserve_fqid(fqid);
1506                 if (ret) {
1507                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1508                                      fqid, ret);
1509                         return -EINVAL;
1510                 }
1511         }
1512
1513         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1514         ret = qman_create_fq(fqid, flags, fq);
1515         if (ret) {
1516                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1517                         fqid, ret);
1518                 return ret;
1519         }
1520         fq->is_static = false;
1521
1522         dpaa_poll_queue_default_config(&opts);
1523
1524         if (cgr_rx) {
1525                 /* Enable tail drop with cgr on this queue */
1526                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1527                 cgr_rx->cb = NULL;
1528                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1529                                       &cgr_opts);
1530                 if (ret) {
1531                         DPAA_PMD_WARN(
1532                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1533                                 fq->fqid, ret);
1534                         goto without_cgr;
1535                 }
1536                 opts.we_mask |= QM_INITFQ_WE_CGID;
1537                 opts.fqd.cgid = cgr_rx->cgrid;
1538                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1539         }
1540 without_cgr:
1541         ret = qman_init_fq(fq, 0, &opts);
1542         if (ret)
1543                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1544         return ret;
1545 }
1546
1547 /* Initialise a Tx FQ */
1548 static int dpaa_tx_queue_init(struct qman_fq *fq,
1549                               struct fman_if *fman_intf,
1550                               struct qman_cgr *cgr_tx)
1551 {
1552         struct qm_mcc_initfq opts = {0};
1553         struct qm_mcc_initcgr cgr_opts = {
1554                 .we_mask = QM_CGR_WE_CS_THRES |
1555                                 QM_CGR_WE_CSTD_EN |
1556                                 QM_CGR_WE_MODE,
1557                 .cgr = {
1558                         .cstd_en = QM_CGR_EN,
1559                         .mode = QMAN_CGR_MODE_FRAME
1560                 }
1561         };
1562         int ret;
1563
1564         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1565                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1566         if (ret) {
1567                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1568                 return ret;
1569         }
1570         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1571                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1572         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1573         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1574         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1575         opts.fqd.context_b = 0;
1576         /* no tx-confirmation */
1577         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1578         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1579         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1580
1581         if (cgr_tx) {
1582                 /* Enable tail drop with cgr on this queue */
1583                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1584                                       td_tx_threshold, 0);
1585                 cgr_tx->cb = NULL;
1586                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1587                                       &cgr_opts);
1588                 if (ret) {
1589                         DPAA_PMD_WARN(
1590                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1591                                 fq->fqid, ret);
1592                         goto without_cgr;
1593                 }
1594                 opts.we_mask |= QM_INITFQ_WE_CGID;
1595                 opts.fqd.cgid = cgr_tx->cgrid;
1596                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1597                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1598                                 td_tx_threshold);
1599         }
1600 without_cgr:
1601         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1602         if (ret)
1603                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1604         return ret;
1605 }
1606
1607 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1608 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1609 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1610 {
1611         struct qm_mcc_initfq opts = {0};
1612         int ret;
1613
1614         PMD_INIT_FUNC_TRACE();
1615
1616         ret = qman_reserve_fqid(fqid);
1617         if (ret) {
1618                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1619                         fqid, ret);
1620                 return -EINVAL;
1621         }
1622         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1623         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1624         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1625         if (ret) {
1626                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1627                         fqid, ret);
1628                 return ret;
1629         }
1630         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1631         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1632         ret = qman_init_fq(fq, 0, &opts);
1633         if (ret)
1634                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1635                             fqid, ret);
1636         return ret;
1637 }
1638 #endif
1639
1640 /* Initialise a network interface */
1641 static int
1642 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1643 {
1644         struct rte_dpaa_device *dpaa_device;
1645         struct fm_eth_port_cfg *cfg;
1646         struct dpaa_if *dpaa_intf;
1647         struct fman_if *fman_intf;
1648         int dev_id;
1649
1650         PMD_INIT_FUNC_TRACE();
1651
1652         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1653         dev_id = dpaa_device->id.dev_id;
1654         cfg = dpaa_get_eth_port_cfg(dev_id);
1655         fman_intf = cfg->fman_if;
1656         eth_dev->process_private = fman_intf;
1657
1658         /* Plugging of UCODE burst API not supported in Secondary */
1659         dpaa_intf = eth_dev->data->dev_private;
1660         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1661         if (dpaa_intf->cgr_tx)
1662                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1663         else
1664                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1665 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1666         qman_set_fq_lookup_table(
1667                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1668 #endif
1669
1670         return 0;
1671 }
1672
1673 /* Initialise a network interface */
1674 static int
1675 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1676 {
1677         int num_rx_fqs, fqid;
1678         int loop, ret = 0;
1679         int dev_id;
1680         struct rte_dpaa_device *dpaa_device;
1681         struct dpaa_if *dpaa_intf;
1682         struct fm_eth_port_cfg *cfg;
1683         struct fman_if *fman_intf;
1684         struct fman_if_bpool *bp, *tmp_bp;
1685         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1686         uint32_t cgrid_tx[MAX_DPAA_CORES];
1687         uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1688         int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES];
1689         int8_t vsp_id = -1;
1690
1691         PMD_INIT_FUNC_TRACE();
1692
1693         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1694         dev_id = dpaa_device->id.dev_id;
1695         dpaa_intf = eth_dev->data->dev_private;
1696         cfg = dpaa_get_eth_port_cfg(dev_id);
1697         fman_intf = cfg->fman_if;
1698
1699         dpaa_intf->name = dpaa_device->name;
1700
1701         /* save fman_if & cfg in the interface struture */
1702         eth_dev->process_private = fman_intf;
1703         dpaa_intf->ifid = dev_id;
1704         dpaa_intf->cfg = cfg;
1705
1706         memset((char *)dev_rx_fqids, 0,
1707                 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1708
1709         memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES);
1710
1711         /* Initialize Rx FQ's */
1712         if (default_q) {
1713                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1714         } else if (fmc_q) {
1715                 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids,
1716                                                 dev_vspids,
1717                                                 DPAA_MAX_NUM_PCD_QUEUES);
1718                 if (num_rx_fqs < 0) {
1719                         DPAA_PMD_ERR("%s FMC initializes failed!",
1720                                 dpaa_intf->name);
1721                         goto free_rx;
1722                 }
1723                 if (!num_rx_fqs) {
1724                         DPAA_PMD_WARN("%s is not configured by FMC.",
1725                                 dpaa_intf->name);
1726                 }
1727         } else {
1728                 /* FMCLESS mode, load balance to multiple cores.*/
1729                 num_rx_fqs = rte_lcore_count();
1730         }
1731
1732         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1733          * queues.
1734          */
1735         if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1736                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1737                 return -EINVAL;
1738         }
1739
1740         if (num_rx_fqs > 0) {
1741                 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1742                         sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1743                 if (!dpaa_intf->rx_queues) {
1744                         DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1745                         return -ENOMEM;
1746                 }
1747         } else {
1748                 dpaa_intf->rx_queues = NULL;
1749         }
1750
1751         memset(cgrid, 0, sizeof(cgrid));
1752         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1753
1754         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1755          * Tx tail drop is disabled.
1756          */
1757         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1758                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1759                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1760                                td_tx_threshold);
1761                 /* if a very large value is being configured */
1762                 if (td_tx_threshold > UINT16_MAX)
1763                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1764         }
1765
1766         /* If congestion control is enabled globally*/
1767         if (num_rx_fqs > 0 && td_threshold) {
1768                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1769                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1770                 if (!dpaa_intf->cgr_rx) {
1771                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1772                         ret = -ENOMEM;
1773                         goto free_rx;
1774                 }
1775
1776                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1777                 if (ret != num_rx_fqs) {
1778                         DPAA_PMD_WARN("insufficient CGRIDs available");
1779                         ret = -EINVAL;
1780                         goto free_rx;
1781                 }
1782         } else {
1783                 dpaa_intf->cgr_rx = NULL;
1784         }
1785
1786         if (!fmc_q && !default_q) {
1787                 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1788                                             num_rx_fqs, 0);
1789                 if (ret < 0) {
1790                         DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1791                         goto free_rx;
1792                 }
1793         }
1794
1795         for (loop = 0; loop < num_rx_fqs; loop++) {
1796                 if (default_q)
1797                         fqid = cfg->rx_def;
1798                 else
1799                         fqid = dev_rx_fqids[loop];
1800
1801                 vsp_id = dev_vspids[loop];
1802
1803                 if (dpaa_intf->cgr_rx)
1804                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1805
1806                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1807                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1808                         fqid);
1809                 if (ret)
1810                         goto free_rx;
1811                 dpaa_intf->rx_queues[loop].vsp_id = vsp_id;
1812                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1813         }
1814         dpaa_intf->nb_rx_queues = num_rx_fqs;
1815
1816         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1817         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1818                 MAX_DPAA_CORES, MAX_CACHELINE);
1819         if (!dpaa_intf->tx_queues) {
1820                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1821                 ret = -ENOMEM;
1822                 goto free_rx;
1823         }
1824
1825         /* If congestion control is enabled globally*/
1826         if (td_tx_threshold) {
1827                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1828                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1829                         MAX_CACHELINE);
1830                 if (!dpaa_intf->cgr_tx) {
1831                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1832                         ret = -ENOMEM;
1833                         goto free_rx;
1834                 }
1835
1836                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1837                                              1, 0);
1838                 if (ret != MAX_DPAA_CORES) {
1839                         DPAA_PMD_WARN("insufficient CGRIDs available");
1840                         ret = -EINVAL;
1841                         goto free_rx;
1842                 }
1843         } else {
1844                 dpaa_intf->cgr_tx = NULL;
1845         }
1846
1847
1848         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1849                 if (dpaa_intf->cgr_tx)
1850                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
1851
1852                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1853                         fman_intf,
1854                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
1855                 if (ret)
1856                         goto free_tx;
1857                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1858         }
1859         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1860
1861 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1862         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1863                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1864         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1865         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1866                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1867         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1868 #endif
1869
1870         DPAA_PMD_DEBUG("All frame queues created");
1871
1872         /* Get the initial configuration for flow control */
1873         dpaa_fc_set_default(dpaa_intf, fman_intf);
1874
1875         /* reset bpool list, initialize bpool dynamically */
1876         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1877                 list_del(&bp->node);
1878                 rte_free(bp);
1879         }
1880
1881         /* Populate ethdev structure */
1882         eth_dev->dev_ops = &dpaa_devops;
1883         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1884         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1885
1886         /* Allocate memory for storing MAC addresses */
1887         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1888                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1889         if (eth_dev->data->mac_addrs == NULL) {
1890                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1891                                                 "store MAC addresses",
1892                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1893                 ret = -ENOMEM;
1894                 goto free_tx;
1895         }
1896
1897         /* copy the primary mac address */
1898         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1899
1900         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1901                 dpaa_device->name,
1902                 fman_intf->mac_addr.addr_bytes[0],
1903                 fman_intf->mac_addr.addr_bytes[1],
1904                 fman_intf->mac_addr.addr_bytes[2],
1905                 fman_intf->mac_addr.addr_bytes[3],
1906                 fman_intf->mac_addr.addr_bytes[4],
1907                 fman_intf->mac_addr.addr_bytes[5]);
1908
1909         if (!fman_intf->is_shared_mac) {
1910                 /* Disable RX mode */
1911                 fman_if_discard_rx_errors(fman_intf);
1912                 fman_if_disable_rx(fman_intf);
1913                 /* Disable promiscuous mode */
1914                 fman_if_promiscuous_disable(fman_intf);
1915                 /* Disable multicast */
1916                 fman_if_reset_mcast_filter_table(fman_intf);
1917                 /* Reset interface statistics */
1918                 fman_if_stats_reset(fman_intf);
1919                 /* Disable SG by default */
1920                 fman_if_set_sg(fman_intf, 0);
1921                 fman_if_set_maxfrm(fman_intf,
1922                                    RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1923         }
1924
1925         return 0;
1926
1927 free_tx:
1928         rte_free(dpaa_intf->tx_queues);
1929         dpaa_intf->tx_queues = NULL;
1930         dpaa_intf->nb_tx_queues = 0;
1931
1932 free_rx:
1933         rte_free(dpaa_intf->cgr_rx);
1934         rte_free(dpaa_intf->cgr_tx);
1935         rte_free(dpaa_intf->rx_queues);
1936         dpaa_intf->rx_queues = NULL;
1937         dpaa_intf->nb_rx_queues = 0;
1938         return ret;
1939 }
1940
1941 static int
1942 dpaa_dev_uninit(struct rte_eth_dev *dev)
1943 {
1944         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1945         int loop;
1946
1947         PMD_INIT_FUNC_TRACE();
1948
1949         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1950                 return -EPERM;
1951
1952         if (!dpaa_intf) {
1953                 DPAA_PMD_WARN("Already closed or not started");
1954                 return -1;
1955         }
1956
1957         /* DPAA FM deconfig */
1958         if (!(default_q || fmc_q)) {
1959                 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
1960                         DPAA_PMD_WARN("DPAA FM deconfig failed\n");
1961         }
1962
1963         dpaa_eth_dev_close(dev);
1964
1965         /* release configuration memory */
1966         if (dpaa_intf->fc_conf)
1967                 rte_free(dpaa_intf->fc_conf);
1968
1969         /* Release RX congestion Groups */
1970         if (dpaa_intf->cgr_rx) {
1971                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1972                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1973
1974                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1975                                          dpaa_intf->nb_rx_queues);
1976         }
1977
1978         rte_free(dpaa_intf->cgr_rx);
1979         dpaa_intf->cgr_rx = NULL;
1980
1981         /* Release TX congestion Groups */
1982         if (dpaa_intf->cgr_tx) {
1983                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
1984                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
1985
1986                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
1987                                          MAX_DPAA_CORES);
1988                 rte_free(dpaa_intf->cgr_tx);
1989                 dpaa_intf->cgr_tx = NULL;
1990         }
1991
1992         rte_free(dpaa_intf->rx_queues);
1993         dpaa_intf->rx_queues = NULL;
1994
1995         rte_free(dpaa_intf->tx_queues);
1996         dpaa_intf->tx_queues = NULL;
1997
1998         dev->dev_ops = NULL;
1999         dev->rx_pkt_burst = NULL;
2000         dev->tx_pkt_burst = NULL;
2001
2002         return 0;
2003 }
2004
2005 static int
2006 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
2007                struct rte_dpaa_device *dpaa_dev)
2008 {
2009         int diag;
2010         int ret;
2011         struct rte_eth_dev *eth_dev;
2012
2013         PMD_INIT_FUNC_TRACE();
2014
2015         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
2016                 RTE_PKTMBUF_HEADROOM) {
2017                 DPAA_PMD_ERR(
2018                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
2019                 RTE_PKTMBUF_HEADROOM,
2020                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
2021
2022                 return -1;
2023         }
2024
2025         /* In case of secondary process, the device is already configured
2026          * and no further action is required, except portal initialization
2027          * and verifying secondary attachment to port name.
2028          */
2029         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2030                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
2031                 if (!eth_dev)
2032                         return -ENOMEM;
2033                 eth_dev->device = &dpaa_dev->device;
2034                 eth_dev->dev_ops = &dpaa_devops;
2035
2036                 ret = dpaa_dev_init_secondary(eth_dev);
2037                 if (ret != 0) {
2038                         RTE_LOG(ERR, PMD, "secondary dev init failed\n");
2039                         return ret;
2040                 }
2041
2042                 rte_eth_dev_probing_finish(eth_dev);
2043                 return 0;
2044         }
2045
2046         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
2047                 if (access("/tmp/fmc.bin", F_OK) == -1) {
2048                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
2049                         default_q = 1;
2050                 }
2051
2052                 if (!(default_q || fmc_q)) {
2053                         if (dpaa_fm_init()) {
2054                                 DPAA_PMD_ERR("FM init failed\n");
2055                                 return -1;
2056                         }
2057                 }
2058
2059                 /* disabling the default push mode for LS1043 */
2060                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
2061                         dpaa_push_mode_max_queue = 0;
2062
2063                 /* if push mode queues to be enabled. Currenly we are allowing
2064                  * only one queue per thread.
2065                  */
2066                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
2067                         dpaa_push_mode_max_queue =
2068                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
2069                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
2070                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
2071                 }
2072
2073                 is_global_init = 1;
2074         }
2075
2076         if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
2077                 ret = rte_dpaa_portal_init((void *)1);
2078                 if (ret) {
2079                         DPAA_PMD_ERR("Unable to initialize portal");
2080                         return ret;
2081                 }
2082         }
2083
2084         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
2085         if (!eth_dev)
2086                 return -ENOMEM;
2087
2088         eth_dev->data->dev_private =
2089                         rte_zmalloc("ethdev private structure",
2090                                         sizeof(struct dpaa_if),
2091                                         RTE_CACHE_LINE_SIZE);
2092         if (!eth_dev->data->dev_private) {
2093                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
2094                 rte_eth_dev_release_port(eth_dev);
2095                 return -ENOMEM;
2096         }
2097
2098         eth_dev->device = &dpaa_dev->device;
2099         dpaa_dev->eth_dev = eth_dev;
2100
2101         qman_ern_register_cb(dpaa_free_mbuf);
2102
2103         if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2104                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2105
2106         /* Invoke PMD device initialization function */
2107         diag = dpaa_dev_init(eth_dev);
2108         if (diag == 0) {
2109                 rte_eth_dev_probing_finish(eth_dev);
2110                 return 0;
2111         }
2112
2113         rte_eth_dev_release_port(eth_dev);
2114         return diag;
2115 }
2116
2117 static int
2118 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2119 {
2120         struct rte_eth_dev *eth_dev;
2121
2122         PMD_INIT_FUNC_TRACE();
2123
2124         eth_dev = dpaa_dev->eth_dev;
2125         dpaa_dev_uninit(eth_dev);
2126
2127         rte_eth_dev_release_port(eth_dev);
2128
2129         return 0;
2130 }
2131
2132 static void __attribute__((destructor(102))) dpaa_finish(void)
2133 {
2134         /* For secondary, primary will do all the cleanup */
2135         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2136                 return;
2137
2138         if (!(default_q || fmc_q)) {
2139                 unsigned int i;
2140
2141                 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2142                         if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2143                                 struct rte_eth_dev *dev = &rte_eth_devices[i];
2144                                 struct dpaa_if *dpaa_intf =
2145                                         dev->data->dev_private;
2146                                 struct fman_if *fif =
2147                                         dev->process_private;
2148                                 if (dpaa_intf->port_handle)
2149                                         if (dpaa_fm_deconfig(dpaa_intf, fif))
2150                                                 DPAA_PMD_WARN("DPAA FM "
2151                                                         "deconfig failed\n");
2152                                 if (fif->num_profiles) {
2153                                         if (dpaa_port_vsp_cleanup(dpaa_intf,
2154                                                                   fif))
2155                                                 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n");
2156                                 }
2157                         }
2158                 }
2159                 if (is_global_init)
2160                         if (dpaa_fm_term())
2161                                 DPAA_PMD_WARN("DPAA FM term failed\n");
2162
2163                 is_global_init = 0;
2164
2165                 DPAA_PMD_INFO("DPAA fman cleaned up");
2166         }
2167 }
2168
2169 static struct rte_dpaa_driver rte_dpaa_pmd = {
2170         .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2171         .drv_type = FSL_DPAA_ETH,
2172         .probe = rte_dpaa_probe,
2173         .remove = rte_dpaa_remove,
2174 };
2175
2176 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2177 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);