1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2017-2020 NXP
15 #include <sys/types.h>
16 #include <sys/syscall.h>
18 #include <rte_string_fns.h>
19 #include <rte_byteorder.h>
20 #include <rte_common.h>
21 #include <rte_interrupts.h>
23 #include <rte_debug.h>
25 #include <rte_atomic.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_memory.h>
28 #include <rte_tailq.h>
30 #include <rte_alarm.h>
31 #include <rte_ether.h>
32 #include <ethdev_driver.h>
33 #include <rte_malloc.h>
36 #include <rte_dpaa_bus.h>
37 #include <rte_dpaa_logs.h>
38 #include <dpaa_mempool.h>
40 #include <dpaa_ethdev.h>
41 #include <dpaa_rxtx.h>
42 #include <dpaa_flow.h>
43 #include <rte_pmd_dpaa.h>
50 #include <fmlib/fm_ext.h>
52 #define CHECK_INTERVAL 100 /* 100ms */
53 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */
55 /* Supported Rx offloads */
56 static uint64_t dev_rx_offloads_sup =
57 DEV_RX_OFFLOAD_JUMBO_FRAME |
58 DEV_RX_OFFLOAD_SCATTER;
60 /* Rx offloads which cannot be disabled */
61 static uint64_t dev_rx_offloads_nodis =
62 DEV_RX_OFFLOAD_IPV4_CKSUM |
63 DEV_RX_OFFLOAD_UDP_CKSUM |
64 DEV_RX_OFFLOAD_TCP_CKSUM |
65 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
66 DEV_RX_OFFLOAD_RSS_HASH;
68 /* Supported Tx offloads */
69 static uint64_t dev_tx_offloads_sup =
70 DEV_TX_OFFLOAD_MT_LOCKFREE |
71 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
73 /* Tx offloads which cannot be disabled */
74 static uint64_t dev_tx_offloads_nodis =
75 DEV_TX_OFFLOAD_IPV4_CKSUM |
76 DEV_TX_OFFLOAD_UDP_CKSUM |
77 DEV_TX_OFFLOAD_TCP_CKSUM |
78 DEV_TX_OFFLOAD_SCTP_CKSUM |
79 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
80 DEV_TX_OFFLOAD_MULTI_SEGS;
82 /* Keep track of whether QMAN and BMAN have been globally initialized */
83 static int is_global_init;
84 static int fmc_q = 1; /* Indicates the use of static fmc for distribution */
85 static int default_q; /* use default queue - FMC is not executed*/
86 /* At present we only allow up to 4 push mode queues as default - as each of
87 * this queue need dedicated portal and we are short of portals.
89 #define DPAA_MAX_PUSH_MODE_QUEUE 8
90 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
92 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
93 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
96 /* Per RX FQ Taildrop in frame count */
97 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
99 /* Per TX FQ Taildrop in frame count, disabled by default */
100 static unsigned int td_tx_threshold;
102 struct rte_dpaa_xstats_name_off {
103 char name[RTE_ETH_XSTATS_NAME_SIZE];
107 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
109 offsetof(struct dpaa_if_stats, raln)},
111 offsetof(struct dpaa_if_stats, rxpf)},
113 offsetof(struct dpaa_if_stats, rfcs)},
115 offsetof(struct dpaa_if_stats, rvlan)},
117 offsetof(struct dpaa_if_stats, rerr)},
119 offsetof(struct dpaa_if_stats, rdrp)},
121 offsetof(struct dpaa_if_stats, rund)},
123 offsetof(struct dpaa_if_stats, rovr)},
125 offsetof(struct dpaa_if_stats, rfrg)},
127 offsetof(struct dpaa_if_stats, txpf)},
129 offsetof(struct dpaa_if_stats, terr)},
131 offsetof(struct dpaa_if_stats, tvlan)},
133 offsetof(struct dpaa_if_stats, tund)},
136 static struct rte_dpaa_driver rte_dpaa_pmd;
139 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
141 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
142 int wait_to_complete __rte_unused);
144 static void dpaa_interrupt_handler(void *param);
147 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
149 memset(opts, 0, sizeof(struct qm_mcc_initfq));
150 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
151 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
152 QM_FQCTRL_PREFERINCACHE;
153 opts->fqd.context_a.stashing.exclusive = 0;
154 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
155 opts->fqd.context_a.stashing.annotation_cl =
156 DPAA_IF_RX_ANNOTATION_STASH;
157 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
158 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
162 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
164 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
166 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
168 PMD_INIT_FUNC_TRACE();
170 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
173 * Refuse mtu that requires the support of scattered packets
174 * when this feature has not been enabled before.
176 if (dev->data->min_rx_buf_size &&
177 !dev->data->scattered_rx && frame_size > buffsz) {
178 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
182 /* check <seg size> * <max_seg> >= max_frame */
183 if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
184 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
185 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
186 buffsz * DPAA_SGT_MAX_ENTRIES);
190 if (frame_size > DPAA_ETH_MAX_LEN)
191 dev->data->dev_conf.rxmode.offloads |=
192 DEV_RX_OFFLOAD_JUMBO_FRAME;
194 dev->data->dev_conf.rxmode.offloads &=
195 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
197 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
199 fman_if_set_maxfrm(dev->process_private, frame_size);
205 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
207 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
208 uint64_t rx_offloads = eth_conf->rxmode.offloads;
209 uint64_t tx_offloads = eth_conf->txmode.offloads;
210 struct rte_device *rdev = dev->device;
211 struct rte_eth_link *link = &dev->data->dev_link;
212 struct rte_dpaa_device *dpaa_dev;
213 struct fman_if *fif = dev->process_private;
214 struct __fman_if *__fif;
215 struct rte_intr_handle *intr_handle;
219 PMD_INIT_FUNC_TRACE();
221 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
222 intr_handle = &dpaa_dev->intr_handle;
223 __fif = container_of(fif, struct __fman_if, __if);
225 /* Rx offloads which are enabled by default */
226 if (dev_rx_offloads_nodis & ~rx_offloads) {
228 "Some of rx offloads enabled by default - requested 0x%" PRIx64
229 " fixed are 0x%" PRIx64,
230 rx_offloads, dev_rx_offloads_nodis);
233 /* Tx offloads which are enabled by default */
234 if (dev_tx_offloads_nodis & ~tx_offloads) {
236 "Some of tx offloads enabled by default - requested 0x%" PRIx64
237 " fixed are 0x%" PRIx64,
238 tx_offloads, dev_tx_offloads_nodis);
241 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
244 DPAA_PMD_DEBUG("enabling jumbo");
246 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
248 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
250 DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
252 dev->data->dev_conf.rxmode.max_rx_pkt_len,
253 DPAA_MAX_RX_PKT_LEN);
254 max_len = DPAA_MAX_RX_PKT_LEN;
257 fman_if_set_maxfrm(dev->process_private, max_len);
258 dev->data->mtu = max_len
259 - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
262 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
263 DPAA_PMD_DEBUG("enabling scatter mode");
264 fman_if_set_sg(dev->process_private, 1);
265 dev->data->scattered_rx = 1;
268 if (!(default_q || fmc_q)) {
269 if (dpaa_fm_config(dev,
270 eth_conf->rx_adv_conf.rss_conf.rss_hf)) {
271 dpaa_write_fm_config_to_file();
272 DPAA_PMD_ERR("FM port configuration: Failed\n");
275 dpaa_write_fm_config_to_file();
278 /* if the interrupts were configured on this devices*/
279 if (intr_handle && intr_handle->fd) {
280 if (dev->data->dev_conf.intr_conf.lsc != 0)
281 rte_intr_callback_register(intr_handle,
282 dpaa_interrupt_handler,
285 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
287 if (dev->data->dev_conf.intr_conf.lsc != 0) {
288 rte_intr_callback_unregister(intr_handle,
289 dpaa_interrupt_handler,
292 printf("Failed to enable interrupt: Not Supported\n");
294 printf("Failed to enable interrupt\n");
296 dev->data->dev_conf.intr_conf.lsc = 0;
297 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
301 /* Wait for link status to get updated */
302 if (!link->link_status)
305 /* Configure link only if link is UP*/
306 if (link->link_status) {
307 if (eth_conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
308 /* Start autoneg only if link is not in autoneg mode */
309 if (!link->link_autoneg)
310 dpaa_restart_link_autoneg(__fif->node_name);
311 } else if (eth_conf->link_speeds & ETH_LINK_SPEED_FIXED) {
312 switch (eth_conf->link_speeds & ~ETH_LINK_SPEED_FIXED) {
313 case ETH_LINK_SPEED_10M_HD:
314 speed = ETH_SPEED_NUM_10M;
315 duplex = ETH_LINK_HALF_DUPLEX;
317 case ETH_LINK_SPEED_10M:
318 speed = ETH_SPEED_NUM_10M;
319 duplex = ETH_LINK_FULL_DUPLEX;
321 case ETH_LINK_SPEED_100M_HD:
322 speed = ETH_SPEED_NUM_100M;
323 duplex = ETH_LINK_HALF_DUPLEX;
325 case ETH_LINK_SPEED_100M:
326 speed = ETH_SPEED_NUM_100M;
327 duplex = ETH_LINK_FULL_DUPLEX;
329 case ETH_LINK_SPEED_1G:
330 speed = ETH_SPEED_NUM_1G;
331 duplex = ETH_LINK_FULL_DUPLEX;
333 case ETH_LINK_SPEED_2_5G:
334 speed = ETH_SPEED_NUM_2_5G;
335 duplex = ETH_LINK_FULL_DUPLEX;
337 case ETH_LINK_SPEED_10G:
338 speed = ETH_SPEED_NUM_10G;
339 duplex = ETH_LINK_FULL_DUPLEX;
342 speed = ETH_SPEED_NUM_NONE;
343 duplex = ETH_LINK_FULL_DUPLEX;
347 dpaa_update_link_speed(__fif->node_name, speed, duplex);
349 /* Manual autoneg - custom advertisement speed. */
350 printf("Custom Advertisement speeds not supported\n");
357 static const uint32_t *
358 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
360 static const uint32_t ptypes[] = {
362 RTE_PTYPE_L2_ETHER_VLAN,
363 RTE_PTYPE_L2_ETHER_ARP,
364 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
365 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
375 PMD_INIT_FUNC_TRACE();
377 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
382 static void dpaa_interrupt_handler(void *param)
384 struct rte_eth_dev *dev = param;
385 struct rte_device *rdev = dev->device;
386 struct rte_dpaa_device *dpaa_dev;
387 struct rte_intr_handle *intr_handle;
391 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
392 intr_handle = &dpaa_dev->intr_handle;
394 bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
396 DPAA_PMD_ERR("Error reading eventfd\n");
397 dpaa_eth_link_update(dev, 0);
398 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
401 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
403 struct dpaa_if *dpaa_intf = dev->data->dev_private;
405 PMD_INIT_FUNC_TRACE();
407 if (!(default_q || fmc_q))
408 dpaa_write_fm_config_to_file();
410 /* Change tx callback to the real one */
411 if (dpaa_intf->cgr_tx)
412 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
414 dev->tx_pkt_burst = dpaa_eth_queue_tx;
416 fman_if_enable_rx(dev->process_private);
421 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev)
423 struct fman_if *fif = dev->process_private;
425 PMD_INIT_FUNC_TRACE();
426 dev->data->dev_started = 0;
428 if (!fif->is_shared_mac)
429 fman_if_disable_rx(fif);
430 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
435 static int dpaa_eth_dev_close(struct rte_eth_dev *dev)
437 struct fman_if *fif = dev->process_private;
438 struct __fman_if *__fif;
439 struct rte_device *rdev = dev->device;
440 struct rte_dpaa_device *dpaa_dev;
441 struct rte_intr_handle *intr_handle;
442 struct rte_eth_link *link = &dev->data->dev_link;
443 struct dpaa_if *dpaa_intf = dev->data->dev_private;
447 PMD_INIT_FUNC_TRACE();
449 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
453 DPAA_PMD_WARN("Already closed or not started");
457 /* DPAA FM deconfig */
458 if (!(default_q || fmc_q)) {
459 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
460 DPAA_PMD_WARN("DPAA FM deconfig failed\n");
463 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
464 intr_handle = &dpaa_dev->intr_handle;
465 __fif = container_of(fif, struct __fman_if, __if);
467 ret = dpaa_eth_dev_stop(dev);
469 /* Reset link to autoneg */
470 if (link->link_status && !link->link_autoneg)
471 dpaa_restart_link_autoneg(__fif->node_name);
473 if (intr_handle && intr_handle->fd &&
474 dev->data->dev_conf.intr_conf.lsc != 0) {
475 dpaa_intr_disable(__fif->node_name);
476 rte_intr_callback_unregister(intr_handle,
477 dpaa_interrupt_handler,
481 /* release configuration memory */
482 if (dpaa_intf->fc_conf)
483 rte_free(dpaa_intf->fc_conf);
485 /* Release RX congestion Groups */
486 if (dpaa_intf->cgr_rx) {
487 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
488 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
491 rte_free(dpaa_intf->cgr_rx);
492 dpaa_intf->cgr_rx = NULL;
493 /* Release TX congestion Groups */
494 if (dpaa_intf->cgr_tx) {
495 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
496 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
497 rte_free(dpaa_intf->cgr_tx);
498 dpaa_intf->cgr_tx = NULL;
501 rte_free(dpaa_intf->rx_queues);
502 dpaa_intf->rx_queues = NULL;
504 rte_free(dpaa_intf->tx_queues);
505 dpaa_intf->tx_queues = NULL;
511 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
516 FILE *svr_file = NULL;
517 unsigned int svr_ver = 0;
519 PMD_INIT_FUNC_TRACE();
521 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
523 DPAA_PMD_ERR("Unable to open SoC device");
524 return -ENOTSUP; /* Not supported on this infra */
526 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
527 dpaa_svr_family = svr_ver & SVR_MASK;
529 DPAA_PMD_ERR("Unable to read SoC device");
533 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
534 svr_ver, fman_ip_rev);
535 ret += 1; /* add the size of '\0' */
537 if (fw_size < (uint32_t)ret)
543 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
544 struct rte_eth_dev_info *dev_info)
546 struct dpaa_if *dpaa_intf = dev->data->dev_private;
547 struct fman_if *fif = dev->process_private;
549 DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
551 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
552 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
553 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
554 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
555 dev_info->max_hash_mac_addrs = 0;
556 dev_info->max_vfs = 0;
557 dev_info->max_vmdq_pools = ETH_16_POOLS;
558 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
560 if (fif->mac_type == fman_mac_1g) {
561 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
563 | ETH_LINK_SPEED_100M_HD
564 | ETH_LINK_SPEED_100M
566 } else if (fif->mac_type == fman_mac_2_5g) {
567 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
569 | ETH_LINK_SPEED_100M_HD
570 | ETH_LINK_SPEED_100M
572 | ETH_LINK_SPEED_2_5G;
573 } else if (fif->mac_type == fman_mac_10g) {
574 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
576 | ETH_LINK_SPEED_100M_HD
577 | ETH_LINK_SPEED_100M
579 | ETH_LINK_SPEED_2_5G
580 | ETH_LINK_SPEED_10G;
582 DPAA_PMD_ERR("invalid link_speed: %s, %d",
583 dpaa_intf->name, fif->mac_type);
587 dev_info->rx_offload_capa = dev_rx_offloads_sup |
588 dev_rx_offloads_nodis;
589 dev_info->tx_offload_capa = dev_tx_offloads_sup |
590 dev_tx_offloads_nodis;
591 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
592 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
593 dev_info->default_rxportconf.nb_queues = 1;
594 dev_info->default_txportconf.nb_queues = 1;
595 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
596 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
602 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
603 __rte_unused uint16_t queue_id,
604 struct rte_eth_burst_mode *mode)
606 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
609 const struct burst_info {
612 } rx_offload_map[] = {
613 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
614 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"},
615 {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
616 {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
617 {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
618 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
619 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}
622 /* Update Rx offload info */
623 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
624 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
625 snprintf(mode->info, sizeof(mode->info), "%s",
626 rx_offload_map[i].output);
635 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
636 __rte_unused uint16_t queue_id,
637 struct rte_eth_burst_mode *mode)
639 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
642 const struct burst_info {
645 } tx_offload_map[] = {
646 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
647 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
648 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
649 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
650 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
651 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
652 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
653 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
656 /* Update Tx offload info */
657 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
658 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
659 snprintf(mode->info, sizeof(mode->info), "%s",
660 tx_offload_map[i].output);
668 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
669 int wait_to_complete)
671 struct dpaa_if *dpaa_intf = dev->data->dev_private;
672 struct rte_eth_link *link = &dev->data->dev_link;
673 struct fman_if *fif = dev->process_private;
674 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
675 int ret, ioctl_version;
678 PMD_INIT_FUNC_TRACE();
680 ioctl_version = dpaa_get_ioctl_version_number();
682 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
683 for (count = 0; count <= MAX_REPEAT_TIME; count++) {
684 ret = dpaa_get_link_status(__fif->node_name, link);
687 if (link->link_status == ETH_LINK_DOWN &&
689 rte_delay_ms(CHECK_INTERVAL);
694 link->link_status = dpaa_intf->valid;
697 if (ioctl_version < 2) {
698 link->link_duplex = ETH_LINK_FULL_DUPLEX;
699 link->link_autoneg = ETH_LINK_AUTONEG;
701 if (fif->mac_type == fman_mac_1g)
702 link->link_speed = ETH_SPEED_NUM_1G;
703 else if (fif->mac_type == fman_mac_2_5g)
704 link->link_speed = ETH_SPEED_NUM_2_5G;
705 else if (fif->mac_type == fman_mac_10g)
706 link->link_speed = ETH_SPEED_NUM_10G;
708 DPAA_PMD_ERR("invalid link_speed: %s, %d",
709 dpaa_intf->name, fif->mac_type);
712 DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
713 link->link_status ? "Up" : "Down");
717 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
718 struct rte_eth_stats *stats)
720 PMD_INIT_FUNC_TRACE();
722 fman_if_stats_get(dev->process_private, stats);
726 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
728 PMD_INIT_FUNC_TRACE();
730 fman_if_stats_reset(dev->process_private);
736 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
739 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
740 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
748 fman_if_stats_get_all(dev->process_private, values,
749 sizeof(struct dpaa_if_stats) / 8);
751 for (i = 0; i < num; i++) {
753 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
759 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
760 struct rte_eth_xstat_name *xstats_names,
763 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
765 if (limit < stat_cnt)
768 if (xstats_names != NULL)
769 for (i = 0; i < stat_cnt; i++)
770 strlcpy(xstats_names[i].name,
771 dpaa_xstats_strings[i].name,
772 sizeof(xstats_names[i].name));
778 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
779 uint64_t *values, unsigned int n)
781 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
782 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
791 fman_if_stats_get_all(dev->process_private, values_copy,
792 sizeof(struct dpaa_if_stats) / 8);
794 for (i = 0; i < stat_cnt; i++)
796 values_copy[dpaa_xstats_strings[i].offset / 8];
801 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
803 for (i = 0; i < n; i++) {
804 if (ids[i] >= stat_cnt) {
805 DPAA_PMD_ERR("id value isn't valid");
808 values[i] = values_copy[ids[i]];
814 dpaa_xstats_get_names_by_id(
815 struct rte_eth_dev *dev,
816 struct rte_eth_xstat_name *xstats_names,
820 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
821 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
824 return dpaa_xstats_get_names(dev, xstats_names, limit);
826 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
828 for (i = 0; i < limit; i++) {
829 if (ids[i] >= stat_cnt) {
830 DPAA_PMD_ERR("id value isn't valid");
833 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
838 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
840 PMD_INIT_FUNC_TRACE();
842 fman_if_promiscuous_enable(dev->process_private);
847 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
849 PMD_INIT_FUNC_TRACE();
851 fman_if_promiscuous_disable(dev->process_private);
856 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
858 PMD_INIT_FUNC_TRACE();
860 fman_if_set_mcast_filter_table(dev->process_private);
865 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
867 PMD_INIT_FUNC_TRACE();
869 fman_if_reset_mcast_filter_table(dev->process_private);
874 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev)
876 struct dpaa_if *dpaa_intf = dev->data->dev_private;
877 struct fman_if_ic_params icp;
881 memset(&icp, 0, sizeof(icp));
882 /* set ICEOF for to the default value , which is 0*/
883 icp.iciof = DEFAULT_ICIOF;
884 icp.iceof = DEFAULT_RX_ICEOF;
885 icp.icsz = DEFAULT_ICSZ;
886 fman_if_set_ic_params(dev->process_private, &icp);
888 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
889 fman_if_set_fdoff(dev->process_private, fd_offset);
891 /* Buffer pool size should be equal to Dataroom Size*/
892 bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp);
894 fman_if_set_bp(dev->process_private,
895 dpaa_intf->bp_info->mp->size,
896 dpaa_intf->bp_info->bpid, bp_size);
899 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev,
900 int8_t vsp_id, uint32_t bpid)
902 struct dpaa_if *dpaa_intf = dev->data->dev_private;
903 struct fman_if *fif = dev->process_private;
905 if (fif->num_profiles) {
907 vsp_id = fif->base_profile_id;
913 if (dpaa_intf->vsp_bpid[vsp_id] &&
914 bpid != dpaa_intf->vsp_bpid[vsp_id]) {
915 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP");
924 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
926 unsigned int socket_id __rte_unused,
927 const struct rte_eth_rxconf *rx_conf,
928 struct rte_mempool *mp)
930 struct dpaa_if *dpaa_intf = dev->data->dev_private;
931 struct fman_if *fif = dev->process_private;
932 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
933 struct qm_mcc_initfq opts = {0};
936 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
938 PMD_INIT_FUNC_TRACE();
940 if (queue_idx >= dev->data->nb_rx_queues) {
941 rte_errno = EOVERFLOW;
942 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
943 (void *)dev, queue_idx, dev->data->nb_rx_queues);
947 /* Rx deferred start is not supported */
948 if (rx_conf->rx_deferred_start) {
949 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
952 rxq->nb_desc = UINT16_MAX;
953 rxq->offloads = rx_conf->offloads;
955 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
956 queue_idx, rxq->fqid);
958 if (!fif->num_profiles) {
959 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
960 dpaa_intf->bp_info->mp != mp) {
961 DPAA_PMD_WARN("Multiple pools on same interface not"
966 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id,
967 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) {
972 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
973 dpaa_intf->bp_info->mp != mp) {
974 DPAA_PMD_WARN("Multiple pools on same interface not supported");
978 /* Max packet can fit in single buffer */
979 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
981 } else if (dev->data->dev_conf.rxmode.offloads &
982 DEV_RX_OFFLOAD_SCATTER) {
983 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
984 buffsz * DPAA_SGT_MAX_ENTRIES) {
985 DPAA_PMD_ERR("max RxPkt size %d too big to fit "
987 dev->data->dev_conf.rxmode.max_rx_pkt_len,
988 buffsz * DPAA_SGT_MAX_ENTRIES);
989 rte_errno = EOVERFLOW;
993 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
994 " larger than a single mbuf (%u) and scattered"
995 " mode has not been requested",
996 dev->data->dev_conf.rxmode.max_rx_pkt_len,
997 buffsz - RTE_PKTMBUF_HEADROOM);
1000 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
1002 /* For shared interface, it's done in kernel, skip.*/
1003 if (!fif->is_shared_mac)
1004 dpaa_fman_if_pool_setup(dev);
1006 if (fif->num_profiles) {
1007 int8_t vsp_id = rxq->vsp_id;
1010 ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id,
1011 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid,
1014 DPAA_PMD_ERR("dpaa_port_vsp_update failed");
1018 DPAA_PMD_INFO("Base profile is associated to"
1019 " RXQ fqid:%d\r\n", rxq->fqid);
1020 if (fif->is_shared_mac) {
1021 DPAA_PMD_ERR("Fatal: Base profile is associated"
1022 " to shared interface on DPDK.");
1025 dpaa_intf->vsp_bpid[fif->base_profile_id] =
1026 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1029 dpaa_intf->vsp_bpid[0] =
1030 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1033 dpaa_intf->valid = 1;
1034 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
1035 fman_if_get_sg_enable(fif),
1036 dev->data->dev_conf.rxmode.max_rx_pkt_len);
1037 /* checking if push mode only, no error check for now */
1038 if (!rxq->is_static &&
1039 dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
1040 struct qman_portal *qp;
1043 dpaa_push_queue_idx++;
1044 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
1045 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
1046 QM_FQCTRL_CTXASTASHING |
1047 QM_FQCTRL_PREFERINCACHE;
1048 opts.fqd.context_a.stashing.exclusive = 0;
1049 /* In muticore scenario stashing becomes a bottleneck on LS1046.
1050 * So do not enable stashing in this case
1052 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
1053 opts.fqd.context_a.stashing.annotation_cl =
1054 DPAA_IF_RX_ANNOTATION_STASH;
1055 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
1056 opts.fqd.context_a.stashing.context_cl =
1057 DPAA_IF_RX_CONTEXT_STASH;
1059 /*Create a channel and associate given queue with the channel*/
1060 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
1061 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1062 opts.fqd.dest.channel = rxq->ch_id;
1063 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
1064 flags = QMAN_INITFQ_FLAG_SCHED;
1066 /* Configure tail drop */
1067 if (dpaa_intf->cgr_rx) {
1068 opts.we_mask |= QM_INITFQ_WE_CGID;
1069 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
1070 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1072 ret = qman_init_fq(rxq, flags, &opts);
1074 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
1075 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1078 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
1079 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
1081 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
1082 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
1085 rxq->is_static = true;
1087 /* Allocate qman specific portals */
1088 qp = fsl_qman_fq_portal_create(&q_fd);
1090 DPAA_PMD_ERR("Unable to alloc fq portal");
1095 /* Set up the device interrupt handler */
1096 if (!dev->intr_handle) {
1097 struct rte_dpaa_device *dpaa_dev;
1098 struct rte_device *rdev = dev->device;
1100 dpaa_dev = container_of(rdev, struct rte_dpaa_device,
1102 dev->intr_handle = &dpaa_dev->intr_handle;
1103 dev->intr_handle->intr_vec = rte_zmalloc(NULL,
1104 dpaa_push_mode_max_queue, 0);
1105 if (!dev->intr_handle->intr_vec) {
1106 DPAA_PMD_ERR("intr_vec alloc failed");
1109 dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
1110 dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
1113 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
1114 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
1115 dev->intr_handle->efds[queue_idx] = q_fd;
1118 rxq->bp_array = rte_dpaa_bpid_info;
1119 dev->data->rx_queues[queue_idx] = rxq;
1121 /* configure the CGR size as per the desc size */
1122 if (dpaa_intf->cgr_rx) {
1123 struct qm_mcc_initcgr cgr_opts = {0};
1125 rxq->nb_desc = nb_desc;
1126 /* Enable tail drop with cgr on this queue */
1127 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
1128 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
1131 "rx taildrop modify fail on fqid %d (ret=%d)",
1135 /* Enable main queue to receive error packets also by default */
1136 fman_if_set_err_fqid(fif, rxq->fqid);
1141 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
1142 int eth_rx_queue_id,
1144 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1148 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1149 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1150 struct qm_mcc_initfq opts = {0};
1152 if (dpaa_push_mode_max_queue)
1153 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
1154 "PUSH mode already enabled for first %d queues.\n"
1155 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
1156 dpaa_push_mode_max_queue);
1158 dpaa_poll_queue_default_config(&opts);
1160 switch (queue_conf->ev.sched_type) {
1161 case RTE_SCHED_TYPE_ATOMIC:
1162 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
1163 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
1164 * configuration with HOLD_ACTIVE setting
1166 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
1167 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
1169 case RTE_SCHED_TYPE_ORDERED:
1170 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
1173 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
1174 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
1178 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1179 opts.fqd.dest.channel = ch_id;
1180 opts.fqd.dest.wq = queue_conf->ev.priority;
1182 if (dpaa_intf->cgr_rx) {
1183 opts.we_mask |= QM_INITFQ_WE_CGID;
1184 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1185 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1188 flags = QMAN_INITFQ_FLAG_SCHED;
1190 ret = qman_init_fq(rxq, flags, &opts);
1192 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
1193 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1197 /* copy configuration which needs to be filled during dequeue */
1198 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
1199 dev->data->rx_queues[eth_rx_queue_id] = rxq;
1205 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1206 int eth_rx_queue_id)
1208 struct qm_mcc_initfq opts;
1211 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1212 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1214 dpaa_poll_queue_default_config(&opts);
1216 if (dpaa_intf->cgr_rx) {
1217 opts.we_mask |= QM_INITFQ_WE_CGID;
1218 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1219 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1222 ret = qman_init_fq(rxq, flags, &opts);
1224 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1228 rxq->cb.dqrr_dpdk_cb = NULL;
1229 dev->data->rx_queues[eth_rx_queue_id] = NULL;
1235 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
1237 PMD_INIT_FUNC_TRACE();
1241 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1242 uint16_t nb_desc __rte_unused,
1243 unsigned int socket_id __rte_unused,
1244 const struct rte_eth_txconf *tx_conf)
1246 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1247 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1249 PMD_INIT_FUNC_TRACE();
1251 /* Tx deferred start is not supported */
1252 if (tx_conf->tx_deferred_start) {
1253 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1256 txq->nb_desc = UINT16_MAX;
1257 txq->offloads = tx_conf->offloads;
1259 if (queue_idx >= dev->data->nb_tx_queues) {
1260 rte_errno = EOVERFLOW;
1261 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1262 (void *)dev, queue_idx, dev->data->nb_tx_queues);
1266 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1267 queue_idx, txq->fqid);
1268 dev->data->tx_queues[queue_idx] = txq;
1273 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
1275 PMD_INIT_FUNC_TRACE();
1279 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1281 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1282 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
1285 PMD_INIT_FUNC_TRACE();
1287 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1288 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
1289 rx_queue_id, frm_cnt);
1294 static int dpaa_link_down(struct rte_eth_dev *dev)
1296 struct fman_if *fif = dev->process_private;
1297 struct __fman_if *__fif;
1299 PMD_INIT_FUNC_TRACE();
1301 __fif = container_of(fif, struct __fman_if, __if);
1303 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1304 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN);
1306 return dpaa_eth_dev_stop(dev);
1310 static int dpaa_link_up(struct rte_eth_dev *dev)
1312 struct fman_if *fif = dev->process_private;
1313 struct __fman_if *__fif;
1315 PMD_INIT_FUNC_TRACE();
1317 __fif = container_of(fif, struct __fman_if, __if);
1319 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1320 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP);
1322 dpaa_eth_dev_start(dev);
1327 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1328 struct rte_eth_fc_conf *fc_conf)
1330 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1331 struct rte_eth_fc_conf *net_fc;
1333 PMD_INIT_FUNC_TRACE();
1335 if (!(dpaa_intf->fc_conf)) {
1336 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1337 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1338 if (!dpaa_intf->fc_conf) {
1339 DPAA_PMD_ERR("unable to save flow control info");
1343 net_fc = dpaa_intf->fc_conf;
1345 if (fc_conf->high_water < fc_conf->low_water) {
1346 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1350 if (fc_conf->mode == RTE_FC_NONE) {
1352 } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1353 fc_conf->mode == RTE_FC_FULL) {
1354 fman_if_set_fc_threshold(dev->process_private,
1355 fc_conf->high_water,
1357 dpaa_intf->bp_info->bpid);
1358 if (fc_conf->pause_time)
1359 fman_if_set_fc_quanta(dev->process_private,
1360 fc_conf->pause_time);
1363 /* Save the information in dpaa device */
1364 net_fc->pause_time = fc_conf->pause_time;
1365 net_fc->high_water = fc_conf->high_water;
1366 net_fc->low_water = fc_conf->low_water;
1367 net_fc->send_xon = fc_conf->send_xon;
1368 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1369 net_fc->mode = fc_conf->mode;
1370 net_fc->autoneg = fc_conf->autoneg;
1376 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1377 struct rte_eth_fc_conf *fc_conf)
1379 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1380 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1383 PMD_INIT_FUNC_TRACE();
1386 fc_conf->pause_time = net_fc->pause_time;
1387 fc_conf->high_water = net_fc->high_water;
1388 fc_conf->low_water = net_fc->low_water;
1389 fc_conf->send_xon = net_fc->send_xon;
1390 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1391 fc_conf->mode = net_fc->mode;
1392 fc_conf->autoneg = net_fc->autoneg;
1395 ret = fman_if_get_fc_threshold(dev->process_private);
1397 fc_conf->mode = RTE_FC_TX_PAUSE;
1398 fc_conf->pause_time =
1399 fman_if_get_fc_quanta(dev->process_private);
1401 fc_conf->mode = RTE_FC_NONE;
1408 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1409 struct rte_ether_addr *addr,
1411 __rte_unused uint32_t pool)
1415 PMD_INIT_FUNC_TRACE();
1417 ret = fman_if_add_mac_addr(dev->process_private,
1418 addr->addr_bytes, index);
1421 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1426 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1429 PMD_INIT_FUNC_TRACE();
1431 fman_if_clear_mac_addr(dev->process_private, index);
1435 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1436 struct rte_ether_addr *addr)
1440 PMD_INIT_FUNC_TRACE();
1442 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1444 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1450 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev,
1451 struct rte_eth_rss_conf *rss_conf)
1453 struct rte_eth_dev_data *data = dev->data;
1454 struct rte_eth_conf *eth_conf = &data->dev_conf;
1456 PMD_INIT_FUNC_TRACE();
1458 if (!(default_q || fmc_q)) {
1459 if (dpaa_fm_config(dev, rss_conf->rss_hf)) {
1460 DPAA_PMD_ERR("FM port configuration: Failed\n");
1463 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1465 DPAA_PMD_ERR("Function not supported\n");
1472 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1473 struct rte_eth_rss_conf *rss_conf)
1475 struct rte_eth_dev_data *data = dev->data;
1476 struct rte_eth_conf *eth_conf = &data->dev_conf;
1478 /* dpaa does not support rss_key, so length should be 0*/
1479 rss_conf->rss_key_len = 0;
1480 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
1484 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1487 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1488 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1490 if (!rxq->is_static)
1493 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1496 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1499 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1500 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1504 if (!rxq->is_static)
1507 qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1509 temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1510 if (temp1 != sizeof(temp))
1511 DPAA_PMD_ERR("irq read error");
1513 qman_fq_portal_thread_irq(rxq->qp);
1519 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1520 struct rte_eth_rxq_info *qinfo)
1522 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1523 struct qman_fq *rxq;
1526 rxq = dev->data->rx_queues[queue_id];
1528 qinfo->mp = dpaa_intf->bp_info->mp;
1529 qinfo->scattered_rx = dev->data->scattered_rx;
1530 qinfo->nb_desc = rxq->nb_desc;
1532 /* Report the HW Rx buffer length to user */
1533 ret = fman_if_get_maxfrm(dev->process_private);
1535 qinfo->rx_buf_size = ret;
1537 qinfo->conf.rx_free_thresh = 1;
1538 qinfo->conf.rx_drop_en = 1;
1539 qinfo->conf.rx_deferred_start = 0;
1540 qinfo->conf.offloads = rxq->offloads;
1544 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1545 struct rte_eth_txq_info *qinfo)
1547 struct qman_fq *txq;
1549 txq = dev->data->tx_queues[queue_id];
1551 qinfo->nb_desc = txq->nb_desc;
1552 qinfo->conf.tx_thresh.pthresh = 0;
1553 qinfo->conf.tx_thresh.hthresh = 0;
1554 qinfo->conf.tx_thresh.wthresh = 0;
1556 qinfo->conf.tx_free_thresh = 0;
1557 qinfo->conf.tx_rs_thresh = 0;
1558 qinfo->conf.offloads = txq->offloads;
1559 qinfo->conf.tx_deferred_start = 0;
1562 static struct eth_dev_ops dpaa_devops = {
1563 .dev_configure = dpaa_eth_dev_configure,
1564 .dev_start = dpaa_eth_dev_start,
1565 .dev_stop = dpaa_eth_dev_stop,
1566 .dev_close = dpaa_eth_dev_close,
1567 .dev_infos_get = dpaa_eth_dev_info,
1568 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1570 .rx_queue_setup = dpaa_eth_rx_queue_setup,
1571 .tx_queue_setup = dpaa_eth_tx_queue_setup,
1572 .rx_queue_release = dpaa_eth_rx_queue_release,
1573 .tx_queue_release = dpaa_eth_tx_queue_release,
1574 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get,
1575 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get,
1576 .rxq_info_get = dpaa_rxq_info_get,
1577 .txq_info_get = dpaa_txq_info_get,
1579 .flow_ctrl_get = dpaa_flow_ctrl_get,
1580 .flow_ctrl_set = dpaa_flow_ctrl_set,
1582 .link_update = dpaa_eth_link_update,
1583 .stats_get = dpaa_eth_stats_get,
1584 .xstats_get = dpaa_dev_xstats_get,
1585 .xstats_get_by_id = dpaa_xstats_get_by_id,
1586 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
1587 .xstats_get_names = dpaa_xstats_get_names,
1588 .xstats_reset = dpaa_eth_stats_reset,
1589 .stats_reset = dpaa_eth_stats_reset,
1590 .promiscuous_enable = dpaa_eth_promiscuous_enable,
1591 .promiscuous_disable = dpaa_eth_promiscuous_disable,
1592 .allmulticast_enable = dpaa_eth_multicast_enable,
1593 .allmulticast_disable = dpaa_eth_multicast_disable,
1594 .mtu_set = dpaa_mtu_set,
1595 .dev_set_link_down = dpaa_link_down,
1596 .dev_set_link_up = dpaa_link_up,
1597 .mac_addr_add = dpaa_dev_add_mac_addr,
1598 .mac_addr_remove = dpaa_dev_remove_mac_addr,
1599 .mac_addr_set = dpaa_dev_set_mac_addr,
1601 .fw_version_get = dpaa_fw_version_get,
1603 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable,
1604 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable,
1605 .rss_hash_update = dpaa_dev_rss_hash_update,
1606 .rss_hash_conf_get = dpaa_dev_rss_hash_conf_get,
1610 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1612 if (strcmp(dev->device->driver->name,
1620 is_dpaa_supported(struct rte_eth_dev *dev)
1622 return is_device_supported(dev, &rte_dpaa_pmd);
1626 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on)
1628 struct rte_eth_dev *dev;
1630 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1632 dev = &rte_eth_devices[port];
1634 if (!is_dpaa_supported(dev))
1638 fman_if_loopback_enable(dev->process_private);
1640 fman_if_loopback_disable(dev->process_private);
1645 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1646 struct fman_if *fman_intf)
1648 struct rte_eth_fc_conf *fc_conf;
1651 PMD_INIT_FUNC_TRACE();
1653 if (!(dpaa_intf->fc_conf)) {
1654 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1655 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1656 if (!dpaa_intf->fc_conf) {
1657 DPAA_PMD_ERR("unable to save flow control info");
1661 fc_conf = dpaa_intf->fc_conf;
1662 ret = fman_if_get_fc_threshold(fman_intf);
1664 fc_conf->mode = RTE_FC_TX_PAUSE;
1665 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1667 fc_conf->mode = RTE_FC_NONE;
1673 /* Initialise an Rx FQ */
1674 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1677 struct qm_mcc_initfq opts = {0};
1679 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1680 struct qm_mcc_initcgr cgr_opts = {
1681 .we_mask = QM_CGR_WE_CS_THRES |
1685 .cstd_en = QM_CGR_EN,
1686 .mode = QMAN_CGR_MODE_FRAME
1690 if (fmc_q || default_q) {
1691 ret = qman_reserve_fqid(fqid);
1693 DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1699 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1700 ret = qman_create_fq(fqid, flags, fq);
1702 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1706 fq->is_static = false;
1708 dpaa_poll_queue_default_config(&opts);
1711 /* Enable tail drop with cgr on this queue */
1712 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1714 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1718 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1722 opts.we_mask |= QM_INITFQ_WE_CGID;
1723 opts.fqd.cgid = cgr_rx->cgrid;
1724 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1727 ret = qman_init_fq(fq, 0, &opts);
1729 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1733 /* Initialise a Tx FQ */
1734 static int dpaa_tx_queue_init(struct qman_fq *fq,
1735 struct fman_if *fman_intf,
1736 struct qman_cgr *cgr_tx)
1738 struct qm_mcc_initfq opts = {0};
1739 struct qm_mcc_initcgr cgr_opts = {
1740 .we_mask = QM_CGR_WE_CS_THRES |
1744 .cstd_en = QM_CGR_EN,
1745 .mode = QMAN_CGR_MODE_FRAME
1750 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1751 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1753 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1756 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1757 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1758 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1759 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1760 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1761 opts.fqd.context_b = 0;
1762 /* no tx-confirmation */
1763 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1764 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1765 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1768 /* Enable tail drop with cgr on this queue */
1769 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1770 td_tx_threshold, 0);
1772 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1776 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1780 opts.we_mask |= QM_INITFQ_WE_CGID;
1781 opts.fqd.cgid = cgr_tx->cgrid;
1782 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1783 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1787 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1789 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1793 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1794 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1795 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1797 struct qm_mcc_initfq opts = {0};
1800 PMD_INIT_FUNC_TRACE();
1802 ret = qman_reserve_fqid(fqid);
1804 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1808 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1809 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1810 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1812 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1816 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1817 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1818 ret = qman_init_fq(fq, 0, &opts);
1820 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1826 /* Initialise a network interface */
1828 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1830 struct rte_dpaa_device *dpaa_device;
1831 struct fm_eth_port_cfg *cfg;
1832 struct dpaa_if *dpaa_intf;
1833 struct fman_if *fman_intf;
1836 PMD_INIT_FUNC_TRACE();
1838 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1839 dev_id = dpaa_device->id.dev_id;
1840 cfg = dpaa_get_eth_port_cfg(dev_id);
1841 fman_intf = cfg->fman_if;
1842 eth_dev->process_private = fman_intf;
1844 /* Plugging of UCODE burst API not supported in Secondary */
1845 dpaa_intf = eth_dev->data->dev_private;
1846 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1847 if (dpaa_intf->cgr_tx)
1848 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1850 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1851 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1852 qman_set_fq_lookup_table(
1853 dpaa_intf->rx_queues->qman_fq_lookup_table);
1859 /* Initialise a network interface */
1861 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1863 int num_rx_fqs, fqid;
1866 struct rte_dpaa_device *dpaa_device;
1867 struct dpaa_if *dpaa_intf;
1868 struct fm_eth_port_cfg *cfg;
1869 struct fman_if *fman_intf;
1870 struct fman_if_bpool *bp, *tmp_bp;
1871 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1872 uint32_t cgrid_tx[MAX_DPAA_CORES];
1873 uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1874 int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES];
1877 PMD_INIT_FUNC_TRACE();
1879 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1880 dev_id = dpaa_device->id.dev_id;
1881 dpaa_intf = eth_dev->data->dev_private;
1882 cfg = dpaa_get_eth_port_cfg(dev_id);
1883 fman_intf = cfg->fman_if;
1885 dpaa_intf->name = dpaa_device->name;
1887 /* save fman_if & cfg in the interface struture */
1888 eth_dev->process_private = fman_intf;
1889 dpaa_intf->ifid = dev_id;
1890 dpaa_intf->cfg = cfg;
1892 memset((char *)dev_rx_fqids, 0,
1893 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1895 memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES);
1897 /* Initialize Rx FQ's */
1899 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1901 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids,
1903 DPAA_MAX_NUM_PCD_QUEUES);
1904 if (num_rx_fqs < 0) {
1905 DPAA_PMD_ERR("%s FMC initializes failed!",
1910 DPAA_PMD_WARN("%s is not configured by FMC.",
1914 /* FMCLESS mode, load balance to multiple cores.*/
1915 num_rx_fqs = rte_lcore_count();
1918 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1921 if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1922 DPAA_PMD_ERR("Invalid number of RX queues\n");
1926 if (num_rx_fqs > 0) {
1927 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1928 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1929 if (!dpaa_intf->rx_queues) {
1930 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1934 dpaa_intf->rx_queues = NULL;
1937 memset(cgrid, 0, sizeof(cgrid));
1938 memset(cgrid_tx, 0, sizeof(cgrid_tx));
1940 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1941 * Tx tail drop is disabled.
1943 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1944 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1945 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1947 /* if a very large value is being configured */
1948 if (td_tx_threshold > UINT16_MAX)
1949 td_tx_threshold = CGR_RX_PERFQ_THRESH;
1952 /* If congestion control is enabled globally*/
1953 if (num_rx_fqs > 0 && td_threshold) {
1954 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1955 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1956 if (!dpaa_intf->cgr_rx) {
1957 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1962 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1963 if (ret != num_rx_fqs) {
1964 DPAA_PMD_WARN("insufficient CGRIDs available");
1969 dpaa_intf->cgr_rx = NULL;
1972 if (!fmc_q && !default_q) {
1973 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1976 DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1981 for (loop = 0; loop < num_rx_fqs; loop++) {
1985 fqid = dev_rx_fqids[loop];
1987 vsp_id = dev_vspids[loop];
1989 if (dpaa_intf->cgr_rx)
1990 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1992 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1993 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1997 dpaa_intf->rx_queues[loop].vsp_id = vsp_id;
1998 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
2000 dpaa_intf->nb_rx_queues = num_rx_fqs;
2002 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
2003 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
2004 MAX_DPAA_CORES, MAX_CACHELINE);
2005 if (!dpaa_intf->tx_queues) {
2006 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
2011 /* If congestion control is enabled globally*/
2012 if (td_tx_threshold) {
2013 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
2014 sizeof(struct qman_cgr) * MAX_DPAA_CORES,
2016 if (!dpaa_intf->cgr_tx) {
2017 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
2022 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
2024 if (ret != MAX_DPAA_CORES) {
2025 DPAA_PMD_WARN("insufficient CGRIDs available");
2030 dpaa_intf->cgr_tx = NULL;
2034 for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
2035 if (dpaa_intf->cgr_tx)
2036 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
2038 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
2040 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
2043 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
2045 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
2047 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
2048 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2049 [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
2051 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!");
2054 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
2055 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2056 [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
2058 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!");
2061 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
2064 DPAA_PMD_DEBUG("All frame queues created");
2066 /* Get the initial configuration for flow control */
2067 dpaa_fc_set_default(dpaa_intf, fman_intf);
2069 /* reset bpool list, initialize bpool dynamically */
2070 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
2071 list_del(&bp->node);
2075 /* Populate ethdev structure */
2076 eth_dev->dev_ops = &dpaa_devops;
2077 eth_dev->rx_queue_count = dpaa_dev_rx_queue_count;
2078 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
2079 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
2081 /* Allocate memory for storing MAC addresses */
2082 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2083 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
2084 if (eth_dev->data->mac_addrs == NULL) {
2085 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
2086 "store MAC addresses",
2087 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
2092 /* copy the primary mac address */
2093 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]);
2095 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
2097 fman_intf->mac_addr.addr_bytes[0],
2098 fman_intf->mac_addr.addr_bytes[1],
2099 fman_intf->mac_addr.addr_bytes[2],
2100 fman_intf->mac_addr.addr_bytes[3],
2101 fman_intf->mac_addr.addr_bytes[4],
2102 fman_intf->mac_addr.addr_bytes[5]);
2104 if (!fman_intf->is_shared_mac) {
2105 /* Configure error packet handling */
2106 fman_if_receive_rx_errors(fman_intf,
2107 FM_FD_RX_STATUS_ERR_MASK);
2108 /* Disable RX mode */
2109 fman_if_disable_rx(fman_intf);
2110 /* Disable promiscuous mode */
2111 fman_if_promiscuous_disable(fman_intf);
2112 /* Disable multicast */
2113 fman_if_reset_mcast_filter_table(fman_intf);
2114 /* Reset interface statistics */
2115 fman_if_stats_reset(fman_intf);
2116 /* Disable SG by default */
2117 fman_if_set_sg(fman_intf, 0);
2118 fman_if_set_maxfrm(fman_intf,
2119 RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
2125 rte_free(dpaa_intf->tx_queues);
2126 dpaa_intf->tx_queues = NULL;
2127 dpaa_intf->nb_tx_queues = 0;
2130 rte_free(dpaa_intf->cgr_rx);
2131 rte_free(dpaa_intf->cgr_tx);
2132 rte_free(dpaa_intf->rx_queues);
2133 dpaa_intf->rx_queues = NULL;
2134 dpaa_intf->nb_rx_queues = 0;
2139 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
2140 struct rte_dpaa_device *dpaa_dev)
2144 struct rte_eth_dev *eth_dev;
2146 PMD_INIT_FUNC_TRACE();
2148 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
2149 RTE_PKTMBUF_HEADROOM) {
2151 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
2152 RTE_PKTMBUF_HEADROOM,
2153 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
2158 /* In case of secondary process, the device is already configured
2159 * and no further action is required, except portal initialization
2160 * and verifying secondary attachment to port name.
2162 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2163 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
2166 eth_dev->device = &dpaa_dev->device;
2167 eth_dev->dev_ops = &dpaa_devops;
2169 ret = dpaa_dev_init_secondary(eth_dev);
2171 RTE_LOG(ERR, PMD, "secondary dev init failed\n");
2175 rte_eth_dev_probing_finish(eth_dev);
2179 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
2180 if (access("/tmp/fmc.bin", F_OK) == -1) {
2181 DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
2185 if (!(default_q || fmc_q)) {
2186 if (dpaa_fm_init()) {
2187 DPAA_PMD_ERR("FM init failed\n");
2192 /* disabling the default push mode for LS1043 */
2193 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
2194 dpaa_push_mode_max_queue = 0;
2196 /* if push mode queues to be enabled. Currenly we are allowing
2197 * only one queue per thread.
2199 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
2200 dpaa_push_mode_max_queue =
2201 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
2202 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
2203 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
2209 if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
2210 ret = rte_dpaa_portal_init((void *)1);
2212 DPAA_PMD_ERR("Unable to initialize portal");
2217 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
2221 eth_dev->data->dev_private =
2222 rte_zmalloc("ethdev private structure",
2223 sizeof(struct dpaa_if),
2224 RTE_CACHE_LINE_SIZE);
2225 if (!eth_dev->data->dev_private) {
2226 DPAA_PMD_ERR("Cannot allocate memzone for port data");
2227 rte_eth_dev_release_port(eth_dev);
2231 eth_dev->device = &dpaa_dev->device;
2232 dpaa_dev->eth_dev = eth_dev;
2234 qman_ern_register_cb(dpaa_free_mbuf);
2236 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2237 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2239 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2241 /* Invoke PMD device initialization function */
2242 diag = dpaa_dev_init(eth_dev);
2244 rte_eth_dev_probing_finish(eth_dev);
2248 rte_eth_dev_release_port(eth_dev);
2253 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2255 struct rte_eth_dev *eth_dev;
2258 PMD_INIT_FUNC_TRACE();
2260 eth_dev = dpaa_dev->eth_dev;
2261 dpaa_eth_dev_close(eth_dev);
2262 ret = rte_eth_dev_release_port(eth_dev);
2267 static void __attribute__((destructor(102))) dpaa_finish(void)
2269 /* For secondary, primary will do all the cleanup */
2270 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2273 if (!(default_q || fmc_q)) {
2276 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2277 if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2278 struct rte_eth_dev *dev = &rte_eth_devices[i];
2279 struct dpaa_if *dpaa_intf =
2280 dev->data->dev_private;
2281 struct fman_if *fif =
2282 dev->process_private;
2283 if (dpaa_intf->port_handle)
2284 if (dpaa_fm_deconfig(dpaa_intf, fif))
2285 DPAA_PMD_WARN("DPAA FM "
2286 "deconfig failed\n");
2287 if (fif->num_profiles) {
2288 if (dpaa_port_vsp_cleanup(dpaa_intf,
2290 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n");
2296 DPAA_PMD_WARN("DPAA FM term failed\n");
2300 DPAA_PMD_INFO("DPAA fman cleaned up");
2304 static struct rte_dpaa_driver rte_dpaa_pmd = {
2305 .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2306 .drv_type = FSL_DPAA_ETH,
2307 .probe = rte_dpaa_probe,
2308 .remove = rte_dpaa_remove,
2311 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2312 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);