1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
15 #include <sys/types.h>
16 #include <sys/syscall.h>
18 #include <rte_byteorder.h>
19 #include <rte_common.h>
20 #include <rte_interrupts.h>
22 #include <rte_debug.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_malloc.h>
35 #include <rte_dpaa_bus.h>
36 #include <rte_dpaa_logs.h>
37 #include <dpaa_mempool.h>
39 #include <dpaa_ethdev.h>
40 #include <dpaa_rxtx.h>
41 #include <rte_pmd_dpaa.h>
48 /* Supported Rx offloads */
49 static uint64_t dev_rx_offloads_sup =
50 DEV_RX_OFFLOAD_JUMBO_FRAME;
52 /* Rx offloads which cannot be disabled */
53 static uint64_t dev_rx_offloads_nodis =
54 DEV_RX_OFFLOAD_IPV4_CKSUM |
55 DEV_RX_OFFLOAD_UDP_CKSUM |
56 DEV_RX_OFFLOAD_TCP_CKSUM |
57 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
58 DEV_RX_OFFLOAD_CRC_STRIP |
59 DEV_RX_OFFLOAD_SCATTER;
61 /* Supported Tx offloads */
62 static uint64_t dev_tx_offloads_sup;
64 /* Tx offloads which cannot be disabled */
65 static uint64_t dev_tx_offloads_nodis =
66 DEV_TX_OFFLOAD_IPV4_CKSUM |
67 DEV_TX_OFFLOAD_UDP_CKSUM |
68 DEV_TX_OFFLOAD_TCP_CKSUM |
69 DEV_TX_OFFLOAD_SCTP_CKSUM |
70 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
71 DEV_TX_OFFLOAD_MULTI_SEGS |
72 DEV_TX_OFFLOAD_MT_LOCKFREE |
73 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
75 /* Keep track of whether QMAN and BMAN have been globally initialized */
76 static int is_global_init;
77 /* At present we only allow up to 4 push mode queues as default - as each of
78 * this queue need dedicated portal and we are short of portals.
80 #define DPAA_MAX_PUSH_MODE_QUEUE 8
81 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
83 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
84 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
87 /* Per FQ Taildrop in frame count */
88 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
90 struct rte_dpaa_xstats_name_off {
91 char name[RTE_ETH_XSTATS_NAME_SIZE];
95 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
97 offsetof(struct dpaa_if_stats, raln)},
99 offsetof(struct dpaa_if_stats, rxpf)},
101 offsetof(struct dpaa_if_stats, rfcs)},
103 offsetof(struct dpaa_if_stats, rvlan)},
105 offsetof(struct dpaa_if_stats, rerr)},
107 offsetof(struct dpaa_if_stats, rdrp)},
109 offsetof(struct dpaa_if_stats, rund)},
111 offsetof(struct dpaa_if_stats, rovr)},
113 offsetof(struct dpaa_if_stats, rfrg)},
115 offsetof(struct dpaa_if_stats, txpf)},
117 offsetof(struct dpaa_if_stats, terr)},
119 offsetof(struct dpaa_if_stats, tvlan)},
121 offsetof(struct dpaa_if_stats, tund)},
124 static struct rte_dpaa_driver rte_dpaa_pmd;
127 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
130 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
132 memset(opts, 0, sizeof(struct qm_mcc_initfq));
133 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
134 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
135 QM_FQCTRL_PREFERINCACHE;
136 opts->fqd.context_a.stashing.exclusive = 0;
137 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
138 opts->fqd.context_a.stashing.annotation_cl =
139 DPAA_IF_RX_ANNOTATION_STASH;
140 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
141 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
145 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
147 struct dpaa_if *dpaa_intf = dev->data->dev_private;
148 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
151 PMD_INIT_FUNC_TRACE();
153 if (mtu < ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
155 if (frame_size > ETHER_MAX_LEN)
156 dev->data->dev_conf.rxmode.offloads &=
157 DEV_RX_OFFLOAD_JUMBO_FRAME;
159 dev->data->dev_conf.rxmode.offloads &=
160 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
162 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
164 fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
170 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
172 struct dpaa_if *dpaa_intf = dev->data->dev_private;
173 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
174 uint64_t rx_offloads = eth_conf->rxmode.offloads;
175 uint64_t tx_offloads = eth_conf->txmode.offloads;
177 PMD_INIT_FUNC_TRACE();
179 /* Rx offloads validation */
180 if (~(dev_rx_offloads_sup | dev_rx_offloads_nodis) & rx_offloads) {
182 "Rx offloads non supported - requested 0x%" PRIx64
183 " supported 0x%" PRIx64,
185 dev_rx_offloads_sup | dev_rx_offloads_nodis);
188 if (dev_rx_offloads_nodis & ~rx_offloads) {
190 "Rx offloads non configurable - requested 0x%" PRIx64
191 " ignored 0x%" PRIx64,
192 rx_offloads, dev_rx_offloads_nodis);
195 /* Tx offloads validation */
196 if (~(dev_tx_offloads_sup | dev_tx_offloads_nodis) & tx_offloads) {
198 "Tx offloads non supported - requested 0x%" PRIx64
199 " supported 0x%" PRIx64,
201 dev_tx_offloads_sup | dev_tx_offloads_nodis);
204 if (dev_tx_offloads_nodis & ~tx_offloads) {
206 "Tx offloads non configurable - requested 0x%" PRIx64
207 " ignored 0x%" PRIx64,
208 tx_offloads, dev_tx_offloads_nodis);
211 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
212 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
213 DPAA_MAX_RX_PKT_LEN) {
214 fman_if_set_maxfrm(dpaa_intf->fif,
215 dev->data->dev_conf.rxmode.max_rx_pkt_len);
224 static const uint32_t *
225 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
227 static const uint32_t ptypes[] = {
228 /*todo -= add more types */
231 RTE_PTYPE_L3_IPV4_EXT,
233 RTE_PTYPE_L3_IPV6_EXT,
239 PMD_INIT_FUNC_TRACE();
241 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
246 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
248 struct dpaa_if *dpaa_intf = dev->data->dev_private;
250 PMD_INIT_FUNC_TRACE();
252 /* Change tx callback to the real one */
253 dev->tx_pkt_burst = dpaa_eth_queue_tx;
254 fman_if_enable_rx(dpaa_intf->fif);
259 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
261 struct dpaa_if *dpaa_intf = dev->data->dev_private;
263 PMD_INIT_FUNC_TRACE();
265 fman_if_disable_rx(dpaa_intf->fif);
266 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
269 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
271 PMD_INIT_FUNC_TRACE();
273 dpaa_eth_dev_stop(dev);
277 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
282 FILE *svr_file = NULL;
283 unsigned int svr_ver = 0;
285 PMD_INIT_FUNC_TRACE();
287 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
289 DPAA_PMD_ERR("Unable to open SoC device");
290 return -ENOTSUP; /* Not supported on this infra */
292 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
293 dpaa_svr_family = svr_ver & SVR_MASK;
295 DPAA_PMD_ERR("Unable to read SoC device");
299 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
300 svr_ver, fman_ip_rev);
301 ret += 1; /* add the size of '\0' */
303 if (fw_size < (uint32_t)ret)
309 static void dpaa_eth_dev_info(struct rte_eth_dev *dev,
310 struct rte_eth_dev_info *dev_info)
312 struct dpaa_if *dpaa_intf = dev->data->dev_private;
314 PMD_INIT_FUNC_TRACE();
316 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
317 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
318 dev_info->min_rx_bufsize = DPAA_MIN_RX_BUF_SIZE;
319 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
320 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
321 dev_info->max_hash_mac_addrs = 0;
322 dev_info->max_vfs = 0;
323 dev_info->max_vmdq_pools = ETH_16_POOLS;
324 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
325 dev_info->speed_capa = (ETH_LINK_SPEED_1G |
327 dev_info->rx_offload_capa = dev_rx_offloads_sup |
328 dev_rx_offloads_nodis;
329 dev_info->tx_offload_capa = dev_tx_offloads_sup |
330 dev_tx_offloads_nodis;
331 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
332 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
335 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
336 int wait_to_complete __rte_unused)
338 struct dpaa_if *dpaa_intf = dev->data->dev_private;
339 struct rte_eth_link *link = &dev->data->dev_link;
341 PMD_INIT_FUNC_TRACE();
343 if (dpaa_intf->fif->mac_type == fman_mac_1g)
344 link->link_speed = ETH_SPEED_NUM_1G;
345 else if (dpaa_intf->fif->mac_type == fman_mac_10g)
346 link->link_speed = ETH_SPEED_NUM_10G;
348 DPAA_PMD_ERR("invalid link_speed: %s, %d",
349 dpaa_intf->name, dpaa_intf->fif->mac_type);
351 link->link_status = dpaa_intf->valid;
352 link->link_duplex = ETH_LINK_FULL_DUPLEX;
353 link->link_autoneg = ETH_LINK_AUTONEG;
357 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
358 struct rte_eth_stats *stats)
360 struct dpaa_if *dpaa_intf = dev->data->dev_private;
362 PMD_INIT_FUNC_TRACE();
364 fman_if_stats_get(dpaa_intf->fif, stats);
368 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev)
370 struct dpaa_if *dpaa_intf = dev->data->dev_private;
372 PMD_INIT_FUNC_TRACE();
374 fman_if_stats_reset(dpaa_intf->fif);
378 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
381 struct dpaa_if *dpaa_intf = dev->data->dev_private;
382 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
383 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
391 fman_if_stats_get_all(dpaa_intf->fif, values,
392 sizeof(struct dpaa_if_stats) / 8);
394 for (i = 0; i < num; i++) {
396 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
402 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
403 struct rte_eth_xstat_name *xstats_names,
406 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
408 if (limit < stat_cnt)
411 if (xstats_names != NULL)
412 for (i = 0; i < stat_cnt; i++)
413 snprintf(xstats_names[i].name,
414 sizeof(xstats_names[i].name),
416 dpaa_xstats_strings[i].name);
422 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
423 uint64_t *values, unsigned int n)
425 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
426 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
429 struct dpaa_if *dpaa_intf = dev->data->dev_private;
437 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
438 sizeof(struct dpaa_if_stats) / 8);
440 for (i = 0; i < stat_cnt; i++)
442 values_copy[dpaa_xstats_strings[i].offset / 8];
447 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
449 for (i = 0; i < n; i++) {
450 if (ids[i] >= stat_cnt) {
451 DPAA_PMD_ERR("id value isn't valid");
454 values[i] = values_copy[ids[i]];
460 dpaa_xstats_get_names_by_id(
461 struct rte_eth_dev *dev,
462 struct rte_eth_xstat_name *xstats_names,
466 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
467 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
470 return dpaa_xstats_get_names(dev, xstats_names, limit);
472 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
474 for (i = 0; i < limit; i++) {
475 if (ids[i] >= stat_cnt) {
476 DPAA_PMD_ERR("id value isn't valid");
479 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
484 static void dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
486 struct dpaa_if *dpaa_intf = dev->data->dev_private;
488 PMD_INIT_FUNC_TRACE();
490 fman_if_promiscuous_enable(dpaa_intf->fif);
493 static void dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
495 struct dpaa_if *dpaa_intf = dev->data->dev_private;
497 PMD_INIT_FUNC_TRACE();
499 fman_if_promiscuous_disable(dpaa_intf->fif);
502 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
504 struct dpaa_if *dpaa_intf = dev->data->dev_private;
506 PMD_INIT_FUNC_TRACE();
508 fman_if_set_mcast_filter_table(dpaa_intf->fif);
511 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
513 struct dpaa_if *dpaa_intf = dev->data->dev_private;
515 PMD_INIT_FUNC_TRACE();
517 fman_if_reset_mcast_filter_table(dpaa_intf->fif);
521 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
523 unsigned int socket_id __rte_unused,
524 const struct rte_eth_rxconf *rx_conf __rte_unused,
525 struct rte_mempool *mp)
527 struct dpaa_if *dpaa_intf = dev->data->dev_private;
528 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
529 struct qm_mcc_initfq opts = {0};
533 PMD_INIT_FUNC_TRACE();
535 DPAA_PMD_INFO("Rx queue setup for queue index: %d", queue_idx);
537 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
538 struct fman_if_ic_params icp;
542 if (!mp->pool_data) {
543 DPAA_PMD_ERR("Not an offloaded buffer pool!");
546 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
548 memset(&icp, 0, sizeof(icp));
549 /* set ICEOF for to the default value , which is 0*/
550 icp.iciof = DEFAULT_ICIOF;
551 icp.iceof = DEFAULT_RX_ICEOF;
552 icp.icsz = DEFAULT_ICSZ;
553 fman_if_set_ic_params(dpaa_intf->fif, &icp);
555 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
556 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
558 /* Buffer pool size should be equal to Dataroom Size*/
559 bp_size = rte_pktmbuf_data_room_size(mp);
560 fman_if_set_bp(dpaa_intf->fif, mp->size,
561 dpaa_intf->bp_info->bpid, bp_size);
562 dpaa_intf->valid = 1;
563 DPAA_PMD_INFO("if =%s - fd_offset = %d offset = %d",
564 dpaa_intf->name, fd_offset,
565 fman_if_get_fdoff(dpaa_intf->fif));
567 /* checking if push mode only, no error check for now */
568 if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
569 dpaa_push_queue_idx++;
570 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
571 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
572 QM_FQCTRL_CTXASTASHING |
573 QM_FQCTRL_PREFERINCACHE;
574 opts.fqd.context_a.stashing.exclusive = 0;
575 /* In muticore scenario stashing becomes a bottleneck on LS1046.
576 * So do not enable stashing in this case
578 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
579 opts.fqd.context_a.stashing.annotation_cl =
580 DPAA_IF_RX_ANNOTATION_STASH;
581 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
582 opts.fqd.context_a.stashing.context_cl =
583 DPAA_IF_RX_CONTEXT_STASH;
585 /*Create a channel and associate given queue with the channel*/
586 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
587 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
588 opts.fqd.dest.channel = rxq->ch_id;
589 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
590 flags = QMAN_INITFQ_FLAG_SCHED;
592 /* Configure tail drop */
593 if (dpaa_intf->cgr_rx) {
594 opts.we_mask |= QM_INITFQ_WE_CGID;
595 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
596 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
598 ret = qman_init_fq(rxq, flags, &opts);
600 DPAA_PMD_ERR("Channel/Queue association failed. fqid %d"
601 " ret: %d", rxq->fqid, ret);
602 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
603 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
604 rxq->is_static = true;
606 dev->data->rx_queues[queue_idx] = rxq;
608 /* configure the CGR size as per the desc size */
609 if (dpaa_intf->cgr_rx) {
610 struct qm_mcc_initcgr cgr_opts = {0};
612 /* Enable tail drop with cgr on this queue */
613 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
614 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
617 "rx taildrop modify fail on fqid %d (ret=%d)",
625 int __rte_experimental
626 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
629 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
633 struct dpaa_if *dpaa_intf = dev->data->dev_private;
634 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
635 struct qm_mcc_initfq opts = {0};
637 if (dpaa_push_mode_max_queue)
638 DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.\n"
639 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
640 dpaa_push_mode_max_queue);
642 dpaa_poll_queue_default_config(&opts);
644 switch (queue_conf->ev.sched_type) {
645 case RTE_SCHED_TYPE_ATOMIC:
646 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
647 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
648 * configuration with HOLD_ACTIVE setting
650 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
651 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
653 case RTE_SCHED_TYPE_ORDERED:
654 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
657 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
658 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
662 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
663 opts.fqd.dest.channel = ch_id;
664 opts.fqd.dest.wq = queue_conf->ev.priority;
666 if (dpaa_intf->cgr_rx) {
667 opts.we_mask |= QM_INITFQ_WE_CGID;
668 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
669 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
672 flags = QMAN_INITFQ_FLAG_SCHED;
674 ret = qman_init_fq(rxq, flags, &opts);
676 DPAA_PMD_ERR("Channel/Queue association failed. fqid %d ret:%d",
681 /* copy configuration which needs to be filled during dequeue */
682 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
683 dev->data->rx_queues[eth_rx_queue_id] = rxq;
688 int __rte_experimental
689 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
692 struct qm_mcc_initfq opts;
695 struct dpaa_if *dpaa_intf = dev->data->dev_private;
696 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
698 dpaa_poll_queue_default_config(&opts);
700 if (dpaa_intf->cgr_rx) {
701 opts.we_mask |= QM_INITFQ_WE_CGID;
702 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
703 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
706 ret = qman_init_fq(rxq, flags, &opts);
708 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
712 rxq->cb.dqrr_dpdk_cb = NULL;
713 dev->data->rx_queues[eth_rx_queue_id] = NULL;
719 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
721 PMD_INIT_FUNC_TRACE();
725 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
726 uint16_t nb_desc __rte_unused,
727 unsigned int socket_id __rte_unused,
728 const struct rte_eth_txconf *tx_conf __rte_unused)
730 struct dpaa_if *dpaa_intf = dev->data->dev_private;
732 PMD_INIT_FUNC_TRACE();
734 DPAA_PMD_INFO("Tx queue setup for queue index: %d", queue_idx);
735 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
739 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
741 PMD_INIT_FUNC_TRACE();
745 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
747 struct dpaa_if *dpaa_intf = dev->data->dev_private;
748 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
751 PMD_INIT_FUNC_TRACE();
753 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
754 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
755 rx_queue_id, frm_cnt);
760 static int dpaa_link_down(struct rte_eth_dev *dev)
762 PMD_INIT_FUNC_TRACE();
764 dpaa_eth_dev_stop(dev);
768 static int dpaa_link_up(struct rte_eth_dev *dev)
770 PMD_INIT_FUNC_TRACE();
772 dpaa_eth_dev_start(dev);
777 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
778 struct rte_eth_fc_conf *fc_conf)
780 struct dpaa_if *dpaa_intf = dev->data->dev_private;
781 struct rte_eth_fc_conf *net_fc;
783 PMD_INIT_FUNC_TRACE();
785 if (!(dpaa_intf->fc_conf)) {
786 dpaa_intf->fc_conf = rte_zmalloc(NULL,
787 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
788 if (!dpaa_intf->fc_conf) {
789 DPAA_PMD_ERR("unable to save flow control info");
793 net_fc = dpaa_intf->fc_conf;
795 if (fc_conf->high_water < fc_conf->low_water) {
796 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
800 if (fc_conf->mode == RTE_FC_NONE) {
802 } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
803 fc_conf->mode == RTE_FC_FULL) {
804 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
806 dpaa_intf->bp_info->bpid);
807 if (fc_conf->pause_time)
808 fman_if_set_fc_quanta(dpaa_intf->fif,
809 fc_conf->pause_time);
812 /* Save the information in dpaa device */
813 net_fc->pause_time = fc_conf->pause_time;
814 net_fc->high_water = fc_conf->high_water;
815 net_fc->low_water = fc_conf->low_water;
816 net_fc->send_xon = fc_conf->send_xon;
817 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
818 net_fc->mode = fc_conf->mode;
819 net_fc->autoneg = fc_conf->autoneg;
825 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
826 struct rte_eth_fc_conf *fc_conf)
828 struct dpaa_if *dpaa_intf = dev->data->dev_private;
829 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
832 PMD_INIT_FUNC_TRACE();
835 fc_conf->pause_time = net_fc->pause_time;
836 fc_conf->high_water = net_fc->high_water;
837 fc_conf->low_water = net_fc->low_water;
838 fc_conf->send_xon = net_fc->send_xon;
839 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
840 fc_conf->mode = net_fc->mode;
841 fc_conf->autoneg = net_fc->autoneg;
844 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
846 fc_conf->mode = RTE_FC_TX_PAUSE;
847 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
849 fc_conf->mode = RTE_FC_NONE;
856 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
857 struct ether_addr *addr,
859 __rte_unused uint32_t pool)
862 struct dpaa_if *dpaa_intf = dev->data->dev_private;
864 PMD_INIT_FUNC_TRACE();
866 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
869 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
875 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
878 struct dpaa_if *dpaa_intf = dev->data->dev_private;
880 PMD_INIT_FUNC_TRACE();
882 fman_if_clear_mac_addr(dpaa_intf->fif, index);
886 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
887 struct ether_addr *addr)
890 struct dpaa_if *dpaa_intf = dev->data->dev_private;
892 PMD_INIT_FUNC_TRACE();
894 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
896 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
901 static struct eth_dev_ops dpaa_devops = {
902 .dev_configure = dpaa_eth_dev_configure,
903 .dev_start = dpaa_eth_dev_start,
904 .dev_stop = dpaa_eth_dev_stop,
905 .dev_close = dpaa_eth_dev_close,
906 .dev_infos_get = dpaa_eth_dev_info,
907 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
909 .rx_queue_setup = dpaa_eth_rx_queue_setup,
910 .tx_queue_setup = dpaa_eth_tx_queue_setup,
911 .rx_queue_release = dpaa_eth_rx_queue_release,
912 .tx_queue_release = dpaa_eth_tx_queue_release,
913 .rx_queue_count = dpaa_dev_rx_queue_count,
915 .flow_ctrl_get = dpaa_flow_ctrl_get,
916 .flow_ctrl_set = dpaa_flow_ctrl_set,
918 .link_update = dpaa_eth_link_update,
919 .stats_get = dpaa_eth_stats_get,
920 .xstats_get = dpaa_dev_xstats_get,
921 .xstats_get_by_id = dpaa_xstats_get_by_id,
922 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
923 .xstats_get_names = dpaa_xstats_get_names,
924 .xstats_reset = dpaa_eth_stats_reset,
925 .stats_reset = dpaa_eth_stats_reset,
926 .promiscuous_enable = dpaa_eth_promiscuous_enable,
927 .promiscuous_disable = dpaa_eth_promiscuous_disable,
928 .allmulticast_enable = dpaa_eth_multicast_enable,
929 .allmulticast_disable = dpaa_eth_multicast_disable,
930 .mtu_set = dpaa_mtu_set,
931 .dev_set_link_down = dpaa_link_down,
932 .dev_set_link_up = dpaa_link_up,
933 .mac_addr_add = dpaa_dev_add_mac_addr,
934 .mac_addr_remove = dpaa_dev_remove_mac_addr,
935 .mac_addr_set = dpaa_dev_set_mac_addr,
937 .fw_version_get = dpaa_fw_version_get,
941 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
943 if (strcmp(dev->device->driver->name,
951 is_dpaa_supported(struct rte_eth_dev *dev)
953 return is_device_supported(dev, &rte_dpaa_pmd);
956 int __rte_experimental
957 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
959 struct rte_eth_dev *dev;
960 struct dpaa_if *dpaa_intf;
962 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
964 dev = &rte_eth_devices[port];
966 if (!is_dpaa_supported(dev))
969 dpaa_intf = dev->data->dev_private;
972 fman_if_loopback_enable(dpaa_intf->fif);
974 fman_if_loopback_disable(dpaa_intf->fif);
979 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
981 struct rte_eth_fc_conf *fc_conf;
984 PMD_INIT_FUNC_TRACE();
986 if (!(dpaa_intf->fc_conf)) {
987 dpaa_intf->fc_conf = rte_zmalloc(NULL,
988 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
989 if (!dpaa_intf->fc_conf) {
990 DPAA_PMD_ERR("unable to save flow control info");
994 fc_conf = dpaa_intf->fc_conf;
995 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
997 fc_conf->mode = RTE_FC_TX_PAUSE;
998 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1000 fc_conf->mode = RTE_FC_NONE;
1006 /* Initialise an Rx FQ */
1007 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1010 struct qm_mcc_initfq opts = {0};
1013 struct qm_mcc_initcgr cgr_opts = {
1014 .we_mask = QM_CGR_WE_CS_THRES |
1018 .cstd_en = QM_CGR_EN,
1019 .mode = QMAN_CGR_MODE_FRAME
1023 PMD_INIT_FUNC_TRACE();
1025 ret = qman_reserve_fqid(fqid);
1027 DPAA_PMD_ERR("reserve rx fqid %d failed with ret: %d",
1032 DPAA_PMD_DEBUG("creating rx fq %p, fqid %d", fq, fqid);
1033 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1035 DPAA_PMD_ERR("create rx fqid %d failed with ret: %d",
1039 fq->is_static = false;
1041 dpaa_poll_queue_default_config(&opts);
1044 /* Enable tail drop with cgr on this queue */
1045 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1047 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1051 "rx taildrop init fail on rx fqid %d (ret=%d)",
1055 opts.we_mask |= QM_INITFQ_WE_CGID;
1056 opts.fqd.cgid = cgr_rx->cgrid;
1057 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1060 ret = qman_init_fq(fq, flags, &opts);
1062 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", fqid, ret);
1066 /* Initialise a Tx FQ */
1067 static int dpaa_tx_queue_init(struct qman_fq *fq,
1068 struct fman_if *fman_intf)
1070 struct qm_mcc_initfq opts = {0};
1073 PMD_INIT_FUNC_TRACE();
1075 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1076 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1078 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1081 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1082 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1083 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1084 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1085 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1086 opts.fqd.context_b = 0;
1087 /* no tx-confirmation */
1088 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1089 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1090 DPAA_PMD_DEBUG("init tx fq %p, fqid %d", fq, fq->fqid);
1091 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1093 DPAA_PMD_ERR("init tx fqid %d failed %d", fq->fqid, ret);
1097 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1098 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1099 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1101 struct qm_mcc_initfq opts = {0};
1104 PMD_INIT_FUNC_TRACE();
1106 ret = qman_reserve_fqid(fqid);
1108 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1112 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1113 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1114 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1116 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1120 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1121 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1122 ret = qman_init_fq(fq, 0, &opts);
1124 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1130 /* Initialise a network interface */
1132 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1134 int num_cores, num_rx_fqs, fqid;
1137 struct rte_dpaa_device *dpaa_device;
1138 struct dpaa_if *dpaa_intf;
1139 struct fm_eth_port_cfg *cfg;
1140 struct fman_if *fman_intf;
1141 struct fman_if_bpool *bp, *tmp_bp;
1142 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1144 PMD_INIT_FUNC_TRACE();
1146 /* For secondary processes, the primary has done all the work */
1147 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1150 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1151 dev_id = dpaa_device->id.dev_id;
1152 dpaa_intf = eth_dev->data->dev_private;
1153 cfg = &dpaa_netcfg->port_cfg[dev_id];
1154 fman_intf = cfg->fman_if;
1156 dpaa_intf->name = dpaa_device->name;
1158 /* save fman_if & cfg in the interface struture */
1159 dpaa_intf->fif = fman_intf;
1160 dpaa_intf->ifid = dev_id;
1161 dpaa_intf->cfg = cfg;
1163 /* Initialize Rx FQ's */
1164 if (getenv("DPAA_NUM_RX_QUEUES"))
1165 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1167 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1169 /* if push mode queues to be enabled. Currenly we are allowing only
1170 * one queue per thread.
1172 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1173 dpaa_push_mode_max_queue =
1174 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1175 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1176 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1179 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1182 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1183 DPAA_PMD_ERR("Invalid number of RX queues\n");
1187 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1188 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1189 if (!dpaa_intf->rx_queues) {
1190 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1194 /* If congestion control is enabled globally*/
1196 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1197 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1198 if (!dpaa_intf->cgr_rx) {
1199 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1204 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1205 if (ret != num_rx_fqs) {
1206 DPAA_PMD_WARN("insufficient CGRIDs available");
1211 dpaa_intf->cgr_rx = NULL;
1214 for (loop = 0; loop < num_rx_fqs; loop++) {
1215 fqid = DPAA_PCD_FQID_START + dpaa_intf->ifid *
1216 DPAA_PCD_FQID_MULTIPLIER + loop;
1218 if (dpaa_intf->cgr_rx)
1219 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1221 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1222 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1226 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1228 dpaa_intf->nb_rx_queues = num_rx_fqs;
1230 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1231 num_cores = rte_lcore_count();
1232 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1233 num_cores, MAX_CACHELINE);
1234 if (!dpaa_intf->tx_queues) {
1235 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1240 for (loop = 0; loop < num_cores; loop++) {
1241 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1245 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1247 dpaa_intf->nb_tx_queues = num_cores;
1249 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1250 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1251 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1252 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1253 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1254 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1255 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1258 DPAA_PMD_DEBUG("All frame queues created");
1260 /* Get the initial configuration for flow control */
1261 dpaa_fc_set_default(dpaa_intf);
1263 /* reset bpool list, initialize bpool dynamically */
1264 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1265 list_del(&bp->node);
1269 /* Populate ethdev structure */
1270 eth_dev->dev_ops = &dpaa_devops;
1271 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1272 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1274 /* Allocate memory for storing MAC addresses */
1275 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1276 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1277 if (eth_dev->data->mac_addrs == NULL) {
1278 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1279 "store MAC addresses",
1280 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1285 /* copy the primary mac address */
1286 ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]);
1288 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1290 fman_intf->mac_addr.addr_bytes[0],
1291 fman_intf->mac_addr.addr_bytes[1],
1292 fman_intf->mac_addr.addr_bytes[2],
1293 fman_intf->mac_addr.addr_bytes[3],
1294 fman_intf->mac_addr.addr_bytes[4],
1295 fman_intf->mac_addr.addr_bytes[5]);
1297 /* Disable RX mode */
1298 fman_if_discard_rx_errors(fman_intf);
1299 fman_if_disable_rx(fman_intf);
1300 /* Disable promiscuous mode */
1301 fman_if_promiscuous_disable(fman_intf);
1302 /* Disable multicast */
1303 fman_if_reset_mcast_filter_table(fman_intf);
1304 /* Reset interface statistics */
1305 fman_if_stats_reset(fman_intf);
1310 rte_free(dpaa_intf->tx_queues);
1311 dpaa_intf->tx_queues = NULL;
1312 dpaa_intf->nb_tx_queues = 0;
1315 rte_free(dpaa_intf->cgr_rx);
1316 rte_free(dpaa_intf->rx_queues);
1317 dpaa_intf->rx_queues = NULL;
1318 dpaa_intf->nb_rx_queues = 0;
1323 dpaa_dev_uninit(struct rte_eth_dev *dev)
1325 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1328 PMD_INIT_FUNC_TRACE();
1330 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1334 DPAA_PMD_WARN("Already closed or not started");
1338 dpaa_eth_dev_close(dev);
1340 /* release configuration memory */
1341 if (dpaa_intf->fc_conf)
1342 rte_free(dpaa_intf->fc_conf);
1344 /* Release RX congestion Groups */
1345 if (dpaa_intf->cgr_rx) {
1346 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1347 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1349 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1350 dpaa_intf->nb_rx_queues);
1353 rte_free(dpaa_intf->cgr_rx);
1354 dpaa_intf->cgr_rx = NULL;
1356 rte_free(dpaa_intf->rx_queues);
1357 dpaa_intf->rx_queues = NULL;
1359 rte_free(dpaa_intf->tx_queues);
1360 dpaa_intf->tx_queues = NULL;
1362 /* free memory for storing MAC addresses */
1363 rte_free(dev->data->mac_addrs);
1364 dev->data->mac_addrs = NULL;
1366 dev->dev_ops = NULL;
1367 dev->rx_pkt_burst = NULL;
1368 dev->tx_pkt_burst = NULL;
1374 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
1375 struct rte_dpaa_device *dpaa_dev)
1379 struct rte_eth_dev *eth_dev;
1381 PMD_INIT_FUNC_TRACE();
1383 /* In case of secondary process, the device is already configured
1384 * and no further action is required, except portal initialization
1385 * and verifying secondary attachment to port name.
1387 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1388 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1394 if (!is_global_init) {
1395 /* One time load of Qman/Bman drivers */
1396 ret = qman_global_init();
1398 DPAA_PMD_ERR("QMAN initialization failed: %d",
1402 ret = bman_global_init();
1404 DPAA_PMD_ERR("BMAN initialization failed: %d",
1412 if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1413 ret = rte_dpaa_portal_init((void *)1);
1415 DPAA_PMD_ERR("Unable to initialize portal");
1420 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1421 if (eth_dev == NULL)
1424 eth_dev->data->dev_private = rte_zmalloc(
1425 "ethdev private structure",
1426 sizeof(struct dpaa_if),
1427 RTE_CACHE_LINE_SIZE);
1428 if (!eth_dev->data->dev_private) {
1429 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1430 rte_eth_dev_release_port(eth_dev);
1434 eth_dev->device = &dpaa_dev->device;
1435 eth_dev->device->driver = &dpaa_drv->driver;
1436 dpaa_dev->eth_dev = eth_dev;
1438 /* Invoke PMD device initialization function */
1439 diag = dpaa_dev_init(eth_dev);
1443 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1444 rte_free(eth_dev->data->dev_private);
1446 rte_eth_dev_release_port(eth_dev);
1451 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1453 struct rte_eth_dev *eth_dev;
1455 PMD_INIT_FUNC_TRACE();
1457 eth_dev = dpaa_dev->eth_dev;
1458 dpaa_dev_uninit(eth_dev);
1460 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1461 rte_free(eth_dev->data->dev_private);
1463 rte_eth_dev_release_port(eth_dev);
1468 static struct rte_dpaa_driver rte_dpaa_pmd = {
1469 .drv_type = FSL_DPAA_ETH,
1470 .probe = rte_dpaa_probe,
1471 .remove = rte_dpaa_remove,
1474 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);