1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
15 #include <sys/types.h>
16 #include <sys/syscall.h>
18 #include <rte_byteorder.h>
19 #include <rte_common.h>
20 #include <rte_interrupts.h>
22 #include <rte_debug.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_malloc.h>
35 #include <rte_dpaa_bus.h>
36 #include <rte_dpaa_logs.h>
37 #include <dpaa_mempool.h>
39 #include <dpaa_ethdev.h>
40 #include <dpaa_rxtx.h>
41 #include <rte_pmd_dpaa.h>
48 /* Supported Rx offloads */
49 static uint64_t dev_rx_offloads_sup =
50 DEV_RX_OFFLOAD_JUMBO_FRAME;
52 /* Rx offloads which cannot be disabled */
53 static uint64_t dev_rx_offloads_nodis =
54 DEV_RX_OFFLOAD_IPV4_CKSUM |
55 DEV_RX_OFFLOAD_UDP_CKSUM |
56 DEV_RX_OFFLOAD_TCP_CKSUM |
57 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
58 DEV_RX_OFFLOAD_CRC_STRIP |
59 DEV_RX_OFFLOAD_SCATTER;
61 /* Supported Tx offloads */
62 static uint64_t dev_tx_offloads_sup;
64 /* Tx offloads which cannot be disabled */
65 static uint64_t dev_tx_offloads_nodis =
66 DEV_TX_OFFLOAD_IPV4_CKSUM |
67 DEV_TX_OFFLOAD_UDP_CKSUM |
68 DEV_TX_OFFLOAD_TCP_CKSUM |
69 DEV_TX_OFFLOAD_SCTP_CKSUM |
70 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
71 DEV_TX_OFFLOAD_MULTI_SEGS |
72 DEV_TX_OFFLOAD_MT_LOCKFREE |
73 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
75 /* Keep track of whether QMAN and BMAN have been globally initialized */
76 static int is_global_init;
77 /* At present we only allow up to 4 push mode queues as default - as each of
78 * this queue need dedicated portal and we are short of portals.
80 #define DPAA_MAX_PUSH_MODE_QUEUE 8
81 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
83 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
84 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
87 /* Per FQ Taildrop in frame count */
88 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
90 struct rte_dpaa_xstats_name_off {
91 char name[RTE_ETH_XSTATS_NAME_SIZE];
95 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
97 offsetof(struct dpaa_if_stats, raln)},
99 offsetof(struct dpaa_if_stats, rxpf)},
101 offsetof(struct dpaa_if_stats, rfcs)},
103 offsetof(struct dpaa_if_stats, rvlan)},
105 offsetof(struct dpaa_if_stats, rerr)},
107 offsetof(struct dpaa_if_stats, rdrp)},
109 offsetof(struct dpaa_if_stats, rund)},
111 offsetof(struct dpaa_if_stats, rovr)},
113 offsetof(struct dpaa_if_stats, rfrg)},
115 offsetof(struct dpaa_if_stats, txpf)},
117 offsetof(struct dpaa_if_stats, terr)},
119 offsetof(struct dpaa_if_stats, tvlan)},
121 offsetof(struct dpaa_if_stats, tund)},
124 static struct rte_dpaa_driver rte_dpaa_pmd;
127 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
130 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
132 memset(opts, 0, sizeof(struct qm_mcc_initfq));
133 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
134 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
135 QM_FQCTRL_PREFERINCACHE;
136 opts->fqd.context_a.stashing.exclusive = 0;
137 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
138 opts->fqd.context_a.stashing.annotation_cl =
139 DPAA_IF_RX_ANNOTATION_STASH;
140 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
141 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
145 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
147 struct dpaa_if *dpaa_intf = dev->data->dev_private;
148 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
151 PMD_INIT_FUNC_TRACE();
153 if (mtu < ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
155 if (frame_size > ETHER_MAX_LEN)
156 dev->data->dev_conf.rxmode.offloads &=
157 DEV_RX_OFFLOAD_JUMBO_FRAME;
159 dev->data->dev_conf.rxmode.offloads &=
160 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
162 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
164 fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
170 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
172 struct dpaa_if *dpaa_intf = dev->data->dev_private;
173 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
174 uint64_t rx_offloads = eth_conf->rxmode.offloads;
175 uint64_t tx_offloads = eth_conf->txmode.offloads;
177 PMD_INIT_FUNC_TRACE();
179 /* Rx offloads validation */
180 if (~(dev_rx_offloads_sup | dev_rx_offloads_nodis) & rx_offloads) {
182 "Rx offloads non supported - requested 0x%" PRIx64
183 " supported 0x%" PRIx64,
185 dev_rx_offloads_sup | dev_rx_offloads_nodis);
188 if (dev_rx_offloads_nodis & ~rx_offloads) {
190 "Rx offloads non configurable - requested 0x%" PRIx64
191 " ignored 0x%" PRIx64,
192 rx_offloads, dev_rx_offloads_nodis);
195 /* Tx offloads validation */
196 if (~(dev_tx_offloads_sup | dev_tx_offloads_nodis) & tx_offloads) {
198 "Tx offloads non supported - requested 0x%" PRIx64
199 " supported 0x%" PRIx64,
201 dev_tx_offloads_sup | dev_tx_offloads_nodis);
204 if (dev_tx_offloads_nodis & ~tx_offloads) {
206 "Tx offloads non configurable - requested 0x%" PRIx64
207 " ignored 0x%" PRIx64,
208 tx_offloads, dev_tx_offloads_nodis);
211 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
212 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
213 DPAA_MAX_RX_PKT_LEN) {
214 fman_if_set_maxfrm(dpaa_intf->fif,
215 dev->data->dev_conf.rxmode.max_rx_pkt_len);
224 static const uint32_t *
225 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
227 static const uint32_t ptypes[] = {
228 /*todo -= add more types */
231 RTE_PTYPE_L3_IPV4_EXT,
233 RTE_PTYPE_L3_IPV6_EXT,
239 PMD_INIT_FUNC_TRACE();
241 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
246 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
248 struct dpaa_if *dpaa_intf = dev->data->dev_private;
250 PMD_INIT_FUNC_TRACE();
252 /* Change tx callback to the real one */
253 dev->tx_pkt_burst = dpaa_eth_queue_tx;
254 fman_if_enable_rx(dpaa_intf->fif);
259 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
261 struct dpaa_if *dpaa_intf = dev->data->dev_private;
263 PMD_INIT_FUNC_TRACE();
265 fman_if_disable_rx(dpaa_intf->fif);
266 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
269 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
271 PMD_INIT_FUNC_TRACE();
273 dpaa_eth_dev_stop(dev);
277 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
282 FILE *svr_file = NULL;
283 unsigned int svr_ver = 0;
285 PMD_INIT_FUNC_TRACE();
287 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
289 DPAA_PMD_ERR("Unable to open SoC device");
290 return -ENOTSUP; /* Not supported on this infra */
292 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
293 dpaa_svr_family = svr_ver & SVR_MASK;
295 DPAA_PMD_ERR("Unable to read SoC device");
299 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
300 svr_ver, fman_ip_rev);
301 ret += 1; /* add the size of '\0' */
303 if (fw_size < (uint32_t)ret)
309 static void dpaa_eth_dev_info(struct rte_eth_dev *dev,
310 struct rte_eth_dev_info *dev_info)
312 struct dpaa_if *dpaa_intf = dev->data->dev_private;
314 PMD_INIT_FUNC_TRACE();
316 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
317 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
318 dev_info->min_rx_bufsize = DPAA_MIN_RX_BUF_SIZE;
319 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
320 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
321 dev_info->max_hash_mac_addrs = 0;
322 dev_info->max_vfs = 0;
323 dev_info->max_vmdq_pools = ETH_16_POOLS;
324 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
325 dev_info->speed_capa = (ETH_LINK_SPEED_1G |
327 dev_info->rx_offload_capa = dev_rx_offloads_sup |
328 dev_rx_offloads_nodis;
329 dev_info->tx_offload_capa = dev_tx_offloads_sup |
330 dev_tx_offloads_nodis;
333 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
334 int wait_to_complete __rte_unused)
336 struct dpaa_if *dpaa_intf = dev->data->dev_private;
337 struct rte_eth_link *link = &dev->data->dev_link;
339 PMD_INIT_FUNC_TRACE();
341 if (dpaa_intf->fif->mac_type == fman_mac_1g)
342 link->link_speed = ETH_SPEED_NUM_1G;
343 else if (dpaa_intf->fif->mac_type == fman_mac_10g)
344 link->link_speed = ETH_SPEED_NUM_10G;
346 DPAA_PMD_ERR("invalid link_speed: %s, %d",
347 dpaa_intf->name, dpaa_intf->fif->mac_type);
349 link->link_status = dpaa_intf->valid;
350 link->link_duplex = ETH_LINK_FULL_DUPLEX;
351 link->link_autoneg = ETH_LINK_AUTONEG;
355 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
356 struct rte_eth_stats *stats)
358 struct dpaa_if *dpaa_intf = dev->data->dev_private;
360 PMD_INIT_FUNC_TRACE();
362 fman_if_stats_get(dpaa_intf->fif, stats);
366 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev)
368 struct dpaa_if *dpaa_intf = dev->data->dev_private;
370 PMD_INIT_FUNC_TRACE();
372 fman_if_stats_reset(dpaa_intf->fif);
376 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
379 struct dpaa_if *dpaa_intf = dev->data->dev_private;
380 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
381 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
389 fman_if_stats_get_all(dpaa_intf->fif, values,
390 sizeof(struct dpaa_if_stats) / 8);
392 for (i = 0; i < num; i++) {
394 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
400 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
401 struct rte_eth_xstat_name *xstats_names,
404 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
406 if (limit < stat_cnt)
409 if (xstats_names != NULL)
410 for (i = 0; i < stat_cnt; i++)
411 snprintf(xstats_names[i].name,
412 sizeof(xstats_names[i].name),
414 dpaa_xstats_strings[i].name);
420 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
421 uint64_t *values, unsigned int n)
423 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
424 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
427 struct dpaa_if *dpaa_intf = dev->data->dev_private;
435 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
436 sizeof(struct dpaa_if_stats) / 8);
438 for (i = 0; i < stat_cnt; i++)
440 values_copy[dpaa_xstats_strings[i].offset / 8];
445 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
447 for (i = 0; i < n; i++) {
448 if (ids[i] >= stat_cnt) {
449 DPAA_PMD_ERR("id value isn't valid");
452 values[i] = values_copy[ids[i]];
458 dpaa_xstats_get_names_by_id(
459 struct rte_eth_dev *dev,
460 struct rte_eth_xstat_name *xstats_names,
464 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
465 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
468 return dpaa_xstats_get_names(dev, xstats_names, limit);
470 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
472 for (i = 0; i < limit; i++) {
473 if (ids[i] >= stat_cnt) {
474 DPAA_PMD_ERR("id value isn't valid");
477 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
482 static void dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
484 struct dpaa_if *dpaa_intf = dev->data->dev_private;
486 PMD_INIT_FUNC_TRACE();
488 fman_if_promiscuous_enable(dpaa_intf->fif);
491 static void dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
493 struct dpaa_if *dpaa_intf = dev->data->dev_private;
495 PMD_INIT_FUNC_TRACE();
497 fman_if_promiscuous_disable(dpaa_intf->fif);
500 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
502 struct dpaa_if *dpaa_intf = dev->data->dev_private;
504 PMD_INIT_FUNC_TRACE();
506 fman_if_set_mcast_filter_table(dpaa_intf->fif);
509 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
511 struct dpaa_if *dpaa_intf = dev->data->dev_private;
513 PMD_INIT_FUNC_TRACE();
515 fman_if_reset_mcast_filter_table(dpaa_intf->fif);
519 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
521 unsigned int socket_id __rte_unused,
522 const struct rte_eth_rxconf *rx_conf __rte_unused,
523 struct rte_mempool *mp)
525 struct dpaa_if *dpaa_intf = dev->data->dev_private;
526 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
527 struct qm_mcc_initfq opts = {0};
531 PMD_INIT_FUNC_TRACE();
533 DPAA_PMD_INFO("Rx queue setup for queue index: %d", queue_idx);
535 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
536 struct fman_if_ic_params icp;
540 if (!mp->pool_data) {
541 DPAA_PMD_ERR("Not an offloaded buffer pool!");
544 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
546 memset(&icp, 0, sizeof(icp));
547 /* set ICEOF for to the default value , which is 0*/
548 icp.iciof = DEFAULT_ICIOF;
549 icp.iceof = DEFAULT_RX_ICEOF;
550 icp.icsz = DEFAULT_ICSZ;
551 fman_if_set_ic_params(dpaa_intf->fif, &icp);
553 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
554 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
556 /* Buffer pool size should be equal to Dataroom Size*/
557 bp_size = rte_pktmbuf_data_room_size(mp);
558 fman_if_set_bp(dpaa_intf->fif, mp->size,
559 dpaa_intf->bp_info->bpid, bp_size);
560 dpaa_intf->valid = 1;
561 DPAA_PMD_INFO("if =%s - fd_offset = %d offset = %d",
562 dpaa_intf->name, fd_offset,
563 fman_if_get_fdoff(dpaa_intf->fif));
565 /* checking if push mode only, no error check for now */
566 if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
567 dpaa_push_queue_idx++;
568 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
569 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
570 QM_FQCTRL_CTXASTASHING |
571 QM_FQCTRL_PREFERINCACHE;
572 opts.fqd.context_a.stashing.exclusive = 0;
573 /* In muticore scenario stashing becomes a bottleneck on LS1046.
574 * So do not enable stashing in this case
576 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
577 opts.fqd.context_a.stashing.annotation_cl =
578 DPAA_IF_RX_ANNOTATION_STASH;
579 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
580 opts.fqd.context_a.stashing.context_cl =
581 DPAA_IF_RX_CONTEXT_STASH;
583 /*Create a channel and associate given queue with the channel*/
584 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
585 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
586 opts.fqd.dest.channel = rxq->ch_id;
587 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
588 flags = QMAN_INITFQ_FLAG_SCHED;
590 /* Configure tail drop */
591 if (dpaa_intf->cgr_rx) {
592 opts.we_mask |= QM_INITFQ_WE_CGID;
593 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
594 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
596 ret = qman_init_fq(rxq, flags, &opts);
598 DPAA_PMD_ERR("Channel/Queue association failed. fqid %d"
599 " ret: %d", rxq->fqid, ret);
600 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
601 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
602 rxq->is_static = true;
604 dev->data->rx_queues[queue_idx] = rxq;
606 /* configure the CGR size as per the desc size */
607 if (dpaa_intf->cgr_rx) {
608 struct qm_mcc_initcgr cgr_opts = {0};
610 /* Enable tail drop with cgr on this queue */
611 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
612 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
615 "rx taildrop modify fail on fqid %d (ret=%d)",
623 int __rte_experimental
624 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
627 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
631 struct dpaa_if *dpaa_intf = dev->data->dev_private;
632 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
633 struct qm_mcc_initfq opts = {0};
635 if (dpaa_push_mode_max_queue)
636 DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.\n"
637 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
638 dpaa_push_mode_max_queue);
640 dpaa_poll_queue_default_config(&opts);
642 switch (queue_conf->ev.sched_type) {
643 case RTE_SCHED_TYPE_ATOMIC:
644 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
645 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
646 * configuration with HOLD_ACTIVE setting
648 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
649 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
651 case RTE_SCHED_TYPE_ORDERED:
652 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
655 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
656 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
660 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
661 opts.fqd.dest.channel = ch_id;
662 opts.fqd.dest.wq = queue_conf->ev.priority;
664 if (dpaa_intf->cgr_rx) {
665 opts.we_mask |= QM_INITFQ_WE_CGID;
666 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
667 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
670 flags = QMAN_INITFQ_FLAG_SCHED;
672 ret = qman_init_fq(rxq, flags, &opts);
674 DPAA_PMD_ERR("Channel/Queue association failed. fqid %d ret:%d",
679 /* copy configuration which needs to be filled during dequeue */
680 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
681 dev->data->rx_queues[eth_rx_queue_id] = rxq;
686 int __rte_experimental
687 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
690 struct qm_mcc_initfq opts;
693 struct dpaa_if *dpaa_intf = dev->data->dev_private;
694 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
696 dpaa_poll_queue_default_config(&opts);
698 if (dpaa_intf->cgr_rx) {
699 opts.we_mask |= QM_INITFQ_WE_CGID;
700 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
701 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
704 ret = qman_init_fq(rxq, flags, &opts);
706 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
710 rxq->cb.dqrr_dpdk_cb = NULL;
711 dev->data->rx_queues[eth_rx_queue_id] = NULL;
717 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
719 PMD_INIT_FUNC_TRACE();
723 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
724 uint16_t nb_desc __rte_unused,
725 unsigned int socket_id __rte_unused,
726 const struct rte_eth_txconf *tx_conf __rte_unused)
728 struct dpaa_if *dpaa_intf = dev->data->dev_private;
730 PMD_INIT_FUNC_TRACE();
732 DPAA_PMD_INFO("Tx queue setup for queue index: %d", queue_idx);
733 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
737 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
739 PMD_INIT_FUNC_TRACE();
743 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
745 struct dpaa_if *dpaa_intf = dev->data->dev_private;
746 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
749 PMD_INIT_FUNC_TRACE();
751 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
752 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
753 rx_queue_id, frm_cnt);
758 static int dpaa_link_down(struct rte_eth_dev *dev)
760 PMD_INIT_FUNC_TRACE();
762 dpaa_eth_dev_stop(dev);
766 static int dpaa_link_up(struct rte_eth_dev *dev)
768 PMD_INIT_FUNC_TRACE();
770 dpaa_eth_dev_start(dev);
775 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
776 struct rte_eth_fc_conf *fc_conf)
778 struct dpaa_if *dpaa_intf = dev->data->dev_private;
779 struct rte_eth_fc_conf *net_fc;
781 PMD_INIT_FUNC_TRACE();
783 if (!(dpaa_intf->fc_conf)) {
784 dpaa_intf->fc_conf = rte_zmalloc(NULL,
785 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
786 if (!dpaa_intf->fc_conf) {
787 DPAA_PMD_ERR("unable to save flow control info");
791 net_fc = dpaa_intf->fc_conf;
793 if (fc_conf->high_water < fc_conf->low_water) {
794 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
798 if (fc_conf->mode == RTE_FC_NONE) {
800 } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
801 fc_conf->mode == RTE_FC_FULL) {
802 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
804 dpaa_intf->bp_info->bpid);
805 if (fc_conf->pause_time)
806 fman_if_set_fc_quanta(dpaa_intf->fif,
807 fc_conf->pause_time);
810 /* Save the information in dpaa device */
811 net_fc->pause_time = fc_conf->pause_time;
812 net_fc->high_water = fc_conf->high_water;
813 net_fc->low_water = fc_conf->low_water;
814 net_fc->send_xon = fc_conf->send_xon;
815 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
816 net_fc->mode = fc_conf->mode;
817 net_fc->autoneg = fc_conf->autoneg;
823 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
824 struct rte_eth_fc_conf *fc_conf)
826 struct dpaa_if *dpaa_intf = dev->data->dev_private;
827 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
830 PMD_INIT_FUNC_TRACE();
833 fc_conf->pause_time = net_fc->pause_time;
834 fc_conf->high_water = net_fc->high_water;
835 fc_conf->low_water = net_fc->low_water;
836 fc_conf->send_xon = net_fc->send_xon;
837 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
838 fc_conf->mode = net_fc->mode;
839 fc_conf->autoneg = net_fc->autoneg;
842 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
844 fc_conf->mode = RTE_FC_TX_PAUSE;
845 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
847 fc_conf->mode = RTE_FC_NONE;
854 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
855 struct ether_addr *addr,
857 __rte_unused uint32_t pool)
860 struct dpaa_if *dpaa_intf = dev->data->dev_private;
862 PMD_INIT_FUNC_TRACE();
864 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
867 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
873 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
876 struct dpaa_if *dpaa_intf = dev->data->dev_private;
878 PMD_INIT_FUNC_TRACE();
880 fman_if_clear_mac_addr(dpaa_intf->fif, index);
884 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
885 struct ether_addr *addr)
888 struct dpaa_if *dpaa_intf = dev->data->dev_private;
890 PMD_INIT_FUNC_TRACE();
892 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
894 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
899 static struct eth_dev_ops dpaa_devops = {
900 .dev_configure = dpaa_eth_dev_configure,
901 .dev_start = dpaa_eth_dev_start,
902 .dev_stop = dpaa_eth_dev_stop,
903 .dev_close = dpaa_eth_dev_close,
904 .dev_infos_get = dpaa_eth_dev_info,
905 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
907 .rx_queue_setup = dpaa_eth_rx_queue_setup,
908 .tx_queue_setup = dpaa_eth_tx_queue_setup,
909 .rx_queue_release = dpaa_eth_rx_queue_release,
910 .tx_queue_release = dpaa_eth_tx_queue_release,
911 .rx_queue_count = dpaa_dev_rx_queue_count,
913 .flow_ctrl_get = dpaa_flow_ctrl_get,
914 .flow_ctrl_set = dpaa_flow_ctrl_set,
916 .link_update = dpaa_eth_link_update,
917 .stats_get = dpaa_eth_stats_get,
918 .xstats_get = dpaa_dev_xstats_get,
919 .xstats_get_by_id = dpaa_xstats_get_by_id,
920 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
921 .xstats_get_names = dpaa_xstats_get_names,
922 .xstats_reset = dpaa_eth_stats_reset,
923 .stats_reset = dpaa_eth_stats_reset,
924 .promiscuous_enable = dpaa_eth_promiscuous_enable,
925 .promiscuous_disable = dpaa_eth_promiscuous_disable,
926 .allmulticast_enable = dpaa_eth_multicast_enable,
927 .allmulticast_disable = dpaa_eth_multicast_disable,
928 .mtu_set = dpaa_mtu_set,
929 .dev_set_link_down = dpaa_link_down,
930 .dev_set_link_up = dpaa_link_up,
931 .mac_addr_add = dpaa_dev_add_mac_addr,
932 .mac_addr_remove = dpaa_dev_remove_mac_addr,
933 .mac_addr_set = dpaa_dev_set_mac_addr,
935 .fw_version_get = dpaa_fw_version_get,
939 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
941 if (strcmp(dev->device->driver->name,
949 is_dpaa_supported(struct rte_eth_dev *dev)
951 return is_device_supported(dev, &rte_dpaa_pmd);
954 int __rte_experimental
955 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
957 struct rte_eth_dev *dev;
958 struct dpaa_if *dpaa_intf;
960 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
962 dev = &rte_eth_devices[port];
964 if (!is_dpaa_supported(dev))
967 dpaa_intf = dev->data->dev_private;
970 fman_if_loopback_enable(dpaa_intf->fif);
972 fman_if_loopback_disable(dpaa_intf->fif);
977 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
979 struct rte_eth_fc_conf *fc_conf;
982 PMD_INIT_FUNC_TRACE();
984 if (!(dpaa_intf->fc_conf)) {
985 dpaa_intf->fc_conf = rte_zmalloc(NULL,
986 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
987 if (!dpaa_intf->fc_conf) {
988 DPAA_PMD_ERR("unable to save flow control info");
992 fc_conf = dpaa_intf->fc_conf;
993 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
995 fc_conf->mode = RTE_FC_TX_PAUSE;
996 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
998 fc_conf->mode = RTE_FC_NONE;
1004 /* Initialise an Rx FQ */
1005 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1008 struct qm_mcc_initfq opts = {0};
1011 struct qm_mcc_initcgr cgr_opts = {
1012 .we_mask = QM_CGR_WE_CS_THRES |
1016 .cstd_en = QM_CGR_EN,
1017 .mode = QMAN_CGR_MODE_FRAME
1021 PMD_INIT_FUNC_TRACE();
1023 ret = qman_reserve_fqid(fqid);
1025 DPAA_PMD_ERR("reserve rx fqid %d failed with ret: %d",
1030 DPAA_PMD_DEBUG("creating rx fq %p, fqid %d", fq, fqid);
1031 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1033 DPAA_PMD_ERR("create rx fqid %d failed with ret: %d",
1037 fq->is_static = false;
1039 dpaa_poll_queue_default_config(&opts);
1042 /* Enable tail drop with cgr on this queue */
1043 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1045 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1049 "rx taildrop init fail on rx fqid %d (ret=%d)",
1053 opts.we_mask |= QM_INITFQ_WE_CGID;
1054 opts.fqd.cgid = cgr_rx->cgrid;
1055 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1058 ret = qman_init_fq(fq, flags, &opts);
1060 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d", fqid, ret);
1064 /* Initialise a Tx FQ */
1065 static int dpaa_tx_queue_init(struct qman_fq *fq,
1066 struct fman_if *fman_intf)
1068 struct qm_mcc_initfq opts = {0};
1071 PMD_INIT_FUNC_TRACE();
1073 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1074 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1076 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1079 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1080 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1081 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1082 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1083 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1084 opts.fqd.context_b = 0;
1085 /* no tx-confirmation */
1086 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1087 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1088 DPAA_PMD_DEBUG("init tx fq %p, fqid %d", fq, fq->fqid);
1089 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1091 DPAA_PMD_ERR("init tx fqid %d failed %d", fq->fqid, ret);
1095 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1096 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1097 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1099 struct qm_mcc_initfq opts = {0};
1102 PMD_INIT_FUNC_TRACE();
1104 ret = qman_reserve_fqid(fqid);
1106 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1110 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1111 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1112 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1114 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1118 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1119 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1120 ret = qman_init_fq(fq, 0, &opts);
1122 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1128 /* Initialise a network interface */
1130 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1132 int num_cores, num_rx_fqs, fqid;
1135 struct rte_dpaa_device *dpaa_device;
1136 struct dpaa_if *dpaa_intf;
1137 struct fm_eth_port_cfg *cfg;
1138 struct fman_if *fman_intf;
1139 struct fman_if_bpool *bp, *tmp_bp;
1140 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1142 PMD_INIT_FUNC_TRACE();
1144 /* For secondary processes, the primary has done all the work */
1145 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1148 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1149 dev_id = dpaa_device->id.dev_id;
1150 dpaa_intf = eth_dev->data->dev_private;
1151 cfg = &dpaa_netcfg->port_cfg[dev_id];
1152 fman_intf = cfg->fman_if;
1154 dpaa_intf->name = dpaa_device->name;
1156 /* save fman_if & cfg in the interface struture */
1157 dpaa_intf->fif = fman_intf;
1158 dpaa_intf->ifid = dev_id;
1159 dpaa_intf->cfg = cfg;
1161 /* Initialize Rx FQ's */
1162 if (getenv("DPAA_NUM_RX_QUEUES"))
1163 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1165 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1167 /* if push mode queues to be enabled. Currenly we are allowing only
1168 * one queue per thread.
1170 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1171 dpaa_push_mode_max_queue =
1172 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1173 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1174 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1177 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1180 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1181 DPAA_PMD_ERR("Invalid number of RX queues\n");
1185 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1186 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1187 if (!dpaa_intf->rx_queues) {
1188 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1192 /* If congestion control is enabled globally*/
1194 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1195 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1196 if (!dpaa_intf->cgr_rx) {
1197 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1202 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1203 if (ret != num_rx_fqs) {
1204 DPAA_PMD_WARN("insufficient CGRIDs available");
1209 dpaa_intf->cgr_rx = NULL;
1212 for (loop = 0; loop < num_rx_fqs; loop++) {
1213 fqid = DPAA_PCD_FQID_START + dpaa_intf->ifid *
1214 DPAA_PCD_FQID_MULTIPLIER + loop;
1216 if (dpaa_intf->cgr_rx)
1217 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1219 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1220 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1224 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1226 dpaa_intf->nb_rx_queues = num_rx_fqs;
1228 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1229 num_cores = rte_lcore_count();
1230 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1231 num_cores, MAX_CACHELINE);
1232 if (!dpaa_intf->tx_queues) {
1233 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1238 for (loop = 0; loop < num_cores; loop++) {
1239 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1243 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1245 dpaa_intf->nb_tx_queues = num_cores;
1247 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1248 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1249 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1250 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1251 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1252 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1253 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1256 DPAA_PMD_DEBUG("All frame queues created");
1258 /* Get the initial configuration for flow control */
1259 dpaa_fc_set_default(dpaa_intf);
1261 /* reset bpool list, initialize bpool dynamically */
1262 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1263 list_del(&bp->node);
1267 /* Populate ethdev structure */
1268 eth_dev->dev_ops = &dpaa_devops;
1269 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1270 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1272 /* Allocate memory for storing MAC addresses */
1273 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1274 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1275 if (eth_dev->data->mac_addrs == NULL) {
1276 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1277 "store MAC addresses",
1278 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1283 /* copy the primary mac address */
1284 ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]);
1286 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1288 fman_intf->mac_addr.addr_bytes[0],
1289 fman_intf->mac_addr.addr_bytes[1],
1290 fman_intf->mac_addr.addr_bytes[2],
1291 fman_intf->mac_addr.addr_bytes[3],
1292 fman_intf->mac_addr.addr_bytes[4],
1293 fman_intf->mac_addr.addr_bytes[5]);
1295 /* Disable RX mode */
1296 fman_if_discard_rx_errors(fman_intf);
1297 fman_if_disable_rx(fman_intf);
1298 /* Disable promiscuous mode */
1299 fman_if_promiscuous_disable(fman_intf);
1300 /* Disable multicast */
1301 fman_if_reset_mcast_filter_table(fman_intf);
1302 /* Reset interface statistics */
1303 fman_if_stats_reset(fman_intf);
1308 rte_free(dpaa_intf->tx_queues);
1309 dpaa_intf->tx_queues = NULL;
1310 dpaa_intf->nb_tx_queues = 0;
1313 rte_free(dpaa_intf->cgr_rx);
1314 rte_free(dpaa_intf->rx_queues);
1315 dpaa_intf->rx_queues = NULL;
1316 dpaa_intf->nb_rx_queues = 0;
1321 dpaa_dev_uninit(struct rte_eth_dev *dev)
1323 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1326 PMD_INIT_FUNC_TRACE();
1328 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1332 DPAA_PMD_WARN("Already closed or not started");
1336 dpaa_eth_dev_close(dev);
1338 /* release configuration memory */
1339 if (dpaa_intf->fc_conf)
1340 rte_free(dpaa_intf->fc_conf);
1342 /* Release RX congestion Groups */
1343 if (dpaa_intf->cgr_rx) {
1344 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1345 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1347 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1348 dpaa_intf->nb_rx_queues);
1351 rte_free(dpaa_intf->cgr_rx);
1352 dpaa_intf->cgr_rx = NULL;
1354 rte_free(dpaa_intf->rx_queues);
1355 dpaa_intf->rx_queues = NULL;
1357 rte_free(dpaa_intf->tx_queues);
1358 dpaa_intf->tx_queues = NULL;
1360 /* free memory for storing MAC addresses */
1361 rte_free(dev->data->mac_addrs);
1362 dev->data->mac_addrs = NULL;
1364 dev->dev_ops = NULL;
1365 dev->rx_pkt_burst = NULL;
1366 dev->tx_pkt_burst = NULL;
1372 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
1373 struct rte_dpaa_device *dpaa_dev)
1377 struct rte_eth_dev *eth_dev;
1379 PMD_INIT_FUNC_TRACE();
1381 /* In case of secondary process, the device is already configured
1382 * and no further action is required, except portal initialization
1383 * and verifying secondary attachment to port name.
1385 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1386 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1392 if (!is_global_init) {
1393 /* One time load of Qman/Bman drivers */
1394 ret = qman_global_init();
1396 DPAA_PMD_ERR("QMAN initialization failed: %d",
1400 ret = bman_global_init();
1402 DPAA_PMD_ERR("BMAN initialization failed: %d",
1410 if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1411 ret = rte_dpaa_portal_init((void *)1);
1413 DPAA_PMD_ERR("Unable to initialize portal");
1418 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1419 if (eth_dev == NULL)
1422 eth_dev->data->dev_private = rte_zmalloc(
1423 "ethdev private structure",
1424 sizeof(struct dpaa_if),
1425 RTE_CACHE_LINE_SIZE);
1426 if (!eth_dev->data->dev_private) {
1427 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1428 rte_eth_dev_release_port(eth_dev);
1432 eth_dev->device = &dpaa_dev->device;
1433 eth_dev->device->driver = &dpaa_drv->driver;
1434 dpaa_dev->eth_dev = eth_dev;
1436 /* Invoke PMD device initialization function */
1437 diag = dpaa_dev_init(eth_dev);
1441 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1442 rte_free(eth_dev->data->dev_private);
1444 rte_eth_dev_release_port(eth_dev);
1449 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1451 struct rte_eth_dev *eth_dev;
1453 PMD_INIT_FUNC_TRACE();
1455 eth_dev = dpaa_dev->eth_dev;
1456 dpaa_dev_uninit(eth_dev);
1458 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1459 rte_free(eth_dev->data->dev_private);
1461 rte_eth_dev_release_port(eth_dev);
1466 static struct rte_dpaa_driver rte_dpaa_pmd = {
1467 .drv_type = FSL_DPAA_ETH,
1468 .probe = rte_dpaa_probe,
1469 .remove = rte_dpaa_remove,
1472 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);