drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <dpaa_flow.h>
  43 #include <rte_pmd_dpaa.h>
  44
  45 #include <fsl_usd.h>
  46 #include <fsl_qman.h>
  47 #include <fsl_bman.h>
  48 #include <fsl_fman.h>
  49 #include <process.h>
  50
  51 /* Supported Rx offloads */
  52 static uint64_t dev_rx_offloads_sup =
  53                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  54                 DEV_RX_OFFLOAD_SCATTER;
  55
  56 /* Rx offloads which cannot be disabled */
  57 static uint64_t dev_rx_offloads_nodis =
  58                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  59                 DEV_RX_OFFLOAD_UDP_CKSUM |
  60                 DEV_RX_OFFLOAD_TCP_CKSUM |
  61                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  62                 DEV_RX_OFFLOAD_RSS_HASH;
  63
  64 /* Supported Tx offloads */
  65 static uint64_t dev_tx_offloads_sup =
  66                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  67                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  68
  69 /* Tx offloads which cannot be disabled */
  70 static uint64_t dev_tx_offloads_nodis =
  71                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  72                 DEV_TX_OFFLOAD_UDP_CKSUM |
  73                 DEV_TX_OFFLOAD_TCP_CKSUM |
  74                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  75                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  76                 DEV_TX_OFFLOAD_MULTI_SEGS;
  77
  78 /* Keep track of whether QMAN and BMAN have been globally initialized */
  79 static int is_global_init;
  80 static int fmc_q = 1;   /* Indicates the use of static fmc for distribution */
  81 static int default_q;   /* use default queue - FMC is not executed*/
  82 /* At present we only allow up to 4 push mode queues as default - as each of
  83  * this queue need dedicated portal and we are short of portals.
  84  */
  85 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  86 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  87
  88 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  89 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  90
  91
  92 /* Per RX FQ Taildrop in frame count */
  93 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  94
  95 /* Per TX FQ Taildrop in frame count, disabled by default */
  96 static unsigned int td_tx_threshold;
  97
  98 struct rte_dpaa_xstats_name_off {
  99         char name[RTE_ETH_XSTATS_NAME_SIZE];
 100         uint32_t offset;
 101 };
 102
 103 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 104         {"rx_align_err",
 105                 offsetof(struct dpaa_if_stats, raln)},
 106         {"rx_valid_pause",
 107                 offsetof(struct dpaa_if_stats, rxpf)},
 108         {"rx_fcs_err",
 109                 offsetof(struct dpaa_if_stats, rfcs)},
 110         {"rx_vlan_frame",
 111                 offsetof(struct dpaa_if_stats, rvlan)},
 112         {"rx_frame_err",
 113                 offsetof(struct dpaa_if_stats, rerr)},
 114         {"rx_drop_err",
 115                 offsetof(struct dpaa_if_stats, rdrp)},
 116         {"rx_undersized",
 117                 offsetof(struct dpaa_if_stats, rund)},
 118         {"rx_oversize_err",
 119                 offsetof(struct dpaa_if_stats, rovr)},
 120         {"rx_fragment_pkt",
 121                 offsetof(struct dpaa_if_stats, rfrg)},
 122         {"tx_valid_pause",
 123                 offsetof(struct dpaa_if_stats, txpf)},
 124         {"tx_fcs_err",
 125                 offsetof(struct dpaa_if_stats, terr)},
 126         {"tx_vlan_frame",
 127                 offsetof(struct dpaa_if_stats, tvlan)},
 128         {"rx_undersized",
 129                 offsetof(struct dpaa_if_stats, tund)},
 130 };
 131
 132 static struct rte_dpaa_driver rte_dpaa_pmd;
 133
 134 static int
 135 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 136
 137 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 138                                 int wait_to_complete __rte_unused);
 139
 140 static void dpaa_interrupt_handler(void *param);
 141
 142 static inline void
 143 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 144 {
 145         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 146         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 147         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 148                            QM_FQCTRL_PREFERINCACHE;
 149         opts->fqd.context_a.stashing.exclusive = 0;
 150         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 151                 opts->fqd.context_a.stashing.annotation_cl =
 152                                                 DPAA_IF_RX_ANNOTATION_STASH;
 153         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 154         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 155 }
 156
 157 static int
 158 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 159 {
 160         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 161                                 + VLAN_TAG_SIZE;
 162         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 163
 164         PMD_INIT_FUNC_TRACE();
 165
 166         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 167                 return -EINVAL;
 168         /*
 169          * Refuse mtu that requires the support of scattered packets
 170          * when this feature has not been enabled before.
 171          */
 172         if (dev->data->min_rx_buf_size &&
 173                 !dev->data->scattered_rx && frame_size > buffsz) {
 174                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 175                 return -EINVAL;
 176         }
 177
 178         /* check <seg size> * <max_seg>  >= max_frame */
 179         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 180                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 181                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 182                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 183                 return -EINVAL;
 184         }
 185
 186         if (frame_size > RTE_ETHER_MAX_LEN)
 187                 dev->data->dev_conf.rxmode.offloads |=
 188                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 189         else
 190                 dev->data->dev_conf.rxmode.offloads &=
 191                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 192
 193         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 194
 195         fman_if_set_maxfrm(dev->process_private, frame_size);
 196
 197         return 0;
 198 }
 199
 200 static int
 201 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 202 {
 203         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 204         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 205         uint64_t tx_offloads = eth_conf->txmode.offloads;
 206         struct rte_device *rdev = dev->device;
 207         struct rte_dpaa_device *dpaa_dev;
 208         struct fman_if *fif = dev->process_private;
 209         struct __fman_if *__fif;
 210         struct rte_intr_handle *intr_handle;
 211         int ret;
 212
 213         PMD_INIT_FUNC_TRACE();
 214
 215         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 216         intr_handle = &dpaa_dev->intr_handle;
 217         __fif = container_of(fif, struct __fman_if, __if);
 218
 219         /* Rx offloads which are enabled by default */
 220         if (dev_rx_offloads_nodis & ~rx_offloads) {
 221                 DPAA_PMD_INFO(
 222                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 223                 " fixed are 0x%" PRIx64,
 224                 rx_offloads, dev_rx_offloads_nodis);
 225         }
 226
 227         /* Tx offloads which are enabled by default */
 228         if (dev_tx_offloads_nodis & ~tx_offloads) {
 229                 DPAA_PMD_INFO(
 230                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 231                 " fixed are 0x%" PRIx64,
 232                 tx_offloads, dev_tx_offloads_nodis);
 233         }
 234
 235         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 236                 uint32_t max_len;
 237
 238                 DPAA_PMD_DEBUG("enabling jumbo");
 239
 240                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 241                     DPAA_MAX_RX_PKT_LEN)
 242                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 243                 else {
 244                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 245                                 "supported is %d",
 246                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 247                                 DPAA_MAX_RX_PKT_LEN);
 248                         max_len = DPAA_MAX_RX_PKT_LEN;
 249                 }
 250
 251                 fman_if_set_maxfrm(dev->process_private, max_len);
 252                 dev->data->mtu = max_len
 253                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 254         }
 255
 256         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 257                 DPAA_PMD_DEBUG("enabling scatter mode");
 258                 fman_if_set_sg(dev->process_private, 1);
 259                 dev->data->scattered_rx = 1;
 260         }
 261
 262         if (!(default_q || fmc_q)) {
 263                 if (dpaa_fm_config(dev,
 264                         eth_conf->rx_adv_conf.rss_conf.rss_hf)) {
 265                         dpaa_write_fm_config_to_file();
 266                         DPAA_PMD_ERR("FM port configuration: Failed\n");
 267                         return -1;
 268                 }
 269                 dpaa_write_fm_config_to_file();
 270         }
 271
 272         /* if the interrupts were configured on this devices*/
 273         if (intr_handle && intr_handle->fd) {
 274                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 275                         rte_intr_callback_register(intr_handle,
 276                                            dpaa_interrupt_handler,
 277                                            (void *)dev);
 278
 279                 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
 280                 if (ret) {
 281                         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 282                                 rte_intr_callback_unregister(intr_handle,
 283                                         dpaa_interrupt_handler,
 284                                         (void *)dev);
 285                                 if (ret == EINVAL)
 286                                         printf("Failed to enable interrupt: Not Supported\n");
 287                                 else
 288                                         printf("Failed to enable interrupt\n");
 289                         }
 290                         dev->data->dev_conf.intr_conf.lsc = 0;
 291                         dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 292                 }
 293         }
 294         return 0;
 295 }
 296
 297 static const uint32_t *
 298 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 299 {
 300         static const uint32_t ptypes[] = {
 301                 RTE_PTYPE_L2_ETHER,
 302                 RTE_PTYPE_L2_ETHER_VLAN,
 303                 RTE_PTYPE_L2_ETHER_ARP,
 304                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 305                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 306                 RTE_PTYPE_L4_ICMP,
 307                 RTE_PTYPE_L4_TCP,
 308                 RTE_PTYPE_L4_UDP,
 309                 RTE_PTYPE_L4_FRAG,
 310                 RTE_PTYPE_L4_TCP,
 311                 RTE_PTYPE_L4_UDP,
 312                 RTE_PTYPE_L4_SCTP
 313         };
 314
 315         PMD_INIT_FUNC_TRACE();
 316
 317         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 318                 return ptypes;
 319         return NULL;
 320 }
 321
 322 static void dpaa_interrupt_handler(void *param)
 323 {
 324         struct rte_eth_dev *dev = param;
 325         struct rte_device *rdev = dev->device;
 326         struct rte_dpaa_device *dpaa_dev;
 327         struct rte_intr_handle *intr_handle;
 328         uint64_t buf;
 329         int bytes_read;
 330
 331         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 332         intr_handle = &dpaa_dev->intr_handle;
 333
 334         bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
 335         if (bytes_read < 0)
 336                 DPAA_PMD_ERR("Error reading eventfd\n");
 337         dpaa_eth_link_update(dev, 0);
 338         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 339 }
 340
 341 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 342 {
 343         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 344
 345         PMD_INIT_FUNC_TRACE();
 346
 347         if (!(default_q || fmc_q))
 348                 dpaa_write_fm_config_to_file();
 349
 350         /* Change tx callback to the real one */
 351         if (dpaa_intf->cgr_tx)
 352                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 353         else
 354                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 355
 356         fman_if_enable_rx(dev->process_private);
 357
 358         return 0;
 359 }
 360
 361 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 362 {
 363         struct fman_if *fif = dev->process_private;
 364
 365         PMD_INIT_FUNC_TRACE();
 366
 367         if (!fif->is_shared_mac)
 368                 fman_if_disable_rx(fif);
 369         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 370 }
 371
 372 static int dpaa_eth_dev_close(struct rte_eth_dev *dev)
 373 {
 374         struct fman_if *fif = dev->process_private;
 375         struct __fman_if *__fif;
 376         struct rte_device *rdev = dev->device;
 377         struct rte_dpaa_device *dpaa_dev;
 378         struct rte_intr_handle *intr_handle;
 379
 380         PMD_INIT_FUNC_TRACE();
 381
 382         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 383         intr_handle = &dpaa_dev->intr_handle;
 384         __fif = container_of(fif, struct __fman_if, __if);
 385
 386         dpaa_eth_dev_stop(dev);
 387
 388         if (intr_handle && intr_handle->fd &&
 389             dev->data->dev_conf.intr_conf.lsc != 0) {
 390                 dpaa_intr_disable(__fif->node_name);
 391                 rte_intr_callback_unregister(intr_handle,
 392                                              dpaa_interrupt_handler,
 393                                              (void *)dev);
 394         }
 395
 396         return 0;
 397 }
 398
 399 static int
 400 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 401                      char *fw_version,
 402                      size_t fw_size)
 403 {
 404         int ret;
 405         FILE *svr_file = NULL;
 406         unsigned int svr_ver = 0;
 407
 408         PMD_INIT_FUNC_TRACE();
 409
 410         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 411         if (!svr_file) {
 412                 DPAA_PMD_ERR("Unable to open SoC device");
 413                 return -ENOTSUP; /* Not supported on this infra */
 414         }
 415         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 416                 dpaa_svr_family = svr_ver & SVR_MASK;
 417         else
 418                 DPAA_PMD_ERR("Unable to read SoC device");
 419
 420         fclose(svr_file);
 421
 422         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 423                        svr_ver, fman_ip_rev);
 424         ret += 1; /* add the size of '\0' */
 425
 426         if (fw_size < (uint32_t)ret)
 427                 return ret;
 428         else
 429                 return 0;
 430 }
 431
 432 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 433                              struct rte_eth_dev_info *dev_info)
 434 {
 435         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 436         struct fman_if *fif = dev->process_private;
 437
 438         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 439
 440         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 441         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 442         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 443         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 444         dev_info->max_hash_mac_addrs = 0;
 445         dev_info->max_vfs = 0;
 446         dev_info->max_vmdq_pools = ETH_16_POOLS;
 447         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 448
 449         if (fif->mac_type == fman_mac_1g) {
 450                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 451         } else if (fif->mac_type == fman_mac_2_5g) {
 452                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 453                                         | ETH_LINK_SPEED_2_5G;
 454         } else if (fif->mac_type == fman_mac_10g) {
 455                 dev_info->speed_capa = ETH_LINK_SPEED_1G
 456                                         | ETH_LINK_SPEED_2_5G
 457                                         | ETH_LINK_SPEED_10G;
 458         } else {
 459                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 460                              dpaa_intf->name, fif->mac_type);
 461                 return -EINVAL;
 462         }
 463
 464         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 465                                         dev_rx_offloads_nodis;
 466         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 467                                         dev_tx_offloads_nodis;
 468         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 469         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 470         dev_info->default_rxportconf.nb_queues = 1;
 471         dev_info->default_txportconf.nb_queues = 1;
 472         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 473         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 474
 475         return 0;
 476 }
 477
 478 static int
 479 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 480                         __rte_unused uint16_t queue_id,
 481                         struct rte_eth_burst_mode *mode)
 482 {
 483         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 484         int ret = -EINVAL;
 485         unsigned int i;
 486         const struct burst_info {
 487                 uint64_t flags;
 488                 const char *output;
 489         } rx_offload_map[] = {
 490                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 491                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"},
 492                         {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 493                         {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 494                         {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 495                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 496                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}
 497         };
 498
 499         /* Update Rx offload info */
 500         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 501                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 502                         snprintf(mode->info, sizeof(mode->info), "%s",
 503                                 rx_offload_map[i].output);
 504                         ret = 0;
 505                         break;
 506                 }
 507         }
 508         return ret;
 509 }
 510
 511 static int
 512 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 513                         __rte_unused uint16_t queue_id,
 514                         struct rte_eth_burst_mode *mode)
 515 {
 516         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 517         int ret = -EINVAL;
 518         unsigned int i;
 519         const struct burst_info {
 520                 uint64_t flags;
 521                 const char *output;
 522         } tx_offload_map[] = {
 523                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 524                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 525                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 526                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 527                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 528                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 529                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 530                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 531         };
 532
 533         /* Update Tx offload info */
 534         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 535                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 536                         snprintf(mode->info, sizeof(mode->info), "%s",
 537                                 tx_offload_map[i].output);
 538                         ret = 0;
 539                         break;
 540                 }
 541         }
 542         return ret;
 543 }
 544
 545 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 546                                 int wait_to_complete __rte_unused)
 547 {
 548         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 549         struct rte_eth_link *link = &dev->data->dev_link;
 550         struct fman_if *fif = dev->process_private;
 551         struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
 552         int ret;
 553
 554         PMD_INIT_FUNC_TRACE();
 555
 556         if (fif->mac_type == fman_mac_1g)
 557                 link->link_speed = ETH_SPEED_NUM_1G;
 558         else if (fif->mac_type == fman_mac_2_5g)
 559                 link->link_speed = ETH_SPEED_NUM_2_5G;
 560         else if (fif->mac_type == fman_mac_10g)
 561                 link->link_speed = ETH_SPEED_NUM_10G;
 562         else
 563                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 564                              dpaa_intf->name, fif->mac_type);
 565
 566         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
 567                 ret = dpaa_get_link_status(__fif->node_name);
 568                 if (ret < 0)
 569                         return ret;
 570                 link->link_status = ret;
 571         } else {
 572                 link->link_status = dpaa_intf->valid;
 573         }
 574
 575         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 576         link->link_autoneg = ETH_LINK_AUTONEG;
 577
 578         DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
 579                       link->link_status ? "Up" : "Down");
 580         return 0;
 581 }
 582
 583 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 584                                struct rte_eth_stats *stats)
 585 {
 586         PMD_INIT_FUNC_TRACE();
 587
 588         fman_if_stats_get(dev->process_private, stats);
 589         return 0;
 590 }
 591
 592 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 593 {
 594         PMD_INIT_FUNC_TRACE();
 595
 596         fman_if_stats_reset(dev->process_private);
 597
 598         return 0;
 599 }
 600
 601 static int
 602 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 603                     unsigned int n)
 604 {
 605         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 606         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 607
 608         if (n < num)
 609                 return num;
 610
 611         if (xstats == NULL)
 612                 return 0;
 613
 614         fman_if_stats_get_all(dev->process_private, values,
 615                               sizeof(struct dpaa_if_stats) / 8);
 616
 617         for (i = 0; i < num; i++) {
 618                 xstats[i].id = i;
 619                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 620         }
 621         return i;
 622 }
 623
 624 static int
 625 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 626                       struct rte_eth_xstat_name *xstats_names,
 627                       unsigned int limit)
 628 {
 629         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 630
 631         if (limit < stat_cnt)
 632                 return stat_cnt;
 633
 634         if (xstats_names != NULL)
 635                 for (i = 0; i < stat_cnt; i++)
 636                         strlcpy(xstats_names[i].name,
 637                                 dpaa_xstats_strings[i].name,
 638                                 sizeof(xstats_names[i].name));
 639
 640         return stat_cnt;
 641 }
 642
 643 static int
 644 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 645                       uint64_t *values, unsigned int n)
 646 {
 647         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 648         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 649
 650         if (!ids) {
 651                 if (n < stat_cnt)
 652                         return stat_cnt;
 653
 654                 if (!values)
 655                         return 0;
 656
 657                 fman_if_stats_get_all(dev->process_private, values_copy,
 658                                       sizeof(struct dpaa_if_stats) / 8);
 659
 660                 for (i = 0; i < stat_cnt; i++)
 661                         values[i] =
 662                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 663
 664                 return stat_cnt;
 665         }
 666
 667         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 668
 669         for (i = 0; i < n; i++) {
 670                 if (ids[i] >= stat_cnt) {
 671                         DPAA_PMD_ERR("id value isn't valid");
 672                         return -1;
 673                 }
 674                 values[i] = values_copy[ids[i]];
 675         }
 676         return n;
 677 }
 678
 679 static int
 680 dpaa_xstats_get_names_by_id(
 681         struct rte_eth_dev *dev,
 682         struct rte_eth_xstat_name *xstats_names,
 683         const uint64_t *ids,
 684         unsigned int limit)
 685 {
 686         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 687         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 688
 689         if (!ids)
 690                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 691
 692         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 693
 694         for (i = 0; i < limit; i++) {
 695                 if (ids[i] >= stat_cnt) {
 696                         DPAA_PMD_ERR("id value isn't valid");
 697                         return -1;
 698                 }
 699                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 700         }
 701         return limit;
 702 }
 703
 704 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 705 {
 706         PMD_INIT_FUNC_TRACE();
 707
 708         fman_if_promiscuous_enable(dev->process_private);
 709
 710         return 0;
 711 }
 712
 713 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 714 {
 715         PMD_INIT_FUNC_TRACE();
 716
 717         fman_if_promiscuous_disable(dev->process_private);
 718
 719         return 0;
 720 }
 721
 722 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 723 {
 724         PMD_INIT_FUNC_TRACE();
 725
 726         fman_if_set_mcast_filter_table(dev->process_private);
 727
 728         return 0;
 729 }
 730
 731 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 732 {
 733         PMD_INIT_FUNC_TRACE();
 734
 735         fman_if_reset_mcast_filter_table(dev->process_private);
 736
 737         return 0;
 738 }
 739
 740 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev)
 741 {
 742         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 743         struct fman_if_ic_params icp;
 744         uint32_t fd_offset;
 745         uint32_t bp_size;
 746
 747         memset(&icp, 0, sizeof(icp));
 748         /* set ICEOF for to the default value , which is 0*/
 749         icp.iciof = DEFAULT_ICIOF;
 750         icp.iceof = DEFAULT_RX_ICEOF;
 751         icp.icsz = DEFAULT_ICSZ;
 752         fman_if_set_ic_params(dev->process_private, &icp);
 753
 754         fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 755         fman_if_set_fdoff(dev->process_private, fd_offset);
 756
 757         /* Buffer pool size should be equal to Dataroom Size*/
 758         bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp);
 759
 760         fman_if_set_bp(dev->process_private,
 761                        dpaa_intf->bp_info->mp->size,
 762                        dpaa_intf->bp_info->bpid, bp_size);
 763 }
 764
 765 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev,
 766                                              int8_t vsp_id, uint32_t bpid)
 767 {
 768         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 769         struct fman_if *fif = dev->process_private;
 770
 771         if (fif->num_profiles) {
 772                 if (vsp_id < 0)
 773                         vsp_id = fif->base_profile_id;
 774         } else {
 775                 if (vsp_id < 0)
 776                         vsp_id = 0;
 777         }
 778
 779         if (dpaa_intf->vsp_bpid[vsp_id] &&
 780                 bpid != dpaa_intf->vsp_bpid[vsp_id]) {
 781                 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP");
 782
 783                 return -1;
 784         }
 785
 786         return 0;
 787 }
 788
 789 static
 790 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 791                             uint16_t nb_desc,
 792                             unsigned int socket_id __rte_unused,
 793                             const struct rte_eth_rxconf *rx_conf,
 794                             struct rte_mempool *mp)
 795 {
 796         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 797         struct fman_if *fif = dev->process_private;
 798         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 799         struct qm_mcc_initfq opts = {0};
 800         u32 flags = 0;
 801         int ret;
 802         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 803
 804         PMD_INIT_FUNC_TRACE();
 805
 806         if (queue_idx >= dev->data->nb_rx_queues) {
 807                 rte_errno = EOVERFLOW;
 808                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 809                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 810                 return -rte_errno;
 811         }
 812
 813         /* Rx deferred start is not supported */
 814         if (rx_conf->rx_deferred_start) {
 815                 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
 816                 return -EINVAL;
 817         }
 818         rxq->nb_desc = UINT16_MAX;
 819         rxq->offloads = rx_conf->offloads;
 820
 821         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 822                         queue_idx, rxq->fqid);
 823
 824         if (!fif->num_profiles) {
 825                 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
 826                         dpaa_intf->bp_info->mp != mp) {
 827                         DPAA_PMD_WARN("Multiple pools on same interface not"
 828                                       " supported");
 829                         return -EINVAL;
 830                 }
 831         } else {
 832                 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id,
 833                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) {
 834                         return -EINVAL;
 835                 }
 836         }
 837
 838         /* Max packet can fit in single buffer */
 839         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 840                 ;
 841         } else if (dev->data->dev_conf.rxmode.offloads &
 842                         DEV_RX_OFFLOAD_SCATTER) {
 843                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 844                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 845                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 846                                 "MaxSGlist %d",
 847                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 848                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 849                         rte_errno = EOVERFLOW;
 850                         return -rte_errno;
 851                 }
 852         } else {
 853                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 854                      " larger than a single mbuf (%u) and scattered"
 855                      " mode has not been requested",
 856                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 857                      buffsz - RTE_PKTMBUF_HEADROOM);
 858         }
 859
 860         dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 861
 862         /* For shared interface, it's done in kernel, skip.*/
 863         if (!fif->is_shared_mac)
 864                 dpaa_fman_if_pool_setup(dev);
 865
 866         if (fif->num_profiles) {
 867                 int8_t vsp_id = rxq->vsp_id;
 868
 869                 if (vsp_id >= 0) {
 870                         ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id,
 871                                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid,
 872                                         fif);
 873                         if (ret) {
 874                                 DPAA_PMD_ERR("dpaa_port_vsp_update failed");
 875                                 return ret;
 876                         }
 877                 } else {
 878                         DPAA_PMD_INFO("Base profile is associated to"
 879                                 " RXQ fqid:%d\r\n", rxq->fqid);
 880                         if (fif->is_shared_mac) {
 881                                 DPAA_PMD_ERR("Fatal: Base profile is associated"
 882                                              " to shared interface on DPDK.");
 883                                 return -EINVAL;
 884                         }
 885                         dpaa_intf->vsp_bpid[fif->base_profile_id] =
 886                                 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
 887                 }
 888         } else {
 889                 dpaa_intf->vsp_bpid[0] =
 890                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
 891         }
 892
 893         dpaa_intf->valid = 1;
 894         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 895                 fman_if_get_sg_enable(fif),
 896                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 897         /* checking if push mode only, no error check for now */
 898         if (!rxq->is_static &&
 899             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 900                 struct qman_portal *qp;
 901                 int q_fd;
 902
 903                 dpaa_push_queue_idx++;
 904                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 905                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 906                                    QM_FQCTRL_CTXASTASHING |
 907                                    QM_FQCTRL_PREFERINCACHE;
 908                 opts.fqd.context_a.stashing.exclusive = 0;
 909                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 910                  * So do not enable stashing in this case
 911                  */
 912                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 913                         opts.fqd.context_a.stashing.annotation_cl =
 914                                                 DPAA_IF_RX_ANNOTATION_STASH;
 915                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 916                 opts.fqd.context_a.stashing.context_cl =
 917                                                 DPAA_IF_RX_CONTEXT_STASH;
 918
 919                 /*Create a channel and associate given queue with the channel*/
 920                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 921                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 922                 opts.fqd.dest.channel = rxq->ch_id;
 923                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 924                 flags = QMAN_INITFQ_FLAG_SCHED;
 925
 926                 /* Configure tail drop */
 927                 if (dpaa_intf->cgr_rx) {
 928                         opts.we_mask |= QM_INITFQ_WE_CGID;
 929                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 930                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 931                 }
 932                 ret = qman_init_fq(rxq, flags, &opts);
 933                 if (ret) {
 934                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 935                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 936                         return ret;
 937                 }
 938                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 939                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 940                 } else {
 941                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 942                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 943                 }
 944
 945                 rxq->is_static = true;
 946
 947                 /* Allocate qman specific portals */
 948                 qp = fsl_qman_fq_portal_create(&q_fd);
 949                 if (!qp) {
 950                         DPAA_PMD_ERR("Unable to alloc fq portal");
 951                         return -1;
 952                 }
 953                 rxq->qp = qp;
 954
 955                 /* Set up the device interrupt handler */
 956                 if (!dev->intr_handle) {
 957                         struct rte_dpaa_device *dpaa_dev;
 958                         struct rte_device *rdev = dev->device;
 959
 960                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
 961                                                 device);
 962                         dev->intr_handle = &dpaa_dev->intr_handle;
 963                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
 964                                         dpaa_push_mode_max_queue, 0);
 965                         if (!dev->intr_handle->intr_vec) {
 966                                 DPAA_PMD_ERR("intr_vec alloc failed");
 967                                 return -ENOMEM;
 968                         }
 969                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
 970                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
 971                 }
 972
 973                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
 974                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
 975                 dev->intr_handle->efds[queue_idx] = q_fd;
 976                 rxq->q_fd = q_fd;
 977         }
 978         rxq->bp_array = rte_dpaa_bpid_info;
 979         dev->data->rx_queues[queue_idx] = rxq;
 980
 981         /* configure the CGR size as per the desc size */
 982         if (dpaa_intf->cgr_rx) {
 983                 struct qm_mcc_initcgr cgr_opts = {0};
 984
 985                 rxq->nb_desc = nb_desc;
 986                 /* Enable tail drop with cgr on this queue */
 987                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 988                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 989                 if (ret) {
 990                         DPAA_PMD_WARN(
 991                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 992                                 rxq->fqid, ret);
 993                 }
 994         }
 995
 996         return 0;
 997 }
 998
 999 int
1000 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
1001                 int eth_rx_queue_id,
1002                 u16 ch_id,
1003                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1004 {
1005         int ret;
1006         u32 flags = 0;
1007         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1008         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1009         struct qm_mcc_initfq opts = {0};
1010
1011         if (dpaa_push_mode_max_queue)
1012                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
1013                               "PUSH mode already enabled for first %d queues.\n"
1014                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
1015                               dpaa_push_mode_max_queue);
1016
1017         dpaa_poll_queue_default_config(&opts);
1018
1019         switch (queue_conf->ev.sched_type) {
1020         case RTE_SCHED_TYPE_ATOMIC:
1021                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
1022                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
1023                  * configuration with HOLD_ACTIVE setting
1024                  */
1025                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
1026                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
1027                 break;
1028         case RTE_SCHED_TYPE_ORDERED:
1029                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
1030                 return -1;
1031         default:
1032                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
1033                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
1034                 break;
1035         }
1036
1037         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1038         opts.fqd.dest.channel = ch_id;
1039         opts.fqd.dest.wq = queue_conf->ev.priority;
1040
1041         if (dpaa_intf->cgr_rx) {
1042                 opts.we_mask |= QM_INITFQ_WE_CGID;
1043                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1044                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1045         }
1046
1047         flags = QMAN_INITFQ_FLAG_SCHED;
1048
1049         ret = qman_init_fq(rxq, flags, &opts);
1050         if (ret) {
1051                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
1052                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1053                 return ret;
1054         }
1055
1056         /* copy configuration which needs to be filled during dequeue */
1057         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
1058         dev->data->rx_queues[eth_rx_queue_id] = rxq;
1059
1060         return ret;
1061 }
1062
1063 int
1064 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1065                 int eth_rx_queue_id)
1066 {
1067         struct qm_mcc_initfq opts;
1068         int ret;
1069         u32 flags = 0;
1070         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1071         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1072
1073         dpaa_poll_queue_default_config(&opts);
1074
1075         if (dpaa_intf->cgr_rx) {
1076                 opts.we_mask |= QM_INITFQ_WE_CGID;
1077                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1078                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1079         }
1080
1081         ret = qman_init_fq(rxq, flags, &opts);
1082         if (ret) {
1083                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1084                              rxq->fqid, ret);
1085         }
1086
1087         rxq->cb.dqrr_dpdk_cb = NULL;
1088         dev->data->rx_queues[eth_rx_queue_id] = NULL;
1089
1090         return 0;
1091 }
1092
1093 static
1094 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
1095 {
1096         PMD_INIT_FUNC_TRACE();
1097 }
1098
1099 static
1100 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1101                             uint16_t nb_desc __rte_unused,
1102                 unsigned int socket_id __rte_unused,
1103                 const struct rte_eth_txconf *tx_conf)
1104 {
1105         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1106         struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1107
1108         PMD_INIT_FUNC_TRACE();
1109
1110         /* Tx deferred start is not supported */
1111         if (tx_conf->tx_deferred_start) {
1112                 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1113                 return -EINVAL;
1114         }
1115         txq->nb_desc = UINT16_MAX;
1116         txq->offloads = tx_conf->offloads;
1117
1118         if (queue_idx >= dev->data->nb_tx_queues) {
1119                 rte_errno = EOVERFLOW;
1120                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1121                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
1122                 return -rte_errno;
1123         }
1124
1125         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1126                         queue_idx, txq->fqid);
1127         dev->data->tx_queues[queue_idx] = txq;
1128
1129         return 0;
1130 }
1131
1132 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
1133 {
1134         PMD_INIT_FUNC_TRACE();
1135 }
1136
1137 static uint32_t
1138 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1139 {
1140         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1141         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
1142         u32 frm_cnt = 0;
1143
1144         PMD_INIT_FUNC_TRACE();
1145
1146         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1147                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
1148                                rx_queue_id, frm_cnt);
1149         }
1150         return frm_cnt;
1151 }
1152
1153 static int dpaa_link_down(struct rte_eth_dev *dev)
1154 {
1155         struct fman_if *fif = dev->process_private;
1156         struct __fman_if *__fif;
1157
1158         PMD_INIT_FUNC_TRACE();
1159
1160         __fif = container_of(fif, struct __fman_if, __if);
1161
1162         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1163                 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN);
1164         else
1165                 dpaa_eth_dev_stop(dev);
1166         return 0;
1167 }
1168
1169 static int dpaa_link_up(struct rte_eth_dev *dev)
1170 {
1171         struct fman_if *fif = dev->process_private;
1172         struct __fman_if *__fif;
1173
1174         PMD_INIT_FUNC_TRACE();
1175
1176         __fif = container_of(fif, struct __fman_if, __if);
1177
1178         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1179                 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP);
1180         else
1181                 dpaa_eth_dev_start(dev);
1182         return 0;
1183 }
1184
1185 static int
1186 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1187                    struct rte_eth_fc_conf *fc_conf)
1188 {
1189         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1190         struct rte_eth_fc_conf *net_fc;
1191
1192         PMD_INIT_FUNC_TRACE();
1193
1194         if (!(dpaa_intf->fc_conf)) {
1195                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1196                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1197                 if (!dpaa_intf->fc_conf) {
1198                         DPAA_PMD_ERR("unable to save flow control info");
1199                         return -ENOMEM;
1200                 }
1201         }
1202         net_fc = dpaa_intf->fc_conf;
1203
1204         if (fc_conf->high_water < fc_conf->low_water) {
1205                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1206                 return -EINVAL;
1207         }
1208
1209         if (fc_conf->mode == RTE_FC_NONE) {
1210                 return 0;
1211         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1212                  fc_conf->mode == RTE_FC_FULL) {
1213                 fman_if_set_fc_threshold(dev->process_private,
1214                                          fc_conf->high_water,
1215                                          fc_conf->low_water,
1216                                          dpaa_intf->bp_info->bpid);
1217                 if (fc_conf->pause_time)
1218                         fman_if_set_fc_quanta(dev->process_private,
1219                                               fc_conf->pause_time);
1220         }
1221
1222         /* Save the information in dpaa device */
1223         net_fc->pause_time = fc_conf->pause_time;
1224         net_fc->high_water = fc_conf->high_water;
1225         net_fc->low_water = fc_conf->low_water;
1226         net_fc->send_xon = fc_conf->send_xon;
1227         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1228         net_fc->mode = fc_conf->mode;
1229         net_fc->autoneg = fc_conf->autoneg;
1230
1231         return 0;
1232 }
1233
1234 static int
1235 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1236                    struct rte_eth_fc_conf *fc_conf)
1237 {
1238         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1239         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1240         int ret;
1241
1242         PMD_INIT_FUNC_TRACE();
1243
1244         if (net_fc) {
1245                 fc_conf->pause_time = net_fc->pause_time;
1246                 fc_conf->high_water = net_fc->high_water;
1247                 fc_conf->low_water = net_fc->low_water;
1248                 fc_conf->send_xon = net_fc->send_xon;
1249                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1250                 fc_conf->mode = net_fc->mode;
1251                 fc_conf->autoneg = net_fc->autoneg;
1252                 return 0;
1253         }
1254         ret = fman_if_get_fc_threshold(dev->process_private);
1255         if (ret) {
1256                 fc_conf->mode = RTE_FC_TX_PAUSE;
1257                 fc_conf->pause_time =
1258                         fman_if_get_fc_quanta(dev->process_private);
1259         } else {
1260                 fc_conf->mode = RTE_FC_NONE;
1261         }
1262
1263         return 0;
1264 }
1265
1266 static int
1267 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1268                              struct rte_ether_addr *addr,
1269                              uint32_t index,
1270                              __rte_unused uint32_t pool)
1271 {
1272         int ret;
1273
1274         PMD_INIT_FUNC_TRACE();
1275
1276         ret = fman_if_add_mac_addr(dev->process_private,
1277                                    addr->addr_bytes, index);
1278
1279         if (ret)
1280                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1281         return 0;
1282 }
1283
1284 static void
1285 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1286                           uint32_t index)
1287 {
1288         PMD_INIT_FUNC_TRACE();
1289
1290         fman_if_clear_mac_addr(dev->process_private, index);
1291 }
1292
1293 static int
1294 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1295                        struct rte_ether_addr *addr)
1296 {
1297         int ret;
1298
1299         PMD_INIT_FUNC_TRACE();
1300
1301         ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1302         if (ret)
1303                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1304
1305         return ret;
1306 }
1307
1308 static int
1309 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev,
1310                          struct rte_eth_rss_conf *rss_conf)
1311 {
1312         struct rte_eth_dev_data *data = dev->data;
1313         struct rte_eth_conf *eth_conf = &data->dev_conf;
1314
1315         PMD_INIT_FUNC_TRACE();
1316
1317         if (!(default_q || fmc_q)) {
1318                 if (dpaa_fm_config(dev, rss_conf->rss_hf)) {
1319                         DPAA_PMD_ERR("FM port configuration: Failed\n");
1320                         return -1;
1321                 }
1322                 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1323         } else {
1324                 DPAA_PMD_ERR("Function not supported\n");
1325                 return -ENOTSUP;
1326         }
1327         return 0;
1328 }
1329
1330 static int
1331 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1332                            struct rte_eth_rss_conf *rss_conf)
1333 {
1334         struct rte_eth_dev_data *data = dev->data;
1335         struct rte_eth_conf *eth_conf = &data->dev_conf;
1336
1337         /* dpaa does not support rss_key, so length should be 0*/
1338         rss_conf->rss_key_len = 0;
1339         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
1340         return 0;
1341 }
1342
1343 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1344                                       uint16_t queue_id)
1345 {
1346         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1347         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1348
1349         if (!rxq->is_static)
1350                 return -EINVAL;
1351
1352         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1353 }
1354
1355 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1356                                        uint16_t queue_id)
1357 {
1358         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1359         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1360         uint32_t temp;
1361         ssize_t temp1;
1362
1363         if (!rxq->is_static)
1364                 return -EINVAL;
1365
1366         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1367
1368         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1369         if (temp1 != sizeof(temp))
1370                 DPAA_PMD_ERR("irq read error");
1371
1372         qman_fq_portal_thread_irq(rxq->qp);
1373
1374         return 0;
1375 }
1376
1377 static void
1378 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1379         struct rte_eth_rxq_info *qinfo)
1380 {
1381         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1382         struct qman_fq *rxq;
1383
1384         rxq = dev->data->rx_queues[queue_id];
1385
1386         qinfo->mp = dpaa_intf->bp_info->mp;
1387         qinfo->scattered_rx = dev->data->scattered_rx;
1388         qinfo->nb_desc = rxq->nb_desc;
1389         qinfo->conf.rx_free_thresh = 1;
1390         qinfo->conf.rx_drop_en = 1;
1391         qinfo->conf.rx_deferred_start = 0;
1392         qinfo->conf.offloads = rxq->offloads;
1393 }
1394
1395 static void
1396 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1397         struct rte_eth_txq_info *qinfo)
1398 {
1399         struct qman_fq *txq;
1400
1401         txq = dev->data->tx_queues[queue_id];
1402
1403         qinfo->nb_desc = txq->nb_desc;
1404         qinfo->conf.tx_thresh.pthresh = 0;
1405         qinfo->conf.tx_thresh.hthresh = 0;
1406         qinfo->conf.tx_thresh.wthresh = 0;
1407
1408         qinfo->conf.tx_free_thresh = 0;
1409         qinfo->conf.tx_rs_thresh = 0;
1410         qinfo->conf.offloads = txq->offloads;
1411         qinfo->conf.tx_deferred_start = 0;
1412 }
1413
1414 static struct eth_dev_ops dpaa_devops = {
1415         .dev_configure            = dpaa_eth_dev_configure,
1416         .dev_start                = dpaa_eth_dev_start,
1417         .dev_stop                 = dpaa_eth_dev_stop,
1418         .dev_close                = dpaa_eth_dev_close,
1419         .dev_infos_get            = dpaa_eth_dev_info,
1420         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1421
1422         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1423         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1424         .rx_queue_release         = dpaa_eth_rx_queue_release,
1425         .tx_queue_release         = dpaa_eth_tx_queue_release,
1426         .rx_burst_mode_get        = dpaa_dev_rx_burst_mode_get,
1427         .tx_burst_mode_get        = dpaa_dev_tx_burst_mode_get,
1428         .rxq_info_get             = dpaa_rxq_info_get,
1429         .txq_info_get             = dpaa_txq_info_get,
1430
1431         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1432         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1433
1434         .link_update              = dpaa_eth_link_update,
1435         .stats_get                = dpaa_eth_stats_get,
1436         .xstats_get               = dpaa_dev_xstats_get,
1437         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1438         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1439         .xstats_get_names         = dpaa_xstats_get_names,
1440         .xstats_reset             = dpaa_eth_stats_reset,
1441         .stats_reset              = dpaa_eth_stats_reset,
1442         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1443         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1444         .allmulticast_enable      = dpaa_eth_multicast_enable,
1445         .allmulticast_disable     = dpaa_eth_multicast_disable,
1446         .mtu_set                  = dpaa_mtu_set,
1447         .dev_set_link_down        = dpaa_link_down,
1448         .dev_set_link_up          = dpaa_link_up,
1449         .mac_addr_add             = dpaa_dev_add_mac_addr,
1450         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1451         .mac_addr_set             = dpaa_dev_set_mac_addr,
1452
1453         .fw_version_get           = dpaa_fw_version_get,
1454
1455         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1456         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1457         .rss_hash_update          = dpaa_dev_rss_hash_update,
1458         .rss_hash_conf_get        = dpaa_dev_rss_hash_conf_get,
1459 };
1460
1461 static bool
1462 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1463 {
1464         if (strcmp(dev->device->driver->name,
1465                    drv->driver.name))
1466                 return false;
1467
1468         return true;
1469 }
1470
1471 static bool
1472 is_dpaa_supported(struct rte_eth_dev *dev)
1473 {
1474         return is_device_supported(dev, &rte_dpaa_pmd);
1475 }
1476
1477 int
1478 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on)
1479 {
1480         struct rte_eth_dev *dev;
1481
1482         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1483
1484         dev = &rte_eth_devices[port];
1485
1486         if (!is_dpaa_supported(dev))
1487                 return -ENOTSUP;
1488
1489         if (on)
1490                 fman_if_loopback_enable(dev->process_private);
1491         else
1492                 fman_if_loopback_disable(dev->process_private);
1493
1494         return 0;
1495 }
1496
1497 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1498                                struct fman_if *fman_intf)
1499 {
1500         struct rte_eth_fc_conf *fc_conf;
1501         int ret;
1502
1503         PMD_INIT_FUNC_TRACE();
1504
1505         if (!(dpaa_intf->fc_conf)) {
1506                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1507                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1508                 if (!dpaa_intf->fc_conf) {
1509                         DPAA_PMD_ERR("unable to save flow control info");
1510                         return -ENOMEM;
1511                 }
1512         }
1513         fc_conf = dpaa_intf->fc_conf;
1514         ret = fman_if_get_fc_threshold(fman_intf);
1515         if (ret) {
1516                 fc_conf->mode = RTE_FC_TX_PAUSE;
1517                 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1518         } else {
1519                 fc_conf->mode = RTE_FC_NONE;
1520         }
1521
1522         return 0;
1523 }
1524
1525 /* Initialise an Rx FQ */
1526 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1527                               uint32_t fqid)
1528 {
1529         struct qm_mcc_initfq opts = {0};
1530         int ret;
1531         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1532         struct qm_mcc_initcgr cgr_opts = {
1533                 .we_mask = QM_CGR_WE_CS_THRES |
1534                                 QM_CGR_WE_CSTD_EN |
1535                                 QM_CGR_WE_MODE,
1536                 .cgr = {
1537                         .cstd_en = QM_CGR_EN,
1538                         .mode = QMAN_CGR_MODE_FRAME
1539                 }
1540         };
1541
1542         if (fmc_q || default_q) {
1543                 ret = qman_reserve_fqid(fqid);
1544                 if (ret) {
1545                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1546                                      fqid, ret);
1547                         return -EINVAL;
1548                 }
1549         }
1550
1551         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1552         ret = qman_create_fq(fqid, flags, fq);
1553         if (ret) {
1554                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1555                         fqid, ret);
1556                 return ret;
1557         }
1558         fq->is_static = false;
1559
1560         dpaa_poll_queue_default_config(&opts);
1561
1562         if (cgr_rx) {
1563                 /* Enable tail drop with cgr on this queue */
1564                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1565                 cgr_rx->cb = NULL;
1566                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1567                                       &cgr_opts);
1568                 if (ret) {
1569                         DPAA_PMD_WARN(
1570                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1571                                 fq->fqid, ret);
1572                         goto without_cgr;
1573                 }
1574                 opts.we_mask |= QM_INITFQ_WE_CGID;
1575                 opts.fqd.cgid = cgr_rx->cgrid;
1576                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1577         }
1578 without_cgr:
1579         ret = qman_init_fq(fq, 0, &opts);
1580         if (ret)
1581                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1582         return ret;
1583 }
1584
1585 /* Initialise a Tx FQ */
1586 static int dpaa_tx_queue_init(struct qman_fq *fq,
1587                               struct fman_if *fman_intf,
1588                               struct qman_cgr *cgr_tx)
1589 {
1590         struct qm_mcc_initfq opts = {0};
1591         struct qm_mcc_initcgr cgr_opts = {
1592                 .we_mask = QM_CGR_WE_CS_THRES |
1593                                 QM_CGR_WE_CSTD_EN |
1594                                 QM_CGR_WE_MODE,
1595                 .cgr = {
1596                         .cstd_en = QM_CGR_EN,
1597                         .mode = QMAN_CGR_MODE_FRAME
1598                 }
1599         };
1600         int ret;
1601
1602         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1603                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1604         if (ret) {
1605                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1606                 return ret;
1607         }
1608         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1609                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1610         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1611         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1612         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1613         opts.fqd.context_b = 0;
1614         /* no tx-confirmation */
1615         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1616         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1617         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1618
1619         if (cgr_tx) {
1620                 /* Enable tail drop with cgr on this queue */
1621                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1622                                       td_tx_threshold, 0);
1623                 cgr_tx->cb = NULL;
1624                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1625                                       &cgr_opts);
1626                 if (ret) {
1627                         DPAA_PMD_WARN(
1628                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1629                                 fq->fqid, ret);
1630                         goto without_cgr;
1631                 }
1632                 opts.we_mask |= QM_INITFQ_WE_CGID;
1633                 opts.fqd.cgid = cgr_tx->cgrid;
1634                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1635                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1636                                 td_tx_threshold);
1637         }
1638 without_cgr:
1639         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1640         if (ret)
1641                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1642         return ret;
1643 }
1644
1645 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1646 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1647 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1648 {
1649         struct qm_mcc_initfq opts = {0};
1650         int ret;
1651
1652         PMD_INIT_FUNC_TRACE();
1653
1654         ret = qman_reserve_fqid(fqid);
1655         if (ret) {
1656                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1657                         fqid, ret);
1658                 return -EINVAL;
1659         }
1660         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1661         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1662         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1663         if (ret) {
1664                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1665                         fqid, ret);
1666                 return ret;
1667         }
1668         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1669         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1670         ret = qman_init_fq(fq, 0, &opts);
1671         if (ret)
1672                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1673                             fqid, ret);
1674         return ret;
1675 }
1676 #endif
1677
1678 /* Initialise a network interface */
1679 static int
1680 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1681 {
1682         struct rte_dpaa_device *dpaa_device;
1683         struct fm_eth_port_cfg *cfg;
1684         struct dpaa_if *dpaa_intf;
1685         struct fman_if *fman_intf;
1686         int dev_id;
1687
1688         PMD_INIT_FUNC_TRACE();
1689
1690         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1691         dev_id = dpaa_device->id.dev_id;
1692         cfg = dpaa_get_eth_port_cfg(dev_id);
1693         fman_intf = cfg->fman_if;
1694         eth_dev->process_private = fman_intf;
1695
1696         /* Plugging of UCODE burst API not supported in Secondary */
1697         dpaa_intf = eth_dev->data->dev_private;
1698         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1699         if (dpaa_intf->cgr_tx)
1700                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1701         else
1702                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1703 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1704         qman_set_fq_lookup_table(
1705                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1706 #endif
1707
1708         return 0;
1709 }
1710
1711 /* Initialise a network interface */
1712 static int
1713 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1714 {
1715         int num_rx_fqs, fqid;
1716         int loop, ret = 0;
1717         int dev_id;
1718         struct rte_dpaa_device *dpaa_device;
1719         struct dpaa_if *dpaa_intf;
1720         struct fm_eth_port_cfg *cfg;
1721         struct fman_if *fman_intf;
1722         struct fman_if_bpool *bp, *tmp_bp;
1723         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1724         uint32_t cgrid_tx[MAX_DPAA_CORES];
1725         uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1726         int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES];
1727         int8_t vsp_id = -1;
1728
1729         PMD_INIT_FUNC_TRACE();
1730
1731         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1732         dev_id = dpaa_device->id.dev_id;
1733         dpaa_intf = eth_dev->data->dev_private;
1734         cfg = dpaa_get_eth_port_cfg(dev_id);
1735         fman_intf = cfg->fman_if;
1736
1737         dpaa_intf->name = dpaa_device->name;
1738
1739         /* save fman_if & cfg in the interface struture */
1740         eth_dev->process_private = fman_intf;
1741         dpaa_intf->ifid = dev_id;
1742         dpaa_intf->cfg = cfg;
1743
1744         memset((char *)dev_rx_fqids, 0,
1745                 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1746
1747         memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES);
1748
1749         /* Initialize Rx FQ's */
1750         if (default_q) {
1751                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1752         } else if (fmc_q) {
1753                 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids,
1754                                                 dev_vspids,
1755                                                 DPAA_MAX_NUM_PCD_QUEUES);
1756                 if (num_rx_fqs < 0) {
1757                         DPAA_PMD_ERR("%s FMC initializes failed!",
1758                                 dpaa_intf->name);
1759                         goto free_rx;
1760                 }
1761                 if (!num_rx_fqs) {
1762                         DPAA_PMD_WARN("%s is not configured by FMC.",
1763                                 dpaa_intf->name);
1764                 }
1765         } else {
1766                 /* FMCLESS mode, load balance to multiple cores.*/
1767                 num_rx_fqs = rte_lcore_count();
1768         }
1769
1770         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1771          * queues.
1772          */
1773         if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1774                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1775                 return -EINVAL;
1776         }
1777
1778         if (num_rx_fqs > 0) {
1779                 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1780                         sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1781                 if (!dpaa_intf->rx_queues) {
1782                         DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1783                         return -ENOMEM;
1784                 }
1785         } else {
1786                 dpaa_intf->rx_queues = NULL;
1787         }
1788
1789         memset(cgrid, 0, sizeof(cgrid));
1790         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1791
1792         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1793          * Tx tail drop is disabled.
1794          */
1795         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1796                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1797                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1798                                td_tx_threshold);
1799                 /* if a very large value is being configured */
1800                 if (td_tx_threshold > UINT16_MAX)
1801                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1802         }
1803
1804         /* If congestion control is enabled globally*/
1805         if (num_rx_fqs > 0 && td_threshold) {
1806                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1807                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1808                 if (!dpaa_intf->cgr_rx) {
1809                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1810                         ret = -ENOMEM;
1811                         goto free_rx;
1812                 }
1813
1814                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1815                 if (ret != num_rx_fqs) {
1816                         DPAA_PMD_WARN("insufficient CGRIDs available");
1817                         ret = -EINVAL;
1818                         goto free_rx;
1819                 }
1820         } else {
1821                 dpaa_intf->cgr_rx = NULL;
1822         }
1823
1824         if (!fmc_q && !default_q) {
1825                 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1826                                             num_rx_fqs, 0);
1827                 if (ret < 0) {
1828                         DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1829                         goto free_rx;
1830                 }
1831         }
1832
1833         for (loop = 0; loop < num_rx_fqs; loop++) {
1834                 if (default_q)
1835                         fqid = cfg->rx_def;
1836                 else
1837                         fqid = dev_rx_fqids[loop];
1838
1839                 vsp_id = dev_vspids[loop];
1840
1841                 if (dpaa_intf->cgr_rx)
1842                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1843
1844                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1845                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1846                         fqid);
1847                 if (ret)
1848                         goto free_rx;
1849                 dpaa_intf->rx_queues[loop].vsp_id = vsp_id;
1850                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1851         }
1852         dpaa_intf->nb_rx_queues = num_rx_fqs;
1853
1854         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1855         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1856                 MAX_DPAA_CORES, MAX_CACHELINE);
1857         if (!dpaa_intf->tx_queues) {
1858                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1859                 ret = -ENOMEM;
1860                 goto free_rx;
1861         }
1862
1863         /* If congestion control is enabled globally*/
1864         if (td_tx_threshold) {
1865                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1866                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1867                         MAX_CACHELINE);
1868                 if (!dpaa_intf->cgr_tx) {
1869                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1870                         ret = -ENOMEM;
1871                         goto free_rx;
1872                 }
1873
1874                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1875                                              1, 0);
1876                 if (ret != MAX_DPAA_CORES) {
1877                         DPAA_PMD_WARN("insufficient CGRIDs available");
1878                         ret = -EINVAL;
1879                         goto free_rx;
1880                 }
1881         } else {
1882                 dpaa_intf->cgr_tx = NULL;
1883         }
1884
1885
1886         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1887                 if (dpaa_intf->cgr_tx)
1888                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
1889
1890                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1891                         fman_intf,
1892                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
1893                 if (ret)
1894                         goto free_tx;
1895                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1896         }
1897         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1898
1899 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1900         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1901                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1902         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1903         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1904                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1905         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1906 #endif
1907
1908         DPAA_PMD_DEBUG("All frame queues created");
1909
1910         /* Get the initial configuration for flow control */
1911         dpaa_fc_set_default(dpaa_intf, fman_intf);
1912
1913         /* reset bpool list, initialize bpool dynamically */
1914         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1915                 list_del(&bp->node);
1916                 rte_free(bp);
1917         }
1918
1919         /* Populate ethdev structure */
1920         eth_dev->dev_ops = &dpaa_devops;
1921         eth_dev->rx_queue_count = dpaa_dev_rx_queue_count;
1922         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1923         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1924
1925         /* Allocate memory for storing MAC addresses */
1926         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1927                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1928         if (eth_dev->data->mac_addrs == NULL) {
1929                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1930                                                 "store MAC addresses",
1931                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1932                 ret = -ENOMEM;
1933                 goto free_tx;
1934         }
1935
1936         /* copy the primary mac address */
1937         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1938
1939         RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1940                 dpaa_device->name,
1941                 fman_intf->mac_addr.addr_bytes[0],
1942                 fman_intf->mac_addr.addr_bytes[1],
1943                 fman_intf->mac_addr.addr_bytes[2],
1944                 fman_intf->mac_addr.addr_bytes[3],
1945                 fman_intf->mac_addr.addr_bytes[4],
1946                 fman_intf->mac_addr.addr_bytes[5]);
1947
1948         if (!fman_intf->is_shared_mac) {
1949                 /* Disable RX mode */
1950                 fman_if_discard_rx_errors(fman_intf);
1951                 fman_if_disable_rx(fman_intf);
1952                 /* Disable promiscuous mode */
1953                 fman_if_promiscuous_disable(fman_intf);
1954                 /* Disable multicast */
1955                 fman_if_reset_mcast_filter_table(fman_intf);
1956                 /* Reset interface statistics */
1957                 fman_if_stats_reset(fman_intf);
1958                 /* Disable SG by default */
1959                 fman_if_set_sg(fman_intf, 0);
1960                 fman_if_set_maxfrm(fman_intf,
1961                                    RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1962         }
1963
1964         return 0;
1965
1966 free_tx:
1967         rte_free(dpaa_intf->tx_queues);
1968         dpaa_intf->tx_queues = NULL;
1969         dpaa_intf->nb_tx_queues = 0;
1970
1971 free_rx:
1972         rte_free(dpaa_intf->cgr_rx);
1973         rte_free(dpaa_intf->cgr_tx);
1974         rte_free(dpaa_intf->rx_queues);
1975         dpaa_intf->rx_queues = NULL;
1976         dpaa_intf->nb_rx_queues = 0;
1977         return ret;
1978 }
1979
1980 static int
1981 dpaa_dev_uninit(struct rte_eth_dev *dev)
1982 {
1983         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1984         int loop;
1985
1986         PMD_INIT_FUNC_TRACE();
1987
1988         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1989                 return -EPERM;
1990
1991         if (!dpaa_intf) {
1992                 DPAA_PMD_WARN("Already closed or not started");
1993                 return -1;
1994         }
1995
1996         /* DPAA FM deconfig */
1997         if (!(default_q || fmc_q)) {
1998                 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
1999                         DPAA_PMD_WARN("DPAA FM deconfig failed\n");
2000         }
2001
2002         dpaa_eth_dev_close(dev);
2003
2004         /* release configuration memory */
2005         if (dpaa_intf->fc_conf)
2006                 rte_free(dpaa_intf->fc_conf);
2007
2008         /* Release RX congestion Groups */
2009         if (dpaa_intf->cgr_rx) {
2010                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
2011                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
2012
2013                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
2014                                          dpaa_intf->nb_rx_queues);
2015         }
2016
2017         rte_free(dpaa_intf->cgr_rx);
2018         dpaa_intf->cgr_rx = NULL;
2019
2020         /* Release TX congestion Groups */
2021         if (dpaa_intf->cgr_tx) {
2022                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
2023                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
2024
2025                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
2026                                          MAX_DPAA_CORES);
2027                 rte_free(dpaa_intf->cgr_tx);
2028                 dpaa_intf->cgr_tx = NULL;
2029         }
2030
2031         rte_free(dpaa_intf->rx_queues);
2032         dpaa_intf->rx_queues = NULL;
2033
2034         rte_free(dpaa_intf->tx_queues);
2035         dpaa_intf->tx_queues = NULL;
2036
2037         dev->dev_ops = NULL;
2038         dev->rx_pkt_burst = NULL;
2039         dev->tx_pkt_burst = NULL;
2040
2041         return 0;
2042 }
2043
2044 static int
2045 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
2046                struct rte_dpaa_device *dpaa_dev)
2047 {
2048         int diag;
2049         int ret;
2050         struct rte_eth_dev *eth_dev;
2051
2052         PMD_INIT_FUNC_TRACE();
2053
2054         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
2055                 RTE_PKTMBUF_HEADROOM) {
2056                 DPAA_PMD_ERR(
2057                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
2058                 RTE_PKTMBUF_HEADROOM,
2059                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
2060
2061                 return -1;
2062         }
2063
2064         /* In case of secondary process, the device is already configured
2065          * and no further action is required, except portal initialization
2066          * and verifying secondary attachment to port name.
2067          */
2068         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2069                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
2070                 if (!eth_dev)
2071                         return -ENOMEM;
2072                 eth_dev->device = &dpaa_dev->device;
2073                 eth_dev->dev_ops = &dpaa_devops;
2074
2075                 ret = dpaa_dev_init_secondary(eth_dev);
2076                 if (ret != 0) {
2077                         RTE_LOG(ERR, PMD, "secondary dev init failed\n");
2078                         return ret;
2079                 }
2080
2081                 rte_eth_dev_probing_finish(eth_dev);
2082                 return 0;
2083         }
2084
2085         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
2086                 if (access("/tmp/fmc.bin", F_OK) == -1) {
2087                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
2088                         default_q = 1;
2089                 }
2090
2091                 if (!(default_q || fmc_q)) {
2092                         if (dpaa_fm_init()) {
2093                                 DPAA_PMD_ERR("FM init failed\n");
2094                                 return -1;
2095                         }
2096                 }
2097
2098                 /* disabling the default push mode for LS1043 */
2099                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
2100                         dpaa_push_mode_max_queue = 0;
2101
2102                 /* if push mode queues to be enabled. Currenly we are allowing
2103                  * only one queue per thread.
2104                  */
2105                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
2106                         dpaa_push_mode_max_queue =
2107                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
2108                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
2109                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
2110                 }
2111
2112                 is_global_init = 1;
2113         }
2114
2115         if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
2116                 ret = rte_dpaa_portal_init((void *)1);
2117                 if (ret) {
2118                         DPAA_PMD_ERR("Unable to initialize portal");
2119                         return ret;
2120                 }
2121         }
2122
2123         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
2124         if (!eth_dev)
2125                 return -ENOMEM;
2126
2127         eth_dev->data->dev_private =
2128                         rte_zmalloc("ethdev private structure",
2129                                         sizeof(struct dpaa_if),
2130                                         RTE_CACHE_LINE_SIZE);
2131         if (!eth_dev->data->dev_private) {
2132                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
2133                 rte_eth_dev_release_port(eth_dev);
2134                 return -ENOMEM;
2135         }
2136
2137         eth_dev->device = &dpaa_dev->device;
2138         dpaa_dev->eth_dev = eth_dev;
2139
2140         qman_ern_register_cb(dpaa_free_mbuf);
2141
2142         if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2143                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2144
2145         /* Invoke PMD device initialization function */
2146         diag = dpaa_dev_init(eth_dev);
2147         if (diag == 0) {
2148                 rte_eth_dev_probing_finish(eth_dev);
2149                 return 0;
2150         }
2151
2152         rte_eth_dev_release_port(eth_dev);
2153         return diag;
2154 }
2155
2156 static int
2157 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2158 {
2159         struct rte_eth_dev *eth_dev;
2160
2161         PMD_INIT_FUNC_TRACE();
2162
2163         eth_dev = dpaa_dev->eth_dev;
2164         dpaa_dev_uninit(eth_dev);
2165
2166         rte_eth_dev_release_port(eth_dev);
2167
2168         return 0;
2169 }
2170
2171 static void __attribute__((destructor(102))) dpaa_finish(void)
2172 {
2173         /* For secondary, primary will do all the cleanup */
2174         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2175                 return;
2176
2177         if (!(default_q || fmc_q)) {
2178                 unsigned int i;
2179
2180                 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2181                         if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2182                                 struct rte_eth_dev *dev = &rte_eth_devices[i];
2183                                 struct dpaa_if *dpaa_intf =
2184                                         dev->data->dev_private;
2185                                 struct fman_if *fif =
2186                                         dev->process_private;
2187                                 if (dpaa_intf->port_handle)
2188                                         if (dpaa_fm_deconfig(dpaa_intf, fif))
2189                                                 DPAA_PMD_WARN("DPAA FM "
2190                                                         "deconfig failed\n");
2191                                 if (fif->num_profiles) {
2192                                         if (dpaa_port_vsp_cleanup(dpaa_intf,
2193                                                                   fif))
2194                                                 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n");
2195                                 }
2196                         }
2197                 }
2198                 if (is_global_init)
2199                         if (dpaa_fm_term())
2200                                 DPAA_PMD_WARN("DPAA FM term failed\n");
2201
2202                 is_global_init = 0;
2203
2204                 DPAA_PMD_INFO("DPAA fman cleaned up");
2205         }
2206 }
2207
2208 static struct rte_dpaa_driver rte_dpaa_pmd = {
2209         .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2210         .drv_type = FSL_DPAA_ETH,
2211         .probe = rte_dpaa_probe,
2212         .remove = rte_dpaa_remove,
2213 };
2214
2215 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2216 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);