1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2017-2020 NXP
15 #include <sys/types.h>
16 #include <sys/syscall.h>
18 #include <rte_string_fns.h>
19 #include <rte_byteorder.h>
20 #include <rte_common.h>
21 #include <rte_interrupts.h>
23 #include <rte_debug.h>
25 #include <rte_atomic.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_memory.h>
28 #include <rte_tailq.h>
30 #include <rte_alarm.h>
31 #include <rte_ether.h>
32 #include <ethdev_driver.h>
33 #include <rte_malloc.h>
36 #include <rte_dpaa_bus.h>
37 #include <rte_dpaa_logs.h>
38 #include <dpaa_mempool.h>
40 #include <dpaa_ethdev.h>
41 #include <dpaa_rxtx.h>
42 #include <dpaa_flow.h>
43 #include <rte_pmd_dpaa.h>
50 #include <fmlib/fm_ext.h>
52 #define CHECK_INTERVAL 100 /* 100ms */
53 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */
55 /* Supported Rx offloads */
56 static uint64_t dev_rx_offloads_sup =
57 RTE_ETH_RX_OFFLOAD_SCATTER;
59 /* Rx offloads which cannot be disabled */
60 static uint64_t dev_rx_offloads_nodis =
61 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
62 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
63 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
64 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
65 RTE_ETH_RX_OFFLOAD_RSS_HASH;
67 /* Supported Tx offloads */
68 static uint64_t dev_tx_offloads_sup =
69 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |
70 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
72 /* Tx offloads which cannot be disabled */
73 static uint64_t dev_tx_offloads_nodis =
74 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
75 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
76 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
77 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
78 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
79 RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
81 /* Keep track of whether QMAN and BMAN have been globally initialized */
82 static int is_global_init;
83 static int fmc_q = 1; /* Indicates the use of static fmc for distribution */
84 static int default_q; /* use default queue - FMC is not executed*/
85 /* At present we only allow up to 4 push mode queues as default - as each of
86 * this queue need dedicated portal and we are short of portals.
88 #define DPAA_MAX_PUSH_MODE_QUEUE 8
89 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
91 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
92 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
95 /* Per RX FQ Taildrop in frame count */
96 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
98 /* Per TX FQ Taildrop in frame count, disabled by default */
99 static unsigned int td_tx_threshold;
101 struct rte_dpaa_xstats_name_off {
102 char name[RTE_ETH_XSTATS_NAME_SIZE];
106 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
108 offsetof(struct dpaa_if_stats, raln)},
110 offsetof(struct dpaa_if_stats, rxpf)},
112 offsetof(struct dpaa_if_stats, rfcs)},
114 offsetof(struct dpaa_if_stats, rvlan)},
116 offsetof(struct dpaa_if_stats, rerr)},
118 offsetof(struct dpaa_if_stats, rdrp)},
120 offsetof(struct dpaa_if_stats, rund)},
122 offsetof(struct dpaa_if_stats, rovr)},
124 offsetof(struct dpaa_if_stats, rfrg)},
126 offsetof(struct dpaa_if_stats, txpf)},
128 offsetof(struct dpaa_if_stats, terr)},
130 offsetof(struct dpaa_if_stats, tvlan)},
132 offsetof(struct dpaa_if_stats, tund)},
135 static struct rte_dpaa_driver rte_dpaa_pmd;
138 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
140 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
141 int wait_to_complete __rte_unused);
143 static void dpaa_interrupt_handler(void *param);
146 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
148 memset(opts, 0, sizeof(struct qm_mcc_initfq));
149 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
150 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
151 QM_FQCTRL_PREFERINCACHE;
152 opts->fqd.context_a.stashing.exclusive = 0;
153 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
154 opts->fqd.context_a.stashing.annotation_cl =
155 DPAA_IF_RX_ANNOTATION_STASH;
156 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
157 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
161 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
163 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
165 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
167 PMD_INIT_FUNC_TRACE();
170 * Refuse mtu that requires the support of scattered packets
171 * when this feature has not been enabled before.
173 if (dev->data->min_rx_buf_size &&
174 !dev->data->scattered_rx && frame_size > buffsz) {
175 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
179 /* check <seg size> * <max_seg> >= max_frame */
180 if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
181 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
182 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
183 buffsz * DPAA_SGT_MAX_ENTRIES);
187 fman_if_set_maxfrm(dev->process_private, frame_size);
193 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
195 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
196 uint64_t rx_offloads = eth_conf->rxmode.offloads;
197 uint64_t tx_offloads = eth_conf->txmode.offloads;
198 struct rte_device *rdev = dev->device;
199 struct rte_eth_link *link = &dev->data->dev_link;
200 struct rte_dpaa_device *dpaa_dev;
201 struct fman_if *fif = dev->process_private;
202 struct __fman_if *__fif;
203 struct rte_intr_handle *intr_handle;
204 uint32_t max_rx_pktlen;
208 PMD_INIT_FUNC_TRACE();
210 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
211 intr_handle = &dpaa_dev->intr_handle;
212 __fif = container_of(fif, struct __fman_if, __if);
214 /* Rx offloads which are enabled by default */
215 if (dev_rx_offloads_nodis & ~rx_offloads) {
217 "Some of rx offloads enabled by default - requested 0x%" PRIx64
218 " fixed are 0x%" PRIx64,
219 rx_offloads, dev_rx_offloads_nodis);
222 /* Tx offloads which are enabled by default */
223 if (dev_tx_offloads_nodis & ~tx_offloads) {
225 "Some of tx offloads enabled by default - requested 0x%" PRIx64
226 " fixed are 0x%" PRIx64,
227 tx_offloads, dev_tx_offloads_nodis);
230 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN +
231 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
232 if (max_rx_pktlen > DPAA_MAX_RX_PKT_LEN) {
233 DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
235 max_rx_pktlen, DPAA_MAX_RX_PKT_LEN);
236 max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
239 fman_if_set_maxfrm(dev->process_private, max_rx_pktlen);
241 if (rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) {
242 DPAA_PMD_DEBUG("enabling scatter mode");
243 fman_if_set_sg(dev->process_private, 1);
244 dev->data->scattered_rx = 1;
247 if (!(default_q || fmc_q)) {
248 if (dpaa_fm_config(dev,
249 eth_conf->rx_adv_conf.rss_conf.rss_hf)) {
250 dpaa_write_fm_config_to_file();
251 DPAA_PMD_ERR("FM port configuration: Failed\n");
254 dpaa_write_fm_config_to_file();
257 /* if the interrupts were configured on this devices*/
258 if (intr_handle && intr_handle->fd) {
259 if (dev->data->dev_conf.intr_conf.lsc != 0)
260 rte_intr_callback_register(intr_handle,
261 dpaa_interrupt_handler,
264 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
266 if (dev->data->dev_conf.intr_conf.lsc != 0) {
267 rte_intr_callback_unregister(intr_handle,
268 dpaa_interrupt_handler,
271 printf("Failed to enable interrupt: Not Supported\n");
273 printf("Failed to enable interrupt\n");
275 dev->data->dev_conf.intr_conf.lsc = 0;
276 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
280 /* Wait for link status to get updated */
281 if (!link->link_status)
284 /* Configure link only if link is UP*/
285 if (link->link_status) {
286 if (eth_conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
287 /* Start autoneg only if link is not in autoneg mode */
288 if (!link->link_autoneg)
289 dpaa_restart_link_autoneg(__fif->node_name);
290 } else if (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
291 switch (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
292 case RTE_ETH_LINK_SPEED_10M_HD:
293 speed = RTE_ETH_SPEED_NUM_10M;
294 duplex = RTE_ETH_LINK_HALF_DUPLEX;
296 case RTE_ETH_LINK_SPEED_10M:
297 speed = RTE_ETH_SPEED_NUM_10M;
298 duplex = RTE_ETH_LINK_FULL_DUPLEX;
300 case RTE_ETH_LINK_SPEED_100M_HD:
301 speed = RTE_ETH_SPEED_NUM_100M;
302 duplex = RTE_ETH_LINK_HALF_DUPLEX;
304 case RTE_ETH_LINK_SPEED_100M:
305 speed = RTE_ETH_SPEED_NUM_100M;
306 duplex = RTE_ETH_LINK_FULL_DUPLEX;
308 case RTE_ETH_LINK_SPEED_1G:
309 speed = RTE_ETH_SPEED_NUM_1G;
310 duplex = RTE_ETH_LINK_FULL_DUPLEX;
312 case RTE_ETH_LINK_SPEED_2_5G:
313 speed = RTE_ETH_SPEED_NUM_2_5G;
314 duplex = RTE_ETH_LINK_FULL_DUPLEX;
316 case RTE_ETH_LINK_SPEED_10G:
317 speed = RTE_ETH_SPEED_NUM_10G;
318 duplex = RTE_ETH_LINK_FULL_DUPLEX;
321 speed = RTE_ETH_SPEED_NUM_NONE;
322 duplex = RTE_ETH_LINK_FULL_DUPLEX;
326 dpaa_update_link_speed(__fif->node_name, speed, duplex);
328 /* Manual autoneg - custom advertisement speed. */
329 printf("Custom Advertisement speeds not supported\n");
336 static const uint32_t *
337 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
339 static const uint32_t ptypes[] = {
341 RTE_PTYPE_L2_ETHER_VLAN,
342 RTE_PTYPE_L2_ETHER_ARP,
343 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
344 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
354 PMD_INIT_FUNC_TRACE();
356 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
361 static void dpaa_interrupt_handler(void *param)
363 struct rte_eth_dev *dev = param;
364 struct rte_device *rdev = dev->device;
365 struct rte_dpaa_device *dpaa_dev;
366 struct rte_intr_handle *intr_handle;
370 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
371 intr_handle = &dpaa_dev->intr_handle;
373 bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
375 DPAA_PMD_ERR("Error reading eventfd\n");
376 dpaa_eth_link_update(dev, 0);
377 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
380 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
382 struct dpaa_if *dpaa_intf = dev->data->dev_private;
384 PMD_INIT_FUNC_TRACE();
386 if (!(default_q || fmc_q))
387 dpaa_write_fm_config_to_file();
389 /* Change tx callback to the real one */
390 if (dpaa_intf->cgr_tx)
391 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
393 dev->tx_pkt_burst = dpaa_eth_queue_tx;
395 fman_if_enable_rx(dev->process_private);
400 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev)
402 struct fman_if *fif = dev->process_private;
404 PMD_INIT_FUNC_TRACE();
405 dev->data->dev_started = 0;
407 if (!fif->is_shared_mac)
408 fman_if_disable_rx(fif);
409 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
414 static int dpaa_eth_dev_close(struct rte_eth_dev *dev)
416 struct fman_if *fif = dev->process_private;
417 struct __fman_if *__fif;
418 struct rte_device *rdev = dev->device;
419 struct rte_dpaa_device *dpaa_dev;
420 struct rte_intr_handle *intr_handle;
421 struct rte_eth_link *link = &dev->data->dev_link;
422 struct dpaa_if *dpaa_intf = dev->data->dev_private;
426 PMD_INIT_FUNC_TRACE();
428 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
432 DPAA_PMD_WARN("Already closed or not started");
436 /* DPAA FM deconfig */
437 if (!(default_q || fmc_q)) {
438 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
439 DPAA_PMD_WARN("DPAA FM deconfig failed\n");
442 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
443 intr_handle = &dpaa_dev->intr_handle;
444 __fif = container_of(fif, struct __fman_if, __if);
446 ret = dpaa_eth_dev_stop(dev);
448 /* Reset link to autoneg */
449 if (link->link_status && !link->link_autoneg)
450 dpaa_restart_link_autoneg(__fif->node_name);
452 if (intr_handle && intr_handle->fd &&
453 dev->data->dev_conf.intr_conf.lsc != 0) {
454 dpaa_intr_disable(__fif->node_name);
455 rte_intr_callback_unregister(intr_handle,
456 dpaa_interrupt_handler,
460 /* release configuration memory */
461 if (dpaa_intf->fc_conf)
462 rte_free(dpaa_intf->fc_conf);
464 /* Release RX congestion Groups */
465 if (dpaa_intf->cgr_rx) {
466 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
467 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
470 rte_free(dpaa_intf->cgr_rx);
471 dpaa_intf->cgr_rx = NULL;
472 /* Release TX congestion Groups */
473 if (dpaa_intf->cgr_tx) {
474 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
475 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
476 rte_free(dpaa_intf->cgr_tx);
477 dpaa_intf->cgr_tx = NULL;
480 rte_free(dpaa_intf->rx_queues);
481 dpaa_intf->rx_queues = NULL;
483 rte_free(dpaa_intf->tx_queues);
484 dpaa_intf->tx_queues = NULL;
490 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
495 FILE *svr_file = NULL;
496 unsigned int svr_ver = 0;
498 PMD_INIT_FUNC_TRACE();
500 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
502 DPAA_PMD_ERR("Unable to open SoC device");
503 return -ENOTSUP; /* Not supported on this infra */
505 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
506 dpaa_svr_family = svr_ver & SVR_MASK;
508 DPAA_PMD_ERR("Unable to read SoC device");
512 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
513 svr_ver, fman_ip_rev);
517 ret += 1; /* add the size of '\0' */
518 if (fw_size < (size_t)ret)
524 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
525 struct rte_eth_dev_info *dev_info)
527 struct dpaa_if *dpaa_intf = dev->data->dev_private;
528 struct fman_if *fif = dev->process_private;
530 DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
532 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
533 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
534 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
535 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
536 dev_info->max_hash_mac_addrs = 0;
537 dev_info->max_vfs = 0;
538 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
539 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
541 if (fif->mac_type == fman_mac_1g) {
542 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD
543 | RTE_ETH_LINK_SPEED_10M
544 | RTE_ETH_LINK_SPEED_100M_HD
545 | RTE_ETH_LINK_SPEED_100M
546 | RTE_ETH_LINK_SPEED_1G;
547 } else if (fif->mac_type == fman_mac_2_5g) {
548 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD
549 | RTE_ETH_LINK_SPEED_10M
550 | RTE_ETH_LINK_SPEED_100M_HD
551 | RTE_ETH_LINK_SPEED_100M
552 | RTE_ETH_LINK_SPEED_1G
553 | RTE_ETH_LINK_SPEED_2_5G;
554 } else if (fif->mac_type == fman_mac_10g) {
555 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD
556 | RTE_ETH_LINK_SPEED_10M
557 | RTE_ETH_LINK_SPEED_100M_HD
558 | RTE_ETH_LINK_SPEED_100M
559 | RTE_ETH_LINK_SPEED_1G
560 | RTE_ETH_LINK_SPEED_2_5G
561 | RTE_ETH_LINK_SPEED_10G;
563 DPAA_PMD_ERR("invalid link_speed: %s, %d",
564 dpaa_intf->name, fif->mac_type);
568 dev_info->rx_offload_capa = dev_rx_offloads_sup |
569 dev_rx_offloads_nodis;
570 dev_info->tx_offload_capa = dev_tx_offloads_sup |
571 dev_tx_offloads_nodis;
572 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
573 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
574 dev_info->default_rxportconf.nb_queues = 1;
575 dev_info->default_txportconf.nb_queues = 1;
576 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
577 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
583 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
584 __rte_unused uint16_t queue_id,
585 struct rte_eth_burst_mode *mode)
587 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
590 const struct burst_info {
593 } rx_offload_map[] = {
594 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"},
595 {RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
596 {RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
597 {RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
598 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
599 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"}
602 /* Update Rx offload info */
603 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
604 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
605 snprintf(mode->info, sizeof(mode->info), "%s",
606 rx_offload_map[i].output);
615 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
616 __rte_unused uint16_t queue_id,
617 struct rte_eth_burst_mode *mode)
619 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
622 const struct burst_info {
625 } tx_offload_map[] = {
626 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
627 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
628 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
629 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
630 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
631 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
632 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
633 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
636 /* Update Tx offload info */
637 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
638 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
639 snprintf(mode->info, sizeof(mode->info), "%s",
640 tx_offload_map[i].output);
648 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
649 int wait_to_complete)
651 struct dpaa_if *dpaa_intf = dev->data->dev_private;
652 struct rte_eth_link *link = &dev->data->dev_link;
653 struct fman_if *fif = dev->process_private;
654 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
655 int ret, ioctl_version;
658 PMD_INIT_FUNC_TRACE();
660 ioctl_version = dpaa_get_ioctl_version_number();
662 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
663 for (count = 0; count <= MAX_REPEAT_TIME; count++) {
664 ret = dpaa_get_link_status(__fif->node_name, link);
667 if (link->link_status == RTE_ETH_LINK_DOWN &&
669 rte_delay_ms(CHECK_INTERVAL);
674 link->link_status = dpaa_intf->valid;
677 if (ioctl_version < 2) {
678 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
679 link->link_autoneg = RTE_ETH_LINK_AUTONEG;
681 if (fif->mac_type == fman_mac_1g)
682 link->link_speed = RTE_ETH_SPEED_NUM_1G;
683 else if (fif->mac_type == fman_mac_2_5g)
684 link->link_speed = RTE_ETH_SPEED_NUM_2_5G;
685 else if (fif->mac_type == fman_mac_10g)
686 link->link_speed = RTE_ETH_SPEED_NUM_10G;
688 DPAA_PMD_ERR("invalid link_speed: %s, %d",
689 dpaa_intf->name, fif->mac_type);
692 DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
693 link->link_status ? "Up" : "Down");
697 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
698 struct rte_eth_stats *stats)
700 PMD_INIT_FUNC_TRACE();
702 fman_if_stats_get(dev->process_private, stats);
706 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
708 PMD_INIT_FUNC_TRACE();
710 fman_if_stats_reset(dev->process_private);
716 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
719 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
720 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
728 fman_if_stats_get_all(dev->process_private, values,
729 sizeof(struct dpaa_if_stats) / 8);
731 for (i = 0; i < num; i++) {
733 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
739 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
740 struct rte_eth_xstat_name *xstats_names,
743 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
745 if (limit < stat_cnt)
748 if (xstats_names != NULL)
749 for (i = 0; i < stat_cnt; i++)
750 strlcpy(xstats_names[i].name,
751 dpaa_xstats_strings[i].name,
752 sizeof(xstats_names[i].name));
758 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
759 uint64_t *values, unsigned int n)
761 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
762 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
771 fman_if_stats_get_all(dev->process_private, values_copy,
772 sizeof(struct dpaa_if_stats) / 8);
774 for (i = 0; i < stat_cnt; i++)
776 values_copy[dpaa_xstats_strings[i].offset / 8];
781 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
783 for (i = 0; i < n; i++) {
784 if (ids[i] >= stat_cnt) {
785 DPAA_PMD_ERR("id value isn't valid");
788 values[i] = values_copy[ids[i]];
794 dpaa_xstats_get_names_by_id(
795 struct rte_eth_dev *dev,
797 struct rte_eth_xstat_name *xstats_names,
800 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
801 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
804 return dpaa_xstats_get_names(dev, xstats_names, limit);
806 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
808 for (i = 0; i < limit; i++) {
809 if (ids[i] >= stat_cnt) {
810 DPAA_PMD_ERR("id value isn't valid");
813 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
818 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
820 PMD_INIT_FUNC_TRACE();
822 fman_if_promiscuous_enable(dev->process_private);
827 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
829 PMD_INIT_FUNC_TRACE();
831 fman_if_promiscuous_disable(dev->process_private);
836 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
838 PMD_INIT_FUNC_TRACE();
840 fman_if_set_mcast_filter_table(dev->process_private);
845 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
847 PMD_INIT_FUNC_TRACE();
849 fman_if_reset_mcast_filter_table(dev->process_private);
854 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev)
856 struct dpaa_if *dpaa_intf = dev->data->dev_private;
857 struct fman_if_ic_params icp;
861 memset(&icp, 0, sizeof(icp));
862 /* set ICEOF for to the default value , which is 0*/
863 icp.iciof = DEFAULT_ICIOF;
864 icp.iceof = DEFAULT_RX_ICEOF;
865 icp.icsz = DEFAULT_ICSZ;
866 fman_if_set_ic_params(dev->process_private, &icp);
868 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
869 fman_if_set_fdoff(dev->process_private, fd_offset);
871 /* Buffer pool size should be equal to Dataroom Size*/
872 bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp);
874 fman_if_set_bp(dev->process_private,
875 dpaa_intf->bp_info->mp->size,
876 dpaa_intf->bp_info->bpid, bp_size);
879 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev,
880 int8_t vsp_id, uint32_t bpid)
882 struct dpaa_if *dpaa_intf = dev->data->dev_private;
883 struct fman_if *fif = dev->process_private;
885 if (fif->num_profiles) {
887 vsp_id = fif->base_profile_id;
893 if (dpaa_intf->vsp_bpid[vsp_id] &&
894 bpid != dpaa_intf->vsp_bpid[vsp_id]) {
895 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP");
904 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
906 unsigned int socket_id __rte_unused,
907 const struct rte_eth_rxconf *rx_conf,
908 struct rte_mempool *mp)
910 struct dpaa_if *dpaa_intf = dev->data->dev_private;
911 struct fman_if *fif = dev->process_private;
912 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
913 struct qm_mcc_initfq opts = {0};
916 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
917 uint32_t max_rx_pktlen;
919 PMD_INIT_FUNC_TRACE();
921 if (queue_idx >= dev->data->nb_rx_queues) {
922 rte_errno = EOVERFLOW;
923 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
924 (void *)dev, queue_idx, dev->data->nb_rx_queues);
928 /* Rx deferred start is not supported */
929 if (rx_conf->rx_deferred_start) {
930 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
933 rxq->nb_desc = UINT16_MAX;
934 rxq->offloads = rx_conf->offloads;
936 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
937 queue_idx, rxq->fqid);
939 if (!fif->num_profiles) {
940 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
941 dpaa_intf->bp_info->mp != mp) {
942 DPAA_PMD_WARN("Multiple pools on same interface not"
947 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id,
948 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) {
953 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
954 dpaa_intf->bp_info->mp != mp) {
955 DPAA_PMD_WARN("Multiple pools on same interface not supported");
959 max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
961 /* Max packet can fit in single buffer */
962 if (max_rx_pktlen <= buffsz) {
964 } else if (dev->data->dev_conf.rxmode.offloads &
965 RTE_ETH_RX_OFFLOAD_SCATTER) {
966 if (max_rx_pktlen > buffsz * DPAA_SGT_MAX_ENTRIES) {
967 DPAA_PMD_ERR("Maximum Rx packet size %d too big to fit "
969 max_rx_pktlen, buffsz * DPAA_SGT_MAX_ENTRIES);
970 rte_errno = EOVERFLOW;
974 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
975 " larger than a single mbuf (%u) and scattered"
976 " mode has not been requested",
977 max_rx_pktlen, buffsz - RTE_PKTMBUF_HEADROOM);
980 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
982 /* For shared interface, it's done in kernel, skip.*/
983 if (!fif->is_shared_mac)
984 dpaa_fman_if_pool_setup(dev);
986 if (fif->num_profiles) {
987 int8_t vsp_id = rxq->vsp_id;
990 ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id,
991 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid,
994 DPAA_PMD_ERR("dpaa_port_vsp_update failed");
998 DPAA_PMD_INFO("Base profile is associated to"
999 " RXQ fqid:%d\r\n", rxq->fqid);
1000 if (fif->is_shared_mac) {
1001 DPAA_PMD_ERR("Fatal: Base profile is associated"
1002 " to shared interface on DPDK.");
1005 dpaa_intf->vsp_bpid[fif->base_profile_id] =
1006 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1009 dpaa_intf->vsp_bpid[0] =
1010 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1013 dpaa_intf->valid = 1;
1014 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
1015 fman_if_get_sg_enable(fif), max_rx_pktlen);
1016 /* checking if push mode only, no error check for now */
1017 if (!rxq->is_static &&
1018 dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
1019 struct qman_portal *qp;
1022 dpaa_push_queue_idx++;
1023 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
1024 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
1025 QM_FQCTRL_CTXASTASHING |
1026 QM_FQCTRL_PREFERINCACHE;
1027 opts.fqd.context_a.stashing.exclusive = 0;
1028 /* In muticore scenario stashing becomes a bottleneck on LS1046.
1029 * So do not enable stashing in this case
1031 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
1032 opts.fqd.context_a.stashing.annotation_cl =
1033 DPAA_IF_RX_ANNOTATION_STASH;
1034 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
1035 opts.fqd.context_a.stashing.context_cl =
1036 DPAA_IF_RX_CONTEXT_STASH;
1038 /*Create a channel and associate given queue with the channel*/
1039 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
1040 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1041 opts.fqd.dest.channel = rxq->ch_id;
1042 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
1043 flags = QMAN_INITFQ_FLAG_SCHED;
1045 /* Configure tail drop */
1046 if (dpaa_intf->cgr_rx) {
1047 opts.we_mask |= QM_INITFQ_WE_CGID;
1048 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
1049 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1051 ret = qman_init_fq(rxq, flags, &opts);
1053 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
1054 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1057 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
1058 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
1060 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
1061 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
1064 rxq->is_static = true;
1066 /* Allocate qman specific portals */
1067 qp = fsl_qman_fq_portal_create(&q_fd);
1069 DPAA_PMD_ERR("Unable to alloc fq portal");
1074 /* Set up the device interrupt handler */
1075 if (!dev->intr_handle) {
1076 struct rte_dpaa_device *dpaa_dev;
1077 struct rte_device *rdev = dev->device;
1079 dpaa_dev = container_of(rdev, struct rte_dpaa_device,
1081 dev->intr_handle = &dpaa_dev->intr_handle;
1082 dev->intr_handle->intr_vec = rte_zmalloc(NULL,
1083 dpaa_push_mode_max_queue, 0);
1084 if (!dev->intr_handle->intr_vec) {
1085 DPAA_PMD_ERR("intr_vec alloc failed");
1088 dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
1089 dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
1092 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
1093 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
1094 dev->intr_handle->efds[queue_idx] = q_fd;
1097 rxq->bp_array = rte_dpaa_bpid_info;
1098 dev->data->rx_queues[queue_idx] = rxq;
1100 /* configure the CGR size as per the desc size */
1101 if (dpaa_intf->cgr_rx) {
1102 struct qm_mcc_initcgr cgr_opts = {0};
1104 rxq->nb_desc = nb_desc;
1105 /* Enable tail drop with cgr on this queue */
1106 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
1107 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
1110 "rx taildrop modify fail on fqid %d (ret=%d)",
1114 /* Enable main queue to receive error packets also by default */
1115 fman_if_set_err_fqid(fif, rxq->fqid);
1120 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
1121 int eth_rx_queue_id,
1123 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1127 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1128 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1129 struct qm_mcc_initfq opts = {0};
1131 if (dpaa_push_mode_max_queue)
1132 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
1133 "PUSH mode already enabled for first %d queues.\n"
1134 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
1135 dpaa_push_mode_max_queue);
1137 dpaa_poll_queue_default_config(&opts);
1139 switch (queue_conf->ev.sched_type) {
1140 case RTE_SCHED_TYPE_ATOMIC:
1141 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
1142 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
1143 * configuration with HOLD_ACTIVE setting
1145 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
1146 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
1148 case RTE_SCHED_TYPE_ORDERED:
1149 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
1152 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
1153 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
1157 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1158 opts.fqd.dest.channel = ch_id;
1159 opts.fqd.dest.wq = queue_conf->ev.priority;
1161 if (dpaa_intf->cgr_rx) {
1162 opts.we_mask |= QM_INITFQ_WE_CGID;
1163 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1164 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1167 flags = QMAN_INITFQ_FLAG_SCHED;
1169 ret = qman_init_fq(rxq, flags, &opts);
1171 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
1172 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1176 /* copy configuration which needs to be filled during dequeue */
1177 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
1178 dev->data->rx_queues[eth_rx_queue_id] = rxq;
1184 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1185 int eth_rx_queue_id)
1187 struct qm_mcc_initfq opts;
1190 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1191 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1193 dpaa_poll_queue_default_config(&opts);
1195 if (dpaa_intf->cgr_rx) {
1196 opts.we_mask |= QM_INITFQ_WE_CGID;
1197 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1198 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1201 ret = qman_init_fq(rxq, flags, &opts);
1203 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1207 rxq->cb.dqrr_dpdk_cb = NULL;
1208 dev->data->rx_queues[eth_rx_queue_id] = NULL;
1214 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1215 uint16_t nb_desc __rte_unused,
1216 unsigned int socket_id __rte_unused,
1217 const struct rte_eth_txconf *tx_conf)
1219 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1220 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1222 PMD_INIT_FUNC_TRACE();
1224 /* Tx deferred start is not supported */
1225 if (tx_conf->tx_deferred_start) {
1226 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1229 txq->nb_desc = UINT16_MAX;
1230 txq->offloads = tx_conf->offloads;
1232 if (queue_idx >= dev->data->nb_tx_queues) {
1233 rte_errno = EOVERFLOW;
1234 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1235 (void *)dev, queue_idx, dev->data->nb_tx_queues);
1239 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1240 queue_idx, txq->fqid);
1241 dev->data->tx_queues[queue_idx] = txq;
1247 dpaa_dev_rx_queue_count(void *rx_queue)
1249 struct qman_fq *rxq = rx_queue;
1252 PMD_INIT_FUNC_TRACE();
1254 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1255 DPAA_PMD_DEBUG("RX frame count for q(%p) is %u",
1261 static int dpaa_link_down(struct rte_eth_dev *dev)
1263 struct fman_if *fif = dev->process_private;
1264 struct __fman_if *__fif;
1266 PMD_INIT_FUNC_TRACE();
1268 __fif = container_of(fif, struct __fman_if, __if);
1270 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1271 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_DOWN);
1273 return dpaa_eth_dev_stop(dev);
1277 static int dpaa_link_up(struct rte_eth_dev *dev)
1279 struct fman_if *fif = dev->process_private;
1280 struct __fman_if *__fif;
1282 PMD_INIT_FUNC_TRACE();
1284 __fif = container_of(fif, struct __fman_if, __if);
1286 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1287 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_UP);
1289 dpaa_eth_dev_start(dev);
1294 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1295 struct rte_eth_fc_conf *fc_conf)
1297 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1298 struct rte_eth_fc_conf *net_fc;
1300 PMD_INIT_FUNC_TRACE();
1302 if (!(dpaa_intf->fc_conf)) {
1303 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1304 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1305 if (!dpaa_intf->fc_conf) {
1306 DPAA_PMD_ERR("unable to save flow control info");
1310 net_fc = dpaa_intf->fc_conf;
1312 if (fc_conf->high_water < fc_conf->low_water) {
1313 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1317 if (fc_conf->mode == RTE_ETH_FC_NONE) {
1319 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE ||
1320 fc_conf->mode == RTE_ETH_FC_FULL) {
1321 fman_if_set_fc_threshold(dev->process_private,
1322 fc_conf->high_water,
1324 dpaa_intf->bp_info->bpid);
1325 if (fc_conf->pause_time)
1326 fman_if_set_fc_quanta(dev->process_private,
1327 fc_conf->pause_time);
1330 /* Save the information in dpaa device */
1331 net_fc->pause_time = fc_conf->pause_time;
1332 net_fc->high_water = fc_conf->high_water;
1333 net_fc->low_water = fc_conf->low_water;
1334 net_fc->send_xon = fc_conf->send_xon;
1335 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1336 net_fc->mode = fc_conf->mode;
1337 net_fc->autoneg = fc_conf->autoneg;
1343 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1344 struct rte_eth_fc_conf *fc_conf)
1346 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1347 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1350 PMD_INIT_FUNC_TRACE();
1353 fc_conf->pause_time = net_fc->pause_time;
1354 fc_conf->high_water = net_fc->high_water;
1355 fc_conf->low_water = net_fc->low_water;
1356 fc_conf->send_xon = net_fc->send_xon;
1357 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1358 fc_conf->mode = net_fc->mode;
1359 fc_conf->autoneg = net_fc->autoneg;
1362 ret = fman_if_get_fc_threshold(dev->process_private);
1364 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
1365 fc_conf->pause_time =
1366 fman_if_get_fc_quanta(dev->process_private);
1368 fc_conf->mode = RTE_ETH_FC_NONE;
1375 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1376 struct rte_ether_addr *addr,
1378 __rte_unused uint32_t pool)
1382 PMD_INIT_FUNC_TRACE();
1384 ret = fman_if_add_mac_addr(dev->process_private,
1385 addr->addr_bytes, index);
1388 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1393 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1396 PMD_INIT_FUNC_TRACE();
1398 fman_if_clear_mac_addr(dev->process_private, index);
1402 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1403 struct rte_ether_addr *addr)
1407 PMD_INIT_FUNC_TRACE();
1409 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1411 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1417 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev,
1418 struct rte_eth_rss_conf *rss_conf)
1420 struct rte_eth_dev_data *data = dev->data;
1421 struct rte_eth_conf *eth_conf = &data->dev_conf;
1423 PMD_INIT_FUNC_TRACE();
1425 if (!(default_q || fmc_q)) {
1426 if (dpaa_fm_config(dev, rss_conf->rss_hf)) {
1427 DPAA_PMD_ERR("FM port configuration: Failed\n");
1430 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1432 DPAA_PMD_ERR("Function not supported\n");
1439 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1440 struct rte_eth_rss_conf *rss_conf)
1442 struct rte_eth_dev_data *data = dev->data;
1443 struct rte_eth_conf *eth_conf = &data->dev_conf;
1445 /* dpaa does not support rss_key, so length should be 0*/
1446 rss_conf->rss_key_len = 0;
1447 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
1451 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1454 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1455 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1457 if (!rxq->is_static)
1460 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1463 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1466 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1467 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1471 if (!rxq->is_static)
1474 qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1476 temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1477 if (temp1 != sizeof(temp))
1478 DPAA_PMD_ERR("irq read error");
1480 qman_fq_portal_thread_irq(rxq->qp);
1486 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1487 struct rte_eth_rxq_info *qinfo)
1489 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1490 struct qman_fq *rxq;
1493 rxq = dev->data->rx_queues[queue_id];
1495 qinfo->mp = dpaa_intf->bp_info->mp;
1496 qinfo->scattered_rx = dev->data->scattered_rx;
1497 qinfo->nb_desc = rxq->nb_desc;
1499 /* Report the HW Rx buffer length to user */
1500 ret = fman_if_get_maxfrm(dev->process_private);
1502 qinfo->rx_buf_size = ret;
1504 qinfo->conf.rx_free_thresh = 1;
1505 qinfo->conf.rx_drop_en = 1;
1506 qinfo->conf.rx_deferred_start = 0;
1507 qinfo->conf.offloads = rxq->offloads;
1511 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1512 struct rte_eth_txq_info *qinfo)
1514 struct qman_fq *txq;
1516 txq = dev->data->tx_queues[queue_id];
1518 qinfo->nb_desc = txq->nb_desc;
1519 qinfo->conf.tx_thresh.pthresh = 0;
1520 qinfo->conf.tx_thresh.hthresh = 0;
1521 qinfo->conf.tx_thresh.wthresh = 0;
1523 qinfo->conf.tx_free_thresh = 0;
1524 qinfo->conf.tx_rs_thresh = 0;
1525 qinfo->conf.offloads = txq->offloads;
1526 qinfo->conf.tx_deferred_start = 0;
1529 static struct eth_dev_ops dpaa_devops = {
1530 .dev_configure = dpaa_eth_dev_configure,
1531 .dev_start = dpaa_eth_dev_start,
1532 .dev_stop = dpaa_eth_dev_stop,
1533 .dev_close = dpaa_eth_dev_close,
1534 .dev_infos_get = dpaa_eth_dev_info,
1535 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1537 .rx_queue_setup = dpaa_eth_rx_queue_setup,
1538 .tx_queue_setup = dpaa_eth_tx_queue_setup,
1539 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get,
1540 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get,
1541 .rxq_info_get = dpaa_rxq_info_get,
1542 .txq_info_get = dpaa_txq_info_get,
1544 .flow_ctrl_get = dpaa_flow_ctrl_get,
1545 .flow_ctrl_set = dpaa_flow_ctrl_set,
1547 .link_update = dpaa_eth_link_update,
1548 .stats_get = dpaa_eth_stats_get,
1549 .xstats_get = dpaa_dev_xstats_get,
1550 .xstats_get_by_id = dpaa_xstats_get_by_id,
1551 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
1552 .xstats_get_names = dpaa_xstats_get_names,
1553 .xstats_reset = dpaa_eth_stats_reset,
1554 .stats_reset = dpaa_eth_stats_reset,
1555 .promiscuous_enable = dpaa_eth_promiscuous_enable,
1556 .promiscuous_disable = dpaa_eth_promiscuous_disable,
1557 .allmulticast_enable = dpaa_eth_multicast_enable,
1558 .allmulticast_disable = dpaa_eth_multicast_disable,
1559 .mtu_set = dpaa_mtu_set,
1560 .dev_set_link_down = dpaa_link_down,
1561 .dev_set_link_up = dpaa_link_up,
1562 .mac_addr_add = dpaa_dev_add_mac_addr,
1563 .mac_addr_remove = dpaa_dev_remove_mac_addr,
1564 .mac_addr_set = dpaa_dev_set_mac_addr,
1566 .fw_version_get = dpaa_fw_version_get,
1568 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable,
1569 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable,
1570 .rss_hash_update = dpaa_dev_rss_hash_update,
1571 .rss_hash_conf_get = dpaa_dev_rss_hash_conf_get,
1575 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1577 if (strcmp(dev->device->driver->name,
1585 is_dpaa_supported(struct rte_eth_dev *dev)
1587 return is_device_supported(dev, &rte_dpaa_pmd);
1591 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on)
1593 struct rte_eth_dev *dev;
1595 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1597 dev = &rte_eth_devices[port];
1599 if (!is_dpaa_supported(dev))
1603 fman_if_loopback_enable(dev->process_private);
1605 fman_if_loopback_disable(dev->process_private);
1610 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1611 struct fman_if *fman_intf)
1613 struct rte_eth_fc_conf *fc_conf;
1616 PMD_INIT_FUNC_TRACE();
1618 if (!(dpaa_intf->fc_conf)) {
1619 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1620 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1621 if (!dpaa_intf->fc_conf) {
1622 DPAA_PMD_ERR("unable to save flow control info");
1626 fc_conf = dpaa_intf->fc_conf;
1627 ret = fman_if_get_fc_threshold(fman_intf);
1629 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
1630 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1632 fc_conf->mode = RTE_ETH_FC_NONE;
1638 /* Initialise an Rx FQ */
1639 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1642 struct qm_mcc_initfq opts = {0};
1644 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1645 struct qm_mcc_initcgr cgr_opts = {
1646 .we_mask = QM_CGR_WE_CS_THRES |
1650 .cstd_en = QM_CGR_EN,
1651 .mode = QMAN_CGR_MODE_FRAME
1655 if (fmc_q || default_q) {
1656 ret = qman_reserve_fqid(fqid);
1658 DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1664 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1665 ret = qman_create_fq(fqid, flags, fq);
1667 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1671 fq->is_static = false;
1673 dpaa_poll_queue_default_config(&opts);
1676 /* Enable tail drop with cgr on this queue */
1677 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1679 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1683 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1687 opts.we_mask |= QM_INITFQ_WE_CGID;
1688 opts.fqd.cgid = cgr_rx->cgrid;
1689 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1692 ret = qman_init_fq(fq, 0, &opts);
1694 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1698 /* Initialise a Tx FQ */
1699 static int dpaa_tx_queue_init(struct qman_fq *fq,
1700 struct fman_if *fman_intf,
1701 struct qman_cgr *cgr_tx)
1703 struct qm_mcc_initfq opts = {0};
1704 struct qm_mcc_initcgr cgr_opts = {
1705 .we_mask = QM_CGR_WE_CS_THRES |
1709 .cstd_en = QM_CGR_EN,
1710 .mode = QMAN_CGR_MODE_FRAME
1715 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1716 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1718 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1721 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1722 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1723 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1724 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1725 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1726 opts.fqd.context_b = 0;
1727 /* no tx-confirmation */
1728 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1729 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1730 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1733 /* Enable tail drop with cgr on this queue */
1734 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1735 td_tx_threshold, 0);
1737 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1741 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1745 opts.we_mask |= QM_INITFQ_WE_CGID;
1746 opts.fqd.cgid = cgr_tx->cgrid;
1747 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1748 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1752 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1754 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1758 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1759 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1760 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1762 struct qm_mcc_initfq opts = {0};
1765 PMD_INIT_FUNC_TRACE();
1767 ret = qman_reserve_fqid(fqid);
1769 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1773 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1774 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1775 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1777 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1781 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1782 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1783 ret = qman_init_fq(fq, 0, &opts);
1785 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1791 /* Initialise a network interface */
1793 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1795 struct rte_dpaa_device *dpaa_device;
1796 struct fm_eth_port_cfg *cfg;
1797 struct dpaa_if *dpaa_intf;
1798 struct fman_if *fman_intf;
1801 PMD_INIT_FUNC_TRACE();
1803 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1804 dev_id = dpaa_device->id.dev_id;
1805 cfg = dpaa_get_eth_port_cfg(dev_id);
1806 fman_intf = cfg->fman_if;
1807 eth_dev->process_private = fman_intf;
1809 /* Plugging of UCODE burst API not supported in Secondary */
1810 dpaa_intf = eth_dev->data->dev_private;
1811 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1812 if (dpaa_intf->cgr_tx)
1813 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1815 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1816 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1817 qman_set_fq_lookup_table(
1818 dpaa_intf->rx_queues->qman_fq_lookup_table);
1824 /* Initialise a network interface */
1826 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1828 int num_rx_fqs, fqid;
1831 struct rte_dpaa_device *dpaa_device;
1832 struct dpaa_if *dpaa_intf;
1833 struct fm_eth_port_cfg *cfg;
1834 struct fman_if *fman_intf;
1835 struct fman_if_bpool *bp, *tmp_bp;
1836 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1837 uint32_t cgrid_tx[MAX_DPAA_CORES];
1838 uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1839 int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES];
1842 PMD_INIT_FUNC_TRACE();
1844 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1845 dev_id = dpaa_device->id.dev_id;
1846 dpaa_intf = eth_dev->data->dev_private;
1847 cfg = dpaa_get_eth_port_cfg(dev_id);
1848 fman_intf = cfg->fman_if;
1850 dpaa_intf->name = dpaa_device->name;
1852 /* save fman_if & cfg in the interface struture */
1853 eth_dev->process_private = fman_intf;
1854 dpaa_intf->ifid = dev_id;
1855 dpaa_intf->cfg = cfg;
1857 memset((char *)dev_rx_fqids, 0,
1858 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1860 memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES);
1862 /* Initialize Rx FQ's */
1864 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1866 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids,
1868 DPAA_MAX_NUM_PCD_QUEUES);
1869 if (num_rx_fqs < 0) {
1870 DPAA_PMD_ERR("%s FMC initializes failed!",
1875 DPAA_PMD_WARN("%s is not configured by FMC.",
1879 /* FMCLESS mode, load balance to multiple cores.*/
1880 num_rx_fqs = rte_lcore_count();
1883 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1886 if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1887 DPAA_PMD_ERR("Invalid number of RX queues\n");
1891 if (num_rx_fqs > 0) {
1892 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1893 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1894 if (!dpaa_intf->rx_queues) {
1895 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1899 dpaa_intf->rx_queues = NULL;
1902 memset(cgrid, 0, sizeof(cgrid));
1903 memset(cgrid_tx, 0, sizeof(cgrid_tx));
1905 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1906 * Tx tail drop is disabled.
1908 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1909 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1910 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1912 /* if a very large value is being configured */
1913 if (td_tx_threshold > UINT16_MAX)
1914 td_tx_threshold = CGR_RX_PERFQ_THRESH;
1917 /* If congestion control is enabled globally*/
1918 if (num_rx_fqs > 0 && td_threshold) {
1919 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1920 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1921 if (!dpaa_intf->cgr_rx) {
1922 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1927 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1928 if (ret != num_rx_fqs) {
1929 DPAA_PMD_WARN("insufficient CGRIDs available");
1934 dpaa_intf->cgr_rx = NULL;
1937 if (!fmc_q && !default_q) {
1938 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1941 DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1946 for (loop = 0; loop < num_rx_fqs; loop++) {
1950 fqid = dev_rx_fqids[loop];
1952 vsp_id = dev_vspids[loop];
1954 if (dpaa_intf->cgr_rx)
1955 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1957 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1958 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1962 dpaa_intf->rx_queues[loop].vsp_id = vsp_id;
1963 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1965 dpaa_intf->nb_rx_queues = num_rx_fqs;
1967 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1968 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1969 MAX_DPAA_CORES, MAX_CACHELINE);
1970 if (!dpaa_intf->tx_queues) {
1971 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1976 /* If congestion control is enabled globally*/
1977 if (td_tx_threshold) {
1978 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1979 sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1981 if (!dpaa_intf->cgr_tx) {
1982 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1987 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1989 if (ret != MAX_DPAA_CORES) {
1990 DPAA_PMD_WARN("insufficient CGRIDs available");
1995 dpaa_intf->cgr_tx = NULL;
1999 for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
2000 if (dpaa_intf->cgr_tx)
2001 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
2003 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
2005 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
2008 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
2010 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
2012 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
2013 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2014 [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
2016 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!");
2019 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
2020 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2021 [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
2023 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!");
2026 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
2029 DPAA_PMD_DEBUG("All frame queues created");
2031 /* Get the initial configuration for flow control */
2032 dpaa_fc_set_default(dpaa_intf, fman_intf);
2034 /* reset bpool list, initialize bpool dynamically */
2035 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
2036 list_del(&bp->node);
2040 /* Populate ethdev structure */
2041 eth_dev->dev_ops = &dpaa_devops;
2042 eth_dev->rx_queue_count = dpaa_dev_rx_queue_count;
2043 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
2044 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
2046 /* Allocate memory for storing MAC addresses */
2047 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2048 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
2049 if (eth_dev->data->mac_addrs == NULL) {
2050 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
2051 "store MAC addresses",
2052 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
2057 /* copy the primary mac address */
2058 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]);
2060 RTE_LOG(INFO, PMD, "net: dpaa: %s: " RTE_ETHER_ADDR_PRT_FMT "\n",
2061 dpaa_device->name, RTE_ETHER_ADDR_BYTES(&fman_intf->mac_addr));
2063 if (!fman_intf->is_shared_mac) {
2064 /* Configure error packet handling */
2065 fman_if_receive_rx_errors(fman_intf,
2066 FM_FD_RX_STATUS_ERR_MASK);
2067 /* Disable RX mode */
2068 fman_if_disable_rx(fman_intf);
2069 /* Disable promiscuous mode */
2070 fman_if_promiscuous_disable(fman_intf);
2071 /* Disable multicast */
2072 fman_if_reset_mcast_filter_table(fman_intf);
2073 /* Reset interface statistics */
2074 fman_if_stats_reset(fman_intf);
2075 /* Disable SG by default */
2076 fman_if_set_sg(fman_intf, 0);
2077 fman_if_set_maxfrm(fman_intf,
2078 RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
2084 rte_free(dpaa_intf->tx_queues);
2085 dpaa_intf->tx_queues = NULL;
2086 dpaa_intf->nb_tx_queues = 0;
2089 rte_free(dpaa_intf->cgr_rx);
2090 rte_free(dpaa_intf->cgr_tx);
2091 rte_free(dpaa_intf->rx_queues);
2092 dpaa_intf->rx_queues = NULL;
2093 dpaa_intf->nb_rx_queues = 0;
2098 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
2099 struct rte_dpaa_device *dpaa_dev)
2103 struct rte_eth_dev *eth_dev;
2105 PMD_INIT_FUNC_TRACE();
2107 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
2108 RTE_PKTMBUF_HEADROOM) {
2110 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
2111 RTE_PKTMBUF_HEADROOM,
2112 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
2117 /* In case of secondary process, the device is already configured
2118 * and no further action is required, except portal initialization
2119 * and verifying secondary attachment to port name.
2121 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2122 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
2125 eth_dev->device = &dpaa_dev->device;
2126 eth_dev->dev_ops = &dpaa_devops;
2128 ret = dpaa_dev_init_secondary(eth_dev);
2130 RTE_LOG(ERR, PMD, "secondary dev init failed\n");
2134 rte_eth_dev_probing_finish(eth_dev);
2138 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
2139 if (access("/tmp/fmc.bin", F_OK) == -1) {
2140 DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
2144 if (!(default_q || fmc_q)) {
2145 if (dpaa_fm_init()) {
2146 DPAA_PMD_ERR("FM init failed\n");
2151 /* disabling the default push mode for LS1043 */
2152 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
2153 dpaa_push_mode_max_queue = 0;
2155 /* if push mode queues to be enabled. Currenly we are allowing
2156 * only one queue per thread.
2158 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
2159 dpaa_push_mode_max_queue =
2160 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
2161 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
2162 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
2168 if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
2169 ret = rte_dpaa_portal_init((void *)1);
2171 DPAA_PMD_ERR("Unable to initialize portal");
2176 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
2180 eth_dev->data->dev_private =
2181 rte_zmalloc("ethdev private structure",
2182 sizeof(struct dpaa_if),
2183 RTE_CACHE_LINE_SIZE);
2184 if (!eth_dev->data->dev_private) {
2185 DPAA_PMD_ERR("Cannot allocate memzone for port data");
2186 rte_eth_dev_release_port(eth_dev);
2190 eth_dev->device = &dpaa_dev->device;
2191 dpaa_dev->eth_dev = eth_dev;
2193 qman_ern_register_cb(dpaa_free_mbuf);
2195 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2196 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2198 /* Invoke PMD device initialization function */
2199 diag = dpaa_dev_init(eth_dev);
2201 rte_eth_dev_probing_finish(eth_dev);
2205 rte_eth_dev_release_port(eth_dev);
2210 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2212 struct rte_eth_dev *eth_dev;
2215 PMD_INIT_FUNC_TRACE();
2217 eth_dev = dpaa_dev->eth_dev;
2218 dpaa_eth_dev_close(eth_dev);
2219 ret = rte_eth_dev_release_port(eth_dev);
2224 static void __attribute__((destructor(102))) dpaa_finish(void)
2226 /* For secondary, primary will do all the cleanup */
2227 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2230 if (!(default_q || fmc_q)) {
2233 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2234 if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2235 struct rte_eth_dev *dev = &rte_eth_devices[i];
2236 struct dpaa_if *dpaa_intf =
2237 dev->data->dev_private;
2238 struct fman_if *fif =
2239 dev->process_private;
2240 if (dpaa_intf->port_handle)
2241 if (dpaa_fm_deconfig(dpaa_intf, fif))
2242 DPAA_PMD_WARN("DPAA FM "
2243 "deconfig failed\n");
2244 if (fif->num_profiles) {
2245 if (dpaa_port_vsp_cleanup(dpaa_intf,
2247 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n");
2253 DPAA_PMD_WARN("DPAA FM term failed\n");
2257 DPAA_PMD_INFO("DPAA fman cleaned up");
2261 static struct rte_dpaa_driver rte_dpaa_pmd = {
2262 .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2263 .drv_type = FSL_DPAA_ETH,
2264 .probe = rte_dpaa_probe,
2265 .remove = rte_dpaa_remove,
2268 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2269 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE);