1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2017-2020 NXP
15 #include <sys/types.h>
16 #include <sys/syscall.h>
18 #include <rte_string_fns.h>
19 #include <rte_byteorder.h>
20 #include <rte_common.h>
21 #include <rte_interrupts.h>
23 #include <rte_debug.h>
25 #include <rte_atomic.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_memory.h>
28 #include <rte_tailq.h>
30 #include <rte_alarm.h>
31 #include <rte_ether.h>
32 #include <ethdev_driver.h>
33 #include <rte_malloc.h>
36 #include <rte_dpaa_bus.h>
37 #include <rte_dpaa_logs.h>
38 #include <dpaa_mempool.h>
40 #include <dpaa_ethdev.h>
41 #include <dpaa_rxtx.h>
42 #include <dpaa_flow.h>
43 #include <rte_pmd_dpaa.h>
50 #include <fmlib/fm_ext.h>
52 #define CHECK_INTERVAL 100 /* 100ms */
53 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */
55 /* Supported Rx offloads */
56 static uint64_t dev_rx_offloads_sup =
57 RTE_ETH_RX_OFFLOAD_SCATTER;
59 /* Rx offloads which cannot be disabled */
60 static uint64_t dev_rx_offloads_nodis =
61 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
62 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
63 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
64 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
65 RTE_ETH_RX_OFFLOAD_RSS_HASH;
67 /* Supported Tx offloads */
68 static uint64_t dev_tx_offloads_sup =
69 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |
70 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
72 /* Tx offloads which cannot be disabled */
73 static uint64_t dev_tx_offloads_nodis =
74 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
75 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
76 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
77 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
78 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
79 RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
81 /* Keep track of whether QMAN and BMAN have been globally initialized */
82 static int is_global_init;
83 static int fmc_q = 1; /* Indicates the use of static fmc for distribution */
84 static int default_q; /* use default queue - FMC is not executed*/
85 /* At present we only allow up to 4 push mode queues as default - as each of
86 * this queue need dedicated portal and we are short of portals.
88 #define DPAA_MAX_PUSH_MODE_QUEUE 8
89 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
91 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
92 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
95 /* Per RX FQ Taildrop in frame count */
96 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
98 /* Per TX FQ Taildrop in frame count, disabled by default */
99 static unsigned int td_tx_threshold;
101 struct rte_dpaa_xstats_name_off {
102 char name[RTE_ETH_XSTATS_NAME_SIZE];
106 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
108 offsetof(struct dpaa_if_stats, raln)},
110 offsetof(struct dpaa_if_stats, rxpf)},
112 offsetof(struct dpaa_if_stats, rfcs)},
114 offsetof(struct dpaa_if_stats, rvlan)},
116 offsetof(struct dpaa_if_stats, rerr)},
118 offsetof(struct dpaa_if_stats, rdrp)},
120 offsetof(struct dpaa_if_stats, rund)},
122 offsetof(struct dpaa_if_stats, rovr)},
124 offsetof(struct dpaa_if_stats, rfrg)},
126 offsetof(struct dpaa_if_stats, txpf)},
128 offsetof(struct dpaa_if_stats, terr)},
130 offsetof(struct dpaa_if_stats, tvlan)},
132 offsetof(struct dpaa_if_stats, tund)},
135 static struct rte_dpaa_driver rte_dpaa_pmd;
138 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
140 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
141 int wait_to_complete __rte_unused);
143 static void dpaa_interrupt_handler(void *param);
146 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
148 memset(opts, 0, sizeof(struct qm_mcc_initfq));
149 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
150 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
151 QM_FQCTRL_PREFERINCACHE;
152 opts->fqd.context_a.stashing.exclusive = 0;
153 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
154 opts->fqd.context_a.stashing.annotation_cl =
155 DPAA_IF_RX_ANNOTATION_STASH;
156 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
157 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
161 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
163 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
165 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
167 PMD_INIT_FUNC_TRACE();
170 * Refuse mtu that requires the support of scattered packets
171 * when this feature has not been enabled before.
173 if (dev->data->min_rx_buf_size &&
174 !dev->data->scattered_rx && frame_size > buffsz) {
175 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
179 /* check <seg size> * <max_seg> >= max_frame */
180 if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
181 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
182 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
183 buffsz * DPAA_SGT_MAX_ENTRIES);
187 fman_if_set_maxfrm(dev->process_private, frame_size);
193 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
195 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
196 uint64_t rx_offloads = eth_conf->rxmode.offloads;
197 uint64_t tx_offloads = eth_conf->txmode.offloads;
198 struct rte_device *rdev = dev->device;
199 struct rte_eth_link *link = &dev->data->dev_link;
200 struct rte_dpaa_device *dpaa_dev;
201 struct fman_if *fif = dev->process_private;
202 struct __fman_if *__fif;
203 struct rte_intr_handle *intr_handle;
204 uint32_t max_rx_pktlen;
208 PMD_INIT_FUNC_TRACE();
210 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
211 intr_handle = dpaa_dev->intr_handle;
212 __fif = container_of(fif, struct __fman_if, __if);
214 /* Rx offloads which are enabled by default */
215 if (dev_rx_offloads_nodis & ~rx_offloads) {
217 "Some of rx offloads enabled by default - requested 0x%" PRIx64
218 " fixed are 0x%" PRIx64,
219 rx_offloads, dev_rx_offloads_nodis);
222 /* Tx offloads which are enabled by default */
223 if (dev_tx_offloads_nodis & ~tx_offloads) {
225 "Some of tx offloads enabled by default - requested 0x%" PRIx64
226 " fixed are 0x%" PRIx64,
227 tx_offloads, dev_tx_offloads_nodis);
230 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN +
231 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
232 if (max_rx_pktlen > DPAA_MAX_RX_PKT_LEN) {
233 DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
235 max_rx_pktlen, DPAA_MAX_RX_PKT_LEN);
236 max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
239 fman_if_set_maxfrm(dev->process_private, max_rx_pktlen);
241 if (rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) {
242 DPAA_PMD_DEBUG("enabling scatter mode");
243 fman_if_set_sg(dev->process_private, 1);
244 dev->data->scattered_rx = 1;
247 if (!(default_q || fmc_q)) {
248 if (dpaa_fm_config(dev,
249 eth_conf->rx_adv_conf.rss_conf.rss_hf)) {
250 dpaa_write_fm_config_to_file();
251 DPAA_PMD_ERR("FM port configuration: Failed\n");
254 dpaa_write_fm_config_to_file();
257 /* if the interrupts were configured on this devices*/
258 if (intr_handle && rte_intr_fd_get(intr_handle)) {
259 if (dev->data->dev_conf.intr_conf.lsc != 0)
260 rte_intr_callback_register(intr_handle,
261 dpaa_interrupt_handler,
264 ret = dpaa_intr_enable(__fif->node_name,
265 rte_intr_fd_get(intr_handle));
267 if (dev->data->dev_conf.intr_conf.lsc != 0) {
268 rte_intr_callback_unregister(intr_handle,
269 dpaa_interrupt_handler,
272 printf("Failed to enable interrupt: Not Supported\n");
274 printf("Failed to enable interrupt\n");
276 dev->data->dev_conf.intr_conf.lsc = 0;
277 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
281 /* Wait for link status to get updated */
282 if (!link->link_status)
285 /* Configure link only if link is UP*/
286 if (link->link_status) {
287 if (eth_conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
288 /* Start autoneg only if link is not in autoneg mode */
289 if (!link->link_autoneg)
290 dpaa_restart_link_autoneg(__fif->node_name);
291 } else if (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
292 switch (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {
293 case RTE_ETH_LINK_SPEED_10M_HD:
294 speed = RTE_ETH_SPEED_NUM_10M;
295 duplex = RTE_ETH_LINK_HALF_DUPLEX;
297 case RTE_ETH_LINK_SPEED_10M:
298 speed = RTE_ETH_SPEED_NUM_10M;
299 duplex = RTE_ETH_LINK_FULL_DUPLEX;
301 case RTE_ETH_LINK_SPEED_100M_HD:
302 speed = RTE_ETH_SPEED_NUM_100M;
303 duplex = RTE_ETH_LINK_HALF_DUPLEX;
305 case RTE_ETH_LINK_SPEED_100M:
306 speed = RTE_ETH_SPEED_NUM_100M;
307 duplex = RTE_ETH_LINK_FULL_DUPLEX;
309 case RTE_ETH_LINK_SPEED_1G:
310 speed = RTE_ETH_SPEED_NUM_1G;
311 duplex = RTE_ETH_LINK_FULL_DUPLEX;
313 case RTE_ETH_LINK_SPEED_2_5G:
314 speed = RTE_ETH_SPEED_NUM_2_5G;
315 duplex = RTE_ETH_LINK_FULL_DUPLEX;
317 case RTE_ETH_LINK_SPEED_10G:
318 speed = RTE_ETH_SPEED_NUM_10G;
319 duplex = RTE_ETH_LINK_FULL_DUPLEX;
322 speed = RTE_ETH_SPEED_NUM_NONE;
323 duplex = RTE_ETH_LINK_FULL_DUPLEX;
327 dpaa_update_link_speed(__fif->node_name, speed, duplex);
329 /* Manual autoneg - custom advertisement speed. */
330 printf("Custom Advertisement speeds not supported\n");
337 static const uint32_t *
338 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
340 static const uint32_t ptypes[] = {
342 RTE_PTYPE_L2_ETHER_VLAN,
343 RTE_PTYPE_L2_ETHER_ARP,
344 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
345 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
355 PMD_INIT_FUNC_TRACE();
357 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
362 static void dpaa_interrupt_handler(void *param)
364 struct rte_eth_dev *dev = param;
365 struct rte_device *rdev = dev->device;
366 struct rte_dpaa_device *dpaa_dev;
367 struct rte_intr_handle *intr_handle;
371 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
372 intr_handle = dpaa_dev->intr_handle;
374 bytes_read = read(rte_intr_fd_get(intr_handle), &buf,
377 DPAA_PMD_ERR("Error reading eventfd\n");
378 dpaa_eth_link_update(dev, 0);
379 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
382 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
384 struct dpaa_if *dpaa_intf = dev->data->dev_private;
386 PMD_INIT_FUNC_TRACE();
388 if (!(default_q || fmc_q))
389 dpaa_write_fm_config_to_file();
391 /* Change tx callback to the real one */
392 if (dpaa_intf->cgr_tx)
393 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
395 dev->tx_pkt_burst = dpaa_eth_queue_tx;
397 fman_if_enable_rx(dev->process_private);
402 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev)
404 struct fman_if *fif = dev->process_private;
406 PMD_INIT_FUNC_TRACE();
407 dev->data->dev_started = 0;
409 if (!fif->is_shared_mac)
410 fman_if_disable_rx(fif);
411 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
416 static int dpaa_eth_dev_close(struct rte_eth_dev *dev)
418 struct fman_if *fif = dev->process_private;
419 struct __fman_if *__fif;
420 struct rte_device *rdev = dev->device;
421 struct rte_dpaa_device *dpaa_dev;
422 struct rte_intr_handle *intr_handle;
423 struct rte_eth_link *link = &dev->data->dev_link;
424 struct dpaa_if *dpaa_intf = dev->data->dev_private;
428 PMD_INIT_FUNC_TRACE();
430 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
434 DPAA_PMD_WARN("Already closed or not started");
438 /* DPAA FM deconfig */
439 if (!(default_q || fmc_q)) {
440 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
441 DPAA_PMD_WARN("DPAA FM deconfig failed\n");
444 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
445 intr_handle = dpaa_dev->intr_handle;
446 __fif = container_of(fif, struct __fman_if, __if);
448 ret = dpaa_eth_dev_stop(dev);
450 /* Reset link to autoneg */
451 if (link->link_status && !link->link_autoneg)
452 dpaa_restart_link_autoneg(__fif->node_name);
454 if (intr_handle && rte_intr_fd_get(intr_handle) &&
455 dev->data->dev_conf.intr_conf.lsc != 0) {
456 dpaa_intr_disable(__fif->node_name);
457 rte_intr_callback_unregister(intr_handle,
458 dpaa_interrupt_handler,
462 /* release configuration memory */
463 if (dpaa_intf->fc_conf)
464 rte_free(dpaa_intf->fc_conf);
466 /* Release RX congestion Groups */
467 if (dpaa_intf->cgr_rx) {
468 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
469 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
472 rte_free(dpaa_intf->cgr_rx);
473 dpaa_intf->cgr_rx = NULL;
474 /* Release TX congestion Groups */
475 if (dpaa_intf->cgr_tx) {
476 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
477 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
478 rte_free(dpaa_intf->cgr_tx);
479 dpaa_intf->cgr_tx = NULL;
482 rte_free(dpaa_intf->rx_queues);
483 dpaa_intf->rx_queues = NULL;
485 rte_free(dpaa_intf->tx_queues);
486 dpaa_intf->tx_queues = NULL;
492 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
497 FILE *svr_file = NULL;
498 unsigned int svr_ver = 0;
500 PMD_INIT_FUNC_TRACE();
502 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
504 DPAA_PMD_ERR("Unable to open SoC device");
505 return -ENOTSUP; /* Not supported on this infra */
507 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
508 dpaa_svr_family = svr_ver & SVR_MASK;
510 DPAA_PMD_ERR("Unable to read SoC device");
514 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
515 svr_ver, fman_ip_rev);
519 ret += 1; /* add the size of '\0' */
520 if (fw_size < (size_t)ret)
526 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
527 struct rte_eth_dev_info *dev_info)
529 struct dpaa_if *dpaa_intf = dev->data->dev_private;
530 struct fman_if *fif = dev->process_private;
532 DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
534 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
535 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
536 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
537 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
538 dev_info->max_hash_mac_addrs = 0;
539 dev_info->max_vfs = 0;
540 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
541 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
543 if (fif->mac_type == fman_mac_1g) {
544 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD
545 | RTE_ETH_LINK_SPEED_10M
546 | RTE_ETH_LINK_SPEED_100M_HD
547 | RTE_ETH_LINK_SPEED_100M
548 | RTE_ETH_LINK_SPEED_1G;
549 } else if (fif->mac_type == fman_mac_2_5g) {
550 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD
551 | RTE_ETH_LINK_SPEED_10M
552 | RTE_ETH_LINK_SPEED_100M_HD
553 | RTE_ETH_LINK_SPEED_100M
554 | RTE_ETH_LINK_SPEED_1G
555 | RTE_ETH_LINK_SPEED_2_5G;
556 } else if (fif->mac_type == fman_mac_10g) {
557 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD
558 | RTE_ETH_LINK_SPEED_10M
559 | RTE_ETH_LINK_SPEED_100M_HD
560 | RTE_ETH_LINK_SPEED_100M
561 | RTE_ETH_LINK_SPEED_1G
562 | RTE_ETH_LINK_SPEED_2_5G
563 | RTE_ETH_LINK_SPEED_10G;
565 DPAA_PMD_ERR("invalid link_speed: %s, %d",
566 dpaa_intf->name, fif->mac_type);
570 dev_info->rx_offload_capa = dev_rx_offloads_sup |
571 dev_rx_offloads_nodis;
572 dev_info->tx_offload_capa = dev_tx_offloads_sup |
573 dev_tx_offloads_nodis;
574 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
575 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
576 dev_info->default_rxportconf.nb_queues = 1;
577 dev_info->default_txportconf.nb_queues = 1;
578 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
579 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
585 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
586 __rte_unused uint16_t queue_id,
587 struct rte_eth_burst_mode *mode)
589 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
592 const struct burst_info {
595 } rx_offload_map[] = {
596 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"},
597 {RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
598 {RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
599 {RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
600 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
601 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"}
604 /* Update Rx offload info */
605 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
606 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
607 snprintf(mode->info, sizeof(mode->info), "%s",
608 rx_offload_map[i].output);
617 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
618 __rte_unused uint16_t queue_id,
619 struct rte_eth_burst_mode *mode)
621 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
624 const struct burst_info {
627 } tx_offload_map[] = {
628 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
629 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
630 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
631 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
632 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
633 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
634 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
635 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
638 /* Update Tx offload info */
639 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
640 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
641 snprintf(mode->info, sizeof(mode->info), "%s",
642 tx_offload_map[i].output);
650 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
651 int wait_to_complete)
653 struct dpaa_if *dpaa_intf = dev->data->dev_private;
654 struct rte_eth_link *link = &dev->data->dev_link;
655 struct fman_if *fif = dev->process_private;
656 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
657 int ret, ioctl_version;
660 PMD_INIT_FUNC_TRACE();
662 ioctl_version = dpaa_get_ioctl_version_number();
664 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
665 for (count = 0; count <= MAX_REPEAT_TIME; count++) {
666 ret = dpaa_get_link_status(__fif->node_name, link);
669 if (link->link_status == RTE_ETH_LINK_DOWN &&
671 rte_delay_ms(CHECK_INTERVAL);
676 link->link_status = dpaa_intf->valid;
679 if (ioctl_version < 2) {
680 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
681 link->link_autoneg = RTE_ETH_LINK_AUTONEG;
683 if (fif->mac_type == fman_mac_1g)
684 link->link_speed = RTE_ETH_SPEED_NUM_1G;
685 else if (fif->mac_type == fman_mac_2_5g)
686 link->link_speed = RTE_ETH_SPEED_NUM_2_5G;
687 else if (fif->mac_type == fman_mac_10g)
688 link->link_speed = RTE_ETH_SPEED_NUM_10G;
690 DPAA_PMD_ERR("invalid link_speed: %s, %d",
691 dpaa_intf->name, fif->mac_type);
694 DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
695 link->link_status ? "Up" : "Down");
699 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
700 struct rte_eth_stats *stats)
702 PMD_INIT_FUNC_TRACE();
704 fman_if_stats_get(dev->process_private, stats);
708 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
710 PMD_INIT_FUNC_TRACE();
712 fman_if_stats_reset(dev->process_private);
718 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
721 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
722 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
730 fman_if_stats_get_all(dev->process_private, values,
731 sizeof(struct dpaa_if_stats) / 8);
733 for (i = 0; i < num; i++) {
735 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
741 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
742 struct rte_eth_xstat_name *xstats_names,
745 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
747 if (limit < stat_cnt)
750 if (xstats_names != NULL)
751 for (i = 0; i < stat_cnt; i++)
752 strlcpy(xstats_names[i].name,
753 dpaa_xstats_strings[i].name,
754 sizeof(xstats_names[i].name));
760 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
761 uint64_t *values, unsigned int n)
763 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
764 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
773 fman_if_stats_get_all(dev->process_private, values_copy,
774 sizeof(struct dpaa_if_stats) / 8);
776 for (i = 0; i < stat_cnt; i++)
778 values_copy[dpaa_xstats_strings[i].offset / 8];
783 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
785 for (i = 0; i < n; i++) {
786 if (ids[i] >= stat_cnt) {
787 DPAA_PMD_ERR("id value isn't valid");
790 values[i] = values_copy[ids[i]];
796 dpaa_xstats_get_names_by_id(
797 struct rte_eth_dev *dev,
799 struct rte_eth_xstat_name *xstats_names,
802 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
803 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
806 return dpaa_xstats_get_names(dev, xstats_names, limit);
808 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
810 for (i = 0; i < limit; i++) {
811 if (ids[i] >= stat_cnt) {
812 DPAA_PMD_ERR("id value isn't valid");
815 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
820 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
822 PMD_INIT_FUNC_TRACE();
824 fman_if_promiscuous_enable(dev->process_private);
829 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
831 PMD_INIT_FUNC_TRACE();
833 fman_if_promiscuous_disable(dev->process_private);
838 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
840 PMD_INIT_FUNC_TRACE();
842 fman_if_set_mcast_filter_table(dev->process_private);
847 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
849 PMD_INIT_FUNC_TRACE();
851 fman_if_reset_mcast_filter_table(dev->process_private);
856 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev)
858 struct dpaa_if *dpaa_intf = dev->data->dev_private;
859 struct fman_if_ic_params icp;
863 memset(&icp, 0, sizeof(icp));
864 /* set ICEOF for to the default value , which is 0*/
865 icp.iciof = DEFAULT_ICIOF;
866 icp.iceof = DEFAULT_RX_ICEOF;
867 icp.icsz = DEFAULT_ICSZ;
868 fman_if_set_ic_params(dev->process_private, &icp);
870 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
871 fman_if_set_fdoff(dev->process_private, fd_offset);
873 /* Buffer pool size should be equal to Dataroom Size*/
874 bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp);
876 fman_if_set_bp(dev->process_private,
877 dpaa_intf->bp_info->mp->size,
878 dpaa_intf->bp_info->bpid, bp_size);
881 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev,
882 int8_t vsp_id, uint32_t bpid)
884 struct dpaa_if *dpaa_intf = dev->data->dev_private;
885 struct fman_if *fif = dev->process_private;
887 if (fif->num_profiles) {
889 vsp_id = fif->base_profile_id;
895 if (dpaa_intf->vsp_bpid[vsp_id] &&
896 bpid != dpaa_intf->vsp_bpid[vsp_id]) {
897 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP");
906 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
908 unsigned int socket_id __rte_unused,
909 const struct rte_eth_rxconf *rx_conf,
910 struct rte_mempool *mp)
912 struct dpaa_if *dpaa_intf = dev->data->dev_private;
913 struct fman_if *fif = dev->process_private;
914 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
915 struct qm_mcc_initfq opts = {0};
918 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
919 uint32_t max_rx_pktlen;
921 PMD_INIT_FUNC_TRACE();
923 if (queue_idx >= dev->data->nb_rx_queues) {
924 rte_errno = EOVERFLOW;
925 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
926 (void *)dev, queue_idx, dev->data->nb_rx_queues);
930 /* Rx deferred start is not supported */
931 if (rx_conf->rx_deferred_start) {
932 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
935 rxq->nb_desc = UINT16_MAX;
936 rxq->offloads = rx_conf->offloads;
938 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
939 queue_idx, rxq->fqid);
941 if (!fif->num_profiles) {
942 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
943 dpaa_intf->bp_info->mp != mp) {
944 DPAA_PMD_WARN("Multiple pools on same interface not"
949 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id,
950 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) {
955 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
956 dpaa_intf->bp_info->mp != mp) {
957 DPAA_PMD_WARN("Multiple pools on same interface not supported");
961 max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
963 /* Max packet can fit in single buffer */
964 if (max_rx_pktlen <= buffsz) {
966 } else if (dev->data->dev_conf.rxmode.offloads &
967 RTE_ETH_RX_OFFLOAD_SCATTER) {
968 if (max_rx_pktlen > buffsz * DPAA_SGT_MAX_ENTRIES) {
969 DPAA_PMD_ERR("Maximum Rx packet size %d too big to fit "
971 max_rx_pktlen, buffsz * DPAA_SGT_MAX_ENTRIES);
972 rte_errno = EOVERFLOW;
976 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
977 " larger than a single mbuf (%u) and scattered"
978 " mode has not been requested",
979 max_rx_pktlen, buffsz - RTE_PKTMBUF_HEADROOM);
982 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
984 /* For shared interface, it's done in kernel, skip.*/
985 if (!fif->is_shared_mac)
986 dpaa_fman_if_pool_setup(dev);
988 if (fif->num_profiles) {
989 int8_t vsp_id = rxq->vsp_id;
992 ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id,
993 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid,
996 DPAA_PMD_ERR("dpaa_port_vsp_update failed");
1000 DPAA_PMD_INFO("Base profile is associated to"
1001 " RXQ fqid:%d\r\n", rxq->fqid);
1002 if (fif->is_shared_mac) {
1003 DPAA_PMD_ERR("Fatal: Base profile is associated"
1004 " to shared interface on DPDK.");
1007 dpaa_intf->vsp_bpid[fif->base_profile_id] =
1008 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1011 dpaa_intf->vsp_bpid[0] =
1012 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1015 dpaa_intf->valid = 1;
1016 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
1017 fman_if_get_sg_enable(fif), max_rx_pktlen);
1018 /* checking if push mode only, no error check for now */
1019 if (!rxq->is_static &&
1020 dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
1021 struct qman_portal *qp;
1024 dpaa_push_queue_idx++;
1025 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
1026 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
1027 QM_FQCTRL_CTXASTASHING |
1028 QM_FQCTRL_PREFERINCACHE;
1029 opts.fqd.context_a.stashing.exclusive = 0;
1030 /* In muticore scenario stashing becomes a bottleneck on LS1046.
1031 * So do not enable stashing in this case
1033 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
1034 opts.fqd.context_a.stashing.annotation_cl =
1035 DPAA_IF_RX_ANNOTATION_STASH;
1036 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
1037 opts.fqd.context_a.stashing.context_cl =
1038 DPAA_IF_RX_CONTEXT_STASH;
1040 /*Create a channel and associate given queue with the channel*/
1041 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
1042 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1043 opts.fqd.dest.channel = rxq->ch_id;
1044 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
1045 flags = QMAN_INITFQ_FLAG_SCHED;
1047 /* Configure tail drop */
1048 if (dpaa_intf->cgr_rx) {
1049 opts.we_mask |= QM_INITFQ_WE_CGID;
1050 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
1051 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1053 ret = qman_init_fq(rxq, flags, &opts);
1055 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
1056 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1059 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
1060 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
1062 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
1063 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
1066 rxq->is_static = true;
1068 /* Allocate qman specific portals */
1069 qp = fsl_qman_fq_portal_create(&q_fd);
1071 DPAA_PMD_ERR("Unable to alloc fq portal");
1076 /* Set up the device interrupt handler */
1077 if (dev->intr_handle == NULL) {
1078 struct rte_dpaa_device *dpaa_dev;
1079 struct rte_device *rdev = dev->device;
1081 dpaa_dev = container_of(rdev, struct rte_dpaa_device,
1083 dev->intr_handle = dpaa_dev->intr_handle;
1084 if (rte_intr_vec_list_alloc(dev->intr_handle,
1085 NULL, dpaa_push_mode_max_queue)) {
1086 DPAA_PMD_ERR("intr_vec alloc failed");
1089 if (rte_intr_nb_efd_set(dev->intr_handle,
1090 dpaa_push_mode_max_queue))
1093 if (rte_intr_max_intr_set(dev->intr_handle,
1094 dpaa_push_mode_max_queue))
1098 if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_EXT))
1101 if (rte_intr_vec_list_index_set(dev->intr_handle,
1102 queue_idx, queue_idx + 1))
1105 if (rte_intr_efds_index_set(dev->intr_handle, queue_idx,
1111 rxq->bp_array = rte_dpaa_bpid_info;
1112 dev->data->rx_queues[queue_idx] = rxq;
1114 /* configure the CGR size as per the desc size */
1115 if (dpaa_intf->cgr_rx) {
1116 struct qm_mcc_initcgr cgr_opts = {0};
1118 rxq->nb_desc = nb_desc;
1119 /* Enable tail drop with cgr on this queue */
1120 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
1121 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
1124 "rx taildrop modify fail on fqid %d (ret=%d)",
1128 /* Enable main queue to receive error packets also by default */
1129 fman_if_set_err_fqid(fif, rxq->fqid);
1134 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
1135 int eth_rx_queue_id,
1137 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1141 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1142 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1143 struct qm_mcc_initfq opts = {0};
1145 if (dpaa_push_mode_max_queue)
1146 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
1147 "PUSH mode already enabled for first %d queues.\n"
1148 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
1149 dpaa_push_mode_max_queue);
1151 dpaa_poll_queue_default_config(&opts);
1153 switch (queue_conf->ev.sched_type) {
1154 case RTE_SCHED_TYPE_ATOMIC:
1155 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
1156 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
1157 * configuration with HOLD_ACTIVE setting
1159 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
1160 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
1162 case RTE_SCHED_TYPE_ORDERED:
1163 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
1166 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
1167 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
1171 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1172 opts.fqd.dest.channel = ch_id;
1173 opts.fqd.dest.wq = queue_conf->ev.priority;
1175 if (dpaa_intf->cgr_rx) {
1176 opts.we_mask |= QM_INITFQ_WE_CGID;
1177 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1178 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1181 flags = QMAN_INITFQ_FLAG_SCHED;
1183 ret = qman_init_fq(rxq, flags, &opts);
1185 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
1186 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1190 /* copy configuration which needs to be filled during dequeue */
1191 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
1192 dev->data->rx_queues[eth_rx_queue_id] = rxq;
1198 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1199 int eth_rx_queue_id)
1201 struct qm_mcc_initfq opts;
1204 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1205 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1207 dpaa_poll_queue_default_config(&opts);
1209 if (dpaa_intf->cgr_rx) {
1210 opts.we_mask |= QM_INITFQ_WE_CGID;
1211 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1212 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1215 ret = qman_init_fq(rxq, flags, &opts);
1217 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1221 rxq->cb.dqrr_dpdk_cb = NULL;
1222 dev->data->rx_queues[eth_rx_queue_id] = NULL;
1228 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1229 uint16_t nb_desc __rte_unused,
1230 unsigned int socket_id __rte_unused,
1231 const struct rte_eth_txconf *tx_conf)
1233 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1234 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1236 PMD_INIT_FUNC_TRACE();
1238 /* Tx deferred start is not supported */
1239 if (tx_conf->tx_deferred_start) {
1240 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1243 txq->nb_desc = UINT16_MAX;
1244 txq->offloads = tx_conf->offloads;
1246 if (queue_idx >= dev->data->nb_tx_queues) {
1247 rte_errno = EOVERFLOW;
1248 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1249 (void *)dev, queue_idx, dev->data->nb_tx_queues);
1253 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1254 queue_idx, txq->fqid);
1255 dev->data->tx_queues[queue_idx] = txq;
1261 dpaa_dev_rx_queue_count(void *rx_queue)
1263 struct qman_fq *rxq = rx_queue;
1266 PMD_INIT_FUNC_TRACE();
1268 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1269 DPAA_PMD_DEBUG("RX frame count for q(%p) is %u",
1275 static int dpaa_link_down(struct rte_eth_dev *dev)
1277 struct fman_if *fif = dev->process_private;
1278 struct __fman_if *__fif;
1280 PMD_INIT_FUNC_TRACE();
1282 __fif = container_of(fif, struct __fman_if, __if);
1284 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1285 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_DOWN);
1287 return dpaa_eth_dev_stop(dev);
1291 static int dpaa_link_up(struct rte_eth_dev *dev)
1293 struct fman_if *fif = dev->process_private;
1294 struct __fman_if *__fif;
1296 PMD_INIT_FUNC_TRACE();
1298 __fif = container_of(fif, struct __fman_if, __if);
1300 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1301 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_UP);
1303 dpaa_eth_dev_start(dev);
1308 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1309 struct rte_eth_fc_conf *fc_conf)
1311 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1312 struct rte_eth_fc_conf *net_fc;
1314 PMD_INIT_FUNC_TRACE();
1316 if (!(dpaa_intf->fc_conf)) {
1317 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1318 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1319 if (!dpaa_intf->fc_conf) {
1320 DPAA_PMD_ERR("unable to save flow control info");
1324 net_fc = dpaa_intf->fc_conf;
1326 if (fc_conf->high_water < fc_conf->low_water) {
1327 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1331 if (fc_conf->mode == RTE_ETH_FC_NONE) {
1333 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE ||
1334 fc_conf->mode == RTE_ETH_FC_FULL) {
1335 fman_if_set_fc_threshold(dev->process_private,
1336 fc_conf->high_water,
1338 dpaa_intf->bp_info->bpid);
1339 if (fc_conf->pause_time)
1340 fman_if_set_fc_quanta(dev->process_private,
1341 fc_conf->pause_time);
1344 /* Save the information in dpaa device */
1345 net_fc->pause_time = fc_conf->pause_time;
1346 net_fc->high_water = fc_conf->high_water;
1347 net_fc->low_water = fc_conf->low_water;
1348 net_fc->send_xon = fc_conf->send_xon;
1349 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1350 net_fc->mode = fc_conf->mode;
1351 net_fc->autoneg = fc_conf->autoneg;
1357 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1358 struct rte_eth_fc_conf *fc_conf)
1360 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1361 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1364 PMD_INIT_FUNC_TRACE();
1367 fc_conf->pause_time = net_fc->pause_time;
1368 fc_conf->high_water = net_fc->high_water;
1369 fc_conf->low_water = net_fc->low_water;
1370 fc_conf->send_xon = net_fc->send_xon;
1371 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1372 fc_conf->mode = net_fc->mode;
1373 fc_conf->autoneg = net_fc->autoneg;
1376 ret = fman_if_get_fc_threshold(dev->process_private);
1378 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
1379 fc_conf->pause_time =
1380 fman_if_get_fc_quanta(dev->process_private);
1382 fc_conf->mode = RTE_ETH_FC_NONE;
1389 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1390 struct rte_ether_addr *addr,
1392 __rte_unused uint32_t pool)
1396 PMD_INIT_FUNC_TRACE();
1398 ret = fman_if_add_mac_addr(dev->process_private,
1399 addr->addr_bytes, index);
1402 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1407 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1410 PMD_INIT_FUNC_TRACE();
1412 fman_if_clear_mac_addr(dev->process_private, index);
1416 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1417 struct rte_ether_addr *addr)
1421 PMD_INIT_FUNC_TRACE();
1423 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1425 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1431 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev,
1432 struct rte_eth_rss_conf *rss_conf)
1434 struct rte_eth_dev_data *data = dev->data;
1435 struct rte_eth_conf *eth_conf = &data->dev_conf;
1437 PMD_INIT_FUNC_TRACE();
1439 if (!(default_q || fmc_q)) {
1440 if (dpaa_fm_config(dev, rss_conf->rss_hf)) {
1441 DPAA_PMD_ERR("FM port configuration: Failed\n");
1444 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1446 DPAA_PMD_ERR("Function not supported\n");
1453 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1454 struct rte_eth_rss_conf *rss_conf)
1456 struct rte_eth_dev_data *data = dev->data;
1457 struct rte_eth_conf *eth_conf = &data->dev_conf;
1459 /* dpaa does not support rss_key, so length should be 0*/
1460 rss_conf->rss_key_len = 0;
1461 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
1465 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1468 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1469 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1471 if (!rxq->is_static)
1474 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1477 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1480 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1481 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1485 if (!rxq->is_static)
1488 qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1490 temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1491 if (temp1 != sizeof(temp))
1492 DPAA_PMD_ERR("irq read error");
1494 qman_fq_portal_thread_irq(rxq->qp);
1500 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1501 struct rte_eth_rxq_info *qinfo)
1503 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1504 struct qman_fq *rxq;
1507 rxq = dev->data->rx_queues[queue_id];
1509 qinfo->mp = dpaa_intf->bp_info->mp;
1510 qinfo->scattered_rx = dev->data->scattered_rx;
1511 qinfo->nb_desc = rxq->nb_desc;
1513 /* Report the HW Rx buffer length to user */
1514 ret = fman_if_get_maxfrm(dev->process_private);
1516 qinfo->rx_buf_size = ret;
1518 qinfo->conf.rx_free_thresh = 1;
1519 qinfo->conf.rx_drop_en = 1;
1520 qinfo->conf.rx_deferred_start = 0;
1521 qinfo->conf.offloads = rxq->offloads;
1525 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1526 struct rte_eth_txq_info *qinfo)
1528 struct qman_fq *txq;
1530 txq = dev->data->tx_queues[queue_id];
1532 qinfo->nb_desc = txq->nb_desc;
1533 qinfo->conf.tx_thresh.pthresh = 0;
1534 qinfo->conf.tx_thresh.hthresh = 0;
1535 qinfo->conf.tx_thresh.wthresh = 0;
1537 qinfo->conf.tx_free_thresh = 0;
1538 qinfo->conf.tx_rs_thresh = 0;
1539 qinfo->conf.offloads = txq->offloads;
1540 qinfo->conf.tx_deferred_start = 0;
1543 static struct eth_dev_ops dpaa_devops = {
1544 .dev_configure = dpaa_eth_dev_configure,
1545 .dev_start = dpaa_eth_dev_start,
1546 .dev_stop = dpaa_eth_dev_stop,
1547 .dev_close = dpaa_eth_dev_close,
1548 .dev_infos_get = dpaa_eth_dev_info,
1549 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1551 .rx_queue_setup = dpaa_eth_rx_queue_setup,
1552 .tx_queue_setup = dpaa_eth_tx_queue_setup,
1553 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get,
1554 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get,
1555 .rxq_info_get = dpaa_rxq_info_get,
1556 .txq_info_get = dpaa_txq_info_get,
1558 .flow_ctrl_get = dpaa_flow_ctrl_get,
1559 .flow_ctrl_set = dpaa_flow_ctrl_set,
1561 .link_update = dpaa_eth_link_update,
1562 .stats_get = dpaa_eth_stats_get,
1563 .xstats_get = dpaa_dev_xstats_get,
1564 .xstats_get_by_id = dpaa_xstats_get_by_id,
1565 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
1566 .xstats_get_names = dpaa_xstats_get_names,
1567 .xstats_reset = dpaa_eth_stats_reset,
1568 .stats_reset = dpaa_eth_stats_reset,
1569 .promiscuous_enable = dpaa_eth_promiscuous_enable,
1570 .promiscuous_disable = dpaa_eth_promiscuous_disable,
1571 .allmulticast_enable = dpaa_eth_multicast_enable,
1572 .allmulticast_disable = dpaa_eth_multicast_disable,
1573 .mtu_set = dpaa_mtu_set,
1574 .dev_set_link_down = dpaa_link_down,
1575 .dev_set_link_up = dpaa_link_up,
1576 .mac_addr_add = dpaa_dev_add_mac_addr,
1577 .mac_addr_remove = dpaa_dev_remove_mac_addr,
1578 .mac_addr_set = dpaa_dev_set_mac_addr,
1580 .fw_version_get = dpaa_fw_version_get,
1582 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable,
1583 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable,
1584 .rss_hash_update = dpaa_dev_rss_hash_update,
1585 .rss_hash_conf_get = dpaa_dev_rss_hash_conf_get,
1589 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1591 if (strcmp(dev->device->driver->name,
1599 is_dpaa_supported(struct rte_eth_dev *dev)
1601 return is_device_supported(dev, &rte_dpaa_pmd);
1605 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on)
1607 struct rte_eth_dev *dev;
1609 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1611 dev = &rte_eth_devices[port];
1613 if (!is_dpaa_supported(dev))
1617 fman_if_loopback_enable(dev->process_private);
1619 fman_if_loopback_disable(dev->process_private);
1624 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1625 struct fman_if *fman_intf)
1627 struct rte_eth_fc_conf *fc_conf;
1630 PMD_INIT_FUNC_TRACE();
1632 if (!(dpaa_intf->fc_conf)) {
1633 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1634 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1635 if (!dpaa_intf->fc_conf) {
1636 DPAA_PMD_ERR("unable to save flow control info");
1640 fc_conf = dpaa_intf->fc_conf;
1641 ret = fman_if_get_fc_threshold(fman_intf);
1643 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
1644 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1646 fc_conf->mode = RTE_ETH_FC_NONE;
1652 /* Initialise an Rx FQ */
1653 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1656 struct qm_mcc_initfq opts = {0};
1658 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1659 struct qm_mcc_initcgr cgr_opts = {
1660 .we_mask = QM_CGR_WE_CS_THRES |
1664 .cstd_en = QM_CGR_EN,
1665 .mode = QMAN_CGR_MODE_FRAME
1669 if (fmc_q || default_q) {
1670 ret = qman_reserve_fqid(fqid);
1672 DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1678 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1679 ret = qman_create_fq(fqid, flags, fq);
1681 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1685 fq->is_static = false;
1687 dpaa_poll_queue_default_config(&opts);
1690 /* Enable tail drop with cgr on this queue */
1691 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1693 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1697 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1701 opts.we_mask |= QM_INITFQ_WE_CGID;
1702 opts.fqd.cgid = cgr_rx->cgrid;
1703 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1706 ret = qman_init_fq(fq, 0, &opts);
1708 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1712 /* Initialise a Tx FQ */
1713 static int dpaa_tx_queue_init(struct qman_fq *fq,
1714 struct fman_if *fman_intf,
1715 struct qman_cgr *cgr_tx)
1717 struct qm_mcc_initfq opts = {0};
1718 struct qm_mcc_initcgr cgr_opts = {
1719 .we_mask = QM_CGR_WE_CS_THRES |
1723 .cstd_en = QM_CGR_EN,
1724 .mode = QMAN_CGR_MODE_FRAME
1729 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1730 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1732 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1735 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1736 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1737 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1738 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1739 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1740 opts.fqd.context_b = 0;
1741 /* no tx-confirmation */
1742 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1743 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1744 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1747 /* Enable tail drop with cgr on this queue */
1748 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1749 td_tx_threshold, 0);
1751 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1755 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1759 opts.we_mask |= QM_INITFQ_WE_CGID;
1760 opts.fqd.cgid = cgr_tx->cgrid;
1761 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1762 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1766 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1768 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1772 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1773 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1774 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1776 struct qm_mcc_initfq opts = {0};
1779 PMD_INIT_FUNC_TRACE();
1781 ret = qman_reserve_fqid(fqid);
1783 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1787 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1788 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1789 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1791 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1795 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1796 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1797 ret = qman_init_fq(fq, 0, &opts);
1799 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1805 /* Initialise a network interface */
1807 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1809 struct rte_dpaa_device *dpaa_device;
1810 struct fm_eth_port_cfg *cfg;
1811 struct dpaa_if *dpaa_intf;
1812 struct fman_if *fman_intf;
1815 PMD_INIT_FUNC_TRACE();
1817 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1818 dev_id = dpaa_device->id.dev_id;
1819 cfg = dpaa_get_eth_port_cfg(dev_id);
1820 fman_intf = cfg->fman_if;
1821 eth_dev->process_private = fman_intf;
1823 /* Plugging of UCODE burst API not supported in Secondary */
1824 dpaa_intf = eth_dev->data->dev_private;
1825 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1826 if (dpaa_intf->cgr_tx)
1827 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1829 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1830 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1831 qman_set_fq_lookup_table(
1832 dpaa_intf->rx_queues->qman_fq_lookup_table);
1838 /* Initialise a network interface */
1840 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1842 int num_rx_fqs, fqid;
1845 struct rte_dpaa_device *dpaa_device;
1846 struct dpaa_if *dpaa_intf;
1847 struct fm_eth_port_cfg *cfg;
1848 struct fman_if *fman_intf;
1849 struct fman_if_bpool *bp, *tmp_bp;
1850 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1851 uint32_t cgrid_tx[MAX_DPAA_CORES];
1852 uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1853 int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES];
1856 PMD_INIT_FUNC_TRACE();
1858 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1859 dev_id = dpaa_device->id.dev_id;
1860 dpaa_intf = eth_dev->data->dev_private;
1861 cfg = dpaa_get_eth_port_cfg(dev_id);
1862 fman_intf = cfg->fman_if;
1864 dpaa_intf->name = dpaa_device->name;
1866 /* save fman_if & cfg in the interface struture */
1867 eth_dev->process_private = fman_intf;
1868 dpaa_intf->ifid = dev_id;
1869 dpaa_intf->cfg = cfg;
1871 memset((char *)dev_rx_fqids, 0,
1872 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1874 memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES);
1876 /* Initialize Rx FQ's */
1878 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1880 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids,
1882 DPAA_MAX_NUM_PCD_QUEUES);
1883 if (num_rx_fqs < 0) {
1884 DPAA_PMD_ERR("%s FMC initializes failed!",
1889 DPAA_PMD_WARN("%s is not configured by FMC.",
1893 /* FMCLESS mode, load balance to multiple cores.*/
1894 num_rx_fqs = rte_lcore_count();
1897 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1900 if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1901 DPAA_PMD_ERR("Invalid number of RX queues\n");
1905 if (num_rx_fqs > 0) {
1906 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1907 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1908 if (!dpaa_intf->rx_queues) {
1909 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1913 dpaa_intf->rx_queues = NULL;
1916 memset(cgrid, 0, sizeof(cgrid));
1917 memset(cgrid_tx, 0, sizeof(cgrid_tx));
1919 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1920 * Tx tail drop is disabled.
1922 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1923 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1924 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1926 /* if a very large value is being configured */
1927 if (td_tx_threshold > UINT16_MAX)
1928 td_tx_threshold = CGR_RX_PERFQ_THRESH;
1931 /* If congestion control is enabled globally*/
1932 if (num_rx_fqs > 0 && td_threshold) {
1933 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1934 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1935 if (!dpaa_intf->cgr_rx) {
1936 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1941 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1942 if (ret != num_rx_fqs) {
1943 DPAA_PMD_WARN("insufficient CGRIDs available");
1948 dpaa_intf->cgr_rx = NULL;
1951 if (!fmc_q && !default_q) {
1952 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1955 DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1960 for (loop = 0; loop < num_rx_fqs; loop++) {
1964 fqid = dev_rx_fqids[loop];
1966 vsp_id = dev_vspids[loop];
1968 if (dpaa_intf->cgr_rx)
1969 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1971 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1972 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1976 dpaa_intf->rx_queues[loop].vsp_id = vsp_id;
1977 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1979 dpaa_intf->nb_rx_queues = num_rx_fqs;
1981 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1982 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1983 MAX_DPAA_CORES, MAX_CACHELINE);
1984 if (!dpaa_intf->tx_queues) {
1985 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1990 /* If congestion control is enabled globally*/
1991 if (td_tx_threshold) {
1992 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1993 sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1995 if (!dpaa_intf->cgr_tx) {
1996 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
2001 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
2003 if (ret != MAX_DPAA_CORES) {
2004 DPAA_PMD_WARN("insufficient CGRIDs available");
2009 dpaa_intf->cgr_tx = NULL;
2013 for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
2014 if (dpaa_intf->cgr_tx)
2015 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
2017 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
2019 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
2022 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
2024 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
2026 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
2027 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2028 [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
2030 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!");
2033 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
2034 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2035 [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
2037 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!");
2040 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
2043 DPAA_PMD_DEBUG("All frame queues created");
2045 /* Get the initial configuration for flow control */
2046 dpaa_fc_set_default(dpaa_intf, fman_intf);
2048 /* reset bpool list, initialize bpool dynamically */
2049 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
2050 list_del(&bp->node);
2054 /* Populate ethdev structure */
2055 eth_dev->dev_ops = &dpaa_devops;
2056 eth_dev->rx_queue_count = dpaa_dev_rx_queue_count;
2057 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
2058 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
2060 /* Allocate memory for storing MAC addresses */
2061 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2062 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
2063 if (eth_dev->data->mac_addrs == NULL) {
2064 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
2065 "store MAC addresses",
2066 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
2071 /* copy the primary mac address */
2072 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]);
2074 RTE_LOG(INFO, PMD, "net: dpaa: %s: " RTE_ETHER_ADDR_PRT_FMT "\n",
2075 dpaa_device->name, RTE_ETHER_ADDR_BYTES(&fman_intf->mac_addr));
2077 if (!fman_intf->is_shared_mac) {
2078 /* Configure error packet handling */
2079 fman_if_receive_rx_errors(fman_intf,
2080 FM_FD_RX_STATUS_ERR_MASK);
2081 /* Disable RX mode */
2082 fman_if_disable_rx(fman_intf);
2083 /* Disable promiscuous mode */
2084 fman_if_promiscuous_disable(fman_intf);
2085 /* Disable multicast */
2086 fman_if_reset_mcast_filter_table(fman_intf);
2087 /* Reset interface statistics */
2088 fman_if_stats_reset(fman_intf);
2089 /* Disable SG by default */
2090 fman_if_set_sg(fman_intf, 0);
2091 fman_if_set_maxfrm(fman_intf,
2092 RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
2098 rte_free(dpaa_intf->tx_queues);
2099 dpaa_intf->tx_queues = NULL;
2100 dpaa_intf->nb_tx_queues = 0;
2103 rte_free(dpaa_intf->cgr_rx);
2104 rte_free(dpaa_intf->cgr_tx);
2105 rte_free(dpaa_intf->rx_queues);
2106 dpaa_intf->rx_queues = NULL;
2107 dpaa_intf->nb_rx_queues = 0;
2112 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
2113 struct rte_dpaa_device *dpaa_dev)
2117 struct rte_eth_dev *eth_dev;
2119 PMD_INIT_FUNC_TRACE();
2121 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
2122 RTE_PKTMBUF_HEADROOM) {
2124 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
2125 RTE_PKTMBUF_HEADROOM,
2126 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
2131 /* In case of secondary process, the device is already configured
2132 * and no further action is required, except portal initialization
2133 * and verifying secondary attachment to port name.
2135 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2136 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
2139 eth_dev->device = &dpaa_dev->device;
2140 eth_dev->dev_ops = &dpaa_devops;
2142 ret = dpaa_dev_init_secondary(eth_dev);
2144 RTE_LOG(ERR, PMD, "secondary dev init failed\n");
2148 rte_eth_dev_probing_finish(eth_dev);
2152 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
2153 if (access("/tmp/fmc.bin", F_OK) == -1) {
2154 DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
2158 if (!(default_q || fmc_q)) {
2159 if (dpaa_fm_init()) {
2160 DPAA_PMD_ERR("FM init failed\n");
2165 /* disabling the default push mode for LS1043 */
2166 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
2167 dpaa_push_mode_max_queue = 0;
2169 /* if push mode queues to be enabled. Currenly we are allowing
2170 * only one queue per thread.
2172 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
2173 dpaa_push_mode_max_queue =
2174 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
2175 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
2176 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
2182 if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
2183 ret = rte_dpaa_portal_init((void *)1);
2185 DPAA_PMD_ERR("Unable to initialize portal");
2190 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
2194 eth_dev->data->dev_private =
2195 rte_zmalloc("ethdev private structure",
2196 sizeof(struct dpaa_if),
2197 RTE_CACHE_LINE_SIZE);
2198 if (!eth_dev->data->dev_private) {
2199 DPAA_PMD_ERR("Cannot allocate memzone for port data");
2200 rte_eth_dev_release_port(eth_dev);
2204 eth_dev->device = &dpaa_dev->device;
2205 dpaa_dev->eth_dev = eth_dev;
2207 qman_ern_register_cb(dpaa_free_mbuf);
2209 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2210 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2212 /* Invoke PMD device initialization function */
2213 diag = dpaa_dev_init(eth_dev);
2215 rte_eth_dev_probing_finish(eth_dev);
2219 rte_eth_dev_release_port(eth_dev);
2224 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2226 struct rte_eth_dev *eth_dev;
2229 PMD_INIT_FUNC_TRACE();
2231 eth_dev = dpaa_dev->eth_dev;
2232 dpaa_eth_dev_close(eth_dev);
2233 ret = rte_eth_dev_release_port(eth_dev);
2238 static void __attribute__((destructor(102))) dpaa_finish(void)
2240 /* For secondary, primary will do all the cleanup */
2241 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2244 if (!(default_q || fmc_q)) {
2247 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2248 if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2249 struct rte_eth_dev *dev = &rte_eth_devices[i];
2250 struct dpaa_if *dpaa_intf =
2251 dev->data->dev_private;
2252 struct fman_if *fif =
2253 dev->process_private;
2254 if (dpaa_intf->port_handle)
2255 if (dpaa_fm_deconfig(dpaa_intf, fif))
2256 DPAA_PMD_WARN("DPAA FM "
2257 "deconfig failed\n");
2258 if (fif->num_profiles) {
2259 if (dpaa_port_vsp_cleanup(dpaa_intf,
2261 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n");
2267 DPAA_PMD_WARN("DPAA FM term failed\n");
2271 DPAA_PMD_INFO("DPAA fman cleaned up");
2275 static struct rte_dpaa_driver rte_dpaa_pmd = {
2276 .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2277 .drv_type = FSL_DPAA_ETH,
2278 .probe = rte_dpaa_probe,
2279 .remove = rte_dpaa_remove,
2282 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2283 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE);