1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
15 #include <sys/types.h>
16 #include <sys/syscall.h>
18 #include <rte_byteorder.h>
19 #include <rte_common.h>
20 #include <rte_interrupts.h>
22 #include <rte_debug.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_malloc.h>
35 #include <rte_dpaa_bus.h>
36 #include <rte_dpaa_logs.h>
37 #include <dpaa_mempool.h>
39 #include <dpaa_ethdev.h>
40 #include <dpaa_rxtx.h>
41 #include <rte_pmd_dpaa.h>
48 /* Supported Rx offloads */
49 static uint64_t dev_rx_offloads_sup =
50 DEV_RX_OFFLOAD_JUMBO_FRAME |
51 DEV_RX_OFFLOAD_SCATTER;
53 /* Rx offloads which cannot be disabled */
54 static uint64_t dev_rx_offloads_nodis =
55 DEV_RX_OFFLOAD_IPV4_CKSUM |
56 DEV_RX_OFFLOAD_UDP_CKSUM |
57 DEV_RX_OFFLOAD_TCP_CKSUM |
58 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
60 /* Supported Tx offloads */
61 static uint64_t dev_tx_offloads_sup;
63 /* Tx offloads which cannot be disabled */
64 static uint64_t dev_tx_offloads_nodis =
65 DEV_TX_OFFLOAD_IPV4_CKSUM |
66 DEV_TX_OFFLOAD_UDP_CKSUM |
67 DEV_TX_OFFLOAD_TCP_CKSUM |
68 DEV_TX_OFFLOAD_SCTP_CKSUM |
69 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
70 DEV_TX_OFFLOAD_MULTI_SEGS |
71 DEV_TX_OFFLOAD_MT_LOCKFREE |
72 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
74 /* Keep track of whether QMAN and BMAN have been globally initialized */
75 static int is_global_init;
76 static int default_q; /* use default queue - FMC is not executed*/
77 /* At present we only allow up to 4 push mode queues as default - as each of
78 * this queue need dedicated portal and we are short of portals.
80 #define DPAA_MAX_PUSH_MODE_QUEUE 8
81 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
83 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
84 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
87 /* Per FQ Taildrop in frame count */
88 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
90 struct rte_dpaa_xstats_name_off {
91 char name[RTE_ETH_XSTATS_NAME_SIZE];
95 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
97 offsetof(struct dpaa_if_stats, raln)},
99 offsetof(struct dpaa_if_stats, rxpf)},
101 offsetof(struct dpaa_if_stats, rfcs)},
103 offsetof(struct dpaa_if_stats, rvlan)},
105 offsetof(struct dpaa_if_stats, rerr)},
107 offsetof(struct dpaa_if_stats, rdrp)},
109 offsetof(struct dpaa_if_stats, rund)},
111 offsetof(struct dpaa_if_stats, rovr)},
113 offsetof(struct dpaa_if_stats, rfrg)},
115 offsetof(struct dpaa_if_stats, txpf)},
117 offsetof(struct dpaa_if_stats, terr)},
119 offsetof(struct dpaa_if_stats, tvlan)},
121 offsetof(struct dpaa_if_stats, tund)},
124 static struct rte_dpaa_driver rte_dpaa_pmd;
127 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
130 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
132 memset(opts, 0, sizeof(struct qm_mcc_initfq));
133 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
134 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
135 QM_FQCTRL_PREFERINCACHE;
136 opts->fqd.context_a.stashing.exclusive = 0;
137 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
138 opts->fqd.context_a.stashing.annotation_cl =
139 DPAA_IF_RX_ANNOTATION_STASH;
140 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
141 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
145 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
147 struct dpaa_if *dpaa_intf = dev->data->dev_private;
148 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
150 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
152 PMD_INIT_FUNC_TRACE();
154 if (mtu < ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
157 * Refuse mtu that requires the support of scattered packets
158 * when this feature has not been enabled before.
160 if (dev->data->min_rx_buf_size &&
161 !dev->data->scattered_rx && frame_size > buffsz) {
162 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
166 /* check <seg size> * <max_seg> >= max_frame */
167 if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
168 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
169 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
170 buffsz * DPAA_SGT_MAX_ENTRIES);
174 if (frame_size > ETHER_MAX_LEN)
175 dev->data->dev_conf.rxmode.offloads &=
176 DEV_RX_OFFLOAD_JUMBO_FRAME;
178 dev->data->dev_conf.rxmode.offloads &=
179 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
181 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
183 fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
189 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
191 struct dpaa_if *dpaa_intf = dev->data->dev_private;
192 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
193 uint64_t rx_offloads = eth_conf->rxmode.offloads;
194 uint64_t tx_offloads = eth_conf->txmode.offloads;
196 PMD_INIT_FUNC_TRACE();
198 /* Rx offloads validation */
199 if (dev_rx_offloads_nodis & ~rx_offloads) {
201 "Rx offloads non configurable - requested 0x%" PRIx64
202 " ignored 0x%" PRIx64,
203 rx_offloads, dev_rx_offloads_nodis);
206 /* Tx offloads validation */
207 if (dev_tx_offloads_nodis & ~tx_offloads) {
209 "Tx offloads non configurable - requested 0x%" PRIx64
210 " ignored 0x%" PRIx64,
211 tx_offloads, dev_tx_offloads_nodis);
214 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
217 DPAA_PMD_DEBUG("enabling jumbo");
219 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
221 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
223 DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
225 dev->data->dev_conf.rxmode.max_rx_pkt_len,
226 DPAA_MAX_RX_PKT_LEN);
227 max_len = DPAA_MAX_RX_PKT_LEN;
230 fman_if_set_maxfrm(dpaa_intf->fif, max_len);
231 dev->data->mtu = max_len
232 - ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
235 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
236 DPAA_PMD_DEBUG("enabling scatter mode");
237 fman_if_set_sg(dpaa_intf->fif, 1);
238 dev->data->scattered_rx = 1;
244 static const uint32_t *
245 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
247 static const uint32_t ptypes[] = {
249 RTE_PTYPE_L2_ETHER_VLAN,
250 RTE_PTYPE_L2_ETHER_ARP,
251 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
252 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
262 PMD_INIT_FUNC_TRACE();
264 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
269 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
271 struct dpaa_if *dpaa_intf = dev->data->dev_private;
273 PMD_INIT_FUNC_TRACE();
275 /* Change tx callback to the real one */
276 dev->tx_pkt_burst = dpaa_eth_queue_tx;
277 fman_if_enable_rx(dpaa_intf->fif);
282 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
284 struct dpaa_if *dpaa_intf = dev->data->dev_private;
286 PMD_INIT_FUNC_TRACE();
288 fman_if_disable_rx(dpaa_intf->fif);
289 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
292 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
294 PMD_INIT_FUNC_TRACE();
296 dpaa_eth_dev_stop(dev);
300 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
305 FILE *svr_file = NULL;
306 unsigned int svr_ver = 0;
308 PMD_INIT_FUNC_TRACE();
310 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
312 DPAA_PMD_ERR("Unable to open SoC device");
313 return -ENOTSUP; /* Not supported on this infra */
315 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
316 dpaa_svr_family = svr_ver & SVR_MASK;
318 DPAA_PMD_ERR("Unable to read SoC device");
322 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
323 svr_ver, fman_ip_rev);
324 ret += 1; /* add the size of '\0' */
326 if (fw_size < (uint32_t)ret)
332 static void dpaa_eth_dev_info(struct rte_eth_dev *dev,
333 struct rte_eth_dev_info *dev_info)
335 struct dpaa_if *dpaa_intf = dev->data->dev_private;
337 PMD_INIT_FUNC_TRACE();
339 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
340 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
341 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
342 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
343 dev_info->max_hash_mac_addrs = 0;
344 dev_info->max_vfs = 0;
345 dev_info->max_vmdq_pools = ETH_16_POOLS;
346 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
348 if (dpaa_intf->fif->mac_type == fman_mac_1g)
349 dev_info->speed_capa = ETH_LINK_SPEED_1G;
350 else if (dpaa_intf->fif->mac_type == fman_mac_10g)
351 dev_info->speed_capa = (ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G);
353 DPAA_PMD_ERR("invalid link_speed: %s, %d",
354 dpaa_intf->name, dpaa_intf->fif->mac_type);
356 dev_info->rx_offload_capa = dev_rx_offloads_sup |
357 dev_rx_offloads_nodis;
358 dev_info->tx_offload_capa = dev_tx_offloads_sup |
359 dev_tx_offloads_nodis;
360 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
361 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
364 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
365 int wait_to_complete __rte_unused)
367 struct dpaa_if *dpaa_intf = dev->data->dev_private;
368 struct rte_eth_link *link = &dev->data->dev_link;
370 PMD_INIT_FUNC_TRACE();
372 if (dpaa_intf->fif->mac_type == fman_mac_1g)
373 link->link_speed = ETH_SPEED_NUM_1G;
374 else if (dpaa_intf->fif->mac_type == fman_mac_10g)
375 link->link_speed = ETH_SPEED_NUM_10G;
377 DPAA_PMD_ERR("invalid link_speed: %s, %d",
378 dpaa_intf->name, dpaa_intf->fif->mac_type);
380 link->link_status = dpaa_intf->valid;
381 link->link_duplex = ETH_LINK_FULL_DUPLEX;
382 link->link_autoneg = ETH_LINK_AUTONEG;
386 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
387 struct rte_eth_stats *stats)
389 struct dpaa_if *dpaa_intf = dev->data->dev_private;
391 PMD_INIT_FUNC_TRACE();
393 fman_if_stats_get(dpaa_intf->fif, stats);
397 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev)
399 struct dpaa_if *dpaa_intf = dev->data->dev_private;
401 PMD_INIT_FUNC_TRACE();
403 fman_if_stats_reset(dpaa_intf->fif);
407 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
410 struct dpaa_if *dpaa_intf = dev->data->dev_private;
411 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
412 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
420 fman_if_stats_get_all(dpaa_intf->fif, values,
421 sizeof(struct dpaa_if_stats) / 8);
423 for (i = 0; i < num; i++) {
425 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
431 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
432 struct rte_eth_xstat_name *xstats_names,
435 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
437 if (limit < stat_cnt)
440 if (xstats_names != NULL)
441 for (i = 0; i < stat_cnt; i++)
442 snprintf(xstats_names[i].name,
443 sizeof(xstats_names[i].name),
445 dpaa_xstats_strings[i].name);
451 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
452 uint64_t *values, unsigned int n)
454 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
455 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
458 struct dpaa_if *dpaa_intf = dev->data->dev_private;
466 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
467 sizeof(struct dpaa_if_stats) / 8);
469 for (i = 0; i < stat_cnt; i++)
471 values_copy[dpaa_xstats_strings[i].offset / 8];
476 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
478 for (i = 0; i < n; i++) {
479 if (ids[i] >= stat_cnt) {
480 DPAA_PMD_ERR("id value isn't valid");
483 values[i] = values_copy[ids[i]];
489 dpaa_xstats_get_names_by_id(
490 struct rte_eth_dev *dev,
491 struct rte_eth_xstat_name *xstats_names,
495 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
496 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
499 return dpaa_xstats_get_names(dev, xstats_names, limit);
501 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
503 for (i = 0; i < limit; i++) {
504 if (ids[i] >= stat_cnt) {
505 DPAA_PMD_ERR("id value isn't valid");
508 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
513 static void dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
515 struct dpaa_if *dpaa_intf = dev->data->dev_private;
517 PMD_INIT_FUNC_TRACE();
519 fman_if_promiscuous_enable(dpaa_intf->fif);
522 static void dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
524 struct dpaa_if *dpaa_intf = dev->data->dev_private;
526 PMD_INIT_FUNC_TRACE();
528 fman_if_promiscuous_disable(dpaa_intf->fif);
531 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
533 struct dpaa_if *dpaa_intf = dev->data->dev_private;
535 PMD_INIT_FUNC_TRACE();
537 fman_if_set_mcast_filter_table(dpaa_intf->fif);
540 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
542 struct dpaa_if *dpaa_intf = dev->data->dev_private;
544 PMD_INIT_FUNC_TRACE();
546 fman_if_reset_mcast_filter_table(dpaa_intf->fif);
550 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
552 unsigned int socket_id __rte_unused,
553 const struct rte_eth_rxconf *rx_conf __rte_unused,
554 struct rte_mempool *mp)
556 struct dpaa_if *dpaa_intf = dev->data->dev_private;
557 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
558 struct qm_mcc_initfq opts = {0};
561 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
563 PMD_INIT_FUNC_TRACE();
565 if (queue_idx >= dev->data->nb_rx_queues) {
566 rte_errno = EOVERFLOW;
567 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
568 (void *)dev, queue_idx, dev->data->nb_rx_queues);
572 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
573 queue_idx, rxq->fqid);
575 /* Max packet can fit in single buffer */
576 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
578 } else if (dev->data->dev_conf.rxmode.offloads &
579 DEV_RX_OFFLOAD_SCATTER) {
580 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
581 buffsz * DPAA_SGT_MAX_ENTRIES) {
582 DPAA_PMD_ERR("max RxPkt size %d too big to fit "
584 dev->data->dev_conf.rxmode.max_rx_pkt_len,
585 buffsz * DPAA_SGT_MAX_ENTRIES);
586 rte_errno = EOVERFLOW;
590 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
591 " larger than a single mbuf (%u) and scattered"
592 " mode has not been requested",
593 dev->data->dev_conf.rxmode.max_rx_pkt_len,
594 buffsz - RTE_PKTMBUF_HEADROOM);
597 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
598 struct fman_if_ic_params icp;
602 if (!mp->pool_data) {
603 DPAA_PMD_ERR("Not an offloaded buffer pool!");
606 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
608 memset(&icp, 0, sizeof(icp));
609 /* set ICEOF for to the default value , which is 0*/
610 icp.iciof = DEFAULT_ICIOF;
611 icp.iceof = DEFAULT_RX_ICEOF;
612 icp.icsz = DEFAULT_ICSZ;
613 fman_if_set_ic_params(dpaa_intf->fif, &icp);
615 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
616 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
618 /* Buffer pool size should be equal to Dataroom Size*/
619 bp_size = rte_pktmbuf_data_room_size(mp);
620 fman_if_set_bp(dpaa_intf->fif, mp->size,
621 dpaa_intf->bp_info->bpid, bp_size);
622 dpaa_intf->valid = 1;
623 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
624 dpaa_intf->name, fd_offset,
625 fman_if_get_fdoff(dpaa_intf->fif));
627 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
628 fman_if_get_sg_enable(dpaa_intf->fif),
629 dev->data->dev_conf.rxmode.max_rx_pkt_len);
630 /* checking if push mode only, no error check for now */
631 if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
632 dpaa_push_queue_idx++;
633 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
634 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
635 QM_FQCTRL_CTXASTASHING |
636 QM_FQCTRL_PREFERINCACHE;
637 opts.fqd.context_a.stashing.exclusive = 0;
638 /* In muticore scenario stashing becomes a bottleneck on LS1046.
639 * So do not enable stashing in this case
641 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
642 opts.fqd.context_a.stashing.annotation_cl =
643 DPAA_IF_RX_ANNOTATION_STASH;
644 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
645 opts.fqd.context_a.stashing.context_cl =
646 DPAA_IF_RX_CONTEXT_STASH;
648 /*Create a channel and associate given queue with the channel*/
649 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
650 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
651 opts.fqd.dest.channel = rxq->ch_id;
652 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
653 flags = QMAN_INITFQ_FLAG_SCHED;
655 /* Configure tail drop */
656 if (dpaa_intf->cgr_rx) {
657 opts.we_mask |= QM_INITFQ_WE_CGID;
658 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
659 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
661 ret = qman_init_fq(rxq, flags, &opts);
663 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
664 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
667 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
668 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
670 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
671 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
674 rxq->is_static = true;
676 dev->data->rx_queues[queue_idx] = rxq;
678 /* configure the CGR size as per the desc size */
679 if (dpaa_intf->cgr_rx) {
680 struct qm_mcc_initcgr cgr_opts = {0};
682 /* Enable tail drop with cgr on this queue */
683 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
684 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
687 "rx taildrop modify fail on fqid %d (ret=%d)",
696 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
699 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
703 struct dpaa_if *dpaa_intf = dev->data->dev_private;
704 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
705 struct qm_mcc_initfq opts = {0};
707 if (dpaa_push_mode_max_queue)
708 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
709 "PUSH mode already enabled for first %d queues.\n"
710 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
711 dpaa_push_mode_max_queue);
713 dpaa_poll_queue_default_config(&opts);
715 switch (queue_conf->ev.sched_type) {
716 case RTE_SCHED_TYPE_ATOMIC:
717 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
718 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
719 * configuration with HOLD_ACTIVE setting
721 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
722 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
724 case RTE_SCHED_TYPE_ORDERED:
725 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
728 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
729 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
733 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
734 opts.fqd.dest.channel = ch_id;
735 opts.fqd.dest.wq = queue_conf->ev.priority;
737 if (dpaa_intf->cgr_rx) {
738 opts.we_mask |= QM_INITFQ_WE_CGID;
739 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
740 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
743 flags = QMAN_INITFQ_FLAG_SCHED;
745 ret = qman_init_fq(rxq, flags, &opts);
747 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
748 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
752 /* copy configuration which needs to be filled during dequeue */
753 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
754 dev->data->rx_queues[eth_rx_queue_id] = rxq;
760 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
763 struct qm_mcc_initfq opts;
766 struct dpaa_if *dpaa_intf = dev->data->dev_private;
767 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
769 dpaa_poll_queue_default_config(&opts);
771 if (dpaa_intf->cgr_rx) {
772 opts.we_mask |= QM_INITFQ_WE_CGID;
773 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
774 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
777 ret = qman_init_fq(rxq, flags, &opts);
779 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
783 rxq->cb.dqrr_dpdk_cb = NULL;
784 dev->data->rx_queues[eth_rx_queue_id] = NULL;
790 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
792 PMD_INIT_FUNC_TRACE();
796 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
797 uint16_t nb_desc __rte_unused,
798 unsigned int socket_id __rte_unused,
799 const struct rte_eth_txconf *tx_conf __rte_unused)
801 struct dpaa_if *dpaa_intf = dev->data->dev_private;
803 PMD_INIT_FUNC_TRACE();
805 if (queue_idx >= dev->data->nb_tx_queues) {
806 rte_errno = EOVERFLOW;
807 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
808 (void *)dev, queue_idx, dev->data->nb_tx_queues);
812 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
813 queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
814 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
818 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
820 PMD_INIT_FUNC_TRACE();
824 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
826 struct dpaa_if *dpaa_intf = dev->data->dev_private;
827 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
830 PMD_INIT_FUNC_TRACE();
832 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
833 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
834 rx_queue_id, frm_cnt);
839 static int dpaa_link_down(struct rte_eth_dev *dev)
841 PMD_INIT_FUNC_TRACE();
843 dpaa_eth_dev_stop(dev);
847 static int dpaa_link_up(struct rte_eth_dev *dev)
849 PMD_INIT_FUNC_TRACE();
851 dpaa_eth_dev_start(dev);
856 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
857 struct rte_eth_fc_conf *fc_conf)
859 struct dpaa_if *dpaa_intf = dev->data->dev_private;
860 struct rte_eth_fc_conf *net_fc;
862 PMD_INIT_FUNC_TRACE();
864 if (!(dpaa_intf->fc_conf)) {
865 dpaa_intf->fc_conf = rte_zmalloc(NULL,
866 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
867 if (!dpaa_intf->fc_conf) {
868 DPAA_PMD_ERR("unable to save flow control info");
872 net_fc = dpaa_intf->fc_conf;
874 if (fc_conf->high_water < fc_conf->low_water) {
875 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
879 if (fc_conf->mode == RTE_FC_NONE) {
881 } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
882 fc_conf->mode == RTE_FC_FULL) {
883 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
885 dpaa_intf->bp_info->bpid);
886 if (fc_conf->pause_time)
887 fman_if_set_fc_quanta(dpaa_intf->fif,
888 fc_conf->pause_time);
891 /* Save the information in dpaa device */
892 net_fc->pause_time = fc_conf->pause_time;
893 net_fc->high_water = fc_conf->high_water;
894 net_fc->low_water = fc_conf->low_water;
895 net_fc->send_xon = fc_conf->send_xon;
896 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
897 net_fc->mode = fc_conf->mode;
898 net_fc->autoneg = fc_conf->autoneg;
904 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
905 struct rte_eth_fc_conf *fc_conf)
907 struct dpaa_if *dpaa_intf = dev->data->dev_private;
908 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
911 PMD_INIT_FUNC_TRACE();
914 fc_conf->pause_time = net_fc->pause_time;
915 fc_conf->high_water = net_fc->high_water;
916 fc_conf->low_water = net_fc->low_water;
917 fc_conf->send_xon = net_fc->send_xon;
918 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
919 fc_conf->mode = net_fc->mode;
920 fc_conf->autoneg = net_fc->autoneg;
923 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
925 fc_conf->mode = RTE_FC_TX_PAUSE;
926 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
928 fc_conf->mode = RTE_FC_NONE;
935 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
936 struct ether_addr *addr,
938 __rte_unused uint32_t pool)
941 struct dpaa_if *dpaa_intf = dev->data->dev_private;
943 PMD_INIT_FUNC_TRACE();
945 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
948 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
954 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
957 struct dpaa_if *dpaa_intf = dev->data->dev_private;
959 PMD_INIT_FUNC_TRACE();
961 fman_if_clear_mac_addr(dpaa_intf->fif, index);
965 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
966 struct ether_addr *addr)
969 struct dpaa_if *dpaa_intf = dev->data->dev_private;
971 PMD_INIT_FUNC_TRACE();
973 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
975 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
980 static struct eth_dev_ops dpaa_devops = {
981 .dev_configure = dpaa_eth_dev_configure,
982 .dev_start = dpaa_eth_dev_start,
983 .dev_stop = dpaa_eth_dev_stop,
984 .dev_close = dpaa_eth_dev_close,
985 .dev_infos_get = dpaa_eth_dev_info,
986 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
988 .rx_queue_setup = dpaa_eth_rx_queue_setup,
989 .tx_queue_setup = dpaa_eth_tx_queue_setup,
990 .rx_queue_release = dpaa_eth_rx_queue_release,
991 .tx_queue_release = dpaa_eth_tx_queue_release,
992 .rx_queue_count = dpaa_dev_rx_queue_count,
994 .flow_ctrl_get = dpaa_flow_ctrl_get,
995 .flow_ctrl_set = dpaa_flow_ctrl_set,
997 .link_update = dpaa_eth_link_update,
998 .stats_get = dpaa_eth_stats_get,
999 .xstats_get = dpaa_dev_xstats_get,
1000 .xstats_get_by_id = dpaa_xstats_get_by_id,
1001 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
1002 .xstats_get_names = dpaa_xstats_get_names,
1003 .xstats_reset = dpaa_eth_stats_reset,
1004 .stats_reset = dpaa_eth_stats_reset,
1005 .promiscuous_enable = dpaa_eth_promiscuous_enable,
1006 .promiscuous_disable = dpaa_eth_promiscuous_disable,
1007 .allmulticast_enable = dpaa_eth_multicast_enable,
1008 .allmulticast_disable = dpaa_eth_multicast_disable,
1009 .mtu_set = dpaa_mtu_set,
1010 .dev_set_link_down = dpaa_link_down,
1011 .dev_set_link_up = dpaa_link_up,
1012 .mac_addr_add = dpaa_dev_add_mac_addr,
1013 .mac_addr_remove = dpaa_dev_remove_mac_addr,
1014 .mac_addr_set = dpaa_dev_set_mac_addr,
1016 .fw_version_get = dpaa_fw_version_get,
1020 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1022 if (strcmp(dev->device->driver->name,
1030 is_dpaa_supported(struct rte_eth_dev *dev)
1032 return is_device_supported(dev, &rte_dpaa_pmd);
1036 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1038 struct rte_eth_dev *dev;
1039 struct dpaa_if *dpaa_intf;
1041 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1043 dev = &rte_eth_devices[port];
1045 if (!is_dpaa_supported(dev))
1048 dpaa_intf = dev->data->dev_private;
1051 fman_if_loopback_enable(dpaa_intf->fif);
1053 fman_if_loopback_disable(dpaa_intf->fif);
1058 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
1060 struct rte_eth_fc_conf *fc_conf;
1063 PMD_INIT_FUNC_TRACE();
1065 if (!(dpaa_intf->fc_conf)) {
1066 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1067 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1068 if (!dpaa_intf->fc_conf) {
1069 DPAA_PMD_ERR("unable to save flow control info");
1073 fc_conf = dpaa_intf->fc_conf;
1074 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
1076 fc_conf->mode = RTE_FC_TX_PAUSE;
1077 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1079 fc_conf->mode = RTE_FC_NONE;
1085 /* Initialise an Rx FQ */
1086 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1089 struct qm_mcc_initfq opts = {0};
1091 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1092 struct qm_mcc_initcgr cgr_opts = {
1093 .we_mask = QM_CGR_WE_CS_THRES |
1097 .cstd_en = QM_CGR_EN,
1098 .mode = QMAN_CGR_MODE_FRAME
1102 PMD_INIT_FUNC_TRACE();
1105 ret = qman_reserve_fqid(fqid);
1107 DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1112 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1114 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1115 ret = qman_create_fq(fqid, flags, fq);
1117 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1121 fq->is_static = false;
1123 dpaa_poll_queue_default_config(&opts);
1126 /* Enable tail drop with cgr on this queue */
1127 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1129 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1133 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1137 opts.we_mask |= QM_INITFQ_WE_CGID;
1138 opts.fqd.cgid = cgr_rx->cgrid;
1139 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1142 ret = qman_init_fq(fq, 0, &opts);
1144 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1148 /* Initialise a Tx FQ */
1149 static int dpaa_tx_queue_init(struct qman_fq *fq,
1150 struct fman_if *fman_intf)
1152 struct qm_mcc_initfq opts = {0};
1155 PMD_INIT_FUNC_TRACE();
1157 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1158 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1160 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1163 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1164 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1165 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1166 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1167 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1168 opts.fqd.context_b = 0;
1169 /* no tx-confirmation */
1170 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1171 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1172 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1173 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1175 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1179 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1180 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1181 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1183 struct qm_mcc_initfq opts = {0};
1186 PMD_INIT_FUNC_TRACE();
1188 ret = qman_reserve_fqid(fqid);
1190 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1194 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1195 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1196 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1198 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1202 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1203 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1204 ret = qman_init_fq(fq, 0, &opts);
1206 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1212 /* Initialise a network interface */
1214 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1216 int num_cores, num_rx_fqs, fqid;
1219 struct rte_dpaa_device *dpaa_device;
1220 struct dpaa_if *dpaa_intf;
1221 struct fm_eth_port_cfg *cfg;
1222 struct fman_if *fman_intf;
1223 struct fman_if_bpool *bp, *tmp_bp;
1224 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1226 PMD_INIT_FUNC_TRACE();
1228 /* For secondary processes, the primary has done all the work */
1229 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1230 eth_dev->dev_ops = &dpaa_devops;
1231 /* Plugging of UCODE burst API not supported in Secondary */
1232 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1236 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1237 dev_id = dpaa_device->id.dev_id;
1238 dpaa_intf = eth_dev->data->dev_private;
1239 cfg = &dpaa_netcfg->port_cfg[dev_id];
1240 fman_intf = cfg->fman_if;
1242 dpaa_intf->name = dpaa_device->name;
1244 /* save fman_if & cfg in the interface struture */
1245 dpaa_intf->fif = fman_intf;
1246 dpaa_intf->ifid = dev_id;
1247 dpaa_intf->cfg = cfg;
1249 /* Initialize Rx FQ's */
1251 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1253 if (getenv("DPAA_NUM_RX_QUEUES"))
1254 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1256 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1260 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1263 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1264 DPAA_PMD_ERR("Invalid number of RX queues\n");
1268 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1269 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1270 if (!dpaa_intf->rx_queues) {
1271 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1275 /* If congestion control is enabled globally*/
1277 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1278 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1279 if (!dpaa_intf->cgr_rx) {
1280 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1285 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1286 if (ret != num_rx_fqs) {
1287 DPAA_PMD_WARN("insufficient CGRIDs available");
1292 dpaa_intf->cgr_rx = NULL;
1295 for (loop = 0; loop < num_rx_fqs; loop++) {
1299 fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx *
1300 DPAA_PCD_FQID_MULTIPLIER + loop;
1302 if (dpaa_intf->cgr_rx)
1303 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1305 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1306 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1310 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1312 dpaa_intf->nb_rx_queues = num_rx_fqs;
1314 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1315 num_cores = rte_lcore_count();
1316 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1317 num_cores, MAX_CACHELINE);
1318 if (!dpaa_intf->tx_queues) {
1319 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1324 for (loop = 0; loop < num_cores; loop++) {
1325 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1329 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1331 dpaa_intf->nb_tx_queues = num_cores;
1333 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1334 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1335 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1336 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1337 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1338 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1339 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1342 DPAA_PMD_DEBUG("All frame queues created");
1344 /* Get the initial configuration for flow control */
1345 dpaa_fc_set_default(dpaa_intf);
1347 /* reset bpool list, initialize bpool dynamically */
1348 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1349 list_del(&bp->node);
1353 /* Populate ethdev structure */
1354 eth_dev->dev_ops = &dpaa_devops;
1355 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1356 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1358 /* Allocate memory for storing MAC addresses */
1359 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1360 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1361 if (eth_dev->data->mac_addrs == NULL) {
1362 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1363 "store MAC addresses",
1364 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1369 /* copy the primary mac address */
1370 ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]);
1372 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1374 fman_intf->mac_addr.addr_bytes[0],
1375 fman_intf->mac_addr.addr_bytes[1],
1376 fman_intf->mac_addr.addr_bytes[2],
1377 fman_intf->mac_addr.addr_bytes[3],
1378 fman_intf->mac_addr.addr_bytes[4],
1379 fman_intf->mac_addr.addr_bytes[5]);
1381 /* Disable RX mode */
1382 fman_if_discard_rx_errors(fman_intf);
1383 fman_if_disable_rx(fman_intf);
1384 /* Disable promiscuous mode */
1385 fman_if_promiscuous_disable(fman_intf);
1386 /* Disable multicast */
1387 fman_if_reset_mcast_filter_table(fman_intf);
1388 /* Reset interface statistics */
1389 fman_if_stats_reset(fman_intf);
1390 /* Disable SG by default */
1391 fman_if_set_sg(fman_intf, 0);
1392 fman_if_set_maxfrm(fman_intf, ETHER_MAX_LEN + VLAN_TAG_SIZE);
1397 rte_free(dpaa_intf->tx_queues);
1398 dpaa_intf->tx_queues = NULL;
1399 dpaa_intf->nb_tx_queues = 0;
1402 rte_free(dpaa_intf->cgr_rx);
1403 rte_free(dpaa_intf->rx_queues);
1404 dpaa_intf->rx_queues = NULL;
1405 dpaa_intf->nb_rx_queues = 0;
1410 dpaa_dev_uninit(struct rte_eth_dev *dev)
1412 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1415 PMD_INIT_FUNC_TRACE();
1417 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1421 DPAA_PMD_WARN("Already closed or not started");
1425 dpaa_eth_dev_close(dev);
1427 /* release configuration memory */
1428 if (dpaa_intf->fc_conf)
1429 rte_free(dpaa_intf->fc_conf);
1431 /* Release RX congestion Groups */
1432 if (dpaa_intf->cgr_rx) {
1433 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1434 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1436 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1437 dpaa_intf->nb_rx_queues);
1440 rte_free(dpaa_intf->cgr_rx);
1441 dpaa_intf->cgr_rx = NULL;
1443 rte_free(dpaa_intf->rx_queues);
1444 dpaa_intf->rx_queues = NULL;
1446 rte_free(dpaa_intf->tx_queues);
1447 dpaa_intf->tx_queues = NULL;
1449 dev->dev_ops = NULL;
1450 dev->rx_pkt_burst = NULL;
1451 dev->tx_pkt_burst = NULL;
1457 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1458 struct rte_dpaa_device *dpaa_dev)
1462 struct rte_eth_dev *eth_dev;
1464 PMD_INIT_FUNC_TRACE();
1466 /* In case of secondary process, the device is already configured
1467 * and no further action is required, except portal initialization
1468 * and verifying secondary attachment to port name.
1470 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1471 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1474 eth_dev->device = &dpaa_dev->device;
1475 eth_dev->dev_ops = &dpaa_devops;
1476 rte_eth_dev_probing_finish(eth_dev);
1480 if (!is_global_init) {
1481 /* One time load of Qman/Bman drivers */
1482 ret = qman_global_init();
1484 DPAA_PMD_ERR("QMAN initialization failed: %d",
1488 ret = bman_global_init();
1490 DPAA_PMD_ERR("BMAN initialization failed: %d",
1495 if (access("/tmp/fmc.bin", F_OK) == -1) {
1497 "* FMC not configured.Enabling default mode\n");
1501 /* disabling the default push mode for LS1043 */
1502 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1503 dpaa_push_mode_max_queue = 0;
1505 /* if push mode queues to be enabled. Currenly we are allowing
1506 * only one queue per thread.
1508 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1509 dpaa_push_mode_max_queue =
1510 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1511 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1512 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1518 if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1519 ret = rte_dpaa_portal_init((void *)1);
1521 DPAA_PMD_ERR("Unable to initialize portal");
1526 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1527 if (eth_dev == NULL)
1530 eth_dev->data->dev_private = rte_zmalloc(
1531 "ethdev private structure",
1532 sizeof(struct dpaa_if),
1533 RTE_CACHE_LINE_SIZE);
1534 if (!eth_dev->data->dev_private) {
1535 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1536 rte_eth_dev_release_port(eth_dev);
1540 eth_dev->device = &dpaa_dev->device;
1541 dpaa_dev->eth_dev = eth_dev;
1543 /* Invoke PMD device initialization function */
1544 diag = dpaa_dev_init(eth_dev);
1546 rte_eth_dev_probing_finish(eth_dev);
1550 rte_eth_dev_release_port(eth_dev);
1555 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1557 struct rte_eth_dev *eth_dev;
1559 PMD_INIT_FUNC_TRACE();
1561 eth_dev = dpaa_dev->eth_dev;
1562 dpaa_dev_uninit(eth_dev);
1564 rte_eth_dev_release_port(eth_dev);
1569 static struct rte_dpaa_driver rte_dpaa_pmd = {
1570 .drv_type = FSL_DPAA_ETH,
1571 .probe = rte_dpaa_probe,
1572 .remove = rte_dpaa_remove,
1575 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);