1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2017-2020 NXP
15 #include <sys/types.h>
16 #include <sys/syscall.h>
18 #include <rte_string_fns.h>
19 #include <rte_byteorder.h>
20 #include <rte_common.h>
21 #include <rte_interrupts.h>
23 #include <rte_debug.h>
25 #include <rte_atomic.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_memory.h>
28 #include <rte_tailq.h>
30 #include <rte_alarm.h>
31 #include <rte_ether.h>
32 #include <rte_ethdev_driver.h>
33 #include <rte_malloc.h>
36 #include <rte_dpaa_bus.h>
37 #include <rte_dpaa_logs.h>
38 #include <dpaa_mempool.h>
40 #include <dpaa_ethdev.h>
41 #include <dpaa_rxtx.h>
42 #include <rte_pmd_dpaa.h>
49 /* Supported Rx offloads */
50 static uint64_t dev_rx_offloads_sup =
51 DEV_RX_OFFLOAD_JUMBO_FRAME |
52 DEV_RX_OFFLOAD_SCATTER;
54 /* Rx offloads which cannot be disabled */
55 static uint64_t dev_rx_offloads_nodis =
56 DEV_RX_OFFLOAD_IPV4_CKSUM |
57 DEV_RX_OFFLOAD_UDP_CKSUM |
58 DEV_RX_OFFLOAD_TCP_CKSUM |
59 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
60 DEV_RX_OFFLOAD_RSS_HASH;
62 /* Supported Tx offloads */
63 static uint64_t dev_tx_offloads_sup =
64 DEV_TX_OFFLOAD_MT_LOCKFREE |
65 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
67 /* Tx offloads which cannot be disabled */
68 static uint64_t dev_tx_offloads_nodis =
69 DEV_TX_OFFLOAD_IPV4_CKSUM |
70 DEV_TX_OFFLOAD_UDP_CKSUM |
71 DEV_TX_OFFLOAD_TCP_CKSUM |
72 DEV_TX_OFFLOAD_SCTP_CKSUM |
73 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
74 DEV_TX_OFFLOAD_MULTI_SEGS;
76 /* Keep track of whether QMAN and BMAN have been globally initialized */
77 static int is_global_init;
78 static int default_q; /* use default queue - FMC is not executed*/
79 /* At present we only allow up to 4 push mode queues as default - as each of
80 * this queue need dedicated portal and we are short of portals.
82 #define DPAA_MAX_PUSH_MODE_QUEUE 8
83 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
85 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
86 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
89 /* Per RX FQ Taildrop in frame count */
90 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
92 /* Per TX FQ Taildrop in frame count, disabled by default */
93 static unsigned int td_tx_threshold;
95 struct rte_dpaa_xstats_name_off {
96 char name[RTE_ETH_XSTATS_NAME_SIZE];
100 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
102 offsetof(struct dpaa_if_stats, raln)},
104 offsetof(struct dpaa_if_stats, rxpf)},
106 offsetof(struct dpaa_if_stats, rfcs)},
108 offsetof(struct dpaa_if_stats, rvlan)},
110 offsetof(struct dpaa_if_stats, rerr)},
112 offsetof(struct dpaa_if_stats, rdrp)},
114 offsetof(struct dpaa_if_stats, rund)},
116 offsetof(struct dpaa_if_stats, rovr)},
118 offsetof(struct dpaa_if_stats, rfrg)},
120 offsetof(struct dpaa_if_stats, txpf)},
122 offsetof(struct dpaa_if_stats, terr)},
124 offsetof(struct dpaa_if_stats, tvlan)},
126 offsetof(struct dpaa_if_stats, tund)},
129 static struct rte_dpaa_driver rte_dpaa_pmd;
132 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
135 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
137 memset(opts, 0, sizeof(struct qm_mcc_initfq));
138 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
139 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
140 QM_FQCTRL_PREFERINCACHE;
141 opts->fqd.context_a.stashing.exclusive = 0;
142 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
143 opts->fqd.context_a.stashing.annotation_cl =
144 DPAA_IF_RX_ANNOTATION_STASH;
145 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
146 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
150 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
152 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
154 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
156 PMD_INIT_FUNC_TRACE();
158 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
161 * Refuse mtu that requires the support of scattered packets
162 * when this feature has not been enabled before.
164 if (dev->data->min_rx_buf_size &&
165 !dev->data->scattered_rx && frame_size > buffsz) {
166 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
170 /* check <seg size> * <max_seg> >= max_frame */
171 if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
172 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
173 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
174 buffsz * DPAA_SGT_MAX_ENTRIES);
178 if (frame_size > RTE_ETHER_MAX_LEN)
179 dev->data->dev_conf.rxmode.offloads |=
180 DEV_RX_OFFLOAD_JUMBO_FRAME;
182 dev->data->dev_conf.rxmode.offloads &=
183 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
185 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
187 fman_if_set_maxfrm(dev->process_private, frame_size);
193 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
195 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
196 uint64_t rx_offloads = eth_conf->rxmode.offloads;
197 uint64_t tx_offloads = eth_conf->txmode.offloads;
199 PMD_INIT_FUNC_TRACE();
201 /* Rx offloads which are enabled by default */
202 if (dev_rx_offloads_nodis & ~rx_offloads) {
204 "Some of rx offloads enabled by default - requested 0x%" PRIx64
205 " fixed are 0x%" PRIx64,
206 rx_offloads, dev_rx_offloads_nodis);
209 /* Tx offloads which are enabled by default */
210 if (dev_tx_offloads_nodis & ~tx_offloads) {
212 "Some of tx offloads enabled by default - requested 0x%" PRIx64
213 " fixed are 0x%" PRIx64,
214 tx_offloads, dev_tx_offloads_nodis);
217 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
220 DPAA_PMD_DEBUG("enabling jumbo");
222 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
224 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
226 DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
228 dev->data->dev_conf.rxmode.max_rx_pkt_len,
229 DPAA_MAX_RX_PKT_LEN);
230 max_len = DPAA_MAX_RX_PKT_LEN;
233 fman_if_set_maxfrm(dev->process_private, max_len);
234 dev->data->mtu = max_len
235 - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
238 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
239 DPAA_PMD_DEBUG("enabling scatter mode");
240 fman_if_set_sg(dev->process_private, 1);
241 dev->data->scattered_rx = 1;
247 static const uint32_t *
248 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
250 static const uint32_t ptypes[] = {
252 RTE_PTYPE_L2_ETHER_VLAN,
253 RTE_PTYPE_L2_ETHER_ARP,
254 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
255 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
265 PMD_INIT_FUNC_TRACE();
267 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
272 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
274 struct dpaa_if *dpaa_intf = dev->data->dev_private;
276 PMD_INIT_FUNC_TRACE();
278 /* Change tx callback to the real one */
279 if (dpaa_intf->cgr_tx)
280 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
282 dev->tx_pkt_burst = dpaa_eth_queue_tx;
284 fman_if_enable_rx(dev->process_private);
289 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
291 struct fman_if *fif = dev->process_private;
293 PMD_INIT_FUNC_TRACE();
295 fman_if_disable_rx(fif);
296 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
299 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
301 PMD_INIT_FUNC_TRACE();
303 dpaa_eth_dev_stop(dev);
307 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
312 FILE *svr_file = NULL;
313 unsigned int svr_ver = 0;
315 PMD_INIT_FUNC_TRACE();
317 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
319 DPAA_PMD_ERR("Unable to open SoC device");
320 return -ENOTSUP; /* Not supported on this infra */
322 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
323 dpaa_svr_family = svr_ver & SVR_MASK;
325 DPAA_PMD_ERR("Unable to read SoC device");
329 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
330 svr_ver, fman_ip_rev);
331 ret += 1; /* add the size of '\0' */
333 if (fw_size < (uint32_t)ret)
339 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
340 struct rte_eth_dev_info *dev_info)
342 struct dpaa_if *dpaa_intf = dev->data->dev_private;
343 struct fman_if *fif = dev->process_private;
345 DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
347 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
348 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
349 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
350 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
351 dev_info->max_hash_mac_addrs = 0;
352 dev_info->max_vfs = 0;
353 dev_info->max_vmdq_pools = ETH_16_POOLS;
354 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
356 if (fif->mac_type == fman_mac_1g) {
357 dev_info->speed_capa = ETH_LINK_SPEED_1G;
358 } else if (fif->mac_type == fman_mac_2_5g) {
359 dev_info->speed_capa = ETH_LINK_SPEED_1G
360 | ETH_LINK_SPEED_2_5G;
361 } else if (fif->mac_type == fman_mac_10g) {
362 dev_info->speed_capa = ETH_LINK_SPEED_1G
363 | ETH_LINK_SPEED_2_5G
364 | ETH_LINK_SPEED_10G;
366 DPAA_PMD_ERR("invalid link_speed: %s, %d",
367 dpaa_intf->name, fif->mac_type);
371 dev_info->rx_offload_capa = dev_rx_offloads_sup |
372 dev_rx_offloads_nodis;
373 dev_info->tx_offload_capa = dev_tx_offloads_sup |
374 dev_tx_offloads_nodis;
375 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
376 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
377 dev_info->default_rxportconf.nb_queues = 1;
378 dev_info->default_txportconf.nb_queues = 1;
379 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
380 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
385 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
386 int wait_to_complete __rte_unused)
388 struct dpaa_if *dpaa_intf = dev->data->dev_private;
389 struct rte_eth_link *link = &dev->data->dev_link;
390 struct fman_if *fif = dev->process_private;
392 PMD_INIT_FUNC_TRACE();
394 if (fif->mac_type == fman_mac_1g)
395 link->link_speed = ETH_SPEED_NUM_1G;
396 else if (fif->mac_type == fman_mac_2_5g)
397 link->link_speed = ETH_SPEED_NUM_2_5G;
398 else if (fif->mac_type == fman_mac_10g)
399 link->link_speed = ETH_SPEED_NUM_10G;
401 DPAA_PMD_ERR("invalid link_speed: %s, %d",
402 dpaa_intf->name, fif->mac_type);
404 link->link_status = dpaa_intf->valid;
405 link->link_duplex = ETH_LINK_FULL_DUPLEX;
406 link->link_autoneg = ETH_LINK_AUTONEG;
410 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
411 struct rte_eth_stats *stats)
413 PMD_INIT_FUNC_TRACE();
415 fman_if_stats_get(dev->process_private, stats);
419 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
421 PMD_INIT_FUNC_TRACE();
423 fman_if_stats_reset(dev->process_private);
429 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
432 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
433 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
441 fman_if_stats_get_all(dev->process_private, values,
442 sizeof(struct dpaa_if_stats) / 8);
444 for (i = 0; i < num; i++) {
446 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
452 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
453 struct rte_eth_xstat_name *xstats_names,
456 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
458 if (limit < stat_cnt)
461 if (xstats_names != NULL)
462 for (i = 0; i < stat_cnt; i++)
463 strlcpy(xstats_names[i].name,
464 dpaa_xstats_strings[i].name,
465 sizeof(xstats_names[i].name));
471 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
472 uint64_t *values, unsigned int n)
474 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
475 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
484 fman_if_stats_get_all(dev->process_private, values_copy,
485 sizeof(struct dpaa_if_stats) / 8);
487 for (i = 0; i < stat_cnt; i++)
489 values_copy[dpaa_xstats_strings[i].offset / 8];
494 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
496 for (i = 0; i < n; i++) {
497 if (ids[i] >= stat_cnt) {
498 DPAA_PMD_ERR("id value isn't valid");
501 values[i] = values_copy[ids[i]];
507 dpaa_xstats_get_names_by_id(
508 struct rte_eth_dev *dev,
509 struct rte_eth_xstat_name *xstats_names,
513 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
514 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
517 return dpaa_xstats_get_names(dev, xstats_names, limit);
519 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
521 for (i = 0; i < limit; i++) {
522 if (ids[i] >= stat_cnt) {
523 DPAA_PMD_ERR("id value isn't valid");
526 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
531 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
533 PMD_INIT_FUNC_TRACE();
535 fman_if_promiscuous_enable(dev->process_private);
540 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
542 PMD_INIT_FUNC_TRACE();
544 fman_if_promiscuous_disable(dev->process_private);
549 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
551 PMD_INIT_FUNC_TRACE();
553 fman_if_set_mcast_filter_table(dev->process_private);
558 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
560 PMD_INIT_FUNC_TRACE();
562 fman_if_reset_mcast_filter_table(dev->process_private);
568 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
570 unsigned int socket_id __rte_unused,
571 const struct rte_eth_rxconf *rx_conf __rte_unused,
572 struct rte_mempool *mp)
574 struct dpaa_if *dpaa_intf = dev->data->dev_private;
575 struct fman_if *fif = dev->process_private;
576 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
577 struct qm_mcc_initfq opts = {0};
580 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
582 PMD_INIT_FUNC_TRACE();
584 if (queue_idx >= dev->data->nb_rx_queues) {
585 rte_errno = EOVERFLOW;
586 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
587 (void *)dev, queue_idx, dev->data->nb_rx_queues);
591 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
592 queue_idx, rxq->fqid);
594 /* Max packet can fit in single buffer */
595 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
597 } else if (dev->data->dev_conf.rxmode.offloads &
598 DEV_RX_OFFLOAD_SCATTER) {
599 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
600 buffsz * DPAA_SGT_MAX_ENTRIES) {
601 DPAA_PMD_ERR("max RxPkt size %d too big to fit "
603 dev->data->dev_conf.rxmode.max_rx_pkt_len,
604 buffsz * DPAA_SGT_MAX_ENTRIES);
605 rte_errno = EOVERFLOW;
609 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
610 " larger than a single mbuf (%u) and scattered"
611 " mode has not been requested",
612 dev->data->dev_conf.rxmode.max_rx_pkt_len,
613 buffsz - RTE_PKTMBUF_HEADROOM);
616 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
617 struct fman_if_ic_params icp;
621 if (!mp->pool_data) {
622 DPAA_PMD_ERR("Not an offloaded buffer pool!");
625 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
627 memset(&icp, 0, sizeof(icp));
628 /* set ICEOF for to the default value , which is 0*/
629 icp.iciof = DEFAULT_ICIOF;
630 icp.iceof = DEFAULT_RX_ICEOF;
631 icp.icsz = DEFAULT_ICSZ;
632 fman_if_set_ic_params(fif, &icp);
634 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
635 fman_if_set_fdoff(fif, fd_offset);
637 /* Buffer pool size should be equal to Dataroom Size*/
638 bp_size = rte_pktmbuf_data_room_size(mp);
639 fman_if_set_bp(fif, mp->size,
640 dpaa_intf->bp_info->bpid, bp_size);
641 dpaa_intf->valid = 1;
642 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
643 dpaa_intf->name, fd_offset,
644 fman_if_get_fdoff(fif));
646 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
647 fman_if_get_sg_enable(fif),
648 dev->data->dev_conf.rxmode.max_rx_pkt_len);
649 /* checking if push mode only, no error check for now */
650 if (!rxq->is_static &&
651 dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
652 struct qman_portal *qp;
655 dpaa_push_queue_idx++;
656 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
657 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
658 QM_FQCTRL_CTXASTASHING |
659 QM_FQCTRL_PREFERINCACHE;
660 opts.fqd.context_a.stashing.exclusive = 0;
661 /* In muticore scenario stashing becomes a bottleneck on LS1046.
662 * So do not enable stashing in this case
664 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
665 opts.fqd.context_a.stashing.annotation_cl =
666 DPAA_IF_RX_ANNOTATION_STASH;
667 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
668 opts.fqd.context_a.stashing.context_cl =
669 DPAA_IF_RX_CONTEXT_STASH;
671 /*Create a channel and associate given queue with the channel*/
672 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
673 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
674 opts.fqd.dest.channel = rxq->ch_id;
675 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
676 flags = QMAN_INITFQ_FLAG_SCHED;
678 /* Configure tail drop */
679 if (dpaa_intf->cgr_rx) {
680 opts.we_mask |= QM_INITFQ_WE_CGID;
681 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
682 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
684 ret = qman_init_fq(rxq, flags, &opts);
686 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
687 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
690 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
691 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
693 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
694 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
697 rxq->is_static = true;
699 /* Allocate qman specific portals */
700 qp = fsl_qman_fq_portal_create(&q_fd);
702 DPAA_PMD_ERR("Unable to alloc fq portal");
707 /* Set up the device interrupt handler */
708 if (!dev->intr_handle) {
709 struct rte_dpaa_device *dpaa_dev;
710 struct rte_device *rdev = dev->device;
712 dpaa_dev = container_of(rdev, struct rte_dpaa_device,
714 dev->intr_handle = &dpaa_dev->intr_handle;
715 dev->intr_handle->intr_vec = rte_zmalloc(NULL,
716 dpaa_push_mode_max_queue, 0);
717 if (!dev->intr_handle->intr_vec) {
718 DPAA_PMD_ERR("intr_vec alloc failed");
721 dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
722 dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
725 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
726 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
727 dev->intr_handle->efds[queue_idx] = q_fd;
730 rxq->bp_array = rte_dpaa_bpid_info;
731 dev->data->rx_queues[queue_idx] = rxq;
733 /* configure the CGR size as per the desc size */
734 if (dpaa_intf->cgr_rx) {
735 struct qm_mcc_initcgr cgr_opts = {0};
737 /* Enable tail drop with cgr on this queue */
738 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
739 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
742 "rx taildrop modify fail on fqid %d (ret=%d)",
751 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
754 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
758 struct dpaa_if *dpaa_intf = dev->data->dev_private;
759 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
760 struct qm_mcc_initfq opts = {0};
762 if (dpaa_push_mode_max_queue)
763 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
764 "PUSH mode already enabled for first %d queues.\n"
765 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
766 dpaa_push_mode_max_queue);
768 dpaa_poll_queue_default_config(&opts);
770 switch (queue_conf->ev.sched_type) {
771 case RTE_SCHED_TYPE_ATOMIC:
772 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
773 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
774 * configuration with HOLD_ACTIVE setting
776 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
777 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
779 case RTE_SCHED_TYPE_ORDERED:
780 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
783 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
784 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
788 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
789 opts.fqd.dest.channel = ch_id;
790 opts.fqd.dest.wq = queue_conf->ev.priority;
792 if (dpaa_intf->cgr_rx) {
793 opts.we_mask |= QM_INITFQ_WE_CGID;
794 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
795 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
798 flags = QMAN_INITFQ_FLAG_SCHED;
800 ret = qman_init_fq(rxq, flags, &opts);
802 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
803 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
807 /* copy configuration which needs to be filled during dequeue */
808 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
809 dev->data->rx_queues[eth_rx_queue_id] = rxq;
815 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
818 struct qm_mcc_initfq opts;
821 struct dpaa_if *dpaa_intf = dev->data->dev_private;
822 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
824 dpaa_poll_queue_default_config(&opts);
826 if (dpaa_intf->cgr_rx) {
827 opts.we_mask |= QM_INITFQ_WE_CGID;
828 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
829 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
832 ret = qman_init_fq(rxq, flags, &opts);
834 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
838 rxq->cb.dqrr_dpdk_cb = NULL;
839 dev->data->rx_queues[eth_rx_queue_id] = NULL;
845 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
847 PMD_INIT_FUNC_TRACE();
851 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
852 uint16_t nb_desc __rte_unused,
853 unsigned int socket_id __rte_unused,
854 const struct rte_eth_txconf *tx_conf __rte_unused)
856 struct dpaa_if *dpaa_intf = dev->data->dev_private;
858 PMD_INIT_FUNC_TRACE();
860 if (queue_idx >= dev->data->nb_tx_queues) {
861 rte_errno = EOVERFLOW;
862 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
863 (void *)dev, queue_idx, dev->data->nb_tx_queues);
867 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
868 queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
869 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
874 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
876 PMD_INIT_FUNC_TRACE();
880 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
882 struct dpaa_if *dpaa_intf = dev->data->dev_private;
883 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
886 PMD_INIT_FUNC_TRACE();
888 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
889 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
890 rx_queue_id, frm_cnt);
895 static int dpaa_link_down(struct rte_eth_dev *dev)
897 PMD_INIT_FUNC_TRACE();
899 dpaa_eth_dev_stop(dev);
903 static int dpaa_link_up(struct rte_eth_dev *dev)
905 PMD_INIT_FUNC_TRACE();
907 dpaa_eth_dev_start(dev);
912 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
913 struct rte_eth_fc_conf *fc_conf)
915 struct dpaa_if *dpaa_intf = dev->data->dev_private;
916 struct rte_eth_fc_conf *net_fc;
918 PMD_INIT_FUNC_TRACE();
920 if (!(dpaa_intf->fc_conf)) {
921 dpaa_intf->fc_conf = rte_zmalloc(NULL,
922 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
923 if (!dpaa_intf->fc_conf) {
924 DPAA_PMD_ERR("unable to save flow control info");
928 net_fc = dpaa_intf->fc_conf;
930 if (fc_conf->high_water < fc_conf->low_water) {
931 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
935 if (fc_conf->mode == RTE_FC_NONE) {
937 } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
938 fc_conf->mode == RTE_FC_FULL) {
939 fman_if_set_fc_threshold(dev->process_private,
942 dpaa_intf->bp_info->bpid);
943 if (fc_conf->pause_time)
944 fman_if_set_fc_quanta(dev->process_private,
945 fc_conf->pause_time);
948 /* Save the information in dpaa device */
949 net_fc->pause_time = fc_conf->pause_time;
950 net_fc->high_water = fc_conf->high_water;
951 net_fc->low_water = fc_conf->low_water;
952 net_fc->send_xon = fc_conf->send_xon;
953 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
954 net_fc->mode = fc_conf->mode;
955 net_fc->autoneg = fc_conf->autoneg;
961 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
962 struct rte_eth_fc_conf *fc_conf)
964 struct dpaa_if *dpaa_intf = dev->data->dev_private;
965 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
968 PMD_INIT_FUNC_TRACE();
971 fc_conf->pause_time = net_fc->pause_time;
972 fc_conf->high_water = net_fc->high_water;
973 fc_conf->low_water = net_fc->low_water;
974 fc_conf->send_xon = net_fc->send_xon;
975 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
976 fc_conf->mode = net_fc->mode;
977 fc_conf->autoneg = net_fc->autoneg;
980 ret = fman_if_get_fc_threshold(dev->process_private);
982 fc_conf->mode = RTE_FC_TX_PAUSE;
983 fc_conf->pause_time =
984 fman_if_get_fc_quanta(dev->process_private);
986 fc_conf->mode = RTE_FC_NONE;
993 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
994 struct rte_ether_addr *addr,
996 __rte_unused uint32_t pool)
1000 PMD_INIT_FUNC_TRACE();
1002 ret = fman_if_add_mac_addr(dev->process_private,
1003 addr->addr_bytes, index);
1006 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1011 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1014 PMD_INIT_FUNC_TRACE();
1016 fman_if_clear_mac_addr(dev->process_private, index);
1020 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1021 struct rte_ether_addr *addr)
1025 PMD_INIT_FUNC_TRACE();
1027 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1029 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1034 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1037 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1038 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1040 if (!rxq->is_static)
1043 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1046 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1049 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1050 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1054 if (!rxq->is_static)
1057 qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1059 temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1060 if (temp1 != sizeof(temp))
1061 DPAA_PMD_ERR("irq read error");
1063 qman_fq_portal_thread_irq(rxq->qp);
1068 static struct eth_dev_ops dpaa_devops = {
1069 .dev_configure = dpaa_eth_dev_configure,
1070 .dev_start = dpaa_eth_dev_start,
1071 .dev_stop = dpaa_eth_dev_stop,
1072 .dev_close = dpaa_eth_dev_close,
1073 .dev_infos_get = dpaa_eth_dev_info,
1074 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1076 .rx_queue_setup = dpaa_eth_rx_queue_setup,
1077 .tx_queue_setup = dpaa_eth_tx_queue_setup,
1078 .rx_queue_release = dpaa_eth_rx_queue_release,
1079 .tx_queue_release = dpaa_eth_tx_queue_release,
1080 .rx_queue_count = dpaa_dev_rx_queue_count,
1082 .flow_ctrl_get = dpaa_flow_ctrl_get,
1083 .flow_ctrl_set = dpaa_flow_ctrl_set,
1085 .link_update = dpaa_eth_link_update,
1086 .stats_get = dpaa_eth_stats_get,
1087 .xstats_get = dpaa_dev_xstats_get,
1088 .xstats_get_by_id = dpaa_xstats_get_by_id,
1089 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
1090 .xstats_get_names = dpaa_xstats_get_names,
1091 .xstats_reset = dpaa_eth_stats_reset,
1092 .stats_reset = dpaa_eth_stats_reset,
1093 .promiscuous_enable = dpaa_eth_promiscuous_enable,
1094 .promiscuous_disable = dpaa_eth_promiscuous_disable,
1095 .allmulticast_enable = dpaa_eth_multicast_enable,
1096 .allmulticast_disable = dpaa_eth_multicast_disable,
1097 .mtu_set = dpaa_mtu_set,
1098 .dev_set_link_down = dpaa_link_down,
1099 .dev_set_link_up = dpaa_link_up,
1100 .mac_addr_add = dpaa_dev_add_mac_addr,
1101 .mac_addr_remove = dpaa_dev_remove_mac_addr,
1102 .mac_addr_set = dpaa_dev_set_mac_addr,
1104 .fw_version_get = dpaa_fw_version_get,
1106 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable,
1107 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable,
1111 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1113 if (strcmp(dev->device->driver->name,
1121 is_dpaa_supported(struct rte_eth_dev *dev)
1123 return is_device_supported(dev, &rte_dpaa_pmd);
1127 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1129 struct rte_eth_dev *dev;
1131 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1133 dev = &rte_eth_devices[port];
1135 if (!is_dpaa_supported(dev))
1139 fman_if_loopback_enable(dev->process_private);
1141 fman_if_loopback_disable(dev->process_private);
1146 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1147 struct fman_if *fman_intf)
1149 struct rte_eth_fc_conf *fc_conf;
1152 PMD_INIT_FUNC_TRACE();
1154 if (!(dpaa_intf->fc_conf)) {
1155 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1156 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1157 if (!dpaa_intf->fc_conf) {
1158 DPAA_PMD_ERR("unable to save flow control info");
1162 fc_conf = dpaa_intf->fc_conf;
1163 ret = fman_if_get_fc_threshold(fman_intf);
1165 fc_conf->mode = RTE_FC_TX_PAUSE;
1166 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1168 fc_conf->mode = RTE_FC_NONE;
1174 /* Initialise an Rx FQ */
1175 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1178 struct qm_mcc_initfq opts = {0};
1180 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1181 struct qm_mcc_initcgr cgr_opts = {
1182 .we_mask = QM_CGR_WE_CS_THRES |
1186 .cstd_en = QM_CGR_EN,
1187 .mode = QMAN_CGR_MODE_FRAME
1192 ret = qman_reserve_fqid(fqid);
1194 DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1199 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1201 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1202 ret = qman_create_fq(fqid, flags, fq);
1204 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1208 fq->is_static = false;
1210 dpaa_poll_queue_default_config(&opts);
1213 /* Enable tail drop with cgr on this queue */
1214 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1216 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1220 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1224 opts.we_mask |= QM_INITFQ_WE_CGID;
1225 opts.fqd.cgid = cgr_rx->cgrid;
1226 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1229 ret = qman_init_fq(fq, 0, &opts);
1231 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1235 /* Initialise a Tx FQ */
1236 static int dpaa_tx_queue_init(struct qman_fq *fq,
1237 struct fman_if *fman_intf,
1238 struct qman_cgr *cgr_tx)
1240 struct qm_mcc_initfq opts = {0};
1241 struct qm_mcc_initcgr cgr_opts = {
1242 .we_mask = QM_CGR_WE_CS_THRES |
1246 .cstd_en = QM_CGR_EN,
1247 .mode = QMAN_CGR_MODE_FRAME
1252 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1253 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1255 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1258 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1259 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1260 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1261 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1262 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1263 opts.fqd.context_b = 0;
1264 /* no tx-confirmation */
1265 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1266 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1267 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1270 /* Enable tail drop with cgr on this queue */
1271 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1272 td_tx_threshold, 0);
1274 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1278 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1282 opts.we_mask |= QM_INITFQ_WE_CGID;
1283 opts.fqd.cgid = cgr_tx->cgrid;
1284 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1285 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1289 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1291 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1295 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1296 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1297 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1299 struct qm_mcc_initfq opts = {0};
1302 PMD_INIT_FUNC_TRACE();
1304 ret = qman_reserve_fqid(fqid);
1306 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1310 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1311 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1312 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1314 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1318 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1319 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1320 ret = qman_init_fq(fq, 0, &opts);
1322 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1328 /* Initialise a network interface */
1330 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1332 struct rte_dpaa_device *dpaa_device;
1333 struct fm_eth_port_cfg *cfg;
1334 struct dpaa_if *dpaa_intf;
1335 struct fman_if *fman_intf;
1338 PMD_INIT_FUNC_TRACE();
1340 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1341 dev_id = dpaa_device->id.dev_id;
1342 cfg = dpaa_get_eth_port_cfg(dev_id);
1343 fman_intf = cfg->fman_if;
1344 eth_dev->process_private = fman_intf;
1346 /* Plugging of UCODE burst API not supported in Secondary */
1347 dpaa_intf = eth_dev->data->dev_private;
1348 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1349 if (dpaa_intf->cgr_tx)
1350 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1352 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1353 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1354 qman_set_fq_lookup_table(
1355 dpaa_intf->rx_queues->qman_fq_lookup_table);
1361 /* Initialise a network interface */
1363 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1365 int num_rx_fqs, fqid;
1368 struct rte_dpaa_device *dpaa_device;
1369 struct dpaa_if *dpaa_intf;
1370 struct fm_eth_port_cfg *cfg;
1371 struct fman_if *fman_intf;
1372 struct fman_if_bpool *bp, *tmp_bp;
1373 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1374 uint32_t cgrid_tx[MAX_DPAA_CORES];
1375 char eth_buf[RTE_ETHER_ADDR_FMT_SIZE];
1377 PMD_INIT_FUNC_TRACE();
1379 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1380 dev_id = dpaa_device->id.dev_id;
1381 dpaa_intf = eth_dev->data->dev_private;
1382 cfg = dpaa_get_eth_port_cfg(dev_id);
1383 fman_intf = cfg->fman_if;
1385 dpaa_intf->name = dpaa_device->name;
1387 /* save fman_if & cfg in the interface struture */
1388 eth_dev->process_private = fman_intf;
1389 dpaa_intf->ifid = dev_id;
1390 dpaa_intf->cfg = cfg;
1392 /* Initialize Rx FQ's */
1394 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1396 if (getenv("DPAA_NUM_RX_QUEUES"))
1397 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1399 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1403 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1406 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1407 DPAA_PMD_ERR("Invalid number of RX queues\n");
1411 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1412 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1413 if (!dpaa_intf->rx_queues) {
1414 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1418 memset(cgrid, 0, sizeof(cgrid));
1419 memset(cgrid_tx, 0, sizeof(cgrid_tx));
1421 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1422 * Tx tail drop is disabled.
1424 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1425 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1426 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1428 /* if a very large value is being configured */
1429 if (td_tx_threshold > UINT16_MAX)
1430 td_tx_threshold = CGR_RX_PERFQ_THRESH;
1433 /* If congestion control is enabled globally*/
1435 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1436 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1437 if (!dpaa_intf->cgr_rx) {
1438 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1443 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1444 if (ret != num_rx_fqs) {
1445 DPAA_PMD_WARN("insufficient CGRIDs available");
1450 dpaa_intf->cgr_rx = NULL;
1453 for (loop = 0; loop < num_rx_fqs; loop++) {
1457 fqid = DPAA_PCD_FQID_START + fman_intf->mac_idx *
1458 DPAA_PCD_FQID_MULTIPLIER + loop;
1460 if (dpaa_intf->cgr_rx)
1461 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1463 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1464 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1468 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1470 dpaa_intf->nb_rx_queues = num_rx_fqs;
1472 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1473 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1474 MAX_DPAA_CORES, MAX_CACHELINE);
1475 if (!dpaa_intf->tx_queues) {
1476 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1481 /* If congestion control is enabled globally*/
1482 if (td_tx_threshold) {
1483 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1484 sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1486 if (!dpaa_intf->cgr_tx) {
1487 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1492 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1494 if (ret != MAX_DPAA_CORES) {
1495 DPAA_PMD_WARN("insufficient CGRIDs available");
1500 dpaa_intf->cgr_tx = NULL;
1504 for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1505 if (dpaa_intf->cgr_tx)
1506 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
1508 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1510 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
1513 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1515 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1517 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1518 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1519 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1520 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1521 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1522 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1523 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1526 DPAA_PMD_DEBUG("All frame queues created");
1528 /* Get the initial configuration for flow control */
1529 dpaa_fc_set_default(dpaa_intf, fman_intf);
1531 /* reset bpool list, initialize bpool dynamically */
1532 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1533 list_del(&bp->node);
1537 /* Populate ethdev structure */
1538 eth_dev->dev_ops = &dpaa_devops;
1539 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1540 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1542 /* Allocate memory for storing MAC addresses */
1543 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1544 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1545 if (eth_dev->data->mac_addrs == NULL) {
1546 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1547 "store MAC addresses",
1548 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1553 /* copy the primary mac address */
1554 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]);
1555 rte_ether_format_addr(eth_buf, sizeof(eth_buf), &fman_intf->mac_addr);
1557 DPAA_PMD_INFO("net: dpaa: %s: %s", dpaa_device->name, eth_buf);
1559 /* Disable RX mode */
1560 fman_if_discard_rx_errors(fman_intf);
1561 fman_if_disable_rx(fman_intf);
1562 /* Disable promiscuous mode */
1563 fman_if_promiscuous_disable(fman_intf);
1564 /* Disable multicast */
1565 fman_if_reset_mcast_filter_table(fman_intf);
1566 /* Reset interface statistics */
1567 fman_if_stats_reset(fman_intf);
1568 /* Disable SG by default */
1569 fman_if_set_sg(fman_intf, 0);
1570 fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1575 rte_free(dpaa_intf->tx_queues);
1576 dpaa_intf->tx_queues = NULL;
1577 dpaa_intf->nb_tx_queues = 0;
1580 rte_free(dpaa_intf->cgr_rx);
1581 rte_free(dpaa_intf->cgr_tx);
1582 rte_free(dpaa_intf->rx_queues);
1583 dpaa_intf->rx_queues = NULL;
1584 dpaa_intf->nb_rx_queues = 0;
1589 dpaa_dev_uninit(struct rte_eth_dev *dev)
1591 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1594 PMD_INIT_FUNC_TRACE();
1596 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1600 DPAA_PMD_WARN("Already closed or not started");
1604 dpaa_eth_dev_close(dev);
1606 /* release configuration memory */
1607 if (dpaa_intf->fc_conf)
1608 rte_free(dpaa_intf->fc_conf);
1610 /* Release RX congestion Groups */
1611 if (dpaa_intf->cgr_rx) {
1612 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1613 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1615 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1616 dpaa_intf->nb_rx_queues);
1619 rte_free(dpaa_intf->cgr_rx);
1620 dpaa_intf->cgr_rx = NULL;
1622 /* Release TX congestion Groups */
1623 if (dpaa_intf->cgr_tx) {
1624 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
1625 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
1627 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
1629 rte_free(dpaa_intf->cgr_tx);
1630 dpaa_intf->cgr_tx = NULL;
1633 rte_free(dpaa_intf->rx_queues);
1634 dpaa_intf->rx_queues = NULL;
1636 rte_free(dpaa_intf->tx_queues);
1637 dpaa_intf->tx_queues = NULL;
1639 dev->dev_ops = NULL;
1640 dev->rx_pkt_burst = NULL;
1641 dev->tx_pkt_burst = NULL;
1647 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1648 struct rte_dpaa_device *dpaa_dev)
1652 struct rte_eth_dev *eth_dev;
1654 PMD_INIT_FUNC_TRACE();
1656 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1657 RTE_PKTMBUF_HEADROOM) {
1659 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1660 RTE_PKTMBUF_HEADROOM,
1661 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1666 /* In case of secondary process, the device is already configured
1667 * and no further action is required, except portal initialization
1668 * and verifying secondary attachment to port name.
1670 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1671 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1674 eth_dev->device = &dpaa_dev->device;
1675 eth_dev->dev_ops = &dpaa_devops;
1677 ret = dpaa_dev_init_secondary(eth_dev);
1679 RTE_LOG(ERR, PMD, "secondary dev init failed\n");
1683 rte_eth_dev_probing_finish(eth_dev);
1687 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
1688 if (access("/tmp/fmc.bin", F_OK) == -1) {
1689 DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
1693 /* disabling the default push mode for LS1043 */
1694 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1695 dpaa_push_mode_max_queue = 0;
1697 /* if push mode queues to be enabled. Currenly we are allowing
1698 * only one queue per thread.
1700 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1701 dpaa_push_mode_max_queue =
1702 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1703 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1704 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1710 if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
1711 ret = rte_dpaa_portal_init((void *)1);
1713 DPAA_PMD_ERR("Unable to initialize portal");
1718 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1722 eth_dev->data->dev_private =
1723 rte_zmalloc("ethdev private structure",
1724 sizeof(struct dpaa_if),
1725 RTE_CACHE_LINE_SIZE);
1726 if (!eth_dev->data->dev_private) {
1727 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1728 rte_eth_dev_release_port(eth_dev);
1732 eth_dev->device = &dpaa_dev->device;
1733 dpaa_dev->eth_dev = eth_dev;
1735 qman_ern_register_cb(dpaa_free_mbuf);
1737 /* Invoke PMD device initialization function */
1738 diag = dpaa_dev_init(eth_dev);
1740 rte_eth_dev_probing_finish(eth_dev);
1744 rte_eth_dev_release_port(eth_dev);
1749 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1751 struct rte_eth_dev *eth_dev;
1753 PMD_INIT_FUNC_TRACE();
1755 eth_dev = dpaa_dev->eth_dev;
1756 dpaa_dev_uninit(eth_dev);
1758 rte_eth_dev_release_port(eth_dev);
1763 static struct rte_dpaa_driver rte_dpaa_pmd = {
1764 .drv_type = FSL_DPAA_ETH,
1765 .probe = rte_dpaa_probe,
1766 .remove = rte_dpaa_remove,
1769 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
1770 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);