1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
15 #include <sys/types.h>
16 #include <sys/syscall.h>
18 #include <rte_byteorder.h>
19 #include <rte_common.h>
20 #include <rte_interrupts.h>
22 #include <rte_debug.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_malloc.h>
35 #include <rte_dpaa_bus.h>
36 #include <rte_dpaa_logs.h>
37 #include <dpaa_mempool.h>
39 #include <dpaa_ethdev.h>
40 #include <dpaa_rxtx.h>
41 #include <rte_pmd_dpaa.h>
48 /* Supported Rx offloads */
49 static uint64_t dev_rx_offloads_sup =
50 DEV_RX_OFFLOAD_JUMBO_FRAME;
52 /* Rx offloads which cannot be disabled */
53 static uint64_t dev_rx_offloads_nodis =
54 DEV_RX_OFFLOAD_IPV4_CKSUM |
55 DEV_RX_OFFLOAD_UDP_CKSUM |
56 DEV_RX_OFFLOAD_TCP_CKSUM |
57 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
58 DEV_RX_OFFLOAD_CRC_STRIP |
59 DEV_RX_OFFLOAD_SCATTER;
61 /* Supported Tx offloads */
62 static uint64_t dev_tx_offloads_sup;
64 /* Tx offloads which cannot be disabled */
65 static uint64_t dev_tx_offloads_nodis =
66 DEV_TX_OFFLOAD_IPV4_CKSUM |
67 DEV_TX_OFFLOAD_UDP_CKSUM |
68 DEV_TX_OFFLOAD_TCP_CKSUM |
69 DEV_TX_OFFLOAD_SCTP_CKSUM |
70 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
71 DEV_TX_OFFLOAD_MULTI_SEGS |
72 DEV_TX_OFFLOAD_MT_LOCKFREE |
73 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
75 /* Keep track of whether QMAN and BMAN have been globally initialized */
76 static int is_global_init;
77 static int default_q; /* use default queue - FMC is not executed*/
78 /* At present we only allow up to 4 push mode queues as default - as each of
79 * this queue need dedicated portal and we are short of portals.
81 #define DPAA_MAX_PUSH_MODE_QUEUE 8
82 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
84 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
85 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
88 /* Per FQ Taildrop in frame count */
89 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
91 struct rte_dpaa_xstats_name_off {
92 char name[RTE_ETH_XSTATS_NAME_SIZE];
96 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
98 offsetof(struct dpaa_if_stats, raln)},
100 offsetof(struct dpaa_if_stats, rxpf)},
102 offsetof(struct dpaa_if_stats, rfcs)},
104 offsetof(struct dpaa_if_stats, rvlan)},
106 offsetof(struct dpaa_if_stats, rerr)},
108 offsetof(struct dpaa_if_stats, rdrp)},
110 offsetof(struct dpaa_if_stats, rund)},
112 offsetof(struct dpaa_if_stats, rovr)},
114 offsetof(struct dpaa_if_stats, rfrg)},
116 offsetof(struct dpaa_if_stats, txpf)},
118 offsetof(struct dpaa_if_stats, terr)},
120 offsetof(struct dpaa_if_stats, tvlan)},
122 offsetof(struct dpaa_if_stats, tund)},
125 static struct rte_dpaa_driver rte_dpaa_pmd;
128 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
131 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
133 memset(opts, 0, sizeof(struct qm_mcc_initfq));
134 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
135 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
136 QM_FQCTRL_PREFERINCACHE;
137 opts->fqd.context_a.stashing.exclusive = 0;
138 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
139 opts->fqd.context_a.stashing.annotation_cl =
140 DPAA_IF_RX_ANNOTATION_STASH;
141 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
142 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
146 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
148 struct dpaa_if *dpaa_intf = dev->data->dev_private;
149 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
152 PMD_INIT_FUNC_TRACE();
154 if (mtu < ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
156 if (frame_size > ETHER_MAX_LEN)
157 dev->data->dev_conf.rxmode.offloads &=
158 DEV_RX_OFFLOAD_JUMBO_FRAME;
160 dev->data->dev_conf.rxmode.offloads &=
161 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
163 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
165 fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
171 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
173 struct dpaa_if *dpaa_intf = dev->data->dev_private;
174 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
175 uint64_t rx_offloads = eth_conf->rxmode.offloads;
176 uint64_t tx_offloads = eth_conf->txmode.offloads;
178 PMD_INIT_FUNC_TRACE();
180 /* Rx offloads validation */
181 if (dev_rx_offloads_nodis & ~rx_offloads) {
183 "Rx offloads non configurable - requested 0x%" PRIx64
184 " ignored 0x%" PRIx64,
185 rx_offloads, dev_rx_offloads_nodis);
188 /* Tx offloads validation */
189 if (dev_tx_offloads_nodis & ~tx_offloads) {
191 "Tx offloads non configurable - requested 0x%" PRIx64
192 " ignored 0x%" PRIx64,
193 tx_offloads, dev_tx_offloads_nodis);
196 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
197 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
198 DPAA_MAX_RX_PKT_LEN) {
199 fman_if_set_maxfrm(dpaa_intf->fif,
200 dev->data->dev_conf.rxmode.max_rx_pkt_len);
209 static const uint32_t *
210 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
212 static const uint32_t ptypes[] = {
213 /*todo -= add more types */
216 RTE_PTYPE_L3_IPV4_EXT,
218 RTE_PTYPE_L3_IPV6_EXT,
224 PMD_INIT_FUNC_TRACE();
226 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
231 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
233 struct dpaa_if *dpaa_intf = dev->data->dev_private;
235 PMD_INIT_FUNC_TRACE();
237 /* Change tx callback to the real one */
238 dev->tx_pkt_burst = dpaa_eth_queue_tx;
239 fman_if_enable_rx(dpaa_intf->fif);
244 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
246 struct dpaa_if *dpaa_intf = dev->data->dev_private;
248 PMD_INIT_FUNC_TRACE();
250 fman_if_disable_rx(dpaa_intf->fif);
251 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
254 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
256 PMD_INIT_FUNC_TRACE();
258 dpaa_eth_dev_stop(dev);
262 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
267 FILE *svr_file = NULL;
268 unsigned int svr_ver = 0;
270 PMD_INIT_FUNC_TRACE();
272 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
274 DPAA_PMD_ERR("Unable to open SoC device");
275 return -ENOTSUP; /* Not supported on this infra */
277 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
278 dpaa_svr_family = svr_ver & SVR_MASK;
280 DPAA_PMD_ERR("Unable to read SoC device");
284 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
285 svr_ver, fman_ip_rev);
286 ret += 1; /* add the size of '\0' */
288 if (fw_size < (uint32_t)ret)
294 static void dpaa_eth_dev_info(struct rte_eth_dev *dev,
295 struct rte_eth_dev_info *dev_info)
297 struct dpaa_if *dpaa_intf = dev->data->dev_private;
299 PMD_INIT_FUNC_TRACE();
301 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
302 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
303 dev_info->min_rx_bufsize = DPAA_MIN_RX_BUF_SIZE;
304 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
305 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
306 dev_info->max_hash_mac_addrs = 0;
307 dev_info->max_vfs = 0;
308 dev_info->max_vmdq_pools = ETH_16_POOLS;
309 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
310 dev_info->speed_capa = (ETH_LINK_SPEED_1G |
312 dev_info->rx_offload_capa = dev_rx_offloads_sup |
313 dev_rx_offloads_nodis;
314 dev_info->tx_offload_capa = dev_tx_offloads_sup |
315 dev_tx_offloads_nodis;
316 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
317 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
320 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
321 int wait_to_complete __rte_unused)
323 struct dpaa_if *dpaa_intf = dev->data->dev_private;
324 struct rte_eth_link *link = &dev->data->dev_link;
326 PMD_INIT_FUNC_TRACE();
328 if (dpaa_intf->fif->mac_type == fman_mac_1g)
329 link->link_speed = ETH_SPEED_NUM_1G;
330 else if (dpaa_intf->fif->mac_type == fman_mac_10g)
331 link->link_speed = ETH_SPEED_NUM_10G;
333 DPAA_PMD_ERR("invalid link_speed: %s, %d",
334 dpaa_intf->name, dpaa_intf->fif->mac_type);
336 link->link_status = dpaa_intf->valid;
337 link->link_duplex = ETH_LINK_FULL_DUPLEX;
338 link->link_autoneg = ETH_LINK_AUTONEG;
342 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
343 struct rte_eth_stats *stats)
345 struct dpaa_if *dpaa_intf = dev->data->dev_private;
347 PMD_INIT_FUNC_TRACE();
349 fman_if_stats_get(dpaa_intf->fif, stats);
353 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev)
355 struct dpaa_if *dpaa_intf = dev->data->dev_private;
357 PMD_INIT_FUNC_TRACE();
359 fman_if_stats_reset(dpaa_intf->fif);
363 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
366 struct dpaa_if *dpaa_intf = dev->data->dev_private;
367 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
368 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
376 fman_if_stats_get_all(dpaa_intf->fif, values,
377 sizeof(struct dpaa_if_stats) / 8);
379 for (i = 0; i < num; i++) {
381 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
387 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
388 struct rte_eth_xstat_name *xstats_names,
391 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
393 if (limit < stat_cnt)
396 if (xstats_names != NULL)
397 for (i = 0; i < stat_cnt; i++)
398 snprintf(xstats_names[i].name,
399 sizeof(xstats_names[i].name),
401 dpaa_xstats_strings[i].name);
407 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
408 uint64_t *values, unsigned int n)
410 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
411 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
414 struct dpaa_if *dpaa_intf = dev->data->dev_private;
422 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
423 sizeof(struct dpaa_if_stats) / 8);
425 for (i = 0; i < stat_cnt; i++)
427 values_copy[dpaa_xstats_strings[i].offset / 8];
432 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
434 for (i = 0; i < n; i++) {
435 if (ids[i] >= stat_cnt) {
436 DPAA_PMD_ERR("id value isn't valid");
439 values[i] = values_copy[ids[i]];
445 dpaa_xstats_get_names_by_id(
446 struct rte_eth_dev *dev,
447 struct rte_eth_xstat_name *xstats_names,
451 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
452 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
455 return dpaa_xstats_get_names(dev, xstats_names, limit);
457 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
459 for (i = 0; i < limit; i++) {
460 if (ids[i] >= stat_cnt) {
461 DPAA_PMD_ERR("id value isn't valid");
464 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
469 static void dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
471 struct dpaa_if *dpaa_intf = dev->data->dev_private;
473 PMD_INIT_FUNC_TRACE();
475 fman_if_promiscuous_enable(dpaa_intf->fif);
478 static void dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
480 struct dpaa_if *dpaa_intf = dev->data->dev_private;
482 PMD_INIT_FUNC_TRACE();
484 fman_if_promiscuous_disable(dpaa_intf->fif);
487 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
489 struct dpaa_if *dpaa_intf = dev->data->dev_private;
491 PMD_INIT_FUNC_TRACE();
493 fman_if_set_mcast_filter_table(dpaa_intf->fif);
496 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
498 struct dpaa_if *dpaa_intf = dev->data->dev_private;
500 PMD_INIT_FUNC_TRACE();
502 fman_if_reset_mcast_filter_table(dpaa_intf->fif);
506 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
508 unsigned int socket_id __rte_unused,
509 const struct rte_eth_rxconf *rx_conf __rte_unused,
510 struct rte_mempool *mp)
512 struct dpaa_if *dpaa_intf = dev->data->dev_private;
513 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
514 struct qm_mcc_initfq opts = {0};
518 PMD_INIT_FUNC_TRACE();
520 if (queue_idx >= dev->data->nb_rx_queues) {
521 rte_errno = EOVERFLOW;
522 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
523 (void *)dev, queue_idx, dev->data->nb_rx_queues);
527 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
528 queue_idx, rxq->fqid);
530 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
531 struct fman_if_ic_params icp;
535 if (!mp->pool_data) {
536 DPAA_PMD_ERR("Not an offloaded buffer pool!");
539 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
541 memset(&icp, 0, sizeof(icp));
542 /* set ICEOF for to the default value , which is 0*/
543 icp.iciof = DEFAULT_ICIOF;
544 icp.iceof = DEFAULT_RX_ICEOF;
545 icp.icsz = DEFAULT_ICSZ;
546 fman_if_set_ic_params(dpaa_intf->fif, &icp);
548 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
549 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
551 /* Buffer pool size should be equal to Dataroom Size*/
552 bp_size = rte_pktmbuf_data_room_size(mp);
553 fman_if_set_bp(dpaa_intf->fif, mp->size,
554 dpaa_intf->bp_info->bpid, bp_size);
555 dpaa_intf->valid = 1;
556 DPAA_PMD_INFO("if =%s - fd_offset = %d offset = %d",
557 dpaa_intf->name, fd_offset,
558 fman_if_get_fdoff(dpaa_intf->fif));
560 /* checking if push mode only, no error check for now */
561 if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
562 dpaa_push_queue_idx++;
563 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
564 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
565 QM_FQCTRL_CTXASTASHING |
566 QM_FQCTRL_PREFERINCACHE;
567 opts.fqd.context_a.stashing.exclusive = 0;
568 /* In muticore scenario stashing becomes a bottleneck on LS1046.
569 * So do not enable stashing in this case
571 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
572 opts.fqd.context_a.stashing.annotation_cl =
573 DPAA_IF_RX_ANNOTATION_STASH;
574 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
575 opts.fqd.context_a.stashing.context_cl =
576 DPAA_IF_RX_CONTEXT_STASH;
578 /*Create a channel and associate given queue with the channel*/
579 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
580 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
581 opts.fqd.dest.channel = rxq->ch_id;
582 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
583 flags = QMAN_INITFQ_FLAG_SCHED;
585 /* Configure tail drop */
586 if (dpaa_intf->cgr_rx) {
587 opts.we_mask |= QM_INITFQ_WE_CGID;
588 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
589 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
591 ret = qman_init_fq(rxq, flags, &opts);
593 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
594 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
597 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
598 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
599 rxq->is_static = true;
601 dev->data->rx_queues[queue_idx] = rxq;
603 /* configure the CGR size as per the desc size */
604 if (dpaa_intf->cgr_rx) {
605 struct qm_mcc_initcgr cgr_opts = {0};
607 /* Enable tail drop with cgr on this queue */
608 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
609 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
612 "rx taildrop modify fail on fqid %d (ret=%d)",
620 int __rte_experimental
621 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
624 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
628 struct dpaa_if *dpaa_intf = dev->data->dev_private;
629 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
630 struct qm_mcc_initfq opts = {0};
632 if (dpaa_push_mode_max_queue)
633 DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.\n"
634 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
635 dpaa_push_mode_max_queue);
637 dpaa_poll_queue_default_config(&opts);
639 switch (queue_conf->ev.sched_type) {
640 case RTE_SCHED_TYPE_ATOMIC:
641 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
642 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
643 * configuration with HOLD_ACTIVE setting
645 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
646 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
648 case RTE_SCHED_TYPE_ORDERED:
649 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
652 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
653 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
657 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
658 opts.fqd.dest.channel = ch_id;
659 opts.fqd.dest.wq = queue_conf->ev.priority;
661 if (dpaa_intf->cgr_rx) {
662 opts.we_mask |= QM_INITFQ_WE_CGID;
663 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
664 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
667 flags = QMAN_INITFQ_FLAG_SCHED;
669 ret = qman_init_fq(rxq, flags, &opts);
671 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
672 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
676 /* copy configuration which needs to be filled during dequeue */
677 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
678 dev->data->rx_queues[eth_rx_queue_id] = rxq;
683 int __rte_experimental
684 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
687 struct qm_mcc_initfq opts;
690 struct dpaa_if *dpaa_intf = dev->data->dev_private;
691 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
693 dpaa_poll_queue_default_config(&opts);
695 if (dpaa_intf->cgr_rx) {
696 opts.we_mask |= QM_INITFQ_WE_CGID;
697 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
698 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
701 ret = qman_init_fq(rxq, flags, &opts);
703 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
707 rxq->cb.dqrr_dpdk_cb = NULL;
708 dev->data->rx_queues[eth_rx_queue_id] = NULL;
714 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
716 PMD_INIT_FUNC_TRACE();
720 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
721 uint16_t nb_desc __rte_unused,
722 unsigned int socket_id __rte_unused,
723 const struct rte_eth_txconf *tx_conf __rte_unused)
725 struct dpaa_if *dpaa_intf = dev->data->dev_private;
727 PMD_INIT_FUNC_TRACE();
729 if (queue_idx >= dev->data->nb_tx_queues) {
730 rte_errno = EOVERFLOW;
731 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
732 (void *)dev, queue_idx, dev->data->nb_tx_queues);
736 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
737 queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
738 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
742 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
744 PMD_INIT_FUNC_TRACE();
748 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
750 struct dpaa_if *dpaa_intf = dev->data->dev_private;
751 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
754 PMD_INIT_FUNC_TRACE();
756 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
757 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
758 rx_queue_id, frm_cnt);
763 static int dpaa_link_down(struct rte_eth_dev *dev)
765 PMD_INIT_FUNC_TRACE();
767 dpaa_eth_dev_stop(dev);
771 static int dpaa_link_up(struct rte_eth_dev *dev)
773 PMD_INIT_FUNC_TRACE();
775 dpaa_eth_dev_start(dev);
780 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
781 struct rte_eth_fc_conf *fc_conf)
783 struct dpaa_if *dpaa_intf = dev->data->dev_private;
784 struct rte_eth_fc_conf *net_fc;
786 PMD_INIT_FUNC_TRACE();
788 if (!(dpaa_intf->fc_conf)) {
789 dpaa_intf->fc_conf = rte_zmalloc(NULL,
790 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
791 if (!dpaa_intf->fc_conf) {
792 DPAA_PMD_ERR("unable to save flow control info");
796 net_fc = dpaa_intf->fc_conf;
798 if (fc_conf->high_water < fc_conf->low_water) {
799 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
803 if (fc_conf->mode == RTE_FC_NONE) {
805 } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
806 fc_conf->mode == RTE_FC_FULL) {
807 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
809 dpaa_intf->bp_info->bpid);
810 if (fc_conf->pause_time)
811 fman_if_set_fc_quanta(dpaa_intf->fif,
812 fc_conf->pause_time);
815 /* Save the information in dpaa device */
816 net_fc->pause_time = fc_conf->pause_time;
817 net_fc->high_water = fc_conf->high_water;
818 net_fc->low_water = fc_conf->low_water;
819 net_fc->send_xon = fc_conf->send_xon;
820 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
821 net_fc->mode = fc_conf->mode;
822 net_fc->autoneg = fc_conf->autoneg;
828 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
829 struct rte_eth_fc_conf *fc_conf)
831 struct dpaa_if *dpaa_intf = dev->data->dev_private;
832 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
835 PMD_INIT_FUNC_TRACE();
838 fc_conf->pause_time = net_fc->pause_time;
839 fc_conf->high_water = net_fc->high_water;
840 fc_conf->low_water = net_fc->low_water;
841 fc_conf->send_xon = net_fc->send_xon;
842 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
843 fc_conf->mode = net_fc->mode;
844 fc_conf->autoneg = net_fc->autoneg;
847 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
849 fc_conf->mode = RTE_FC_TX_PAUSE;
850 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
852 fc_conf->mode = RTE_FC_NONE;
859 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
860 struct ether_addr *addr,
862 __rte_unused uint32_t pool)
865 struct dpaa_if *dpaa_intf = dev->data->dev_private;
867 PMD_INIT_FUNC_TRACE();
869 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
872 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
878 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
881 struct dpaa_if *dpaa_intf = dev->data->dev_private;
883 PMD_INIT_FUNC_TRACE();
885 fman_if_clear_mac_addr(dpaa_intf->fif, index);
889 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
890 struct ether_addr *addr)
893 struct dpaa_if *dpaa_intf = dev->data->dev_private;
895 PMD_INIT_FUNC_TRACE();
897 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
899 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
904 static struct eth_dev_ops dpaa_devops = {
905 .dev_configure = dpaa_eth_dev_configure,
906 .dev_start = dpaa_eth_dev_start,
907 .dev_stop = dpaa_eth_dev_stop,
908 .dev_close = dpaa_eth_dev_close,
909 .dev_infos_get = dpaa_eth_dev_info,
910 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
912 .rx_queue_setup = dpaa_eth_rx_queue_setup,
913 .tx_queue_setup = dpaa_eth_tx_queue_setup,
914 .rx_queue_release = dpaa_eth_rx_queue_release,
915 .tx_queue_release = dpaa_eth_tx_queue_release,
916 .rx_queue_count = dpaa_dev_rx_queue_count,
918 .flow_ctrl_get = dpaa_flow_ctrl_get,
919 .flow_ctrl_set = dpaa_flow_ctrl_set,
921 .link_update = dpaa_eth_link_update,
922 .stats_get = dpaa_eth_stats_get,
923 .xstats_get = dpaa_dev_xstats_get,
924 .xstats_get_by_id = dpaa_xstats_get_by_id,
925 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
926 .xstats_get_names = dpaa_xstats_get_names,
927 .xstats_reset = dpaa_eth_stats_reset,
928 .stats_reset = dpaa_eth_stats_reset,
929 .promiscuous_enable = dpaa_eth_promiscuous_enable,
930 .promiscuous_disable = dpaa_eth_promiscuous_disable,
931 .allmulticast_enable = dpaa_eth_multicast_enable,
932 .allmulticast_disable = dpaa_eth_multicast_disable,
933 .mtu_set = dpaa_mtu_set,
934 .dev_set_link_down = dpaa_link_down,
935 .dev_set_link_up = dpaa_link_up,
936 .mac_addr_add = dpaa_dev_add_mac_addr,
937 .mac_addr_remove = dpaa_dev_remove_mac_addr,
938 .mac_addr_set = dpaa_dev_set_mac_addr,
940 .fw_version_get = dpaa_fw_version_get,
944 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
946 if (strcmp(dev->device->driver->name,
954 is_dpaa_supported(struct rte_eth_dev *dev)
956 return is_device_supported(dev, &rte_dpaa_pmd);
959 int __rte_experimental
960 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
962 struct rte_eth_dev *dev;
963 struct dpaa_if *dpaa_intf;
965 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
967 dev = &rte_eth_devices[port];
969 if (!is_dpaa_supported(dev))
972 dpaa_intf = dev->data->dev_private;
975 fman_if_loopback_enable(dpaa_intf->fif);
977 fman_if_loopback_disable(dpaa_intf->fif);
982 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
984 struct rte_eth_fc_conf *fc_conf;
987 PMD_INIT_FUNC_TRACE();
989 if (!(dpaa_intf->fc_conf)) {
990 dpaa_intf->fc_conf = rte_zmalloc(NULL,
991 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
992 if (!dpaa_intf->fc_conf) {
993 DPAA_PMD_ERR("unable to save flow control info");
997 fc_conf = dpaa_intf->fc_conf;
998 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
1000 fc_conf->mode = RTE_FC_TX_PAUSE;
1001 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1003 fc_conf->mode = RTE_FC_NONE;
1009 /* Initialise an Rx FQ */
1010 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1013 struct qm_mcc_initfq opts = {0};
1016 struct qm_mcc_initcgr cgr_opts = {
1017 .we_mask = QM_CGR_WE_CS_THRES |
1021 .cstd_en = QM_CGR_EN,
1022 .mode = QMAN_CGR_MODE_FRAME
1026 PMD_INIT_FUNC_TRACE();
1028 ret = qman_reserve_fqid(fqid);
1030 DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1035 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1036 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1038 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1042 fq->is_static = false;
1044 dpaa_poll_queue_default_config(&opts);
1047 /* Enable tail drop with cgr on this queue */
1048 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1050 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1054 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1058 opts.we_mask |= QM_INITFQ_WE_CGID;
1059 opts.fqd.cgid = cgr_rx->cgrid;
1060 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1063 ret = qman_init_fq(fq, flags, &opts);
1065 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1069 /* Initialise a Tx FQ */
1070 static int dpaa_tx_queue_init(struct qman_fq *fq,
1071 struct fman_if *fman_intf)
1073 struct qm_mcc_initfq opts = {0};
1076 PMD_INIT_FUNC_TRACE();
1078 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1079 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1081 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1084 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1085 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1086 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1087 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1088 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1089 opts.fqd.context_b = 0;
1090 /* no tx-confirmation */
1091 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1092 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1093 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1094 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1096 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1100 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1101 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1102 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1104 struct qm_mcc_initfq opts = {0};
1107 PMD_INIT_FUNC_TRACE();
1109 ret = qman_reserve_fqid(fqid);
1111 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1115 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1116 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1117 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1119 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1123 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1124 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1125 ret = qman_init_fq(fq, 0, &opts);
1127 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1133 /* Initialise a network interface */
1135 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1137 int num_cores, num_rx_fqs, fqid;
1140 struct rte_dpaa_device *dpaa_device;
1141 struct dpaa_if *dpaa_intf;
1142 struct fm_eth_port_cfg *cfg;
1143 struct fman_if *fman_intf;
1144 struct fman_if_bpool *bp, *tmp_bp;
1145 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1147 PMD_INIT_FUNC_TRACE();
1149 /* For secondary processes, the primary has done all the work */
1150 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1153 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1154 dev_id = dpaa_device->id.dev_id;
1155 dpaa_intf = eth_dev->data->dev_private;
1156 cfg = &dpaa_netcfg->port_cfg[dev_id];
1157 fman_intf = cfg->fman_if;
1159 dpaa_intf->name = dpaa_device->name;
1161 /* save fman_if & cfg in the interface struture */
1162 dpaa_intf->fif = fman_intf;
1163 dpaa_intf->ifid = dev_id;
1164 dpaa_intf->cfg = cfg;
1166 /* Initialize Rx FQ's */
1168 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1170 if (getenv("DPAA_NUM_RX_QUEUES"))
1171 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1173 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1177 /* if push mode queues to be enabled. Currenly we are allowing only
1178 * one queue per thread.
1180 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1181 dpaa_push_mode_max_queue =
1182 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1183 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1184 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1187 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1190 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1191 DPAA_PMD_ERR("Invalid number of RX queues\n");
1195 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1196 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1197 if (!dpaa_intf->rx_queues) {
1198 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1202 /* If congestion control is enabled globally*/
1204 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1205 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1206 if (!dpaa_intf->cgr_rx) {
1207 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1212 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1213 if (ret != num_rx_fqs) {
1214 DPAA_PMD_WARN("insufficient CGRIDs available");
1219 dpaa_intf->cgr_rx = NULL;
1222 for (loop = 0; loop < num_rx_fqs; loop++) {
1226 fqid = DPAA_PCD_FQID_START + dpaa_intf->ifid *
1227 DPAA_PCD_FQID_MULTIPLIER + loop;
1229 if (dpaa_intf->cgr_rx)
1230 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1232 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1233 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1237 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1239 dpaa_intf->nb_rx_queues = num_rx_fqs;
1241 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1242 num_cores = rte_lcore_count();
1243 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1244 num_cores, MAX_CACHELINE);
1245 if (!dpaa_intf->tx_queues) {
1246 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1251 for (loop = 0; loop < num_cores; loop++) {
1252 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1256 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1258 dpaa_intf->nb_tx_queues = num_cores;
1260 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1261 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1262 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1263 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1264 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1265 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1266 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1269 DPAA_PMD_DEBUG("All frame queues created");
1271 /* Get the initial configuration for flow control */
1272 dpaa_fc_set_default(dpaa_intf);
1274 /* reset bpool list, initialize bpool dynamically */
1275 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1276 list_del(&bp->node);
1280 /* Populate ethdev structure */
1281 eth_dev->dev_ops = &dpaa_devops;
1282 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1283 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1285 /* Allocate memory for storing MAC addresses */
1286 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1287 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1288 if (eth_dev->data->mac_addrs == NULL) {
1289 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1290 "store MAC addresses",
1291 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1296 /* copy the primary mac address */
1297 ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]);
1299 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1301 fman_intf->mac_addr.addr_bytes[0],
1302 fman_intf->mac_addr.addr_bytes[1],
1303 fman_intf->mac_addr.addr_bytes[2],
1304 fman_intf->mac_addr.addr_bytes[3],
1305 fman_intf->mac_addr.addr_bytes[4],
1306 fman_intf->mac_addr.addr_bytes[5]);
1308 /* Disable RX mode */
1309 fman_if_discard_rx_errors(fman_intf);
1310 fman_if_disable_rx(fman_intf);
1311 /* Disable promiscuous mode */
1312 fman_if_promiscuous_disable(fman_intf);
1313 /* Disable multicast */
1314 fman_if_reset_mcast_filter_table(fman_intf);
1315 /* Reset interface statistics */
1316 fman_if_stats_reset(fman_intf);
1321 rte_free(dpaa_intf->tx_queues);
1322 dpaa_intf->tx_queues = NULL;
1323 dpaa_intf->nb_tx_queues = 0;
1326 rte_free(dpaa_intf->cgr_rx);
1327 rte_free(dpaa_intf->rx_queues);
1328 dpaa_intf->rx_queues = NULL;
1329 dpaa_intf->nb_rx_queues = 0;
1334 dpaa_dev_uninit(struct rte_eth_dev *dev)
1336 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1339 PMD_INIT_FUNC_TRACE();
1341 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1345 DPAA_PMD_WARN("Already closed or not started");
1349 dpaa_eth_dev_close(dev);
1351 /* release configuration memory */
1352 if (dpaa_intf->fc_conf)
1353 rte_free(dpaa_intf->fc_conf);
1355 /* Release RX congestion Groups */
1356 if (dpaa_intf->cgr_rx) {
1357 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1358 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1360 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1361 dpaa_intf->nb_rx_queues);
1364 rte_free(dpaa_intf->cgr_rx);
1365 dpaa_intf->cgr_rx = NULL;
1367 rte_free(dpaa_intf->rx_queues);
1368 dpaa_intf->rx_queues = NULL;
1370 rte_free(dpaa_intf->tx_queues);
1371 dpaa_intf->tx_queues = NULL;
1373 /* free memory for storing MAC addresses */
1374 rte_free(dev->data->mac_addrs);
1375 dev->data->mac_addrs = NULL;
1377 dev->dev_ops = NULL;
1378 dev->rx_pkt_burst = NULL;
1379 dev->tx_pkt_burst = NULL;
1385 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
1386 struct rte_dpaa_device *dpaa_dev)
1390 struct rte_eth_dev *eth_dev;
1392 PMD_INIT_FUNC_TRACE();
1394 /* In case of secondary process, the device is already configured
1395 * and no further action is required, except portal initialization
1396 * and verifying secondary attachment to port name.
1398 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1399 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1402 rte_eth_dev_probing_finish(eth_dev);
1406 if (!is_global_init) {
1407 /* One time load of Qman/Bman drivers */
1408 ret = qman_global_init();
1410 DPAA_PMD_ERR("QMAN initialization failed: %d",
1414 ret = bman_global_init();
1416 DPAA_PMD_ERR("BMAN initialization failed: %d",
1421 if (access("/tmp/fmc.bin", F_OK) == -1) {
1423 "* FMC not configured.Enabling default mode\n");
1430 if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1431 ret = rte_dpaa_portal_init((void *)1);
1433 DPAA_PMD_ERR("Unable to initialize portal");
1438 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1439 if (eth_dev == NULL)
1442 eth_dev->data->dev_private = rte_zmalloc(
1443 "ethdev private structure",
1444 sizeof(struct dpaa_if),
1445 RTE_CACHE_LINE_SIZE);
1446 if (!eth_dev->data->dev_private) {
1447 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1448 rte_eth_dev_release_port(eth_dev);
1452 eth_dev->device = &dpaa_dev->device;
1453 eth_dev->device->driver = &dpaa_drv->driver;
1454 dpaa_dev->eth_dev = eth_dev;
1456 /* Invoke PMD device initialization function */
1457 diag = dpaa_dev_init(eth_dev);
1459 rte_eth_dev_probing_finish(eth_dev);
1463 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1464 rte_free(eth_dev->data->dev_private);
1466 rte_eth_dev_release_port(eth_dev);
1471 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1473 struct rte_eth_dev *eth_dev;
1475 PMD_INIT_FUNC_TRACE();
1477 eth_dev = dpaa_dev->eth_dev;
1478 dpaa_dev_uninit(eth_dev);
1480 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1481 rte_free(eth_dev->data->dev_private);
1483 rte_eth_dev_release_port(eth_dev);
1488 static struct rte_dpaa_driver rte_dpaa_pmd = {
1489 .drv_type = FSL_DPAA_ETH,
1490 .probe = rte_dpaa_probe,
1491 .remove = rte_dpaa_remove,
1494 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);