drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <rte_ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <rte_pmd_dpaa.h>
  43
  44 #include <fsl_usd.h>
  45 #include <fsl_qman.h>
  46 #include <fsl_bman.h>
  47 #include <fsl_fman.h>
  48
  49 /* Supported Rx offloads */
  50 static uint64_t dev_rx_offloads_sup =
  51                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  52                 DEV_RX_OFFLOAD_SCATTER;
  53
  54 /* Rx offloads which cannot be disabled */
  55 static uint64_t dev_rx_offloads_nodis =
  56                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  57                 DEV_RX_OFFLOAD_UDP_CKSUM |
  58                 DEV_RX_OFFLOAD_TCP_CKSUM |
  59                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  60                 DEV_RX_OFFLOAD_RSS_HASH;
  61
  62 /* Supported Tx offloads */
  63 static uint64_t dev_tx_offloads_sup =
  64                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  65                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  66
  67 /* Tx offloads which cannot be disabled */
  68 static uint64_t dev_tx_offloads_nodis =
  69                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  70                 DEV_TX_OFFLOAD_UDP_CKSUM |
  71                 DEV_TX_OFFLOAD_TCP_CKSUM |
  72                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  73                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  74                 DEV_TX_OFFLOAD_MULTI_SEGS;
  75
  76 /* Keep track of whether QMAN and BMAN have been globally initialized */
  77 static int is_global_init;
  78 static int default_q;   /* use default queue - FMC is not executed*/
  79 /* At present we only allow up to 4 push mode queues as default - as each of
  80  * this queue need dedicated portal and we are short of portals.
  81  */
  82 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  83 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  84
  85 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  86 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  87
  88
  89 /* Per RX FQ Taildrop in frame count */
  90 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  91
  92 /* Per TX FQ Taildrop in frame count, disabled by default */
  93 static unsigned int td_tx_threshold;
  94
  95 struct rte_dpaa_xstats_name_off {
  96         char name[RTE_ETH_XSTATS_NAME_SIZE];
  97         uint32_t offset;
  98 };
  99
 100 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 101         {"rx_align_err",
 102                 offsetof(struct dpaa_if_stats, raln)},
 103         {"rx_valid_pause",
 104                 offsetof(struct dpaa_if_stats, rxpf)},
 105         {"rx_fcs_err",
 106                 offsetof(struct dpaa_if_stats, rfcs)},
 107         {"rx_vlan_frame",
 108                 offsetof(struct dpaa_if_stats, rvlan)},
 109         {"rx_frame_err",
 110                 offsetof(struct dpaa_if_stats, rerr)},
 111         {"rx_drop_err",
 112                 offsetof(struct dpaa_if_stats, rdrp)},
 113         {"rx_undersized",
 114                 offsetof(struct dpaa_if_stats, rund)},
 115         {"rx_oversize_err",
 116                 offsetof(struct dpaa_if_stats, rovr)},
 117         {"rx_fragment_pkt",
 118                 offsetof(struct dpaa_if_stats, rfrg)},
 119         {"tx_valid_pause",
 120                 offsetof(struct dpaa_if_stats, txpf)},
 121         {"tx_fcs_err",
 122                 offsetof(struct dpaa_if_stats, terr)},
 123         {"tx_vlan_frame",
 124                 offsetof(struct dpaa_if_stats, tvlan)},
 125         {"rx_undersized",
 126                 offsetof(struct dpaa_if_stats, tund)},
 127 };
 128
 129 static struct rte_dpaa_driver rte_dpaa_pmd;
 130
 131 static int
 132 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 133
 134 static inline void
 135 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 136 {
 137         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 138         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 139         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 140                            QM_FQCTRL_PREFERINCACHE;
 141         opts->fqd.context_a.stashing.exclusive = 0;
 142         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 143                 opts->fqd.context_a.stashing.annotation_cl =
 144                                                 DPAA_IF_RX_ANNOTATION_STASH;
 145         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 146         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 147 }
 148
 149 static int
 150 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 151 {
 152         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 153         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 154                                 + VLAN_TAG_SIZE;
 155         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 156
 157         PMD_INIT_FUNC_TRACE();
 158
 159         if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
 160                 return -EINVAL;
 161         /*
 162          * Refuse mtu that requires the support of scattered packets
 163          * when this feature has not been enabled before.
 164          */
 165         if (dev->data->min_rx_buf_size &&
 166                 !dev->data->scattered_rx && frame_size > buffsz) {
 167                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 168                 return -EINVAL;
 169         }
 170
 171         /* check <seg size> * <max_seg>  >= max_frame */
 172         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 173                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 174                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 175                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 176                 return -EINVAL;
 177         }
 178
 179         if (frame_size > RTE_ETHER_MAX_LEN)
 180                 dev->data->dev_conf.rxmode.offloads |=
 181                                                 DEV_RX_OFFLOAD_JUMBO_FRAME;
 182         else
 183                 dev->data->dev_conf.rxmode.offloads &=
 184                                                 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 185
 186         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
 187
 188         fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
 189
 190         return 0;
 191 }
 192
 193 static int
 194 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 195 {
 196         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 197         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 198         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 199         uint64_t tx_offloads = eth_conf->txmode.offloads;
 200
 201         PMD_INIT_FUNC_TRACE();
 202
 203         /* Rx offloads which are enabled by default */
 204         if (dev_rx_offloads_nodis & ~rx_offloads) {
 205                 DPAA_PMD_INFO(
 206                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 207                 " fixed are 0x%" PRIx64,
 208                 rx_offloads, dev_rx_offloads_nodis);
 209         }
 210
 211         /* Tx offloads which are enabled by default */
 212         if (dev_tx_offloads_nodis & ~tx_offloads) {
 213                 DPAA_PMD_INFO(
 214                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 215                 " fixed are 0x%" PRIx64,
 216                 tx_offloads, dev_tx_offloads_nodis);
 217         }
 218
 219         if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 220                 uint32_t max_len;
 221
 222                 DPAA_PMD_DEBUG("enabling jumbo");
 223
 224                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
 225                     DPAA_MAX_RX_PKT_LEN)
 226                         max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
 227                 else {
 228                         DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 229                                 "supported is %d",
 230                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 231                                 DPAA_MAX_RX_PKT_LEN);
 232                         max_len = DPAA_MAX_RX_PKT_LEN;
 233                 }
 234
 235                 fman_if_set_maxfrm(dpaa_intf->fif, max_len);
 236                 dev->data->mtu = max_len
 237                         - RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE;
 238         }
 239
 240         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 241                 DPAA_PMD_DEBUG("enabling scatter mode");
 242                 fman_if_set_sg(dpaa_intf->fif, 1);
 243                 dev->data->scattered_rx = 1;
 244         }
 245
 246         return 0;
 247 }
 248
 249 static const uint32_t *
 250 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 251 {
 252         static const uint32_t ptypes[] = {
 253                 RTE_PTYPE_L2_ETHER,
 254                 RTE_PTYPE_L2_ETHER_VLAN,
 255                 RTE_PTYPE_L2_ETHER_ARP,
 256                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 257                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 258                 RTE_PTYPE_L4_ICMP,
 259                 RTE_PTYPE_L4_TCP,
 260                 RTE_PTYPE_L4_UDP,
 261                 RTE_PTYPE_L4_FRAG,
 262                 RTE_PTYPE_L4_TCP,
 263                 RTE_PTYPE_L4_UDP,
 264                 RTE_PTYPE_L4_SCTP
 265         };
 266
 267         PMD_INIT_FUNC_TRACE();
 268
 269         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 270                 return ptypes;
 271         return NULL;
 272 }
 273
 274 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 275 {
 276         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 277
 278         PMD_INIT_FUNC_TRACE();
 279
 280         /* Change tx callback to the real one */
 281         if (dpaa_intf->cgr_tx)
 282                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 283         else
 284                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 285
 286         fman_if_enable_rx(dpaa_intf->fif);
 287
 288         return 0;
 289 }
 290
 291 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 292 {
 293         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 294
 295         PMD_INIT_FUNC_TRACE();
 296
 297         fman_if_disable_rx(dpaa_intf->fif);
 298         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 299 }
 300
 301 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
 302 {
 303         PMD_INIT_FUNC_TRACE();
 304
 305         dpaa_eth_dev_stop(dev);
 306 }
 307
 308 static int
 309 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 310                      char *fw_version,
 311                      size_t fw_size)
 312 {
 313         int ret;
 314         FILE *svr_file = NULL;
 315         unsigned int svr_ver = 0;
 316
 317         PMD_INIT_FUNC_TRACE();
 318
 319         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 320         if (!svr_file) {
 321                 DPAA_PMD_ERR("Unable to open SoC device");
 322                 return -ENOTSUP; /* Not supported on this infra */
 323         }
 324         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 325                 dpaa_svr_family = svr_ver & SVR_MASK;
 326         else
 327                 DPAA_PMD_ERR("Unable to read SoC device");
 328
 329         fclose(svr_file);
 330
 331         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 332                        svr_ver, fman_ip_rev);
 333         ret += 1; /* add the size of '\0' */
 334
 335         if (fw_size < (uint32_t)ret)
 336                 return ret;
 337         else
 338                 return 0;
 339 }
 340
 341 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 342                              struct rte_eth_dev_info *dev_info)
 343 {
 344         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 345
 346         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 347
 348         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 349         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 350         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 351         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 352         dev_info->max_hash_mac_addrs = 0;
 353         dev_info->max_vfs = 0;
 354         dev_info->max_vmdq_pools = ETH_16_POOLS;
 355         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 356
 357         if (dpaa_intf->fif->mac_type == fman_mac_1g) {
 358                 dev_info->speed_capa = ETH_LINK_SPEED_1G;
 359         } else if (dpaa_intf->fif->mac_type == fman_mac_10g) {
 360                 dev_info->speed_capa = (ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G);
 361         } else {
 362                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 363                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 364                 return -EINVAL;
 365         }
 366
 367         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 368                                         dev_rx_offloads_nodis;
 369         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 370                                         dev_tx_offloads_nodis;
 371         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 372         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 373         dev_info->default_rxportconf.nb_queues = 1;
 374         dev_info->default_txportconf.nb_queues = 1;
 375         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 376         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 377
 378         return 0;
 379 }
 380
 381 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 382                                 int wait_to_complete __rte_unused)
 383 {
 384         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 385         struct rte_eth_link *link = &dev->data->dev_link;
 386
 387         PMD_INIT_FUNC_TRACE();
 388
 389         if (dpaa_intf->fif->mac_type == fman_mac_1g)
 390                 link->link_speed = ETH_SPEED_NUM_1G;
 391         else if (dpaa_intf->fif->mac_type == fman_mac_10g)
 392                 link->link_speed = ETH_SPEED_NUM_10G;
 393         else
 394                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 395                              dpaa_intf->name, dpaa_intf->fif->mac_type);
 396
 397         link->link_status = dpaa_intf->valid;
 398         link->link_duplex = ETH_LINK_FULL_DUPLEX;
 399         link->link_autoneg = ETH_LINK_AUTONEG;
 400         return 0;
 401 }
 402
 403 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 404                                struct rte_eth_stats *stats)
 405 {
 406         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 407
 408         PMD_INIT_FUNC_TRACE();
 409
 410         fman_if_stats_get(dpaa_intf->fif, stats);
 411         return 0;
 412 }
 413
 414 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 415 {
 416         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 417
 418         PMD_INIT_FUNC_TRACE();
 419
 420         fman_if_stats_reset(dpaa_intf->fif);
 421
 422         return 0;
 423 }
 424
 425 static int
 426 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 427                     unsigned int n)
 428 {
 429         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 430         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 431         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 432
 433         if (n < num)
 434                 return num;
 435
 436         if (xstats == NULL)
 437                 return 0;
 438
 439         fman_if_stats_get_all(dpaa_intf->fif, values,
 440                               sizeof(struct dpaa_if_stats) / 8);
 441
 442         for (i = 0; i < num; i++) {
 443                 xstats[i].id = i;
 444                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 445         }
 446         return i;
 447 }
 448
 449 static int
 450 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 451                       struct rte_eth_xstat_name *xstats_names,
 452                       unsigned int limit)
 453 {
 454         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 455
 456         if (limit < stat_cnt)
 457                 return stat_cnt;
 458
 459         if (xstats_names != NULL)
 460                 for (i = 0; i < stat_cnt; i++)
 461                         strlcpy(xstats_names[i].name,
 462                                 dpaa_xstats_strings[i].name,
 463                                 sizeof(xstats_names[i].name));
 464
 465         return stat_cnt;
 466 }
 467
 468 static int
 469 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 470                       uint64_t *values, unsigned int n)
 471 {
 472         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 473         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 474
 475         if (!ids) {
 476                 struct dpaa_if *dpaa_intf = dev->data->dev_private;
 477
 478                 if (n < stat_cnt)
 479                         return stat_cnt;
 480
 481                 if (!values)
 482                         return 0;
 483
 484                 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
 485                                       sizeof(struct dpaa_if_stats) / 8);
 486
 487                 for (i = 0; i < stat_cnt; i++)
 488                         values[i] =
 489                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 490
 491                 return stat_cnt;
 492         }
 493
 494         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 495
 496         for (i = 0; i < n; i++) {
 497                 if (ids[i] >= stat_cnt) {
 498                         DPAA_PMD_ERR("id value isn't valid");
 499                         return -1;
 500                 }
 501                 values[i] = values_copy[ids[i]];
 502         }
 503         return n;
 504 }
 505
 506 static int
 507 dpaa_xstats_get_names_by_id(
 508         struct rte_eth_dev *dev,
 509         struct rte_eth_xstat_name *xstats_names,
 510         const uint64_t *ids,
 511         unsigned int limit)
 512 {
 513         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 514         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 515
 516         if (!ids)
 517                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 518
 519         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 520
 521         for (i = 0; i < limit; i++) {
 522                 if (ids[i] >= stat_cnt) {
 523                         DPAA_PMD_ERR("id value isn't valid");
 524                         return -1;
 525                 }
 526                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 527         }
 528         return limit;
 529 }
 530
 531 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 532 {
 533         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 534
 535         PMD_INIT_FUNC_TRACE();
 536
 537         fman_if_promiscuous_enable(dpaa_intf->fif);
 538
 539         return 0;
 540 }
 541
 542 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 543 {
 544         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 545
 546         PMD_INIT_FUNC_TRACE();
 547
 548         fman_if_promiscuous_disable(dpaa_intf->fif);
 549
 550         return 0;
 551 }
 552
 553 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 554 {
 555         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 556
 557         PMD_INIT_FUNC_TRACE();
 558
 559         fman_if_set_mcast_filter_table(dpaa_intf->fif);
 560
 561         return 0;
 562 }
 563
 564 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 565 {
 566         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 567
 568         PMD_INIT_FUNC_TRACE();
 569
 570         fman_if_reset_mcast_filter_table(dpaa_intf->fif);
 571
 572         return 0;
 573 }
 574
 575 static
 576 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 577                             uint16_t nb_desc,
 578                             unsigned int socket_id __rte_unused,
 579                             const struct rte_eth_rxconf *rx_conf __rte_unused,
 580                             struct rte_mempool *mp)
 581 {
 582         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 583         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 584         struct qm_mcc_initfq opts = {0};
 585         u32 flags = 0;
 586         int ret;
 587         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 588
 589         PMD_INIT_FUNC_TRACE();
 590
 591         if (queue_idx >= dev->data->nb_rx_queues) {
 592                 rte_errno = EOVERFLOW;
 593                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 594                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 595                 return -rte_errno;
 596         }
 597
 598         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 599                         queue_idx, rxq->fqid);
 600
 601         /* Max packet can fit in single buffer */
 602         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
 603                 ;
 604         } else if (dev->data->dev_conf.rxmode.offloads &
 605                         DEV_RX_OFFLOAD_SCATTER) {
 606                 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
 607                         buffsz * DPAA_SGT_MAX_ENTRIES) {
 608                         DPAA_PMD_ERR("max RxPkt size %d too big to fit "
 609                                 "MaxSGlist %d",
 610                                 dev->data->dev_conf.rxmode.max_rx_pkt_len,
 611                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 612                         rte_errno = EOVERFLOW;
 613                         return -rte_errno;
 614                 }
 615         } else {
 616                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 617                      " larger than a single mbuf (%u) and scattered"
 618                      " mode has not been requested",
 619                      dev->data->dev_conf.rxmode.max_rx_pkt_len,
 620                      buffsz - RTE_PKTMBUF_HEADROOM);
 621         }
 622
 623         if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
 624                 struct fman_if_ic_params icp;
 625                 uint32_t fd_offset;
 626                 uint32_t bp_size;
 627
 628                 if (!mp->pool_data) {
 629                         DPAA_PMD_ERR("Not an offloaded buffer pool!");
 630                         return -1;
 631                 }
 632                 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 633
 634                 memset(&icp, 0, sizeof(icp));
 635                 /* set ICEOF for to the default value , which is 0*/
 636                 icp.iciof = DEFAULT_ICIOF;
 637                 icp.iceof = DEFAULT_RX_ICEOF;
 638                 icp.icsz = DEFAULT_ICSZ;
 639                 fman_if_set_ic_params(dpaa_intf->fif, &icp);
 640
 641                 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 642                 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
 643
 644                 /* Buffer pool size should be equal to Dataroom Size*/
 645                 bp_size = rte_pktmbuf_data_room_size(mp);
 646                 fman_if_set_bp(dpaa_intf->fif, mp->size,
 647                                dpaa_intf->bp_info->bpid, bp_size);
 648                 dpaa_intf->valid = 1;
 649                 DPAA_PMD_DEBUG("if:%s fd_offset = %d offset = %d",
 650                                 dpaa_intf->name, fd_offset,
 651                                 fman_if_get_fdoff(dpaa_intf->fif));
 652         }
 653         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
 654                 fman_if_get_sg_enable(dpaa_intf->fif),
 655                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
 656         /* checking if push mode only, no error check for now */
 657         if (!rxq->is_static &&
 658             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
 659                 struct qman_portal *qp;
 660                 int q_fd;
 661
 662                 dpaa_push_queue_idx++;
 663                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 664                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
 665                                    QM_FQCTRL_CTXASTASHING |
 666                                    QM_FQCTRL_PREFERINCACHE;
 667                 opts.fqd.context_a.stashing.exclusive = 0;
 668                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
 669                  * So do not enable stashing in this case
 670                  */
 671                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 672                         opts.fqd.context_a.stashing.annotation_cl =
 673                                                 DPAA_IF_RX_ANNOTATION_STASH;
 674                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 675                 opts.fqd.context_a.stashing.context_cl =
 676                                                 DPAA_IF_RX_CONTEXT_STASH;
 677
 678                 /*Create a channel and associate given queue with the channel*/
 679                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
 680                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 681                 opts.fqd.dest.channel = rxq->ch_id;
 682                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
 683                 flags = QMAN_INITFQ_FLAG_SCHED;
 684
 685                 /* Configure tail drop */
 686                 if (dpaa_intf->cgr_rx) {
 687                         opts.we_mask |= QM_INITFQ_WE_CGID;
 688                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
 689                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 690                 }
 691                 ret = qman_init_fq(rxq, flags, &opts);
 692                 if (ret) {
 693                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
 694                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 695                         return ret;
 696                 }
 697                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
 698                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
 699                 } else {
 700                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
 701                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
 702                 }
 703
 704                 rxq->is_static = true;
 705
 706                 /* Allocate qman specific portals */
 707                 qp = fsl_qman_fq_portal_create(&q_fd);
 708                 if (!qp) {
 709                         DPAA_PMD_ERR("Unable to alloc fq portal");
 710                         return -1;
 711                 }
 712                 rxq->qp = qp;
 713
 714                 /* Set up the device interrupt handler */
 715                 if (!dev->intr_handle) {
 716                         struct rte_dpaa_device *dpaa_dev;
 717                         struct rte_device *rdev = dev->device;
 718
 719                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
 720                                                 device);
 721                         dev->intr_handle = &dpaa_dev->intr_handle;
 722                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
 723                                         dpaa_push_mode_max_queue, 0);
 724                         if (!dev->intr_handle->intr_vec) {
 725                                 DPAA_PMD_ERR("intr_vec alloc failed");
 726                                 return -ENOMEM;
 727                         }
 728                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
 729                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
 730                 }
 731
 732                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
 733                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
 734                 dev->intr_handle->efds[queue_idx] = q_fd;
 735                 rxq->q_fd = q_fd;
 736         }
 737         rxq->bp_array = rte_dpaa_bpid_info;
 738         dev->data->rx_queues[queue_idx] = rxq;
 739
 740         /* configure the CGR size as per the desc size */
 741         if (dpaa_intf->cgr_rx) {
 742                 struct qm_mcc_initcgr cgr_opts = {0};
 743
 744                 /* Enable tail drop with cgr on this queue */
 745                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
 746                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
 747                 if (ret) {
 748                         DPAA_PMD_WARN(
 749                                 "rx taildrop modify fail on fqid %d (ret=%d)",
 750                                 rxq->fqid, ret);
 751                 }
 752         }
 753
 754         return 0;
 755 }
 756
 757 int
 758 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
 759                 int eth_rx_queue_id,
 760                 u16 ch_id,
 761                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
 762 {
 763         int ret;
 764         u32 flags = 0;
 765         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 766         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 767         struct qm_mcc_initfq opts = {0};
 768
 769         if (dpaa_push_mode_max_queue)
 770                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
 771                               "PUSH mode already enabled for first %d queues.\n"
 772                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
 773                               dpaa_push_mode_max_queue);
 774
 775         dpaa_poll_queue_default_config(&opts);
 776
 777         switch (queue_conf->ev.sched_type) {
 778         case RTE_SCHED_TYPE_ATOMIC:
 779                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
 780                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
 781                  * configuration with HOLD_ACTIVE setting
 782                  */
 783                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
 784                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
 785                 break;
 786         case RTE_SCHED_TYPE_ORDERED:
 787                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
 788                 return -1;
 789         default:
 790                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
 791                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
 792                 break;
 793         }
 794
 795         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
 796         opts.fqd.dest.channel = ch_id;
 797         opts.fqd.dest.wq = queue_conf->ev.priority;
 798
 799         if (dpaa_intf->cgr_rx) {
 800                 opts.we_mask |= QM_INITFQ_WE_CGID;
 801                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 802                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 803         }
 804
 805         flags = QMAN_INITFQ_FLAG_SCHED;
 806
 807         ret = qman_init_fq(rxq, flags, &opts);
 808         if (ret) {
 809                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
 810                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
 811                 return ret;
 812         }
 813
 814         /* copy configuration which needs to be filled during dequeue */
 815         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
 816         dev->data->rx_queues[eth_rx_queue_id] = rxq;
 817
 818         return ret;
 819 }
 820
 821 int
 822 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
 823                 int eth_rx_queue_id)
 824 {
 825         struct qm_mcc_initfq opts;
 826         int ret;
 827         u32 flags = 0;
 828         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 829         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
 830
 831         dpaa_poll_queue_default_config(&opts);
 832
 833         if (dpaa_intf->cgr_rx) {
 834                 opts.we_mask |= QM_INITFQ_WE_CGID;
 835                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
 836                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
 837         }
 838
 839         ret = qman_init_fq(rxq, flags, &opts);
 840         if (ret) {
 841                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
 842                              rxq->fqid, ret);
 843         }
 844
 845         rxq->cb.dqrr_dpdk_cb = NULL;
 846         dev->data->rx_queues[eth_rx_queue_id] = NULL;
 847
 848         return 0;
 849 }
 850
 851 static
 852 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
 853 {
 854         PMD_INIT_FUNC_TRACE();
 855 }
 856
 857 static
 858 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 859                             uint16_t nb_desc __rte_unused,
 860                 unsigned int socket_id __rte_unused,
 861                 const struct rte_eth_txconf *tx_conf __rte_unused)
 862 {
 863         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 864
 865         PMD_INIT_FUNC_TRACE();
 866
 867         if (queue_idx >= dev->data->nb_tx_queues) {
 868                 rte_errno = EOVERFLOW;
 869                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 870                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
 871                 return -rte_errno;
 872         }
 873
 874         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
 875                         queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
 876         dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
 877
 878         return 0;
 879 }
 880
 881 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
 882 {
 883         PMD_INIT_FUNC_TRACE();
 884 }
 885
 886 static uint32_t
 887 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 888 {
 889         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 890         struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
 891         u32 frm_cnt = 0;
 892
 893         PMD_INIT_FUNC_TRACE();
 894
 895         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
 896                 DPAA_PMD_DEBUG("RX frame count for q(%d) is %u",
 897                                rx_queue_id, frm_cnt);
 898         }
 899         return frm_cnt;
 900 }
 901
 902 static int dpaa_link_down(struct rte_eth_dev *dev)
 903 {
 904         PMD_INIT_FUNC_TRACE();
 905
 906         dpaa_eth_dev_stop(dev);
 907         return 0;
 908 }
 909
 910 static int dpaa_link_up(struct rte_eth_dev *dev)
 911 {
 912         PMD_INIT_FUNC_TRACE();
 913
 914         dpaa_eth_dev_start(dev);
 915         return 0;
 916 }
 917
 918 static int
 919 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
 920                    struct rte_eth_fc_conf *fc_conf)
 921 {
 922         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 923         struct rte_eth_fc_conf *net_fc;
 924
 925         PMD_INIT_FUNC_TRACE();
 926
 927         if (!(dpaa_intf->fc_conf)) {
 928                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
 929                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
 930                 if (!dpaa_intf->fc_conf) {
 931                         DPAA_PMD_ERR("unable to save flow control info");
 932                         return -ENOMEM;
 933                 }
 934         }
 935         net_fc = dpaa_intf->fc_conf;
 936
 937         if (fc_conf->high_water < fc_conf->low_water) {
 938                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
 939                 return -EINVAL;
 940         }
 941
 942         if (fc_conf->mode == RTE_FC_NONE) {
 943                 return 0;
 944         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
 945                  fc_conf->mode == RTE_FC_FULL) {
 946                 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
 947                                          fc_conf->low_water,
 948                                 dpaa_intf->bp_info->bpid);
 949                 if (fc_conf->pause_time)
 950                         fman_if_set_fc_quanta(dpaa_intf->fif,
 951                                               fc_conf->pause_time);
 952         }
 953
 954         /* Save the information in dpaa device */
 955         net_fc->pause_time = fc_conf->pause_time;
 956         net_fc->high_water = fc_conf->high_water;
 957         net_fc->low_water = fc_conf->low_water;
 958         net_fc->send_xon = fc_conf->send_xon;
 959         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
 960         net_fc->mode = fc_conf->mode;
 961         net_fc->autoneg = fc_conf->autoneg;
 962
 963         return 0;
 964 }
 965
 966 static int
 967 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
 968                    struct rte_eth_fc_conf *fc_conf)
 969 {
 970         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 971         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
 972         int ret;
 973
 974         PMD_INIT_FUNC_TRACE();
 975
 976         if (net_fc) {
 977                 fc_conf->pause_time = net_fc->pause_time;
 978                 fc_conf->high_water = net_fc->high_water;
 979                 fc_conf->low_water = net_fc->low_water;
 980                 fc_conf->send_xon = net_fc->send_xon;
 981                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
 982                 fc_conf->mode = net_fc->mode;
 983                 fc_conf->autoneg = net_fc->autoneg;
 984                 return 0;
 985         }
 986         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
 987         if (ret) {
 988                 fc_conf->mode = RTE_FC_TX_PAUSE;
 989                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
 990         } else {
 991                 fc_conf->mode = RTE_FC_NONE;
 992         }
 993
 994         return 0;
 995 }
 996
 997 static int
 998 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
 999                              struct rte_ether_addr *addr,
1000                              uint32_t index,
1001                              __rte_unused uint32_t pool)
1002 {
1003         int ret;
1004         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1005
1006         PMD_INIT_FUNC_TRACE();
1007
1008         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
1009
1010         if (ret)
1011                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1012         return 0;
1013 }
1014
1015 static void
1016 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1017                           uint32_t index)
1018 {
1019         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1020
1021         PMD_INIT_FUNC_TRACE();
1022
1023         fman_if_clear_mac_addr(dpaa_intf->fif, index);
1024 }
1025
1026 static int
1027 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1028                        struct rte_ether_addr *addr)
1029 {
1030         int ret;
1031         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1032
1033         PMD_INIT_FUNC_TRACE();
1034
1035         ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
1036         if (ret)
1037                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1038
1039         return ret;
1040 }
1041
1042 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1043                                       uint16_t queue_id)
1044 {
1045         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1046         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1047
1048         if (!rxq->is_static)
1049                 return -EINVAL;
1050
1051         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1052 }
1053
1054 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1055                                        uint16_t queue_id)
1056 {
1057         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1058         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1059         uint32_t temp;
1060         ssize_t temp1;
1061
1062         if (!rxq->is_static)
1063                 return -EINVAL;
1064
1065         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1066
1067         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1068         if (temp1 != sizeof(temp))
1069                 DPAA_PMD_ERR("irq read error");
1070
1071         qman_fq_portal_thread_irq(rxq->qp);
1072
1073         return 0;
1074 }
1075
1076 static struct eth_dev_ops dpaa_devops = {
1077         .dev_configure            = dpaa_eth_dev_configure,
1078         .dev_start                = dpaa_eth_dev_start,
1079         .dev_stop                 = dpaa_eth_dev_stop,
1080         .dev_close                = dpaa_eth_dev_close,
1081         .dev_infos_get            = dpaa_eth_dev_info,
1082         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1083
1084         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1085         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1086         .rx_queue_release         = dpaa_eth_rx_queue_release,
1087         .tx_queue_release         = dpaa_eth_tx_queue_release,
1088         .rx_queue_count           = dpaa_dev_rx_queue_count,
1089
1090         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1091         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1092
1093         .link_update              = dpaa_eth_link_update,
1094         .stats_get                = dpaa_eth_stats_get,
1095         .xstats_get               = dpaa_dev_xstats_get,
1096         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1097         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1098         .xstats_get_names         = dpaa_xstats_get_names,
1099         .xstats_reset             = dpaa_eth_stats_reset,
1100         .stats_reset              = dpaa_eth_stats_reset,
1101         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1102         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1103         .allmulticast_enable      = dpaa_eth_multicast_enable,
1104         .allmulticast_disable     = dpaa_eth_multicast_disable,
1105         .mtu_set                  = dpaa_mtu_set,
1106         .dev_set_link_down        = dpaa_link_down,
1107         .dev_set_link_up          = dpaa_link_up,
1108         .mac_addr_add             = dpaa_dev_add_mac_addr,
1109         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1110         .mac_addr_set             = dpaa_dev_set_mac_addr,
1111
1112         .fw_version_get           = dpaa_fw_version_get,
1113
1114         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1115         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1116 };
1117
1118 static bool
1119 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1120 {
1121         if (strcmp(dev->device->driver->name,
1122                    drv->driver.name))
1123                 return false;
1124
1125         return true;
1126 }
1127
1128 static bool
1129 is_dpaa_supported(struct rte_eth_dev *dev)
1130 {
1131         return is_device_supported(dev, &rte_dpaa_pmd);
1132 }
1133
1134 int
1135 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1136 {
1137         struct rte_eth_dev *dev;
1138         struct dpaa_if *dpaa_intf;
1139
1140         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1141
1142         dev = &rte_eth_devices[port];
1143
1144         if (!is_dpaa_supported(dev))
1145                 return -ENOTSUP;
1146
1147         dpaa_intf = dev->data->dev_private;
1148
1149         if (on)
1150                 fman_if_loopback_enable(dpaa_intf->fif);
1151         else
1152                 fman_if_loopback_disable(dpaa_intf->fif);
1153
1154         return 0;
1155 }
1156
1157 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
1158 {
1159         struct rte_eth_fc_conf *fc_conf;
1160         int ret;
1161
1162         PMD_INIT_FUNC_TRACE();
1163
1164         if (!(dpaa_intf->fc_conf)) {
1165                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1166                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1167                 if (!dpaa_intf->fc_conf) {
1168                         DPAA_PMD_ERR("unable to save flow control info");
1169                         return -ENOMEM;
1170                 }
1171         }
1172         fc_conf = dpaa_intf->fc_conf;
1173         ret = fman_if_get_fc_threshold(dpaa_intf->fif);
1174         if (ret) {
1175                 fc_conf->mode = RTE_FC_TX_PAUSE;
1176                 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1177         } else {
1178                 fc_conf->mode = RTE_FC_NONE;
1179         }
1180
1181         return 0;
1182 }
1183
1184 /* Initialise an Rx FQ */
1185 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1186                               uint32_t fqid)
1187 {
1188         struct qm_mcc_initfq opts = {0};
1189         int ret;
1190         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1191         struct qm_mcc_initcgr cgr_opts = {
1192                 .we_mask = QM_CGR_WE_CS_THRES |
1193                                 QM_CGR_WE_CSTD_EN |
1194                                 QM_CGR_WE_MODE,
1195                 .cgr = {
1196                         .cstd_en = QM_CGR_EN,
1197                         .mode = QMAN_CGR_MODE_FRAME
1198                 }
1199         };
1200
1201         if (fqid) {
1202                 ret = qman_reserve_fqid(fqid);
1203                 if (ret) {
1204                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1205                                      fqid, ret);
1206                         return -EINVAL;
1207                 }
1208         } else {
1209                 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1210         }
1211         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1212         ret = qman_create_fq(fqid, flags, fq);
1213         if (ret) {
1214                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1215                         fqid, ret);
1216                 return ret;
1217         }
1218         fq->is_static = false;
1219
1220         dpaa_poll_queue_default_config(&opts);
1221
1222         if (cgr_rx) {
1223                 /* Enable tail drop with cgr on this queue */
1224                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1225                 cgr_rx->cb = NULL;
1226                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1227                                       &cgr_opts);
1228                 if (ret) {
1229                         DPAA_PMD_WARN(
1230                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1231                                 fq->fqid, ret);
1232                         goto without_cgr;
1233                 }
1234                 opts.we_mask |= QM_INITFQ_WE_CGID;
1235                 opts.fqd.cgid = cgr_rx->cgrid;
1236                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1237         }
1238 without_cgr:
1239         ret = qman_init_fq(fq, 0, &opts);
1240         if (ret)
1241                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1242         return ret;
1243 }
1244
1245 /* Initialise a Tx FQ */
1246 static int dpaa_tx_queue_init(struct qman_fq *fq,
1247                               struct fman_if *fman_intf,
1248                               struct qman_cgr *cgr_tx)
1249 {
1250         struct qm_mcc_initfq opts = {0};
1251         struct qm_mcc_initcgr cgr_opts = {
1252                 .we_mask = QM_CGR_WE_CS_THRES |
1253                                 QM_CGR_WE_CSTD_EN |
1254                                 QM_CGR_WE_MODE,
1255                 .cgr = {
1256                         .cstd_en = QM_CGR_EN,
1257                         .mode = QMAN_CGR_MODE_FRAME
1258                 }
1259         };
1260         int ret;
1261
1262         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1263                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1264         if (ret) {
1265                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1266                 return ret;
1267         }
1268         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1269                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1270         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1271         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1272         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1273         opts.fqd.context_b = 0;
1274         /* no tx-confirmation */
1275         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1276         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1277         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1278
1279         if (cgr_tx) {
1280                 /* Enable tail drop with cgr on this queue */
1281                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1282                                       td_tx_threshold, 0);
1283                 cgr_tx->cb = NULL;
1284                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1285                                       &cgr_opts);
1286                 if (ret) {
1287                         DPAA_PMD_WARN(
1288                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1289                                 fq->fqid, ret);
1290                         goto without_cgr;
1291                 }
1292                 opts.we_mask |= QM_INITFQ_WE_CGID;
1293                 opts.fqd.cgid = cgr_tx->cgrid;
1294                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1295                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1296                                 td_tx_threshold);
1297         }
1298 without_cgr:
1299         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1300         if (ret)
1301                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1302         return ret;
1303 }
1304
1305 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1306 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1307 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1308 {
1309         struct qm_mcc_initfq opts = {0};
1310         int ret;
1311
1312         PMD_INIT_FUNC_TRACE();
1313
1314         ret = qman_reserve_fqid(fqid);
1315         if (ret) {
1316                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1317                         fqid, ret);
1318                 return -EINVAL;
1319         }
1320         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1321         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1322         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1323         if (ret) {
1324                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1325                         fqid, ret);
1326                 return ret;
1327         }
1328         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1329         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1330         ret = qman_init_fq(fq, 0, &opts);
1331         if (ret)
1332                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1333                             fqid, ret);
1334         return ret;
1335 }
1336 #endif
1337
1338 /* Initialise a network interface */
1339 static int
1340 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1341 {
1342         int num_rx_fqs, fqid;
1343         int loop, ret = 0;
1344         int dev_id;
1345         struct rte_dpaa_device *dpaa_device;
1346         struct dpaa_if *dpaa_intf;
1347         struct fm_eth_port_cfg *cfg;
1348         struct fman_if *fman_intf;
1349         struct fman_if_bpool *bp, *tmp_bp;
1350         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1351         uint32_t cgrid_tx[MAX_DPAA_CORES];
1352         char eth_buf[RTE_ETHER_ADDR_FMT_SIZE];
1353
1354         PMD_INIT_FUNC_TRACE();
1355
1356         dpaa_intf = eth_dev->data->dev_private;
1357         /* For secondary processes, the primary has done all the work */
1358         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1359                 eth_dev->dev_ops = &dpaa_devops;
1360                 /* Plugging of UCODE burst API not supported in Secondary */
1361                 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1362                 if (dpaa_intf->cgr_tx)
1363                         eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1364                 else
1365                         eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1366 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1367                 qman_set_fq_lookup_table(
1368                                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1369 #endif
1370                 return 0;
1371         }
1372
1373         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1374         dev_id = dpaa_device->id.dev_id;
1375         dpaa_intf = eth_dev->data->dev_private;
1376         cfg = dpaa_get_eth_port_cfg(dev_id);
1377         fman_intf = cfg->fman_if;
1378
1379         dpaa_intf->name = dpaa_device->name;
1380
1381         /* save fman_if & cfg in the interface struture */
1382         dpaa_intf->fif = fman_intf;
1383         dpaa_intf->ifid = dev_id;
1384         dpaa_intf->cfg = cfg;
1385
1386         /* Initialize Rx FQ's */
1387         if (default_q) {
1388                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1389         } else {
1390                 if (getenv("DPAA_NUM_RX_QUEUES"))
1391                         num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1392                 else
1393                         num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1394         }
1395
1396
1397         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1398          * queues.
1399          */
1400         if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1401                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1402                 return -EINVAL;
1403         }
1404
1405         dpaa_intf->rx_queues = rte_zmalloc(NULL,
1406                 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1407         if (!dpaa_intf->rx_queues) {
1408                 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1409                 return -ENOMEM;
1410         }
1411
1412         memset(cgrid, 0, sizeof(cgrid));
1413         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1414
1415         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1416          * Tx tail drop is disabled.
1417          */
1418         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1419                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1420                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1421                                td_tx_threshold);
1422                 /* if a very large value is being configured */
1423                 if (td_tx_threshold > UINT16_MAX)
1424                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1425         }
1426
1427         /* If congestion control is enabled globally*/
1428         if (td_threshold) {
1429                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1430                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1431                 if (!dpaa_intf->cgr_rx) {
1432                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1433                         ret = -ENOMEM;
1434                         goto free_rx;
1435                 }
1436
1437                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1438                 if (ret != num_rx_fqs) {
1439                         DPAA_PMD_WARN("insufficient CGRIDs available");
1440                         ret = -EINVAL;
1441                         goto free_rx;
1442                 }
1443         } else {
1444                 dpaa_intf->cgr_rx = NULL;
1445         }
1446
1447         for (loop = 0; loop < num_rx_fqs; loop++) {
1448                 if (default_q)
1449                         fqid = cfg->rx_def;
1450                 else
1451                         fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx *
1452                                 DPAA_PCD_FQID_MULTIPLIER + loop;
1453
1454                 if (dpaa_intf->cgr_rx)
1455                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1456
1457                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1458                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1459                         fqid);
1460                 if (ret)
1461                         goto free_rx;
1462                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1463         }
1464         dpaa_intf->nb_rx_queues = num_rx_fqs;
1465
1466         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1467         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1468                 MAX_DPAA_CORES, MAX_CACHELINE);
1469         if (!dpaa_intf->tx_queues) {
1470                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1471                 ret = -ENOMEM;
1472                 goto free_rx;
1473         }
1474
1475         /* If congestion control is enabled globally*/
1476         if (td_tx_threshold) {
1477                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1478                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1479                         MAX_CACHELINE);
1480                 if (!dpaa_intf->cgr_tx) {
1481                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1482                         ret = -ENOMEM;
1483                         goto free_rx;
1484                 }
1485
1486                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1487                                              1, 0);
1488                 if (ret != MAX_DPAA_CORES) {
1489                         DPAA_PMD_WARN("insufficient CGRIDs available");
1490                         ret = -EINVAL;
1491                         goto free_rx;
1492                 }
1493         } else {
1494                 dpaa_intf->cgr_tx = NULL;
1495         }
1496
1497
1498         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
1499                 if (dpaa_intf->cgr_tx)
1500                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
1501
1502                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1503                         fman_intf,
1504                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
1505                 if (ret)
1506                         goto free_tx;
1507                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1508         }
1509         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
1510
1511 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1512         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1513                 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1514         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1515         dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1516                 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1517         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1518 #endif
1519
1520         DPAA_PMD_DEBUG("All frame queues created");
1521
1522         /* Get the initial configuration for flow control */
1523         dpaa_fc_set_default(dpaa_intf);
1524
1525         /* reset bpool list, initialize bpool dynamically */
1526         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1527                 list_del(&bp->node);
1528                 rte_free(bp);
1529         }
1530
1531         /* Populate ethdev structure */
1532         eth_dev->dev_ops = &dpaa_devops;
1533         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1534         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1535
1536         /* Allocate memory for storing MAC addresses */
1537         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1538                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1539         if (eth_dev->data->mac_addrs == NULL) {
1540                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1541                                                 "store MAC addresses",
1542                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1543                 ret = -ENOMEM;
1544                 goto free_tx;
1545         }
1546
1547         /* copy the primary mac address */
1548         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
1549         rte_ether_format_addr(eth_buf, sizeof(eth_buf), &fman_intf->mac_addr);
1550
1551         DPAA_PMD_INFO("net: dpaa: %s: %s", dpaa_device->name, eth_buf);
1552
1553         /* Disable RX mode */
1554         fman_if_discard_rx_errors(fman_intf);
1555         fman_if_disable_rx(fman_intf);
1556         /* Disable promiscuous mode */
1557         fman_if_promiscuous_disable(fman_intf);
1558         /* Disable multicast */
1559         fman_if_reset_mcast_filter_table(fman_intf);
1560         /* Reset interface statistics */
1561         fman_if_stats_reset(fman_intf);
1562         /* Disable SG by default */
1563         fman_if_set_sg(fman_intf, 0);
1564         fman_if_set_maxfrm(fman_intf, RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
1565
1566         return 0;
1567
1568 free_tx:
1569         rte_free(dpaa_intf->tx_queues);
1570         dpaa_intf->tx_queues = NULL;
1571         dpaa_intf->nb_tx_queues = 0;
1572
1573 free_rx:
1574         rte_free(dpaa_intf->cgr_rx);
1575         rte_free(dpaa_intf->cgr_tx);
1576         rte_free(dpaa_intf->rx_queues);
1577         dpaa_intf->rx_queues = NULL;
1578         dpaa_intf->nb_rx_queues = 0;
1579         return ret;
1580 }
1581
1582 static int
1583 dpaa_dev_uninit(struct rte_eth_dev *dev)
1584 {
1585         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1586         int loop;
1587
1588         PMD_INIT_FUNC_TRACE();
1589
1590         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1591                 return -EPERM;
1592
1593         if (!dpaa_intf) {
1594                 DPAA_PMD_WARN("Already closed or not started");
1595                 return -1;
1596         }
1597
1598         dpaa_eth_dev_close(dev);
1599
1600         /* release configuration memory */
1601         if (dpaa_intf->fc_conf)
1602                 rte_free(dpaa_intf->fc_conf);
1603
1604         /* Release RX congestion Groups */
1605         if (dpaa_intf->cgr_rx) {
1606                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1607                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1608
1609                 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1610                                          dpaa_intf->nb_rx_queues);
1611         }
1612
1613         rte_free(dpaa_intf->cgr_rx);
1614         dpaa_intf->cgr_rx = NULL;
1615
1616         /* Release TX congestion Groups */
1617         if (dpaa_intf->cgr_tx) {
1618                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
1619                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
1620
1621                 qman_release_cgrid_range(dpaa_intf->cgr_tx[loop].cgrid,
1622                                          MAX_DPAA_CORES);
1623                 rte_free(dpaa_intf->cgr_tx);
1624                 dpaa_intf->cgr_tx = NULL;
1625         }
1626
1627         rte_free(dpaa_intf->rx_queues);
1628         dpaa_intf->rx_queues = NULL;
1629
1630         rte_free(dpaa_intf->tx_queues);
1631         dpaa_intf->tx_queues = NULL;
1632
1633         dev->dev_ops = NULL;
1634         dev->rx_pkt_burst = NULL;
1635         dev->tx_pkt_burst = NULL;
1636
1637         return 0;
1638 }
1639
1640 static int
1641 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1642                struct rte_dpaa_device *dpaa_dev)
1643 {
1644         int diag;
1645         int ret;
1646         struct rte_eth_dev *eth_dev;
1647
1648         PMD_INIT_FUNC_TRACE();
1649
1650         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
1651                 RTE_PKTMBUF_HEADROOM) {
1652                 DPAA_PMD_ERR(
1653                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
1654                 RTE_PKTMBUF_HEADROOM,
1655                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
1656
1657                 return -1;
1658         }
1659
1660         /* In case of secondary process, the device is already configured
1661          * and no further action is required, except portal initialization
1662          * and verifying secondary attachment to port name.
1663          */
1664         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1665                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1666                 if (!eth_dev)
1667                         return -ENOMEM;
1668                 eth_dev->device = &dpaa_dev->device;
1669                 eth_dev->dev_ops = &dpaa_devops;
1670                 rte_eth_dev_probing_finish(eth_dev);
1671                 return 0;
1672         }
1673
1674         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
1675                 if (access("/tmp/fmc.bin", F_OK) == -1) {
1676                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
1677                         default_q = 1;
1678                 }
1679
1680                 /* disabling the default push mode for LS1043 */
1681                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1682                         dpaa_push_mode_max_queue = 0;
1683
1684                 /* if push mode queues to be enabled. Currenly we are allowing
1685                  * only one queue per thread.
1686                  */
1687                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1688                         dpaa_push_mode_max_queue =
1689                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1690                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1691                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1692                 }
1693
1694                 is_global_init = 1;
1695         }
1696
1697         if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1698                 ret = rte_dpaa_portal_init((void *)1);
1699                 if (ret) {
1700                         DPAA_PMD_ERR("Unable to initialize portal");
1701                         return ret;
1702                 }
1703         }
1704
1705         /* In case of secondary process, the device is already configured
1706          * and no further action is required, except portal initialization
1707          * and verifying secondary attachment to port name.
1708          */
1709         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1710                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1711                 if (!eth_dev)
1712                         return -ENOMEM;
1713         } else {
1714                 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1715                 if (eth_dev == NULL)
1716                         return -ENOMEM;
1717
1718                 eth_dev->data->dev_private = rte_zmalloc(
1719                                                 "ethdev private structure",
1720                                                 sizeof(struct dpaa_if),
1721                                                 RTE_CACHE_LINE_SIZE);
1722                 if (!eth_dev->data->dev_private) {
1723                         DPAA_PMD_ERR("Cannot allocate memzone for port data");
1724                         rte_eth_dev_release_port(eth_dev);
1725                         return -ENOMEM;
1726                 }
1727         }
1728         eth_dev->device = &dpaa_dev->device;
1729         dpaa_dev->eth_dev = eth_dev;
1730
1731         qman_ern_register_cb(dpaa_free_mbuf);
1732
1733         /* Invoke PMD device initialization function */
1734         diag = dpaa_dev_init(eth_dev);
1735         if (diag == 0) {
1736                 rte_eth_dev_probing_finish(eth_dev);
1737                 return 0;
1738         }
1739
1740         rte_eth_dev_release_port(eth_dev);
1741         return diag;
1742 }
1743
1744 static int
1745 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1746 {
1747         struct rte_eth_dev *eth_dev;
1748
1749         PMD_INIT_FUNC_TRACE();
1750
1751         eth_dev = dpaa_dev->eth_dev;
1752         dpaa_dev_uninit(eth_dev);
1753
1754         rte_eth_dev_release_port(eth_dev);
1755
1756         return 0;
1757 }
1758
1759 static struct rte_dpaa_driver rte_dpaa_pmd = {
1760         .drv_type = FSL_DPAA_ETH,
1761         .probe = rte_dpaa_probe,
1762         .remove = rte_dpaa_remove,
1763 };
1764
1765 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
1766 RTE_LOG_REGISTER(dpaa_logtype_pmd, pmd.net.dpaa, NOTICE);