1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
15 #include <sys/types.h>
16 #include <sys/syscall.h>
18 #include <rte_byteorder.h>
19 #include <rte_common.h>
20 #include <rte_interrupts.h>
22 #include <rte_debug.h>
24 #include <rte_atomic.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_memory.h>
27 #include <rte_tailq.h>
29 #include <rte_alarm.h>
30 #include <rte_ether.h>
31 #include <rte_ethdev_driver.h>
32 #include <rte_malloc.h>
35 #include <rte_dpaa_bus.h>
36 #include <rte_dpaa_logs.h>
37 #include <dpaa_mempool.h>
39 #include <dpaa_ethdev.h>
40 #include <dpaa_rxtx.h>
41 #include <rte_pmd_dpaa.h>
48 /* Supported Rx offloads */
49 static uint64_t dev_rx_offloads_sup =
50 DEV_RX_OFFLOAD_JUMBO_FRAME |
51 DEV_RX_OFFLOAD_SCATTER;
53 /* Rx offloads which cannot be disabled */
54 static uint64_t dev_rx_offloads_nodis =
55 DEV_RX_OFFLOAD_IPV4_CKSUM |
56 DEV_RX_OFFLOAD_UDP_CKSUM |
57 DEV_RX_OFFLOAD_TCP_CKSUM |
58 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM;
60 /* Supported Tx offloads */
61 static uint64_t dev_tx_offloads_sup;
63 /* Tx offloads which cannot be disabled */
64 static uint64_t dev_tx_offloads_nodis =
65 DEV_TX_OFFLOAD_IPV4_CKSUM |
66 DEV_TX_OFFLOAD_UDP_CKSUM |
67 DEV_TX_OFFLOAD_TCP_CKSUM |
68 DEV_TX_OFFLOAD_SCTP_CKSUM |
69 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
70 DEV_TX_OFFLOAD_MULTI_SEGS |
71 DEV_TX_OFFLOAD_MT_LOCKFREE |
72 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
74 /* Keep track of whether QMAN and BMAN have been globally initialized */
75 static int is_global_init;
76 static int default_q; /* use default queue - FMC is not executed*/
77 /* At present we only allow up to 4 push mode queues as default - as each of
78 * this queue need dedicated portal and we are short of portals.
80 #define DPAA_MAX_PUSH_MODE_QUEUE 8
81 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4
83 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
84 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
87 /* Per FQ Taildrop in frame count */
88 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
90 struct rte_dpaa_xstats_name_off {
91 char name[RTE_ETH_XSTATS_NAME_SIZE];
95 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
97 offsetof(struct dpaa_if_stats, raln)},
99 offsetof(struct dpaa_if_stats, rxpf)},
101 offsetof(struct dpaa_if_stats, rfcs)},
103 offsetof(struct dpaa_if_stats, rvlan)},
105 offsetof(struct dpaa_if_stats, rerr)},
107 offsetof(struct dpaa_if_stats, rdrp)},
109 offsetof(struct dpaa_if_stats, rund)},
111 offsetof(struct dpaa_if_stats, rovr)},
113 offsetof(struct dpaa_if_stats, rfrg)},
115 offsetof(struct dpaa_if_stats, txpf)},
117 offsetof(struct dpaa_if_stats, terr)},
119 offsetof(struct dpaa_if_stats, tvlan)},
121 offsetof(struct dpaa_if_stats, tund)},
124 static struct rte_dpaa_driver rte_dpaa_pmd;
127 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
130 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
132 memset(opts, 0, sizeof(struct qm_mcc_initfq));
133 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
134 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
135 QM_FQCTRL_PREFERINCACHE;
136 opts->fqd.context_a.stashing.exclusive = 0;
137 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
138 opts->fqd.context_a.stashing.annotation_cl =
139 DPAA_IF_RX_ANNOTATION_STASH;
140 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
141 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
145 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
147 struct dpaa_if *dpaa_intf = dev->data->dev_private;
148 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
150 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
152 PMD_INIT_FUNC_TRACE();
154 if (mtu < ETHER_MIN_MTU || frame_size > DPAA_MAX_RX_PKT_LEN)
157 * Refuse mtu that requires the support of scattered packets
158 * when this feature has not been enabled before.
160 if (dev->data->min_rx_buf_size &&
161 !dev->data->scattered_rx && frame_size > buffsz) {
162 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
166 /* check <seg size> * <max_seg> >= max_frame */
167 if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
168 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
169 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
170 buffsz * DPAA_SGT_MAX_ENTRIES);
174 if (frame_size > ETHER_MAX_LEN)
175 dev->data->dev_conf.rxmode.offloads &=
176 DEV_RX_OFFLOAD_JUMBO_FRAME;
178 dev->data->dev_conf.rxmode.offloads &=
179 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
181 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
183 fman_if_set_maxfrm(dpaa_intf->fif, frame_size);
189 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
191 struct dpaa_if *dpaa_intf = dev->data->dev_private;
192 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
193 uint64_t rx_offloads = eth_conf->rxmode.offloads;
194 uint64_t tx_offloads = eth_conf->txmode.offloads;
196 PMD_INIT_FUNC_TRACE();
198 /* Rx offloads validation */
199 if (dev_rx_offloads_nodis & ~rx_offloads) {
201 "Rx offloads non configurable - requested 0x%" PRIx64
202 " ignored 0x%" PRIx64,
203 rx_offloads, dev_rx_offloads_nodis);
206 /* Tx offloads validation */
207 if (dev_tx_offloads_nodis & ~tx_offloads) {
209 "Tx offloads non configurable - requested 0x%" PRIx64
210 " ignored 0x%" PRIx64,
211 tx_offloads, dev_tx_offloads_nodis);
214 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
217 DPAA_PMD_DEBUG("enabling jumbo");
219 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
221 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
223 DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
225 dev->data->dev_conf.rxmode.max_rx_pkt_len,
226 DPAA_MAX_RX_PKT_LEN);
227 max_len = DPAA_MAX_RX_PKT_LEN;
230 fman_if_set_maxfrm(dpaa_intf->fif, max_len);
231 dev->data->mtu = max_len
232 - ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE;
235 if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
236 DPAA_PMD_DEBUG("enabling scatter mode");
237 fman_if_set_sg(dpaa_intf->fif, 1);
238 dev->data->scattered_rx = 1;
244 static const uint32_t *
245 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
247 static const uint32_t ptypes[] = {
248 /*todo -= add more types */
251 RTE_PTYPE_L3_IPV4_EXT,
253 RTE_PTYPE_L3_IPV6_EXT,
259 PMD_INIT_FUNC_TRACE();
261 if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
266 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
268 struct dpaa_if *dpaa_intf = dev->data->dev_private;
270 PMD_INIT_FUNC_TRACE();
272 /* Change tx callback to the real one */
273 dev->tx_pkt_burst = dpaa_eth_queue_tx;
274 fman_if_enable_rx(dpaa_intf->fif);
279 static void dpaa_eth_dev_stop(struct rte_eth_dev *dev)
281 struct dpaa_if *dpaa_intf = dev->data->dev_private;
283 PMD_INIT_FUNC_TRACE();
285 fman_if_disable_rx(dpaa_intf->fif);
286 dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
289 static void dpaa_eth_dev_close(struct rte_eth_dev *dev)
291 PMD_INIT_FUNC_TRACE();
293 dpaa_eth_dev_stop(dev);
297 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
302 FILE *svr_file = NULL;
303 unsigned int svr_ver = 0;
305 PMD_INIT_FUNC_TRACE();
307 svr_file = fopen(DPAA_SOC_ID_FILE, "r");
309 DPAA_PMD_ERR("Unable to open SoC device");
310 return -ENOTSUP; /* Not supported on this infra */
312 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
313 dpaa_svr_family = svr_ver & SVR_MASK;
315 DPAA_PMD_ERR("Unable to read SoC device");
319 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
320 svr_ver, fman_ip_rev);
321 ret += 1; /* add the size of '\0' */
323 if (fw_size < (uint32_t)ret)
329 static void dpaa_eth_dev_info(struct rte_eth_dev *dev,
330 struct rte_eth_dev_info *dev_info)
332 struct dpaa_if *dpaa_intf = dev->data->dev_private;
334 PMD_INIT_FUNC_TRACE();
336 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
337 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
338 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
339 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
340 dev_info->max_hash_mac_addrs = 0;
341 dev_info->max_vfs = 0;
342 dev_info->max_vmdq_pools = ETH_16_POOLS;
343 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
344 dev_info->speed_capa = (ETH_LINK_SPEED_1G |
346 dev_info->rx_offload_capa = dev_rx_offloads_sup |
347 dev_rx_offloads_nodis;
348 dev_info->tx_offload_capa = dev_tx_offloads_sup |
349 dev_tx_offloads_nodis;
350 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
351 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
354 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
355 int wait_to_complete __rte_unused)
357 struct dpaa_if *dpaa_intf = dev->data->dev_private;
358 struct rte_eth_link *link = &dev->data->dev_link;
360 PMD_INIT_FUNC_TRACE();
362 if (dpaa_intf->fif->mac_type == fman_mac_1g)
363 link->link_speed = ETH_SPEED_NUM_1G;
364 else if (dpaa_intf->fif->mac_type == fman_mac_10g)
365 link->link_speed = ETH_SPEED_NUM_10G;
367 DPAA_PMD_ERR("invalid link_speed: %s, %d",
368 dpaa_intf->name, dpaa_intf->fif->mac_type);
370 link->link_status = dpaa_intf->valid;
371 link->link_duplex = ETH_LINK_FULL_DUPLEX;
372 link->link_autoneg = ETH_LINK_AUTONEG;
376 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
377 struct rte_eth_stats *stats)
379 struct dpaa_if *dpaa_intf = dev->data->dev_private;
381 PMD_INIT_FUNC_TRACE();
383 fman_if_stats_get(dpaa_intf->fif, stats);
387 static void dpaa_eth_stats_reset(struct rte_eth_dev *dev)
389 struct dpaa_if *dpaa_intf = dev->data->dev_private;
391 PMD_INIT_FUNC_TRACE();
393 fman_if_stats_reset(dpaa_intf->fif);
397 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
400 struct dpaa_if *dpaa_intf = dev->data->dev_private;
401 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
402 uint64_t values[sizeof(struct dpaa_if_stats) / 8];
410 fman_if_stats_get_all(dpaa_intf->fif, values,
411 sizeof(struct dpaa_if_stats) / 8);
413 for (i = 0; i < num; i++) {
415 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
421 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
422 struct rte_eth_xstat_name *xstats_names,
425 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
427 if (limit < stat_cnt)
430 if (xstats_names != NULL)
431 for (i = 0; i < stat_cnt; i++)
432 snprintf(xstats_names[i].name,
433 sizeof(xstats_names[i].name),
435 dpaa_xstats_strings[i].name);
441 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
442 uint64_t *values, unsigned int n)
444 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
445 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
448 struct dpaa_if *dpaa_intf = dev->data->dev_private;
456 fman_if_stats_get_all(dpaa_intf->fif, values_copy,
457 sizeof(struct dpaa_if_stats) / 8);
459 for (i = 0; i < stat_cnt; i++)
461 values_copy[dpaa_xstats_strings[i].offset / 8];
466 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
468 for (i = 0; i < n; i++) {
469 if (ids[i] >= stat_cnt) {
470 DPAA_PMD_ERR("id value isn't valid");
473 values[i] = values_copy[ids[i]];
479 dpaa_xstats_get_names_by_id(
480 struct rte_eth_dev *dev,
481 struct rte_eth_xstat_name *xstats_names,
485 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
486 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
489 return dpaa_xstats_get_names(dev, xstats_names, limit);
491 dpaa_xstats_get_names(dev, xstats_names_copy, limit);
493 for (i = 0; i < limit; i++) {
494 if (ids[i] >= stat_cnt) {
495 DPAA_PMD_ERR("id value isn't valid");
498 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
503 static void dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
505 struct dpaa_if *dpaa_intf = dev->data->dev_private;
507 PMD_INIT_FUNC_TRACE();
509 fman_if_promiscuous_enable(dpaa_intf->fif);
512 static void dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
514 struct dpaa_if *dpaa_intf = dev->data->dev_private;
516 PMD_INIT_FUNC_TRACE();
518 fman_if_promiscuous_disable(dpaa_intf->fif);
521 static void dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
523 struct dpaa_if *dpaa_intf = dev->data->dev_private;
525 PMD_INIT_FUNC_TRACE();
527 fman_if_set_mcast_filter_table(dpaa_intf->fif);
530 static void dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
532 struct dpaa_if *dpaa_intf = dev->data->dev_private;
534 PMD_INIT_FUNC_TRACE();
536 fman_if_reset_mcast_filter_table(dpaa_intf->fif);
540 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
542 unsigned int socket_id __rte_unused,
543 const struct rte_eth_rxconf *rx_conf __rte_unused,
544 struct rte_mempool *mp)
546 struct dpaa_if *dpaa_intf = dev->data->dev_private;
547 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
548 struct qm_mcc_initfq opts = {0};
551 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
553 PMD_INIT_FUNC_TRACE();
555 if (queue_idx >= dev->data->nb_rx_queues) {
556 rte_errno = EOVERFLOW;
557 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
558 (void *)dev, queue_idx, dev->data->nb_rx_queues);
562 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
563 queue_idx, rxq->fqid);
565 /* Max packet can fit in single buffer */
566 if (dev->data->dev_conf.rxmode.max_rx_pkt_len <= buffsz) {
568 } else if (dev->data->dev_conf.rxmode.offloads &
569 DEV_RX_OFFLOAD_SCATTER) {
570 if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
571 buffsz * DPAA_SGT_MAX_ENTRIES) {
572 DPAA_PMD_ERR("max RxPkt size %d too big to fit "
574 dev->data->dev_conf.rxmode.max_rx_pkt_len,
575 buffsz * DPAA_SGT_MAX_ENTRIES);
576 rte_errno = EOVERFLOW;
580 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
581 " larger than a single mbuf (%u) and scattered"
582 " mode has not been requested",
583 dev->data->dev_conf.rxmode.max_rx_pkt_len,
584 buffsz - RTE_PKTMBUF_HEADROOM);
587 if (!dpaa_intf->bp_info || dpaa_intf->bp_info->mp != mp) {
588 struct fman_if_ic_params icp;
592 if (!mp->pool_data) {
593 DPAA_PMD_ERR("Not an offloaded buffer pool!");
596 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
598 memset(&icp, 0, sizeof(icp));
599 /* set ICEOF for to the default value , which is 0*/
600 icp.iciof = DEFAULT_ICIOF;
601 icp.iceof = DEFAULT_RX_ICEOF;
602 icp.icsz = DEFAULT_ICSZ;
603 fman_if_set_ic_params(dpaa_intf->fif, &icp);
605 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
606 fman_if_set_fdoff(dpaa_intf->fif, fd_offset);
608 /* Buffer pool size should be equal to Dataroom Size*/
609 bp_size = rte_pktmbuf_data_room_size(mp);
610 fman_if_set_bp(dpaa_intf->fif, mp->size,
611 dpaa_intf->bp_info->bpid, bp_size);
612 dpaa_intf->valid = 1;
613 DPAA_PMD_INFO("if =%s - fd_offset = %d offset = %d",
614 dpaa_intf->name, fd_offset,
615 fman_if_get_fdoff(dpaa_intf->fif));
617 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
618 fman_if_get_sg_enable(dpaa_intf->fif),
619 dev->data->dev_conf.rxmode.max_rx_pkt_len);
620 /* checking if push mode only, no error check for now */
621 if (dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
622 dpaa_push_queue_idx++;
623 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
624 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
625 QM_FQCTRL_CTXASTASHING |
626 QM_FQCTRL_PREFERINCACHE;
627 opts.fqd.context_a.stashing.exclusive = 0;
628 /* In muticore scenario stashing becomes a bottleneck on LS1046.
629 * So do not enable stashing in this case
631 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
632 opts.fqd.context_a.stashing.annotation_cl =
633 DPAA_IF_RX_ANNOTATION_STASH;
634 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
635 opts.fqd.context_a.stashing.context_cl =
636 DPAA_IF_RX_CONTEXT_STASH;
638 /*Create a channel and associate given queue with the channel*/
639 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
640 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
641 opts.fqd.dest.channel = rxq->ch_id;
642 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
643 flags = QMAN_INITFQ_FLAG_SCHED;
645 /* Configure tail drop */
646 if (dpaa_intf->cgr_rx) {
647 opts.we_mask |= QM_INITFQ_WE_CGID;
648 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
649 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
651 ret = qman_init_fq(rxq, flags, &opts);
653 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
654 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
657 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
658 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
659 rxq->is_static = true;
661 dev->data->rx_queues[queue_idx] = rxq;
663 /* configure the CGR size as per the desc size */
664 if (dpaa_intf->cgr_rx) {
665 struct qm_mcc_initcgr cgr_opts = {0};
667 /* Enable tail drop with cgr on this queue */
668 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
669 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
672 "rx taildrop modify fail on fqid %d (ret=%d)",
681 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
684 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
688 struct dpaa_if *dpaa_intf = dev->data->dev_private;
689 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
690 struct qm_mcc_initfq opts = {0};
692 if (dpaa_push_mode_max_queue)
693 DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.\n"
694 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
695 dpaa_push_mode_max_queue);
697 dpaa_poll_queue_default_config(&opts);
699 switch (queue_conf->ev.sched_type) {
700 case RTE_SCHED_TYPE_ATOMIC:
701 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
702 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
703 * configuration with HOLD_ACTIVE setting
705 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
706 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
708 case RTE_SCHED_TYPE_ORDERED:
709 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
712 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
713 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
717 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
718 opts.fqd.dest.channel = ch_id;
719 opts.fqd.dest.wq = queue_conf->ev.priority;
721 if (dpaa_intf->cgr_rx) {
722 opts.we_mask |= QM_INITFQ_WE_CGID;
723 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
724 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
727 flags = QMAN_INITFQ_FLAG_SCHED;
729 ret = qman_init_fq(rxq, flags, &opts);
731 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
732 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
736 /* copy configuration which needs to be filled during dequeue */
737 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
738 dev->data->rx_queues[eth_rx_queue_id] = rxq;
744 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
747 struct qm_mcc_initfq opts;
750 struct dpaa_if *dpaa_intf = dev->data->dev_private;
751 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
753 dpaa_poll_queue_default_config(&opts);
755 if (dpaa_intf->cgr_rx) {
756 opts.we_mask |= QM_INITFQ_WE_CGID;
757 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
758 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
761 ret = qman_init_fq(rxq, flags, &opts);
763 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
767 rxq->cb.dqrr_dpdk_cb = NULL;
768 dev->data->rx_queues[eth_rx_queue_id] = NULL;
774 void dpaa_eth_rx_queue_release(void *rxq __rte_unused)
776 PMD_INIT_FUNC_TRACE();
780 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
781 uint16_t nb_desc __rte_unused,
782 unsigned int socket_id __rte_unused,
783 const struct rte_eth_txconf *tx_conf __rte_unused)
785 struct dpaa_if *dpaa_intf = dev->data->dev_private;
787 PMD_INIT_FUNC_TRACE();
789 if (queue_idx >= dev->data->nb_tx_queues) {
790 rte_errno = EOVERFLOW;
791 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
792 (void *)dev, queue_idx, dev->data->nb_tx_queues);
796 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
797 queue_idx, dpaa_intf->tx_queues[queue_idx].fqid);
798 dev->data->tx_queues[queue_idx] = &dpaa_intf->tx_queues[queue_idx];
802 static void dpaa_eth_tx_queue_release(void *txq __rte_unused)
804 PMD_INIT_FUNC_TRACE();
808 dpaa_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
810 struct dpaa_if *dpaa_intf = dev->data->dev_private;
811 struct qman_fq *rxq = &dpaa_intf->rx_queues[rx_queue_id];
814 PMD_INIT_FUNC_TRACE();
816 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
817 RTE_LOG(DEBUG, PMD, "RX frame count for q(%d) is %u\n",
818 rx_queue_id, frm_cnt);
823 static int dpaa_link_down(struct rte_eth_dev *dev)
825 PMD_INIT_FUNC_TRACE();
827 dpaa_eth_dev_stop(dev);
831 static int dpaa_link_up(struct rte_eth_dev *dev)
833 PMD_INIT_FUNC_TRACE();
835 dpaa_eth_dev_start(dev);
840 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
841 struct rte_eth_fc_conf *fc_conf)
843 struct dpaa_if *dpaa_intf = dev->data->dev_private;
844 struct rte_eth_fc_conf *net_fc;
846 PMD_INIT_FUNC_TRACE();
848 if (!(dpaa_intf->fc_conf)) {
849 dpaa_intf->fc_conf = rte_zmalloc(NULL,
850 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
851 if (!dpaa_intf->fc_conf) {
852 DPAA_PMD_ERR("unable to save flow control info");
856 net_fc = dpaa_intf->fc_conf;
858 if (fc_conf->high_water < fc_conf->low_water) {
859 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
863 if (fc_conf->mode == RTE_FC_NONE) {
865 } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
866 fc_conf->mode == RTE_FC_FULL) {
867 fman_if_set_fc_threshold(dpaa_intf->fif, fc_conf->high_water,
869 dpaa_intf->bp_info->bpid);
870 if (fc_conf->pause_time)
871 fman_if_set_fc_quanta(dpaa_intf->fif,
872 fc_conf->pause_time);
875 /* Save the information in dpaa device */
876 net_fc->pause_time = fc_conf->pause_time;
877 net_fc->high_water = fc_conf->high_water;
878 net_fc->low_water = fc_conf->low_water;
879 net_fc->send_xon = fc_conf->send_xon;
880 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
881 net_fc->mode = fc_conf->mode;
882 net_fc->autoneg = fc_conf->autoneg;
888 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
889 struct rte_eth_fc_conf *fc_conf)
891 struct dpaa_if *dpaa_intf = dev->data->dev_private;
892 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
895 PMD_INIT_FUNC_TRACE();
898 fc_conf->pause_time = net_fc->pause_time;
899 fc_conf->high_water = net_fc->high_water;
900 fc_conf->low_water = net_fc->low_water;
901 fc_conf->send_xon = net_fc->send_xon;
902 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
903 fc_conf->mode = net_fc->mode;
904 fc_conf->autoneg = net_fc->autoneg;
907 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
909 fc_conf->mode = RTE_FC_TX_PAUSE;
910 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
912 fc_conf->mode = RTE_FC_NONE;
919 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
920 struct ether_addr *addr,
922 __rte_unused uint32_t pool)
925 struct dpaa_if *dpaa_intf = dev->data->dev_private;
927 PMD_INIT_FUNC_TRACE();
929 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, index);
932 RTE_LOG(ERR, PMD, "error: Adding the MAC ADDR failed:"
938 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
941 struct dpaa_if *dpaa_intf = dev->data->dev_private;
943 PMD_INIT_FUNC_TRACE();
945 fman_if_clear_mac_addr(dpaa_intf->fif, index);
949 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
950 struct ether_addr *addr)
953 struct dpaa_if *dpaa_intf = dev->data->dev_private;
955 PMD_INIT_FUNC_TRACE();
957 ret = fman_if_add_mac_addr(dpaa_intf->fif, addr->addr_bytes, 0);
959 RTE_LOG(ERR, PMD, "error: Setting the MAC ADDR failed %d", ret);
964 static struct eth_dev_ops dpaa_devops = {
965 .dev_configure = dpaa_eth_dev_configure,
966 .dev_start = dpaa_eth_dev_start,
967 .dev_stop = dpaa_eth_dev_stop,
968 .dev_close = dpaa_eth_dev_close,
969 .dev_infos_get = dpaa_eth_dev_info,
970 .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
972 .rx_queue_setup = dpaa_eth_rx_queue_setup,
973 .tx_queue_setup = dpaa_eth_tx_queue_setup,
974 .rx_queue_release = dpaa_eth_rx_queue_release,
975 .tx_queue_release = dpaa_eth_tx_queue_release,
976 .rx_queue_count = dpaa_dev_rx_queue_count,
978 .flow_ctrl_get = dpaa_flow_ctrl_get,
979 .flow_ctrl_set = dpaa_flow_ctrl_set,
981 .link_update = dpaa_eth_link_update,
982 .stats_get = dpaa_eth_stats_get,
983 .xstats_get = dpaa_dev_xstats_get,
984 .xstats_get_by_id = dpaa_xstats_get_by_id,
985 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id,
986 .xstats_get_names = dpaa_xstats_get_names,
987 .xstats_reset = dpaa_eth_stats_reset,
988 .stats_reset = dpaa_eth_stats_reset,
989 .promiscuous_enable = dpaa_eth_promiscuous_enable,
990 .promiscuous_disable = dpaa_eth_promiscuous_disable,
991 .allmulticast_enable = dpaa_eth_multicast_enable,
992 .allmulticast_disable = dpaa_eth_multicast_disable,
993 .mtu_set = dpaa_mtu_set,
994 .dev_set_link_down = dpaa_link_down,
995 .dev_set_link_up = dpaa_link_up,
996 .mac_addr_add = dpaa_dev_add_mac_addr,
997 .mac_addr_remove = dpaa_dev_remove_mac_addr,
998 .mac_addr_set = dpaa_dev_set_mac_addr,
1000 .fw_version_get = dpaa_fw_version_get,
1004 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1006 if (strcmp(dev->device->driver->name,
1014 is_dpaa_supported(struct rte_eth_dev *dev)
1016 return is_device_supported(dev, &rte_dpaa_pmd);
1020 rte_pmd_dpaa_set_tx_loopback(uint8_t port, uint8_t on)
1022 struct rte_eth_dev *dev;
1023 struct dpaa_if *dpaa_intf;
1025 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1027 dev = &rte_eth_devices[port];
1029 if (!is_dpaa_supported(dev))
1032 dpaa_intf = dev->data->dev_private;
1035 fman_if_loopback_enable(dpaa_intf->fif);
1037 fman_if_loopback_disable(dpaa_intf->fif);
1042 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf)
1044 struct rte_eth_fc_conf *fc_conf;
1047 PMD_INIT_FUNC_TRACE();
1049 if (!(dpaa_intf->fc_conf)) {
1050 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1051 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1052 if (!dpaa_intf->fc_conf) {
1053 DPAA_PMD_ERR("unable to save flow control info");
1057 fc_conf = dpaa_intf->fc_conf;
1058 ret = fman_if_get_fc_threshold(dpaa_intf->fif);
1060 fc_conf->mode = RTE_FC_TX_PAUSE;
1061 fc_conf->pause_time = fman_if_get_fc_quanta(dpaa_intf->fif);
1063 fc_conf->mode = RTE_FC_NONE;
1069 /* Initialise an Rx FQ */
1070 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1073 struct qm_mcc_initfq opts = {0};
1075 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1076 struct qm_mcc_initcgr cgr_opts = {
1077 .we_mask = QM_CGR_WE_CS_THRES |
1081 .cstd_en = QM_CGR_EN,
1082 .mode = QMAN_CGR_MODE_FRAME
1086 PMD_INIT_FUNC_TRACE();
1089 ret = qman_reserve_fqid(fqid);
1091 DPAA_PMD_ERR("reserve rx fqid 0x%x failed with ret: %d",
1096 flags |= QMAN_FQ_FLAG_DYNAMIC_FQID;
1098 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1099 ret = qman_create_fq(fqid, flags, fq);
1101 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1105 fq->is_static = false;
1107 dpaa_poll_queue_default_config(&opts);
1110 /* Enable tail drop with cgr on this queue */
1111 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1113 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1117 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1121 opts.we_mask |= QM_INITFQ_WE_CGID;
1122 opts.fqd.cgid = cgr_rx->cgrid;
1123 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1126 ret = qman_init_fq(fq, 0, &opts);
1128 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1132 /* Initialise a Tx FQ */
1133 static int dpaa_tx_queue_init(struct qman_fq *fq,
1134 struct fman_if *fman_intf)
1136 struct qm_mcc_initfq opts = {0};
1139 PMD_INIT_FUNC_TRACE();
1141 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1142 QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1144 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1147 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1148 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1149 opts.fqd.dest.channel = fman_intf->tx_channel_id;
1150 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1151 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1152 opts.fqd.context_b = 0;
1153 /* no tx-confirmation */
1154 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1155 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1156 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1157 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1159 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1163 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1164 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1165 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1167 struct qm_mcc_initfq opts = {0};
1170 PMD_INIT_FUNC_TRACE();
1172 ret = qman_reserve_fqid(fqid);
1174 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1178 /* "map" this Rx FQ to one of the interfaces Tx FQID */
1179 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1180 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1182 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1186 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1187 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1188 ret = qman_init_fq(fq, 0, &opts);
1190 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1196 /* Initialise a network interface */
1198 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1200 int num_cores, num_rx_fqs, fqid;
1203 struct rte_dpaa_device *dpaa_device;
1204 struct dpaa_if *dpaa_intf;
1205 struct fm_eth_port_cfg *cfg;
1206 struct fman_if *fman_intf;
1207 struct fman_if_bpool *bp, *tmp_bp;
1208 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1210 PMD_INIT_FUNC_TRACE();
1212 /* For secondary processes, the primary has done all the work */
1213 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1216 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1217 dev_id = dpaa_device->id.dev_id;
1218 dpaa_intf = eth_dev->data->dev_private;
1219 cfg = &dpaa_netcfg->port_cfg[dev_id];
1220 fman_intf = cfg->fman_if;
1222 dpaa_intf->name = dpaa_device->name;
1224 /* save fman_if & cfg in the interface struture */
1225 dpaa_intf->fif = fman_intf;
1226 dpaa_intf->ifid = dev_id;
1227 dpaa_intf->cfg = cfg;
1229 /* Initialize Rx FQ's */
1231 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1233 if (getenv("DPAA_NUM_RX_QUEUES"))
1234 num_rx_fqs = atoi(getenv("DPAA_NUM_RX_QUEUES"));
1236 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1240 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1243 if (num_rx_fqs <= 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1244 DPAA_PMD_ERR("Invalid number of RX queues\n");
1248 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1249 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1250 if (!dpaa_intf->rx_queues) {
1251 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1255 /* If congestion control is enabled globally*/
1257 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1258 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1259 if (!dpaa_intf->cgr_rx) {
1260 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1265 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1266 if (ret != num_rx_fqs) {
1267 DPAA_PMD_WARN("insufficient CGRIDs available");
1272 dpaa_intf->cgr_rx = NULL;
1275 for (loop = 0; loop < num_rx_fqs; loop++) {
1279 fqid = DPAA_PCD_FQID_START + dpaa_intf->fif->mac_idx *
1280 DPAA_PCD_FQID_MULTIPLIER + loop;
1282 if (dpaa_intf->cgr_rx)
1283 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1285 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1286 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1290 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1292 dpaa_intf->nb_rx_queues = num_rx_fqs;
1294 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1295 num_cores = rte_lcore_count();
1296 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1297 num_cores, MAX_CACHELINE);
1298 if (!dpaa_intf->tx_queues) {
1299 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1304 for (loop = 0; loop < num_cores; loop++) {
1305 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
1309 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
1311 dpaa_intf->nb_tx_queues = num_cores;
1313 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1314 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1315 DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
1316 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
1317 dpaa_debug_queue_init(&dpaa_intf->debug_queues[
1318 DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
1319 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
1322 DPAA_PMD_DEBUG("All frame queues created");
1324 /* Get the initial configuration for flow control */
1325 dpaa_fc_set_default(dpaa_intf);
1327 /* reset bpool list, initialize bpool dynamically */
1328 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
1329 list_del(&bp->node);
1333 /* Populate ethdev structure */
1334 eth_dev->dev_ops = &dpaa_devops;
1335 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1336 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
1338 /* Allocate memory for storing MAC addresses */
1339 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
1340 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
1341 if (eth_dev->data->mac_addrs == NULL) {
1342 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
1343 "store MAC addresses",
1344 ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
1349 /* copy the primary mac address */
1350 ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]);
1352 RTE_LOG(INFO, PMD, "net: dpaa: %s: %02x:%02x:%02x:%02x:%02x:%02x\n",
1354 fman_intf->mac_addr.addr_bytes[0],
1355 fman_intf->mac_addr.addr_bytes[1],
1356 fman_intf->mac_addr.addr_bytes[2],
1357 fman_intf->mac_addr.addr_bytes[3],
1358 fman_intf->mac_addr.addr_bytes[4],
1359 fman_intf->mac_addr.addr_bytes[5]);
1361 /* Disable RX mode */
1362 fman_if_discard_rx_errors(fman_intf);
1363 fman_if_disable_rx(fman_intf);
1364 /* Disable promiscuous mode */
1365 fman_if_promiscuous_disable(fman_intf);
1366 /* Disable multicast */
1367 fman_if_reset_mcast_filter_table(fman_intf);
1368 /* Reset interface statistics */
1369 fman_if_stats_reset(fman_intf);
1370 /* Disable SG by default */
1371 fman_if_set_sg(fman_intf, 0);
1372 fman_if_set_maxfrm(fman_intf, ETHER_MAX_LEN + VLAN_TAG_SIZE);
1377 rte_free(dpaa_intf->tx_queues);
1378 dpaa_intf->tx_queues = NULL;
1379 dpaa_intf->nb_tx_queues = 0;
1382 rte_free(dpaa_intf->cgr_rx);
1383 rte_free(dpaa_intf->rx_queues);
1384 dpaa_intf->rx_queues = NULL;
1385 dpaa_intf->nb_rx_queues = 0;
1390 dpaa_dev_uninit(struct rte_eth_dev *dev)
1392 struct dpaa_if *dpaa_intf = dev->data->dev_private;
1395 PMD_INIT_FUNC_TRACE();
1397 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1401 DPAA_PMD_WARN("Already closed or not started");
1405 dpaa_eth_dev_close(dev);
1407 /* release configuration memory */
1408 if (dpaa_intf->fc_conf)
1409 rte_free(dpaa_intf->fc_conf);
1411 /* Release RX congestion Groups */
1412 if (dpaa_intf->cgr_rx) {
1413 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
1414 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
1416 qman_release_cgrid_range(dpaa_intf->cgr_rx[loop].cgrid,
1417 dpaa_intf->nb_rx_queues);
1420 rte_free(dpaa_intf->cgr_rx);
1421 dpaa_intf->cgr_rx = NULL;
1423 rte_free(dpaa_intf->rx_queues);
1424 dpaa_intf->rx_queues = NULL;
1426 rte_free(dpaa_intf->tx_queues);
1427 dpaa_intf->tx_queues = NULL;
1429 /* free memory for storing MAC addresses */
1430 rte_free(dev->data->mac_addrs);
1431 dev->data->mac_addrs = NULL;
1433 dev->dev_ops = NULL;
1434 dev->rx_pkt_burst = NULL;
1435 dev->tx_pkt_burst = NULL;
1441 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv __rte_unused,
1442 struct rte_dpaa_device *dpaa_dev)
1446 struct rte_eth_dev *eth_dev;
1448 PMD_INIT_FUNC_TRACE();
1450 /* In case of secondary process, the device is already configured
1451 * and no further action is required, except portal initialization
1452 * and verifying secondary attachment to port name.
1454 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1455 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
1458 eth_dev->device = &dpaa_dev->device;
1459 eth_dev->dev_ops = &dpaa_devops;
1460 rte_eth_dev_probing_finish(eth_dev);
1464 if (!is_global_init) {
1465 /* One time load of Qman/Bman drivers */
1466 ret = qman_global_init();
1468 DPAA_PMD_ERR("QMAN initialization failed: %d",
1472 ret = bman_global_init();
1474 DPAA_PMD_ERR("BMAN initialization failed: %d",
1479 if (access("/tmp/fmc.bin", F_OK) == -1) {
1481 "* FMC not configured.Enabling default mode\n");
1485 /* disabling the default push mode for LS1043 */
1486 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
1487 dpaa_push_mode_max_queue = 0;
1489 /* if push mode queues to be enabled. Currenly we are allowing
1490 * only one queue per thread.
1492 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
1493 dpaa_push_mode_max_queue =
1494 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
1495 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
1496 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
1502 if (unlikely(!RTE_PER_LCORE(dpaa_io))) {
1503 ret = rte_dpaa_portal_init((void *)1);
1505 DPAA_PMD_ERR("Unable to initialize portal");
1510 eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
1511 if (eth_dev == NULL)
1514 eth_dev->data->dev_private = rte_zmalloc(
1515 "ethdev private structure",
1516 sizeof(struct dpaa_if),
1517 RTE_CACHE_LINE_SIZE);
1518 if (!eth_dev->data->dev_private) {
1519 DPAA_PMD_ERR("Cannot allocate memzone for port data");
1520 rte_eth_dev_release_port(eth_dev);
1524 eth_dev->device = &dpaa_dev->device;
1525 dpaa_dev->eth_dev = eth_dev;
1527 /* Invoke PMD device initialization function */
1528 diag = dpaa_dev_init(eth_dev);
1530 rte_eth_dev_probing_finish(eth_dev);
1534 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1535 rte_free(eth_dev->data->dev_private);
1537 rte_eth_dev_release_port(eth_dev);
1542 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
1544 struct rte_eth_dev *eth_dev;
1546 PMD_INIT_FUNC_TRACE();
1548 eth_dev = dpaa_dev->eth_dev;
1549 dpaa_dev_uninit(eth_dev);
1551 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
1552 rte_free(eth_dev->data->dev_private);
1554 rte_eth_dev_release_port(eth_dev);
1559 static struct rte_dpaa_driver rte_dpaa_pmd = {
1560 .drv_type = FSL_DPAA_ETH,
1561 .probe = rte_dpaa_probe,
1562 .remove = rte_dpaa_remove,
1565 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);