drivers/net/dpaa/dpaa_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2017-2020 NXP
   5  *
   6  */
   7 /* System headers */
   8 #include <stdio.h>
   9 #include <inttypes.h>
  10 #include <unistd.h>
  11 #include <limits.h>
  12 #include <sched.h>
  13 #include <signal.h>
  14 #include <pthread.h>
  15 #include <sys/types.h>
  16 #include <sys/syscall.h>
  17
  18 #include <rte_string_fns.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_interrupts.h>
  22 #include <rte_log.h>
  23 #include <rte_debug.h>
  24 #include <rte_pci.h>
  25 #include <rte_atomic.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_memory.h>
  28 #include <rte_tailq.h>
  29 #include <rte_eal.h>
  30 #include <rte_alarm.h>
  31 #include <rte_ether.h>
  32 #include <ethdev_driver.h>
  33 #include <rte_malloc.h>
  34 #include <rte_ring.h>
  35
  36 #include <rte_dpaa_bus.h>
  37 #include <rte_dpaa_logs.h>
  38 #include <dpaa_mempool.h>
  39
  40 #include <dpaa_ethdev.h>
  41 #include <dpaa_rxtx.h>
  42 #include <dpaa_flow.h>
  43 #include <rte_pmd_dpaa.h>
  44
  45 #include <fsl_usd.h>
  46 #include <fsl_qman.h>
  47 #include <fsl_bman.h>
  48 #include <fsl_fman.h>
  49 #include <process.h>
  50 #include <fmlib/fm_ext.h>
  51
  52 #define CHECK_INTERVAL         100  /* 100ms */
  53 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
  54
  55 /* Supported Rx offloads */
  56 static uint64_t dev_rx_offloads_sup =
  57                 DEV_RX_OFFLOAD_JUMBO_FRAME |
  58                 DEV_RX_OFFLOAD_SCATTER;
  59
  60 /* Rx offloads which cannot be disabled */
  61 static uint64_t dev_rx_offloads_nodis =
  62                 DEV_RX_OFFLOAD_IPV4_CKSUM |
  63                 DEV_RX_OFFLOAD_UDP_CKSUM |
  64                 DEV_RX_OFFLOAD_TCP_CKSUM |
  65                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  66                 DEV_RX_OFFLOAD_RSS_HASH;
  67
  68 /* Supported Tx offloads */
  69 static uint64_t dev_tx_offloads_sup =
  70                 DEV_TX_OFFLOAD_MT_LOCKFREE |
  71                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
  72
  73 /* Tx offloads which cannot be disabled */
  74 static uint64_t dev_tx_offloads_nodis =
  75                 DEV_TX_OFFLOAD_IPV4_CKSUM |
  76                 DEV_TX_OFFLOAD_UDP_CKSUM |
  77                 DEV_TX_OFFLOAD_TCP_CKSUM |
  78                 DEV_TX_OFFLOAD_SCTP_CKSUM |
  79                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  80                 DEV_TX_OFFLOAD_MULTI_SEGS;
  81
  82 /* Keep track of whether QMAN and BMAN have been globally initialized */
  83 static int is_global_init;
  84 static int fmc_q = 1;   /* Indicates the use of static fmc for distribution */
  85 static int default_q;   /* use default queue - FMC is not executed*/
  86 /* At present we only allow up to 4 push mode queues as default - as each of
  87  * this queue need dedicated portal and we are short of portals.
  88  */
  89 #define DPAA_MAX_PUSH_MODE_QUEUE       8
  90 #define DPAA_DEFAULT_PUSH_MODE_QUEUE   4
  91
  92 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE;
  93 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/
  94
  95
  96 /* Per RX FQ Taildrop in frame count */
  97 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH;
  98
  99 /* Per TX FQ Taildrop in frame count, disabled by default */
 100 static unsigned int td_tx_threshold;
 101
 102 struct rte_dpaa_xstats_name_off {
 103         char name[RTE_ETH_XSTATS_NAME_SIZE];
 104         uint32_t offset;
 105 };
 106
 107 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = {
 108         {"rx_align_err",
 109                 offsetof(struct dpaa_if_stats, raln)},
 110         {"rx_valid_pause",
 111                 offsetof(struct dpaa_if_stats, rxpf)},
 112         {"rx_fcs_err",
 113                 offsetof(struct dpaa_if_stats, rfcs)},
 114         {"rx_vlan_frame",
 115                 offsetof(struct dpaa_if_stats, rvlan)},
 116         {"rx_frame_err",
 117                 offsetof(struct dpaa_if_stats, rerr)},
 118         {"rx_drop_err",
 119                 offsetof(struct dpaa_if_stats, rdrp)},
 120         {"rx_undersized",
 121                 offsetof(struct dpaa_if_stats, rund)},
 122         {"rx_oversize_err",
 123                 offsetof(struct dpaa_if_stats, rovr)},
 124         {"rx_fragment_pkt",
 125                 offsetof(struct dpaa_if_stats, rfrg)},
 126         {"tx_valid_pause",
 127                 offsetof(struct dpaa_if_stats, txpf)},
 128         {"tx_fcs_err",
 129                 offsetof(struct dpaa_if_stats, terr)},
 130         {"tx_vlan_frame",
 131                 offsetof(struct dpaa_if_stats, tvlan)},
 132         {"rx_undersized",
 133                 offsetof(struct dpaa_if_stats, tund)},
 134 };
 135
 136 static struct rte_dpaa_driver rte_dpaa_pmd;
 137
 138 static int
 139 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info);
 140
 141 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 142                                 int wait_to_complete __rte_unused);
 143
 144 static void dpaa_interrupt_handler(void *param);
 145
 146 static inline void
 147 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts)
 148 {
 149         memset(opts, 0, sizeof(struct qm_mcc_initfq));
 150         opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
 151         opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING |
 152                            QM_FQCTRL_PREFERINCACHE;
 153         opts->fqd.context_a.stashing.exclusive = 0;
 154         if (dpaa_svr_family != SVR_LS1046A_FAMILY)
 155                 opts->fqd.context_a.stashing.annotation_cl =
 156                                                 DPAA_IF_RX_ANNOTATION_STASH;
 157         opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
 158         opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH;
 159 }
 160
 161 static int
 162 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
 163 {
 164         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
 165                                 + VLAN_TAG_SIZE;
 166         uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 167
 168         PMD_INIT_FUNC_TRACE();
 169
 170         /*
 171          * Refuse mtu that requires the support of scattered packets
 172          * when this feature has not been enabled before.
 173          */
 174         if (dev->data->min_rx_buf_size &&
 175                 !dev->data->scattered_rx && frame_size > buffsz) {
 176                 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer");
 177                 return -EINVAL;
 178         }
 179
 180         /* check <seg size> * <max_seg>  >= max_frame */
 181         if (dev->data->min_rx_buf_size && dev->data->scattered_rx &&
 182                 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) {
 183                 DPAA_PMD_ERR("Too big to fit for Max SG list %d",
 184                                 buffsz * DPAA_SGT_MAX_ENTRIES);
 185                 return -EINVAL;
 186         }
 187
 188         fman_if_set_maxfrm(dev->process_private, frame_size);
 189
 190         return 0;
 191 }
 192
 193 static int
 194 dpaa_eth_dev_configure(struct rte_eth_dev *dev)
 195 {
 196         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 197         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 198         uint64_t tx_offloads = eth_conf->txmode.offloads;
 199         struct rte_device *rdev = dev->device;
 200         struct rte_eth_link *link = &dev->data->dev_link;
 201         struct rte_dpaa_device *dpaa_dev;
 202         struct fman_if *fif = dev->process_private;
 203         struct __fman_if *__fif;
 204         struct rte_intr_handle *intr_handle;
 205         uint32_t max_rx_pktlen;
 206         int speed, duplex;
 207         int ret;
 208
 209         PMD_INIT_FUNC_TRACE();
 210
 211         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 212         intr_handle = &dpaa_dev->intr_handle;
 213         __fif = container_of(fif, struct __fman_if, __if);
 214
 215         /* Rx offloads which are enabled by default */
 216         if (dev_rx_offloads_nodis & ~rx_offloads) {
 217                 DPAA_PMD_INFO(
 218                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 219                 " fixed are 0x%" PRIx64,
 220                 rx_offloads, dev_rx_offloads_nodis);
 221         }
 222
 223         /* Tx offloads which are enabled by default */
 224         if (dev_tx_offloads_nodis & ~tx_offloads) {
 225                 DPAA_PMD_INFO(
 226                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 227                 " fixed are 0x%" PRIx64,
 228                 tx_offloads, dev_tx_offloads_nodis);
 229         }
 230
 231         max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN +
 232                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
 233         if (max_rx_pktlen > DPAA_MAX_RX_PKT_LEN) {
 234                 DPAA_PMD_INFO("enabling jumbo override conf max len=%d "
 235                         "supported is %d",
 236                         max_rx_pktlen, DPAA_MAX_RX_PKT_LEN);
 237                 max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 238         }
 239
 240         fman_if_set_maxfrm(dev->process_private, max_rx_pktlen);
 241
 242         if (rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
 243                 DPAA_PMD_DEBUG("enabling scatter mode");
 244                 fman_if_set_sg(dev->process_private, 1);
 245                 dev->data->scattered_rx = 1;
 246         }
 247
 248         if (!(default_q || fmc_q)) {
 249                 if (dpaa_fm_config(dev,
 250                         eth_conf->rx_adv_conf.rss_conf.rss_hf)) {
 251                         dpaa_write_fm_config_to_file();
 252                         DPAA_PMD_ERR("FM port configuration: Failed\n");
 253                         return -1;
 254                 }
 255                 dpaa_write_fm_config_to_file();
 256         }
 257
 258         /* if the interrupts were configured on this devices*/
 259         if (intr_handle && intr_handle->fd) {
 260                 if (dev->data->dev_conf.intr_conf.lsc != 0)
 261                         rte_intr_callback_register(intr_handle,
 262                                            dpaa_interrupt_handler,
 263                                            (void *)dev);
 264
 265                 ret = dpaa_intr_enable(__fif->node_name, intr_handle->fd);
 266                 if (ret) {
 267                         if (dev->data->dev_conf.intr_conf.lsc != 0) {
 268                                 rte_intr_callback_unregister(intr_handle,
 269                                         dpaa_interrupt_handler,
 270                                         (void *)dev);
 271                                 if (ret == EINVAL)
 272                                         printf("Failed to enable interrupt: Not Supported\n");
 273                                 else
 274                                         printf("Failed to enable interrupt\n");
 275                         }
 276                         dev->data->dev_conf.intr_conf.lsc = 0;
 277                         dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC;
 278                 }
 279         }
 280
 281         /* Wait for link status to get updated */
 282         if (!link->link_status)
 283                 sleep(1);
 284
 285         /* Configure link only if link is UP*/
 286         if (link->link_status) {
 287                 if (eth_conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
 288                         /* Start autoneg only if link is not in autoneg mode */
 289                         if (!link->link_autoneg)
 290                                 dpaa_restart_link_autoneg(__fif->node_name);
 291                 } else if (eth_conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 292                         switch (eth_conf->link_speeds & ~ETH_LINK_SPEED_FIXED) {
 293                         case ETH_LINK_SPEED_10M_HD:
 294                                 speed = ETH_SPEED_NUM_10M;
 295                                 duplex = ETH_LINK_HALF_DUPLEX;
 296                                 break;
 297                         case ETH_LINK_SPEED_10M:
 298                                 speed = ETH_SPEED_NUM_10M;
 299                                 duplex = ETH_LINK_FULL_DUPLEX;
 300                                 break;
 301                         case ETH_LINK_SPEED_100M_HD:
 302                                 speed = ETH_SPEED_NUM_100M;
 303                                 duplex = ETH_LINK_HALF_DUPLEX;
 304                                 break;
 305                         case ETH_LINK_SPEED_100M:
 306                                 speed = ETH_SPEED_NUM_100M;
 307                                 duplex = ETH_LINK_FULL_DUPLEX;
 308                                 break;
 309                         case ETH_LINK_SPEED_1G:
 310                                 speed = ETH_SPEED_NUM_1G;
 311                                 duplex = ETH_LINK_FULL_DUPLEX;
 312                                 break;
 313                         case ETH_LINK_SPEED_2_5G:
 314                                 speed = ETH_SPEED_NUM_2_5G;
 315                                 duplex = ETH_LINK_FULL_DUPLEX;
 316                                 break;
 317                         case ETH_LINK_SPEED_10G:
 318                                 speed = ETH_SPEED_NUM_10G;
 319                                 duplex = ETH_LINK_FULL_DUPLEX;
 320                                 break;
 321                         default:
 322                                 speed = ETH_SPEED_NUM_NONE;
 323                                 duplex = ETH_LINK_FULL_DUPLEX;
 324                                 break;
 325                         }
 326                         /* Set link speed */
 327                         dpaa_update_link_speed(__fif->node_name, speed, duplex);
 328                 } else {
 329                         /* Manual autoneg - custom advertisement speed. */
 330                         printf("Custom Advertisement speeds not supported\n");
 331                 }
 332         }
 333
 334         return 0;
 335 }
 336
 337 static const uint32_t *
 338 dpaa_supported_ptypes_get(struct rte_eth_dev *dev)
 339 {
 340         static const uint32_t ptypes[] = {
 341                 RTE_PTYPE_L2_ETHER,
 342                 RTE_PTYPE_L2_ETHER_VLAN,
 343                 RTE_PTYPE_L2_ETHER_ARP,
 344                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 345                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 346                 RTE_PTYPE_L4_ICMP,
 347                 RTE_PTYPE_L4_TCP,
 348                 RTE_PTYPE_L4_UDP,
 349                 RTE_PTYPE_L4_FRAG,
 350                 RTE_PTYPE_L4_TCP,
 351                 RTE_PTYPE_L4_UDP,
 352                 RTE_PTYPE_L4_SCTP
 353         };
 354
 355         PMD_INIT_FUNC_TRACE();
 356
 357         if (dev->rx_pkt_burst == dpaa_eth_queue_rx)
 358                 return ptypes;
 359         return NULL;
 360 }
 361
 362 static void dpaa_interrupt_handler(void *param)
 363 {
 364         struct rte_eth_dev *dev = param;
 365         struct rte_device *rdev = dev->device;
 366         struct rte_dpaa_device *dpaa_dev;
 367         struct rte_intr_handle *intr_handle;
 368         uint64_t buf;
 369         int bytes_read;
 370
 371         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 372         intr_handle = &dpaa_dev->intr_handle;
 373
 374         bytes_read = read(intr_handle->fd, &buf, sizeof(uint64_t));
 375         if (bytes_read < 0)
 376                 DPAA_PMD_ERR("Error reading eventfd\n");
 377         dpaa_eth_link_update(dev, 0);
 378         rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 379 }
 380
 381 static int dpaa_eth_dev_start(struct rte_eth_dev *dev)
 382 {
 383         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 384
 385         PMD_INIT_FUNC_TRACE();
 386
 387         if (!(default_q || fmc_q))
 388                 dpaa_write_fm_config_to_file();
 389
 390         /* Change tx callback to the real one */
 391         if (dpaa_intf->cgr_tx)
 392                 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
 393         else
 394                 dev->tx_pkt_burst = dpaa_eth_queue_tx;
 395
 396         fman_if_enable_rx(dev->process_private);
 397
 398         return 0;
 399 }
 400
 401 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev)
 402 {
 403         struct fman_if *fif = dev->process_private;
 404
 405         PMD_INIT_FUNC_TRACE();
 406         dev->data->dev_started = 0;
 407
 408         if (!fif->is_shared_mac)
 409                 fman_if_disable_rx(fif);
 410         dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
 411
 412         return 0;
 413 }
 414
 415 static int dpaa_eth_dev_close(struct rte_eth_dev *dev)
 416 {
 417         struct fman_if *fif = dev->process_private;
 418         struct __fman_if *__fif;
 419         struct rte_device *rdev = dev->device;
 420         struct rte_dpaa_device *dpaa_dev;
 421         struct rte_intr_handle *intr_handle;
 422         struct rte_eth_link *link = &dev->data->dev_link;
 423         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 424         int loop;
 425         int ret;
 426
 427         PMD_INIT_FUNC_TRACE();
 428
 429         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 430                 return 0;
 431
 432         if (!dpaa_intf) {
 433                 DPAA_PMD_WARN("Already closed or not started");
 434                 return -1;
 435         }
 436
 437         /* DPAA FM deconfig */
 438         if (!(default_q || fmc_q)) {
 439                 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private))
 440                         DPAA_PMD_WARN("DPAA FM deconfig failed\n");
 441         }
 442
 443         dpaa_dev = container_of(rdev, struct rte_dpaa_device, device);
 444         intr_handle = &dpaa_dev->intr_handle;
 445         __fif = container_of(fif, struct __fman_if, __if);
 446
 447         ret = dpaa_eth_dev_stop(dev);
 448
 449         /* Reset link to autoneg */
 450         if (link->link_status && !link->link_autoneg)
 451                 dpaa_restart_link_autoneg(__fif->node_name);
 452
 453         if (intr_handle && intr_handle->fd &&
 454             dev->data->dev_conf.intr_conf.lsc != 0) {
 455                 dpaa_intr_disable(__fif->node_name);
 456                 rte_intr_callback_unregister(intr_handle,
 457                                              dpaa_interrupt_handler,
 458                                              (void *)dev);
 459         }
 460
 461         /* release configuration memory */
 462         if (dpaa_intf->fc_conf)
 463                 rte_free(dpaa_intf->fc_conf);
 464
 465         /* Release RX congestion Groups */
 466         if (dpaa_intf->cgr_rx) {
 467                 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++)
 468                         qman_delete_cgr(&dpaa_intf->cgr_rx[loop]);
 469         }
 470
 471         rte_free(dpaa_intf->cgr_rx);
 472         dpaa_intf->cgr_rx = NULL;
 473         /* Release TX congestion Groups */
 474         if (dpaa_intf->cgr_tx) {
 475                 for (loop = 0; loop < MAX_DPAA_CORES; loop++)
 476                         qman_delete_cgr(&dpaa_intf->cgr_tx[loop]);
 477                 rte_free(dpaa_intf->cgr_tx);
 478                 dpaa_intf->cgr_tx = NULL;
 479         }
 480
 481         rte_free(dpaa_intf->rx_queues);
 482         dpaa_intf->rx_queues = NULL;
 483
 484         rte_free(dpaa_intf->tx_queues);
 485         dpaa_intf->tx_queues = NULL;
 486
 487         return ret;
 488 }
 489
 490 static int
 491 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused,
 492                      char *fw_version,
 493                      size_t fw_size)
 494 {
 495         int ret;
 496         FILE *svr_file = NULL;
 497         unsigned int svr_ver = 0;
 498
 499         PMD_INIT_FUNC_TRACE();
 500
 501         svr_file = fopen(DPAA_SOC_ID_FILE, "r");
 502         if (!svr_file) {
 503                 DPAA_PMD_ERR("Unable to open SoC device");
 504                 return -ENOTSUP; /* Not supported on this infra */
 505         }
 506         if (fscanf(svr_file, "svr:%x", &svr_ver) > 0)
 507                 dpaa_svr_family = svr_ver & SVR_MASK;
 508         else
 509                 DPAA_PMD_ERR("Unable to read SoC device");
 510
 511         fclose(svr_file);
 512
 513         ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x",
 514                        svr_ver, fman_ip_rev);
 515         if (ret < 0)
 516                 return -EINVAL;
 517
 518         ret += 1; /* add the size of '\0' */
 519         if (fw_size < (size_t)ret)
 520                 return ret;
 521         else
 522                 return 0;
 523 }
 524
 525 static int dpaa_eth_dev_info(struct rte_eth_dev *dev,
 526                              struct rte_eth_dev_info *dev_info)
 527 {
 528         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 529         struct fman_if *fif = dev->process_private;
 530
 531         DPAA_PMD_DEBUG(": %s", dpaa_intf->name);
 532
 533         dev_info->max_rx_queues = dpaa_intf->nb_rx_queues;
 534         dev_info->max_tx_queues = dpaa_intf->nb_tx_queues;
 535         dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN;
 536         dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER;
 537         dev_info->max_hash_mac_addrs = 0;
 538         dev_info->max_vfs = 0;
 539         dev_info->max_vmdq_pools = ETH_16_POOLS;
 540         dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL;
 541
 542         if (fif->mac_type == fman_mac_1g) {
 543                 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
 544                                         | ETH_LINK_SPEED_10M
 545                                         | ETH_LINK_SPEED_100M_HD
 546                                         | ETH_LINK_SPEED_100M
 547                                         | ETH_LINK_SPEED_1G;
 548         } else if (fif->mac_type == fman_mac_2_5g) {
 549                 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
 550                                         | ETH_LINK_SPEED_10M
 551                                         | ETH_LINK_SPEED_100M_HD
 552                                         | ETH_LINK_SPEED_100M
 553                                         | ETH_LINK_SPEED_1G
 554                                         | ETH_LINK_SPEED_2_5G;
 555         } else if (fif->mac_type == fman_mac_10g) {
 556                 dev_info->speed_capa = ETH_LINK_SPEED_10M_HD
 557                                         | ETH_LINK_SPEED_10M
 558                                         | ETH_LINK_SPEED_100M_HD
 559                                         | ETH_LINK_SPEED_100M
 560                                         | ETH_LINK_SPEED_1G
 561                                         | ETH_LINK_SPEED_2_5G
 562                                         | ETH_LINK_SPEED_10G;
 563         } else {
 564                 DPAA_PMD_ERR("invalid link_speed: %s, %d",
 565                              dpaa_intf->name, fif->mac_type);
 566                 return -EINVAL;
 567         }
 568
 569         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 570                                         dev_rx_offloads_nodis;
 571         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 572                                         dev_tx_offloads_nodis;
 573         dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE;
 574         dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE;
 575         dev_info->default_rxportconf.nb_queues = 1;
 576         dev_info->default_txportconf.nb_queues = 1;
 577         dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH;
 578         dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH;
 579
 580         return 0;
 581 }
 582
 583 static int
 584 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 585                         __rte_unused uint16_t queue_id,
 586                         struct rte_eth_burst_mode *mode)
 587 {
 588         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 589         int ret = -EINVAL;
 590         unsigned int i;
 591         const struct burst_info {
 592                 uint64_t flags;
 593                 const char *output;
 594         } rx_offload_map[] = {
 595                         {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
 596                         {DEV_RX_OFFLOAD_SCATTER, " Scattered,"},
 597                         {DEV_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 598                         {DEV_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 599                         {DEV_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 600                         {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 601                         {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}
 602         };
 603
 604         /* Update Rx offload info */
 605         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 606                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 607                         snprintf(mode->info, sizeof(mode->info), "%s",
 608                                 rx_offload_map[i].output);
 609                         ret = 0;
 610                         break;
 611                 }
 612         }
 613         return ret;
 614 }
 615
 616 static int
 617 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 618                         __rte_unused uint16_t queue_id,
 619                         struct rte_eth_burst_mode *mode)
 620 {
 621         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 622         int ret = -EINVAL;
 623         unsigned int i;
 624         const struct burst_info {
 625                 uint64_t flags;
 626                 const char *output;
 627         } tx_offload_map[] = {
 628                         {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 629                         {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 630                         {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 631                         {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 632                         {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 633                         {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 634                         {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 635                         {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 636         };
 637
 638         /* Update Tx offload info */
 639         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 640                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 641                         snprintf(mode->info, sizeof(mode->info), "%s",
 642                                 tx_offload_map[i].output);
 643                         ret = 0;
 644                         break;
 645                 }
 646         }
 647         return ret;
 648 }
 649
 650 static int dpaa_eth_link_update(struct rte_eth_dev *dev,
 651                                 int wait_to_complete)
 652 {
 653         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 654         struct rte_eth_link *link = &dev->data->dev_link;
 655         struct fman_if *fif = dev->process_private;
 656         struct __fman_if *__fif = container_of(fif, struct __fman_if, __if);
 657         int ret, ioctl_version;
 658         uint8_t count;
 659
 660         PMD_INIT_FUNC_TRACE();
 661
 662         ioctl_version = dpaa_get_ioctl_version_number();
 663
 664         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) {
 665                 for (count = 0; count <= MAX_REPEAT_TIME; count++) {
 666                         ret = dpaa_get_link_status(__fif->node_name, link);
 667                         if (ret)
 668                                 return ret;
 669                         if (link->link_status == ETH_LINK_DOWN &&
 670                             wait_to_complete)
 671                                 rte_delay_ms(CHECK_INTERVAL);
 672                         else
 673                                 break;
 674                 }
 675         } else {
 676                 link->link_status = dpaa_intf->valid;
 677         }
 678
 679         if (ioctl_version < 2) {
 680                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
 681                 link->link_autoneg = ETH_LINK_AUTONEG;
 682
 683                 if (fif->mac_type == fman_mac_1g)
 684                         link->link_speed = ETH_SPEED_NUM_1G;
 685                 else if (fif->mac_type == fman_mac_2_5g)
 686                         link->link_speed = ETH_SPEED_NUM_2_5G;
 687                 else if (fif->mac_type == fman_mac_10g)
 688                         link->link_speed = ETH_SPEED_NUM_10G;
 689                 else
 690                         DPAA_PMD_ERR("invalid link_speed: %s, %d",
 691                                      dpaa_intf->name, fif->mac_type);
 692         }
 693
 694         DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
 695                       link->link_status ? "Up" : "Down");
 696         return 0;
 697 }
 698
 699 static int dpaa_eth_stats_get(struct rte_eth_dev *dev,
 700                                struct rte_eth_stats *stats)
 701 {
 702         PMD_INIT_FUNC_TRACE();
 703
 704         fman_if_stats_get(dev->process_private, stats);
 705         return 0;
 706 }
 707
 708 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev)
 709 {
 710         PMD_INIT_FUNC_TRACE();
 711
 712         fman_if_stats_reset(dev->process_private);
 713
 714         return 0;
 715 }
 716
 717 static int
 718 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 719                     unsigned int n)
 720 {
 721         unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings);
 722         uint64_t values[sizeof(struct dpaa_if_stats) / 8];
 723
 724         if (n < num)
 725                 return num;
 726
 727         if (xstats == NULL)
 728                 return 0;
 729
 730         fman_if_stats_get_all(dev->process_private, values,
 731                               sizeof(struct dpaa_if_stats) / 8);
 732
 733         for (i = 0; i < num; i++) {
 734                 xstats[i].id = i;
 735                 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8];
 736         }
 737         return i;
 738 }
 739
 740 static int
 741 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 742                       struct rte_eth_xstat_name *xstats_names,
 743                       unsigned int limit)
 744 {
 745         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 746
 747         if (limit < stat_cnt)
 748                 return stat_cnt;
 749
 750         if (xstats_names != NULL)
 751                 for (i = 0; i < stat_cnt; i++)
 752                         strlcpy(xstats_names[i].name,
 753                                 dpaa_xstats_strings[i].name,
 754                                 sizeof(xstats_names[i].name));
 755
 756         return stat_cnt;
 757 }
 758
 759 static int
 760 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
 761                       uint64_t *values, unsigned int n)
 762 {
 763         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 764         uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8];
 765
 766         if (!ids) {
 767                 if (n < stat_cnt)
 768                         return stat_cnt;
 769
 770                 if (!values)
 771                         return 0;
 772
 773                 fman_if_stats_get_all(dev->process_private, values_copy,
 774                                       sizeof(struct dpaa_if_stats) / 8);
 775
 776                 for (i = 0; i < stat_cnt; i++)
 777                         values[i] =
 778                                 values_copy[dpaa_xstats_strings[i].offset / 8];
 779
 780                 return stat_cnt;
 781         }
 782
 783         dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
 784
 785         for (i = 0; i < n; i++) {
 786                 if (ids[i] >= stat_cnt) {
 787                         DPAA_PMD_ERR("id value isn't valid");
 788                         return -1;
 789                 }
 790                 values[i] = values_copy[ids[i]];
 791         }
 792         return n;
 793 }
 794
 795 static int
 796 dpaa_xstats_get_names_by_id(
 797         struct rte_eth_dev *dev,
 798         const uint64_t *ids,
 799         struct rte_eth_xstat_name *xstats_names,
 800         unsigned int limit)
 801 {
 802         unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings);
 803         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
 804
 805         if (!ids)
 806                 return dpaa_xstats_get_names(dev, xstats_names, limit);
 807
 808         dpaa_xstats_get_names(dev, xstats_names_copy, limit);
 809
 810         for (i = 0; i < limit; i++) {
 811                 if (ids[i] >= stat_cnt) {
 812                         DPAA_PMD_ERR("id value isn't valid");
 813                         return -1;
 814                 }
 815                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
 816         }
 817         return limit;
 818 }
 819
 820 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev)
 821 {
 822         PMD_INIT_FUNC_TRACE();
 823
 824         fman_if_promiscuous_enable(dev->process_private);
 825
 826         return 0;
 827 }
 828
 829 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev)
 830 {
 831         PMD_INIT_FUNC_TRACE();
 832
 833         fman_if_promiscuous_disable(dev->process_private);
 834
 835         return 0;
 836 }
 837
 838 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev)
 839 {
 840         PMD_INIT_FUNC_TRACE();
 841
 842         fman_if_set_mcast_filter_table(dev->process_private);
 843
 844         return 0;
 845 }
 846
 847 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev)
 848 {
 849         PMD_INIT_FUNC_TRACE();
 850
 851         fman_if_reset_mcast_filter_table(dev->process_private);
 852
 853         return 0;
 854 }
 855
 856 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev)
 857 {
 858         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 859         struct fman_if_ic_params icp;
 860         uint32_t fd_offset;
 861         uint32_t bp_size;
 862
 863         memset(&icp, 0, sizeof(icp));
 864         /* set ICEOF for to the default value , which is 0*/
 865         icp.iciof = DEFAULT_ICIOF;
 866         icp.iceof = DEFAULT_RX_ICEOF;
 867         icp.icsz = DEFAULT_ICSZ;
 868         fman_if_set_ic_params(dev->process_private, &icp);
 869
 870         fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE;
 871         fman_if_set_fdoff(dev->process_private, fd_offset);
 872
 873         /* Buffer pool size should be equal to Dataroom Size*/
 874         bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp);
 875
 876         fman_if_set_bp(dev->process_private,
 877                        dpaa_intf->bp_info->mp->size,
 878                        dpaa_intf->bp_info->bpid, bp_size);
 879 }
 880
 881 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev,
 882                                              int8_t vsp_id, uint32_t bpid)
 883 {
 884         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 885         struct fman_if *fif = dev->process_private;
 886
 887         if (fif->num_profiles) {
 888                 if (vsp_id < 0)
 889                         vsp_id = fif->base_profile_id;
 890         } else {
 891                 if (vsp_id < 0)
 892                         vsp_id = 0;
 893         }
 894
 895         if (dpaa_intf->vsp_bpid[vsp_id] &&
 896                 bpid != dpaa_intf->vsp_bpid[vsp_id]) {
 897                 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP");
 898
 899                 return -1;
 900         }
 901
 902         return 0;
 903 }
 904
 905 static
 906 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 907                             uint16_t nb_desc,
 908                             unsigned int socket_id __rte_unused,
 909                             const struct rte_eth_rxconf *rx_conf,
 910                             struct rte_mempool *mp)
 911 {
 912         struct dpaa_if *dpaa_intf = dev->data->dev_private;
 913         struct fman_if *fif = dev->process_private;
 914         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx];
 915         struct qm_mcc_initfq opts = {0};
 916         u32 flags = 0;
 917         int ret;
 918         u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 919         uint32_t max_rx_pktlen;
 920
 921         PMD_INIT_FUNC_TRACE();
 922
 923         if (queue_idx >= dev->data->nb_rx_queues) {
 924                 rte_errno = EOVERFLOW;
 925                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
 926                       (void *)dev, queue_idx, dev->data->nb_rx_queues);
 927                 return -rte_errno;
 928         }
 929
 930         /* Rx deferred start is not supported */
 931         if (rx_conf->rx_deferred_start) {
 932                 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev);
 933                 return -EINVAL;
 934         }
 935         rxq->nb_desc = UINT16_MAX;
 936         rxq->offloads = rx_conf->offloads;
 937
 938         DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)",
 939                         queue_idx, rxq->fqid);
 940
 941         if (!fif->num_profiles) {
 942                 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
 943                         dpaa_intf->bp_info->mp != mp) {
 944                         DPAA_PMD_WARN("Multiple pools on same interface not"
 945                                       " supported");
 946                         return -EINVAL;
 947                 }
 948         } else {
 949                 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id,
 950                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) {
 951                         return -EINVAL;
 952                 }
 953         }
 954
 955         if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp &&
 956             dpaa_intf->bp_info->mp != mp) {
 957                 DPAA_PMD_WARN("Multiple pools on same interface not supported");
 958                 return -EINVAL;
 959         }
 960
 961         max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
 962                 VLAN_TAG_SIZE;
 963         /* Max packet can fit in single buffer */
 964         if (max_rx_pktlen <= buffsz) {
 965                 ;
 966         } else if (dev->data->dev_conf.rxmode.offloads &
 967                         DEV_RX_OFFLOAD_SCATTER) {
 968                 if (max_rx_pktlen > buffsz * DPAA_SGT_MAX_ENTRIES) {
 969                         DPAA_PMD_ERR("Maximum Rx packet size %d too big to fit "
 970                                 "MaxSGlist %d",
 971                                 max_rx_pktlen, buffsz * DPAA_SGT_MAX_ENTRIES);
 972                         rte_errno = EOVERFLOW;
 973                         return -rte_errno;
 974                 }
 975         } else {
 976                 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is"
 977                      " larger than a single mbuf (%u) and scattered"
 978                      " mode has not been requested",
 979                      max_rx_pktlen, buffsz - RTE_PKTMBUF_HEADROOM);
 980         }
 981
 982         dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp);
 983
 984         /* For shared interface, it's done in kernel, skip.*/
 985         if (!fif->is_shared_mac)
 986                 dpaa_fman_if_pool_setup(dev);
 987
 988         if (fif->num_profiles) {
 989                 int8_t vsp_id = rxq->vsp_id;
 990
 991                 if (vsp_id >= 0) {
 992                         ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id,
 993                                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid,
 994                                         fif);
 995                         if (ret) {
 996                                 DPAA_PMD_ERR("dpaa_port_vsp_update failed");
 997                                 return ret;
 998                         }
 999                 } else {
1000                         DPAA_PMD_INFO("Base profile is associated to"
1001                                 " RXQ fqid:%d\r\n", rxq->fqid);
1002                         if (fif->is_shared_mac) {
1003                                 DPAA_PMD_ERR("Fatal: Base profile is associated"
1004                                              " to shared interface on DPDK.");
1005                                 return -EINVAL;
1006                         }
1007                         dpaa_intf->vsp_bpid[fif->base_profile_id] =
1008                                 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1009                 }
1010         } else {
1011                 dpaa_intf->vsp_bpid[0] =
1012                         DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid;
1013         }
1014
1015         dpaa_intf->valid = 1;
1016         DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name,
1017                 fman_if_get_sg_enable(fif), max_rx_pktlen);
1018         /* checking if push mode only, no error check for now */
1019         if (!rxq->is_static &&
1020             dpaa_push_mode_max_queue > dpaa_push_queue_idx) {
1021                 struct qman_portal *qp;
1022                 int q_fd;
1023
1024                 dpaa_push_queue_idx++;
1025                 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA;
1026                 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK |
1027                                    QM_FQCTRL_CTXASTASHING |
1028                                    QM_FQCTRL_PREFERINCACHE;
1029                 opts.fqd.context_a.stashing.exclusive = 0;
1030                 /* In muticore scenario stashing becomes a bottleneck on LS1046.
1031                  * So do not enable stashing in this case
1032                  */
1033                 if (dpaa_svr_family != SVR_LS1046A_FAMILY)
1034                         opts.fqd.context_a.stashing.annotation_cl =
1035                                                 DPAA_IF_RX_ANNOTATION_STASH;
1036                 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH;
1037                 opts.fqd.context_a.stashing.context_cl =
1038                                                 DPAA_IF_RX_CONTEXT_STASH;
1039
1040                 /*Create a channel and associate given queue with the channel*/
1041                 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0);
1042                 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1043                 opts.fqd.dest.channel = rxq->ch_id;
1044                 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY;
1045                 flags = QMAN_INITFQ_FLAG_SCHED;
1046
1047                 /* Configure tail drop */
1048                 if (dpaa_intf->cgr_rx) {
1049                         opts.we_mask |= QM_INITFQ_WE_CGID;
1050                         opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid;
1051                         opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1052                 }
1053                 ret = qman_init_fq(rxq, flags, &opts);
1054                 if (ret) {
1055                         DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x "
1056                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1057                         return ret;
1058                 }
1059                 if (dpaa_svr_family == SVR_LS1043A_FAMILY) {
1060                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch;
1061                 } else {
1062                         rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb;
1063                         rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare;
1064                 }
1065
1066                 rxq->is_static = true;
1067
1068                 /* Allocate qman specific portals */
1069                 qp = fsl_qman_fq_portal_create(&q_fd);
1070                 if (!qp) {
1071                         DPAA_PMD_ERR("Unable to alloc fq portal");
1072                         return -1;
1073                 }
1074                 rxq->qp = qp;
1075
1076                 /* Set up the device interrupt handler */
1077                 if (!dev->intr_handle) {
1078                         struct rte_dpaa_device *dpaa_dev;
1079                         struct rte_device *rdev = dev->device;
1080
1081                         dpaa_dev = container_of(rdev, struct rte_dpaa_device,
1082                                                 device);
1083                         dev->intr_handle = &dpaa_dev->intr_handle;
1084                         dev->intr_handle->intr_vec = rte_zmalloc(NULL,
1085                                         dpaa_push_mode_max_queue, 0);
1086                         if (!dev->intr_handle->intr_vec) {
1087                                 DPAA_PMD_ERR("intr_vec alloc failed");
1088                                 return -ENOMEM;
1089                         }
1090                         dev->intr_handle->nb_efd = dpaa_push_mode_max_queue;
1091                         dev->intr_handle->max_intr = dpaa_push_mode_max_queue;
1092                 }
1093
1094                 dev->intr_handle->type = RTE_INTR_HANDLE_EXT;
1095                 dev->intr_handle->intr_vec[queue_idx] = queue_idx + 1;
1096                 dev->intr_handle->efds[queue_idx] = q_fd;
1097                 rxq->q_fd = q_fd;
1098         }
1099         rxq->bp_array = rte_dpaa_bpid_info;
1100         dev->data->rx_queues[queue_idx] = rxq;
1101
1102         /* configure the CGR size as per the desc size */
1103         if (dpaa_intf->cgr_rx) {
1104                 struct qm_mcc_initcgr cgr_opts = {0};
1105
1106                 rxq->nb_desc = nb_desc;
1107                 /* Enable tail drop with cgr on this queue */
1108                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0);
1109                 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts);
1110                 if (ret) {
1111                         DPAA_PMD_WARN(
1112                                 "rx taildrop modify fail on fqid %d (ret=%d)",
1113                                 rxq->fqid, ret);
1114                 }
1115         }
1116         /* Enable main queue to receive error packets also by default */
1117         fman_if_set_err_fqid(fif, rxq->fqid);
1118         return 0;
1119 }
1120
1121 int
1122 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev,
1123                 int eth_rx_queue_id,
1124                 u16 ch_id,
1125                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
1126 {
1127         int ret;
1128         u32 flags = 0;
1129         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1130         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1131         struct qm_mcc_initfq opts = {0};
1132
1133         if (dpaa_push_mode_max_queue)
1134                 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n"
1135                               "PUSH mode already enabled for first %d queues.\n"
1136                               "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n",
1137                               dpaa_push_mode_max_queue);
1138
1139         dpaa_poll_queue_default_config(&opts);
1140
1141         switch (queue_conf->ev.sched_type) {
1142         case RTE_SCHED_TYPE_ATOMIC:
1143                 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE;
1144                 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary
1145                  * configuration with HOLD_ACTIVE setting
1146                  */
1147                 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK);
1148                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic;
1149                 break;
1150         case RTE_SCHED_TYPE_ORDERED:
1151                 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n");
1152                 return -1;
1153         default:
1154                 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK;
1155                 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel;
1156                 break;
1157         }
1158
1159         opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ;
1160         opts.fqd.dest.channel = ch_id;
1161         opts.fqd.dest.wq = queue_conf->ev.priority;
1162
1163         if (dpaa_intf->cgr_rx) {
1164                 opts.we_mask |= QM_INITFQ_WE_CGID;
1165                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1166                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1167         }
1168
1169         flags = QMAN_INITFQ_FLAG_SCHED;
1170
1171         ret = qman_init_fq(rxq, flags, &opts);
1172         if (ret) {
1173                 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x "
1174                                 "ret:%d(%s)", rxq->fqid, ret, strerror(ret));
1175                 return ret;
1176         }
1177
1178         /* copy configuration which needs to be filled during dequeue */
1179         memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event));
1180         dev->data->rx_queues[eth_rx_queue_id] = rxq;
1181
1182         return ret;
1183 }
1184
1185 int
1186 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev,
1187                 int eth_rx_queue_id)
1188 {
1189         struct qm_mcc_initfq opts;
1190         int ret;
1191         u32 flags = 0;
1192         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1193         struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id];
1194
1195         dpaa_poll_queue_default_config(&opts);
1196
1197         if (dpaa_intf->cgr_rx) {
1198                 opts.we_mask |= QM_INITFQ_WE_CGID;
1199                 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid;
1200                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1201         }
1202
1203         ret = qman_init_fq(rxq, flags, &opts);
1204         if (ret) {
1205                 DPAA_PMD_ERR("init rx fqid %d failed with ret: %d",
1206                              rxq->fqid, ret);
1207         }
1208
1209         rxq->cb.dqrr_dpdk_cb = NULL;
1210         dev->data->rx_queues[eth_rx_queue_id] = NULL;
1211
1212         return 0;
1213 }
1214
1215 static
1216 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
1217                             uint16_t nb_desc __rte_unused,
1218                 unsigned int socket_id __rte_unused,
1219                 const struct rte_eth_txconf *tx_conf)
1220 {
1221         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1222         struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx];
1223
1224         PMD_INIT_FUNC_TRACE();
1225
1226         /* Tx deferred start is not supported */
1227         if (tx_conf->tx_deferred_start) {
1228                 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev);
1229                 return -EINVAL;
1230         }
1231         txq->nb_desc = UINT16_MAX;
1232         txq->offloads = tx_conf->offloads;
1233
1234         if (queue_idx >= dev->data->nb_tx_queues) {
1235                 rte_errno = EOVERFLOW;
1236                 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)",
1237                       (void *)dev, queue_idx, dev->data->nb_tx_queues);
1238                 return -rte_errno;
1239         }
1240
1241         DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)",
1242                         queue_idx, txq->fqid);
1243         dev->data->tx_queues[queue_idx] = txq;
1244
1245         return 0;
1246 }
1247
1248 static uint32_t
1249 dpaa_dev_rx_queue_count(void *rx_queue)
1250 {
1251         struct qman_fq *rxq = rx_queue;
1252         u32 frm_cnt = 0;
1253
1254         PMD_INIT_FUNC_TRACE();
1255
1256         if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) {
1257                 DPAA_PMD_DEBUG("RX frame count for q(%p) is %u",
1258                                rx_queue, frm_cnt);
1259         }
1260         return frm_cnt;
1261 }
1262
1263 static int dpaa_link_down(struct rte_eth_dev *dev)
1264 {
1265         struct fman_if *fif = dev->process_private;
1266         struct __fman_if *__fif;
1267
1268         PMD_INIT_FUNC_TRACE();
1269
1270         __fif = container_of(fif, struct __fman_if, __if);
1271
1272         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1273                 dpaa_update_link_status(__fif->node_name, ETH_LINK_DOWN);
1274         else
1275                 return dpaa_eth_dev_stop(dev);
1276         return 0;
1277 }
1278
1279 static int dpaa_link_up(struct rte_eth_dev *dev)
1280 {
1281         struct fman_if *fif = dev->process_private;
1282         struct __fman_if *__fif;
1283
1284         PMD_INIT_FUNC_TRACE();
1285
1286         __fif = container_of(fif, struct __fman_if, __if);
1287
1288         if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC)
1289                 dpaa_update_link_status(__fif->node_name, ETH_LINK_UP);
1290         else
1291                 dpaa_eth_dev_start(dev);
1292         return 0;
1293 }
1294
1295 static int
1296 dpaa_flow_ctrl_set(struct rte_eth_dev *dev,
1297                    struct rte_eth_fc_conf *fc_conf)
1298 {
1299         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1300         struct rte_eth_fc_conf *net_fc;
1301
1302         PMD_INIT_FUNC_TRACE();
1303
1304         if (!(dpaa_intf->fc_conf)) {
1305                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1306                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1307                 if (!dpaa_intf->fc_conf) {
1308                         DPAA_PMD_ERR("unable to save flow control info");
1309                         return -ENOMEM;
1310                 }
1311         }
1312         net_fc = dpaa_intf->fc_conf;
1313
1314         if (fc_conf->high_water < fc_conf->low_water) {
1315                 DPAA_PMD_ERR("Incorrect Flow Control Configuration");
1316                 return -EINVAL;
1317         }
1318
1319         if (fc_conf->mode == RTE_FC_NONE) {
1320                 return 0;
1321         } else if (fc_conf->mode == RTE_FC_TX_PAUSE ||
1322                  fc_conf->mode == RTE_FC_FULL) {
1323                 fman_if_set_fc_threshold(dev->process_private,
1324                                          fc_conf->high_water,
1325                                          fc_conf->low_water,
1326                                          dpaa_intf->bp_info->bpid);
1327                 if (fc_conf->pause_time)
1328                         fman_if_set_fc_quanta(dev->process_private,
1329                                               fc_conf->pause_time);
1330         }
1331
1332         /* Save the information in dpaa device */
1333         net_fc->pause_time = fc_conf->pause_time;
1334         net_fc->high_water = fc_conf->high_water;
1335         net_fc->low_water = fc_conf->low_water;
1336         net_fc->send_xon = fc_conf->send_xon;
1337         net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd;
1338         net_fc->mode = fc_conf->mode;
1339         net_fc->autoneg = fc_conf->autoneg;
1340
1341         return 0;
1342 }
1343
1344 static int
1345 dpaa_flow_ctrl_get(struct rte_eth_dev *dev,
1346                    struct rte_eth_fc_conf *fc_conf)
1347 {
1348         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1349         struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf;
1350         int ret;
1351
1352         PMD_INIT_FUNC_TRACE();
1353
1354         if (net_fc) {
1355                 fc_conf->pause_time = net_fc->pause_time;
1356                 fc_conf->high_water = net_fc->high_water;
1357                 fc_conf->low_water = net_fc->low_water;
1358                 fc_conf->send_xon = net_fc->send_xon;
1359                 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd;
1360                 fc_conf->mode = net_fc->mode;
1361                 fc_conf->autoneg = net_fc->autoneg;
1362                 return 0;
1363         }
1364         ret = fman_if_get_fc_threshold(dev->process_private);
1365         if (ret) {
1366                 fc_conf->mode = RTE_FC_TX_PAUSE;
1367                 fc_conf->pause_time =
1368                         fman_if_get_fc_quanta(dev->process_private);
1369         } else {
1370                 fc_conf->mode = RTE_FC_NONE;
1371         }
1372
1373         return 0;
1374 }
1375
1376 static int
1377 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev,
1378                              struct rte_ether_addr *addr,
1379                              uint32_t index,
1380                              __rte_unused uint32_t pool)
1381 {
1382         int ret;
1383
1384         PMD_INIT_FUNC_TRACE();
1385
1386         ret = fman_if_add_mac_addr(dev->process_private,
1387                                    addr->addr_bytes, index);
1388
1389         if (ret)
1390                 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret);
1391         return 0;
1392 }
1393
1394 static void
1395 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev,
1396                           uint32_t index)
1397 {
1398         PMD_INIT_FUNC_TRACE();
1399
1400         fman_if_clear_mac_addr(dev->process_private, index);
1401 }
1402
1403 static int
1404 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev,
1405                        struct rte_ether_addr *addr)
1406 {
1407         int ret;
1408
1409         PMD_INIT_FUNC_TRACE();
1410
1411         ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0);
1412         if (ret)
1413                 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret);
1414
1415         return ret;
1416 }
1417
1418 static int
1419 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev,
1420                          struct rte_eth_rss_conf *rss_conf)
1421 {
1422         struct rte_eth_dev_data *data = dev->data;
1423         struct rte_eth_conf *eth_conf = &data->dev_conf;
1424
1425         PMD_INIT_FUNC_TRACE();
1426
1427         if (!(default_q || fmc_q)) {
1428                 if (dpaa_fm_config(dev, rss_conf->rss_hf)) {
1429                         DPAA_PMD_ERR("FM port configuration: Failed\n");
1430                         return -1;
1431                 }
1432                 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1433         } else {
1434                 DPAA_PMD_ERR("Function not supported\n");
1435                 return -ENOTSUP;
1436         }
1437         return 0;
1438 }
1439
1440 static int
1441 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1442                            struct rte_eth_rss_conf *rss_conf)
1443 {
1444         struct rte_eth_dev_data *data = dev->data;
1445         struct rte_eth_conf *eth_conf = &data->dev_conf;
1446
1447         /* dpaa does not support rss_key, so length should be 0*/
1448         rss_conf->rss_key_len = 0;
1449         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
1450         return 0;
1451 }
1452
1453 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev,
1454                                       uint16_t queue_id)
1455 {
1456         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1457         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1458
1459         if (!rxq->is_static)
1460                 return -EINVAL;
1461
1462         return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI);
1463 }
1464
1465 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev,
1466                                        uint16_t queue_id)
1467 {
1468         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1469         struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id];
1470         uint32_t temp;
1471         ssize_t temp1;
1472
1473         if (!rxq->is_static)
1474                 return -EINVAL;
1475
1476         qman_fq_portal_irqsource_remove(rxq->qp, ~0);
1477
1478         temp1 = read(rxq->q_fd, &temp, sizeof(temp));
1479         if (temp1 != sizeof(temp))
1480                 DPAA_PMD_ERR("irq read error");
1481
1482         qman_fq_portal_thread_irq(rxq->qp);
1483
1484         return 0;
1485 }
1486
1487 static void
1488 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1489         struct rte_eth_rxq_info *qinfo)
1490 {
1491         struct dpaa_if *dpaa_intf = dev->data->dev_private;
1492         struct qman_fq *rxq;
1493         int ret;
1494
1495         rxq = dev->data->rx_queues[queue_id];
1496
1497         qinfo->mp = dpaa_intf->bp_info->mp;
1498         qinfo->scattered_rx = dev->data->scattered_rx;
1499         qinfo->nb_desc = rxq->nb_desc;
1500
1501         /* Report the HW Rx buffer length to user */
1502         ret = fman_if_get_maxfrm(dev->process_private);
1503         if (ret > 0)
1504                 qinfo->rx_buf_size = ret;
1505
1506         qinfo->conf.rx_free_thresh = 1;
1507         qinfo->conf.rx_drop_en = 1;
1508         qinfo->conf.rx_deferred_start = 0;
1509         qinfo->conf.offloads = rxq->offloads;
1510 }
1511
1512 static void
1513 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1514         struct rte_eth_txq_info *qinfo)
1515 {
1516         struct qman_fq *txq;
1517
1518         txq = dev->data->tx_queues[queue_id];
1519
1520         qinfo->nb_desc = txq->nb_desc;
1521         qinfo->conf.tx_thresh.pthresh = 0;
1522         qinfo->conf.tx_thresh.hthresh = 0;
1523         qinfo->conf.tx_thresh.wthresh = 0;
1524
1525         qinfo->conf.tx_free_thresh = 0;
1526         qinfo->conf.tx_rs_thresh = 0;
1527         qinfo->conf.offloads = txq->offloads;
1528         qinfo->conf.tx_deferred_start = 0;
1529 }
1530
1531 static struct eth_dev_ops dpaa_devops = {
1532         .dev_configure            = dpaa_eth_dev_configure,
1533         .dev_start                = dpaa_eth_dev_start,
1534         .dev_stop                 = dpaa_eth_dev_stop,
1535         .dev_close                = dpaa_eth_dev_close,
1536         .dev_infos_get            = dpaa_eth_dev_info,
1537         .dev_supported_ptypes_get = dpaa_supported_ptypes_get,
1538
1539         .rx_queue_setup           = dpaa_eth_rx_queue_setup,
1540         .tx_queue_setup           = dpaa_eth_tx_queue_setup,
1541         .rx_burst_mode_get        = dpaa_dev_rx_burst_mode_get,
1542         .tx_burst_mode_get        = dpaa_dev_tx_burst_mode_get,
1543         .rxq_info_get             = dpaa_rxq_info_get,
1544         .txq_info_get             = dpaa_txq_info_get,
1545
1546         .flow_ctrl_get            = dpaa_flow_ctrl_get,
1547         .flow_ctrl_set            = dpaa_flow_ctrl_set,
1548
1549         .link_update              = dpaa_eth_link_update,
1550         .stats_get                = dpaa_eth_stats_get,
1551         .xstats_get               = dpaa_dev_xstats_get,
1552         .xstats_get_by_id         = dpaa_xstats_get_by_id,
1553         .xstats_get_names_by_id   = dpaa_xstats_get_names_by_id,
1554         .xstats_get_names         = dpaa_xstats_get_names,
1555         .xstats_reset             = dpaa_eth_stats_reset,
1556         .stats_reset              = dpaa_eth_stats_reset,
1557         .promiscuous_enable       = dpaa_eth_promiscuous_enable,
1558         .promiscuous_disable      = dpaa_eth_promiscuous_disable,
1559         .allmulticast_enable      = dpaa_eth_multicast_enable,
1560         .allmulticast_disable     = dpaa_eth_multicast_disable,
1561         .mtu_set                  = dpaa_mtu_set,
1562         .dev_set_link_down        = dpaa_link_down,
1563         .dev_set_link_up          = dpaa_link_up,
1564         .mac_addr_add             = dpaa_dev_add_mac_addr,
1565         .mac_addr_remove          = dpaa_dev_remove_mac_addr,
1566         .mac_addr_set             = dpaa_dev_set_mac_addr,
1567
1568         .fw_version_get           = dpaa_fw_version_get,
1569
1570         .rx_queue_intr_enable     = dpaa_dev_queue_intr_enable,
1571         .rx_queue_intr_disable    = dpaa_dev_queue_intr_disable,
1572         .rss_hash_update          = dpaa_dev_rss_hash_update,
1573         .rss_hash_conf_get        = dpaa_dev_rss_hash_conf_get,
1574 };
1575
1576 static bool
1577 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv)
1578 {
1579         if (strcmp(dev->device->driver->name,
1580                    drv->driver.name))
1581                 return false;
1582
1583         return true;
1584 }
1585
1586 static bool
1587 is_dpaa_supported(struct rte_eth_dev *dev)
1588 {
1589         return is_device_supported(dev, &rte_dpaa_pmd);
1590 }
1591
1592 int
1593 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on)
1594 {
1595         struct rte_eth_dev *dev;
1596
1597         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
1598
1599         dev = &rte_eth_devices[port];
1600
1601         if (!is_dpaa_supported(dev))
1602                 return -ENOTSUP;
1603
1604         if (on)
1605                 fman_if_loopback_enable(dev->process_private);
1606         else
1607                 fman_if_loopback_disable(dev->process_private);
1608
1609         return 0;
1610 }
1611
1612 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf,
1613                                struct fman_if *fman_intf)
1614 {
1615         struct rte_eth_fc_conf *fc_conf;
1616         int ret;
1617
1618         PMD_INIT_FUNC_TRACE();
1619
1620         if (!(dpaa_intf->fc_conf)) {
1621                 dpaa_intf->fc_conf = rte_zmalloc(NULL,
1622                         sizeof(struct rte_eth_fc_conf), MAX_CACHELINE);
1623                 if (!dpaa_intf->fc_conf) {
1624                         DPAA_PMD_ERR("unable to save flow control info");
1625                         return -ENOMEM;
1626                 }
1627         }
1628         fc_conf = dpaa_intf->fc_conf;
1629         ret = fman_if_get_fc_threshold(fman_intf);
1630         if (ret) {
1631                 fc_conf->mode = RTE_FC_TX_PAUSE;
1632                 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf);
1633         } else {
1634                 fc_conf->mode = RTE_FC_NONE;
1635         }
1636
1637         return 0;
1638 }
1639
1640 /* Initialise an Rx FQ */
1641 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx,
1642                               uint32_t fqid)
1643 {
1644         struct qm_mcc_initfq opts = {0};
1645         int ret;
1646         u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE;
1647         struct qm_mcc_initcgr cgr_opts = {
1648                 .we_mask = QM_CGR_WE_CS_THRES |
1649                                 QM_CGR_WE_CSTD_EN |
1650                                 QM_CGR_WE_MODE,
1651                 .cgr = {
1652                         .cstd_en = QM_CGR_EN,
1653                         .mode = QMAN_CGR_MODE_FRAME
1654                 }
1655         };
1656
1657         if (fmc_q || default_q) {
1658                 ret = qman_reserve_fqid(fqid);
1659                 if (ret) {
1660                         DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d",
1661                                      fqid, ret);
1662                         return -EINVAL;
1663                 }
1664         }
1665
1666         DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid);
1667         ret = qman_create_fq(fqid, flags, fq);
1668         if (ret) {
1669                 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d",
1670                         fqid, ret);
1671                 return ret;
1672         }
1673         fq->is_static = false;
1674
1675         dpaa_poll_queue_default_config(&opts);
1676
1677         if (cgr_rx) {
1678                 /* Enable tail drop with cgr on this queue */
1679                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0);
1680                 cgr_rx->cb = NULL;
1681                 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT,
1682                                       &cgr_opts);
1683                 if (ret) {
1684                         DPAA_PMD_WARN(
1685                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1686                                 fq->fqid, ret);
1687                         goto without_cgr;
1688                 }
1689                 opts.we_mask |= QM_INITFQ_WE_CGID;
1690                 opts.fqd.cgid = cgr_rx->cgrid;
1691                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1692         }
1693 without_cgr:
1694         ret = qman_init_fq(fq, 0, &opts);
1695         if (ret)
1696                 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret);
1697         return ret;
1698 }
1699
1700 /* Initialise a Tx FQ */
1701 static int dpaa_tx_queue_init(struct qman_fq *fq,
1702                               struct fman_if *fman_intf,
1703                               struct qman_cgr *cgr_tx)
1704 {
1705         struct qm_mcc_initfq opts = {0};
1706         struct qm_mcc_initcgr cgr_opts = {
1707                 .we_mask = QM_CGR_WE_CS_THRES |
1708                                 QM_CGR_WE_CSTD_EN |
1709                                 QM_CGR_WE_MODE,
1710                 .cgr = {
1711                         .cstd_en = QM_CGR_EN,
1712                         .mode = QMAN_CGR_MODE_FRAME
1713                 }
1714         };
1715         int ret;
1716
1717         ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID |
1718                              QMAN_FQ_FLAG_TO_DCPORTAL, fq);
1719         if (ret) {
1720                 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret);
1721                 return ret;
1722         }
1723         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL |
1724                        QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA;
1725         opts.fqd.dest.channel = fman_intf->tx_channel_id;
1726         opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY;
1727         opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE;
1728         opts.fqd.context_b = 0;
1729         /* no tx-confirmation */
1730         opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi;
1731         opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo;
1732         DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid);
1733
1734         if (cgr_tx) {
1735                 /* Enable tail drop with cgr on this queue */
1736                 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres,
1737                                       td_tx_threshold, 0);
1738                 cgr_tx->cb = NULL;
1739                 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT,
1740                                       &cgr_opts);
1741                 if (ret) {
1742                         DPAA_PMD_WARN(
1743                                 "rx taildrop init fail on rx fqid 0x%x(ret=%d)",
1744                                 fq->fqid, ret);
1745                         goto without_cgr;
1746                 }
1747                 opts.we_mask |= QM_INITFQ_WE_CGID;
1748                 opts.fqd.cgid = cgr_tx->cgrid;
1749                 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE;
1750                 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n",
1751                                 td_tx_threshold);
1752         }
1753 without_cgr:
1754         ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts);
1755         if (ret)
1756                 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret);
1757         return ret;
1758 }
1759
1760 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
1761 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */
1762 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid)
1763 {
1764         struct qm_mcc_initfq opts = {0};
1765         int ret;
1766
1767         PMD_INIT_FUNC_TRACE();
1768
1769         ret = qman_reserve_fqid(fqid);
1770         if (ret) {
1771                 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d",
1772                         fqid, ret);
1773                 return -EINVAL;
1774         }
1775         /* "map" this Rx FQ to one of the interfaces Tx FQID */
1776         DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid);
1777         ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq);
1778         if (ret) {
1779                 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d",
1780                         fqid, ret);
1781                 return ret;
1782         }
1783         opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL;
1784         opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY;
1785         ret = qman_init_fq(fq, 0, &opts);
1786         if (ret)
1787                 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d",
1788                             fqid, ret);
1789         return ret;
1790 }
1791 #endif
1792
1793 /* Initialise a network interface */
1794 static int
1795 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev)
1796 {
1797         struct rte_dpaa_device *dpaa_device;
1798         struct fm_eth_port_cfg *cfg;
1799         struct dpaa_if *dpaa_intf;
1800         struct fman_if *fman_intf;
1801         int dev_id;
1802
1803         PMD_INIT_FUNC_TRACE();
1804
1805         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1806         dev_id = dpaa_device->id.dev_id;
1807         cfg = dpaa_get_eth_port_cfg(dev_id);
1808         fman_intf = cfg->fman_if;
1809         eth_dev->process_private = fman_intf;
1810
1811         /* Plugging of UCODE burst API not supported in Secondary */
1812         dpaa_intf = eth_dev->data->dev_private;
1813         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
1814         if (dpaa_intf->cgr_tx)
1815                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow;
1816         else
1817                 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx;
1818 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1819         qman_set_fq_lookup_table(
1820                 dpaa_intf->rx_queues->qman_fq_lookup_table);
1821 #endif
1822
1823         return 0;
1824 }
1825
1826 /* Initialise a network interface */
1827 static int
1828 dpaa_dev_init(struct rte_eth_dev *eth_dev)
1829 {
1830         int num_rx_fqs, fqid;
1831         int loop, ret = 0;
1832         int dev_id;
1833         struct rte_dpaa_device *dpaa_device;
1834         struct dpaa_if *dpaa_intf;
1835         struct fm_eth_port_cfg *cfg;
1836         struct fman_if *fman_intf;
1837         struct fman_if_bpool *bp, *tmp_bp;
1838         uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES];
1839         uint32_t cgrid_tx[MAX_DPAA_CORES];
1840         uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES];
1841         int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES];
1842         int8_t vsp_id = -1;
1843
1844         PMD_INIT_FUNC_TRACE();
1845
1846         dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device);
1847         dev_id = dpaa_device->id.dev_id;
1848         dpaa_intf = eth_dev->data->dev_private;
1849         cfg = dpaa_get_eth_port_cfg(dev_id);
1850         fman_intf = cfg->fman_if;
1851
1852         dpaa_intf->name = dpaa_device->name;
1853
1854         /* save fman_if & cfg in the interface struture */
1855         eth_dev->process_private = fman_intf;
1856         dpaa_intf->ifid = dev_id;
1857         dpaa_intf->cfg = cfg;
1858
1859         memset((char *)dev_rx_fqids, 0,
1860                 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES);
1861
1862         memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES);
1863
1864         /* Initialize Rx FQ's */
1865         if (default_q) {
1866                 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES;
1867         } else if (fmc_q) {
1868                 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids,
1869                                                 dev_vspids,
1870                                                 DPAA_MAX_NUM_PCD_QUEUES);
1871                 if (num_rx_fqs < 0) {
1872                         DPAA_PMD_ERR("%s FMC initializes failed!",
1873                                 dpaa_intf->name);
1874                         goto free_rx;
1875                 }
1876                 if (!num_rx_fqs) {
1877                         DPAA_PMD_WARN("%s is not configured by FMC.",
1878                                 dpaa_intf->name);
1879                 }
1880         } else {
1881                 /* FMCLESS mode, load balance to multiple cores.*/
1882                 num_rx_fqs = rte_lcore_count();
1883         }
1884
1885         /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX
1886          * queues.
1887          */
1888         if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) {
1889                 DPAA_PMD_ERR("Invalid number of RX queues\n");
1890                 return -EINVAL;
1891         }
1892
1893         if (num_rx_fqs > 0) {
1894                 dpaa_intf->rx_queues = rte_zmalloc(NULL,
1895                         sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE);
1896                 if (!dpaa_intf->rx_queues) {
1897                         DPAA_PMD_ERR("Failed to alloc mem for RX queues\n");
1898                         return -ENOMEM;
1899                 }
1900         } else {
1901                 dpaa_intf->rx_queues = NULL;
1902         }
1903
1904         memset(cgrid, 0, sizeof(cgrid));
1905         memset(cgrid_tx, 0, sizeof(cgrid_tx));
1906
1907         /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means
1908          * Tx tail drop is disabled.
1909          */
1910         if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) {
1911                 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD"));
1912                 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u",
1913                                td_tx_threshold);
1914                 /* if a very large value is being configured */
1915                 if (td_tx_threshold > UINT16_MAX)
1916                         td_tx_threshold = CGR_RX_PERFQ_THRESH;
1917         }
1918
1919         /* If congestion control is enabled globally*/
1920         if (num_rx_fqs > 0 && td_threshold) {
1921                 dpaa_intf->cgr_rx = rte_zmalloc(NULL,
1922                         sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE);
1923                 if (!dpaa_intf->cgr_rx) {
1924                         DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n");
1925                         ret = -ENOMEM;
1926                         goto free_rx;
1927                 }
1928
1929                 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0);
1930                 if (ret != num_rx_fqs) {
1931                         DPAA_PMD_WARN("insufficient CGRIDs available");
1932                         ret = -EINVAL;
1933                         goto free_rx;
1934                 }
1935         } else {
1936                 dpaa_intf->cgr_rx = NULL;
1937         }
1938
1939         if (!fmc_q && !default_q) {
1940                 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs,
1941                                             num_rx_fqs, 0);
1942                 if (ret < 0) {
1943                         DPAA_PMD_ERR("Failed to alloc rx fqid's\n");
1944                         goto free_rx;
1945                 }
1946         }
1947
1948         for (loop = 0; loop < num_rx_fqs; loop++) {
1949                 if (default_q)
1950                         fqid = cfg->rx_def;
1951                 else
1952                         fqid = dev_rx_fqids[loop];
1953
1954                 vsp_id = dev_vspids[loop];
1955
1956                 if (dpaa_intf->cgr_rx)
1957                         dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop];
1958
1959                 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop],
1960                         dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL,
1961                         fqid);
1962                 if (ret)
1963                         goto free_rx;
1964                 dpaa_intf->rx_queues[loop].vsp_id = vsp_id;
1965                 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf;
1966         }
1967         dpaa_intf->nb_rx_queues = num_rx_fqs;
1968
1969         /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */
1970         dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) *
1971                 MAX_DPAA_CORES, MAX_CACHELINE);
1972         if (!dpaa_intf->tx_queues) {
1973                 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n");
1974                 ret = -ENOMEM;
1975                 goto free_rx;
1976         }
1977
1978         /* If congestion control is enabled globally*/
1979         if (td_tx_threshold) {
1980                 dpaa_intf->cgr_tx = rte_zmalloc(NULL,
1981                         sizeof(struct qman_cgr) * MAX_DPAA_CORES,
1982                         MAX_CACHELINE);
1983                 if (!dpaa_intf->cgr_tx) {
1984                         DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n");
1985                         ret = -ENOMEM;
1986                         goto free_rx;
1987                 }
1988
1989                 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES,
1990                                              1, 0);
1991                 if (ret != MAX_DPAA_CORES) {
1992                         DPAA_PMD_WARN("insufficient CGRIDs available");
1993                         ret = -EINVAL;
1994                         goto free_rx;
1995                 }
1996         } else {
1997                 dpaa_intf->cgr_tx = NULL;
1998         }
1999
2000
2001         for (loop = 0; loop < MAX_DPAA_CORES; loop++) {
2002                 if (dpaa_intf->cgr_tx)
2003                         dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop];
2004
2005                 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop],
2006                         fman_intf,
2007                         dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL);
2008                 if (ret)
2009                         goto free_tx;
2010                 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf;
2011         }
2012         dpaa_intf->nb_tx_queues = MAX_DPAA_CORES;
2013
2014 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER
2015         ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2016                         [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err);
2017         if (ret) {
2018                 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!");
2019                 goto free_tx;
2020         }
2021         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf;
2022         ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues
2023                         [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err);
2024         if (ret) {
2025                 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!");
2026                 goto free_tx;
2027         }
2028         dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf;
2029 #endif
2030
2031         DPAA_PMD_DEBUG("All frame queues created");
2032
2033         /* Get the initial configuration for flow control */
2034         dpaa_fc_set_default(dpaa_intf, fman_intf);
2035
2036         /* reset bpool list, initialize bpool dynamically */
2037         list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) {
2038                 list_del(&bp->node);
2039                 rte_free(bp);
2040         }
2041
2042         /* Populate ethdev structure */
2043         eth_dev->dev_ops = &dpaa_devops;
2044         eth_dev->rx_queue_count = dpaa_dev_rx_queue_count;
2045         eth_dev->rx_pkt_burst = dpaa_eth_queue_rx;
2046         eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all;
2047
2048         /* Allocate memory for storing MAC addresses */
2049         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2050                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0);
2051         if (eth_dev->data->mac_addrs == NULL) {
2052                 DPAA_PMD_ERR("Failed to allocate %d bytes needed to "
2053                                                 "store MAC addresses",
2054                                 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER);
2055                 ret = -ENOMEM;
2056                 goto free_tx;
2057         }
2058
2059         /* copy the primary mac address */
2060         rte_ether_addr_copy(&fman_intf->mac_addr, &eth_dev->data->mac_addrs[0]);
2061
2062         RTE_LOG(INFO, PMD, "net: dpaa: %s: " RTE_ETHER_ADDR_PRT_FMT "\n",
2063                 dpaa_device->name, RTE_ETHER_ADDR_BYTES(&fman_intf->mac_addr));
2064
2065         if (!fman_intf->is_shared_mac) {
2066                 /* Configure error packet handling */
2067                 fman_if_receive_rx_errors(fman_intf,
2068                         FM_FD_RX_STATUS_ERR_MASK);
2069                 /* Disable RX mode */
2070                 fman_if_disable_rx(fman_intf);
2071                 /* Disable promiscuous mode */
2072                 fman_if_promiscuous_disable(fman_intf);
2073                 /* Disable multicast */
2074                 fman_if_reset_mcast_filter_table(fman_intf);
2075                 /* Reset interface statistics */
2076                 fman_if_stats_reset(fman_intf);
2077                 /* Disable SG by default */
2078                 fman_if_set_sg(fman_intf, 0);
2079                 fman_if_set_maxfrm(fman_intf,
2080                                    RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE);
2081         }
2082
2083         return 0;
2084
2085 free_tx:
2086         rte_free(dpaa_intf->tx_queues);
2087         dpaa_intf->tx_queues = NULL;
2088         dpaa_intf->nb_tx_queues = 0;
2089
2090 free_rx:
2091         rte_free(dpaa_intf->cgr_rx);
2092         rte_free(dpaa_intf->cgr_tx);
2093         rte_free(dpaa_intf->rx_queues);
2094         dpaa_intf->rx_queues = NULL;
2095         dpaa_intf->nb_rx_queues = 0;
2096         return ret;
2097 }
2098
2099 static int
2100 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv,
2101                struct rte_dpaa_device *dpaa_dev)
2102 {
2103         int diag;
2104         int ret;
2105         struct rte_eth_dev *eth_dev;
2106
2107         PMD_INIT_FUNC_TRACE();
2108
2109         if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) >
2110                 RTE_PKTMBUF_HEADROOM) {
2111                 DPAA_PMD_ERR(
2112                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)",
2113                 RTE_PKTMBUF_HEADROOM,
2114                 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE);
2115
2116                 return -1;
2117         }
2118
2119         /* In case of secondary process, the device is already configured
2120          * and no further action is required, except portal initialization
2121          * and verifying secondary attachment to port name.
2122          */
2123         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2124                 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name);
2125                 if (!eth_dev)
2126                         return -ENOMEM;
2127                 eth_dev->device = &dpaa_dev->device;
2128                 eth_dev->dev_ops = &dpaa_devops;
2129
2130                 ret = dpaa_dev_init_secondary(eth_dev);
2131                 if (ret != 0) {
2132                         RTE_LOG(ERR, PMD, "secondary dev init failed\n");
2133                         return ret;
2134                 }
2135
2136                 rte_eth_dev_probing_finish(eth_dev);
2137                 return 0;
2138         }
2139
2140         if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) {
2141                 if (access("/tmp/fmc.bin", F_OK) == -1) {
2142                         DPAA_PMD_INFO("* FMC not configured.Enabling default mode");
2143                         default_q = 1;
2144                 }
2145
2146                 if (!(default_q || fmc_q)) {
2147                         if (dpaa_fm_init()) {
2148                                 DPAA_PMD_ERR("FM init failed\n");
2149                                 return -1;
2150                         }
2151                 }
2152
2153                 /* disabling the default push mode for LS1043 */
2154                 if (dpaa_svr_family == SVR_LS1043A_FAMILY)
2155                         dpaa_push_mode_max_queue = 0;
2156
2157                 /* if push mode queues to be enabled. Currenly we are allowing
2158                  * only one queue per thread.
2159                  */
2160                 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) {
2161                         dpaa_push_mode_max_queue =
2162                                         atoi(getenv("DPAA_PUSH_QUEUES_NUMBER"));
2163                         if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE)
2164                             dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE;
2165                 }
2166
2167                 is_global_init = 1;
2168         }
2169
2170         if (unlikely(!DPAA_PER_LCORE_PORTAL)) {
2171                 ret = rte_dpaa_portal_init((void *)1);
2172                 if (ret) {
2173                         DPAA_PMD_ERR("Unable to initialize portal");
2174                         return ret;
2175                 }
2176         }
2177
2178         eth_dev = rte_eth_dev_allocate(dpaa_dev->name);
2179         if (!eth_dev)
2180                 return -ENOMEM;
2181
2182         eth_dev->data->dev_private =
2183                         rte_zmalloc("ethdev private structure",
2184                                         sizeof(struct dpaa_if),
2185                                         RTE_CACHE_LINE_SIZE);
2186         if (!eth_dev->data->dev_private) {
2187                 DPAA_PMD_ERR("Cannot allocate memzone for port data");
2188                 rte_eth_dev_release_port(eth_dev);
2189                 return -ENOMEM;
2190         }
2191
2192         eth_dev->device = &dpaa_dev->device;
2193         dpaa_dev->eth_dev = eth_dev;
2194
2195         qman_ern_register_cb(dpaa_free_mbuf);
2196
2197         if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC)
2198                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2199
2200         /* Invoke PMD device initialization function */
2201         diag = dpaa_dev_init(eth_dev);
2202         if (diag == 0) {
2203                 rte_eth_dev_probing_finish(eth_dev);
2204                 return 0;
2205         }
2206
2207         rte_eth_dev_release_port(eth_dev);
2208         return diag;
2209 }
2210
2211 static int
2212 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev)
2213 {
2214         struct rte_eth_dev *eth_dev;
2215         int ret;
2216
2217         PMD_INIT_FUNC_TRACE();
2218
2219         eth_dev = dpaa_dev->eth_dev;
2220         dpaa_eth_dev_close(eth_dev);
2221         ret = rte_eth_dev_release_port(eth_dev);
2222
2223         return ret;
2224 }
2225
2226 static void __attribute__((destructor(102))) dpaa_finish(void)
2227 {
2228         /* For secondary, primary will do all the cleanup */
2229         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2230                 return;
2231
2232         if (!(default_q || fmc_q)) {
2233                 unsigned int i;
2234
2235                 for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
2236                         if (rte_eth_devices[i].dev_ops == &dpaa_devops) {
2237                                 struct rte_eth_dev *dev = &rte_eth_devices[i];
2238                                 struct dpaa_if *dpaa_intf =
2239                                         dev->data->dev_private;
2240                                 struct fman_if *fif =
2241                                         dev->process_private;
2242                                 if (dpaa_intf->port_handle)
2243                                         if (dpaa_fm_deconfig(dpaa_intf, fif))
2244                                                 DPAA_PMD_WARN("DPAA FM "
2245                                                         "deconfig failed\n");
2246                                 if (fif->num_profiles) {
2247                                         if (dpaa_port_vsp_cleanup(dpaa_intf,
2248                                                                   fif))
2249                                                 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n");
2250                                 }
2251                         }
2252                 }
2253                 if (is_global_init)
2254                         if (dpaa_fm_term())
2255                                 DPAA_PMD_WARN("DPAA FM term failed\n");
2256
2257                 is_global_init = 0;
2258
2259                 DPAA_PMD_INFO("DPAA fman cleaned up");
2260         }
2261 }
2262
2263 static struct rte_dpaa_driver rte_dpaa_pmd = {
2264         .drv_flags = RTE_DPAA_DRV_INTR_LSC,
2265         .drv_type = FSL_DPAA_ETH,
2266         .probe = rte_dpaa_probe,
2267         .remove = rte_dpaa_remove,
2268 };
2269
2270 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd);
2271 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE);