4 * Copyright (c) 2014-2016 Freescale Semiconductor, Inc. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Freescale Semiconductor, Inc nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 #ifndef __DPAA_ETHDEV_H__
34 #define __DPAA_ETHDEV_H__
38 #include <rte_ethdev.h>
46 #define DPAA_MBUF_HW_ANNOTATION 64
47 #define DPAA_FD_PTA_SIZE 64
49 #if (DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM
50 #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM"
53 /* we will re-use the HEADROOM for annotation in RX */
54 #define DPAA_HW_BUF_RESERVE 0
55 #define DPAA_PACKET_LAYOUT_ALIGN 64
57 /* Alignment to use for cpu-local structs to avoid coherency problems. */
58 #define MAX_CACHELINE 64
60 #define DPAA_MIN_RX_BUF_SIZE 512
61 #define DPAA_MAX_RX_PKT_LEN 10240
63 /* RX queue tail drop threshold
64 * currently considering 32 KB packets.
66 #define CONG_THRESHOLD_RX_Q (32 * 1024)
68 /*max mac filter for memac(8) including primary mac addr*/
69 #define DPAA_MAX_MAC_FILTER (MEMAC_NUM_OF_PADDRS + 1)
71 /*Maximum number of slots available in TX ring*/
72 #define MAX_TX_RING_SLOTS 8
74 /* PCD frame queues */
75 #define DPAA_PCD_FQID_START 0x400
76 #define DPAA_PCD_FQID_MULTIPLIER 0x100
77 #define DPAA_DEFAULT_NUM_PCD_QUEUES 1
79 #define DPAA_IF_TX_PRIORITY 3
80 #define DPAA_IF_RX_PRIORITY 4
81 #define DPAA_IF_DEBUG_PRIORITY 7
83 #define DPAA_IF_RX_ANNOTATION_STASH 1
84 #define DPAA_IF_RX_DATA_STASH 1
85 #define DPAA_IF_RX_CONTEXT_STASH 0
87 /* Each "debug" FQ is represented by one of these */
88 #define DPAA_DEBUG_FQ_RX_ERROR 0
89 #define DPAA_DEBUG_FQ_TX_ERROR 1
91 #define DPAA_RSS_OFFLOAD_ALL ( \
93 ETH_RSS_NONFRAG_IPV4_TCP | \
94 ETH_RSS_NONFRAG_IPV4_UDP | \
95 ETH_RSS_NONFRAG_IPV4_SCTP | \
97 ETH_RSS_NONFRAG_IPV6_TCP | \
98 ETH_RSS_NONFRAG_IPV6_UDP | \
99 ETH_RSS_NONFRAG_IPV6_SCTP)
101 #define DPAA_TX_CKSUM_OFFLOAD_MASK ( \
106 /* DPAA Frame descriptor macros */
108 #define DPAA_FD_CMD_FCO 0x80000000
109 /**< Frame queue Context Override */
110 #define DPAA_FD_CMD_RPD 0x40000000
111 /**< Read Prepended Data */
112 #define DPAA_FD_CMD_UPD 0x20000000
113 /**< Update Prepended Data */
114 #define DPAA_FD_CMD_DTC 0x10000000
115 /**< Do IP/TCP/UDP Checksum */
116 #define DPAA_FD_CMD_DCL4C 0x10000000
117 /**< Didn't calculate L4 Checksum */
118 #define DPAA_FD_CMD_CFQ 0x00ffffff
119 /**< Confirmation Frame Queue */
121 /* Each network interface is represented by one of these */
125 const struct fm_eth_port_cfg *cfg;
126 struct qman_fq *rx_queues;
127 struct qman_fq *tx_queues;
128 struct qman_fq debug_queues[2];
129 uint16_t nb_rx_queues;
130 uint16_t nb_tx_queues;
133 struct dpaa_bp_info *bp_info;
134 struct rte_eth_fc_conf *fc_conf;