1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
12 #include <rte_ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
35 /* Supported Rx offloads */
36 static uint64_t dev_rx_offloads_sup =
37 DEV_RX_OFFLOAD_CHECKSUM |
38 DEV_RX_OFFLOAD_SCTP_CKSUM |
39 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
40 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
41 DEV_RX_OFFLOAD_VLAN_STRIP |
42 DEV_RX_OFFLOAD_VLAN_FILTER |
43 DEV_RX_OFFLOAD_JUMBO_FRAME |
44 DEV_RX_OFFLOAD_TIMESTAMP;
46 /* Rx offloads which cannot be disabled */
47 static uint64_t dev_rx_offloads_nodis =
48 DEV_RX_OFFLOAD_SCATTER;
50 /* Supported Tx offloads */
51 static uint64_t dev_tx_offloads_sup =
52 DEV_TX_OFFLOAD_VLAN_INSERT |
53 DEV_TX_OFFLOAD_IPV4_CKSUM |
54 DEV_TX_OFFLOAD_UDP_CKSUM |
55 DEV_TX_OFFLOAD_TCP_CKSUM |
56 DEV_TX_OFFLOAD_SCTP_CKSUM |
57 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
58 DEV_TX_OFFLOAD_MT_LOCKFREE |
59 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
61 /* Tx offloads which cannot be disabled */
62 static uint64_t dev_tx_offloads_nodis =
63 DEV_TX_OFFLOAD_MULTI_SEGS;
65 /* enable timestamp in mbuf */
66 enum pmd_dpaa2_ts dpaa2_enable_ts;
68 struct rte_dpaa2_xstats_name_off {
69 char name[RTE_ETH_XSTATS_NAME_SIZE];
70 uint8_t page_id; /* dpni statistics page id */
71 uint8_t stats_id; /* stats id in the given page */
74 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
75 {"ingress_multicast_frames", 0, 2},
76 {"ingress_multicast_bytes", 0, 3},
77 {"ingress_broadcast_frames", 0, 4},
78 {"ingress_broadcast_bytes", 0, 5},
79 {"egress_multicast_frames", 1, 2},
80 {"egress_multicast_bytes", 1, 3},
81 {"egress_broadcast_frames", 1, 4},
82 {"egress_broadcast_bytes", 1, 5},
83 {"ingress_filtered_frames", 2, 0},
84 {"ingress_discarded_frames", 2, 1},
85 {"ingress_nobuffer_discards", 2, 2},
86 {"egress_discarded_frames", 2, 3},
87 {"egress_confirmed_frames", 2, 4},
88 {"cgr_reject_frames", 4, 0},
89 {"cgr_reject_bytes", 4, 1},
92 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
94 RTE_ETH_FILTER_DELETE,
95 RTE_ETH_FILTER_UPDATE,
100 static struct rte_dpaa2_driver rte_dpaa2_pmd;
101 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev);
102 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
103 int wait_to_complete);
104 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
105 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
106 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
108 int dpaa2_logtype_pmd;
111 rte_pmd_dpaa2_set_timestamp(enum pmd_dpaa2_ts enable)
113 dpaa2_enable_ts = enable;
117 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
120 struct dpaa2_dev_priv *priv = dev->data->dev_private;
121 struct fsl_mc_io *dpni = dev->process_private;
123 PMD_INIT_FUNC_TRACE();
126 DPAA2_PMD_ERR("dpni is NULL");
131 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
134 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
135 priv->token, vlan_id);
138 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
139 ret, vlan_id, priv->hw_id);
145 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
147 struct dpaa2_dev_priv *priv = dev->data->dev_private;
148 struct fsl_mc_io *dpni = dev->process_private;
151 PMD_INIT_FUNC_TRACE();
153 if (mask & ETH_VLAN_FILTER_MASK) {
154 /* VLAN Filter not avaialble */
155 if (!priv->max_vlan_filters) {
156 DPAA2_PMD_INFO("VLAN filter not available");
160 if (dev->data->dev_conf.rxmode.offloads &
161 DEV_RX_OFFLOAD_VLAN_FILTER)
162 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
165 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
168 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
171 if (mask & ETH_VLAN_EXTEND_MASK) {
172 if (dev->data->dev_conf.rxmode.offloads &
173 DEV_RX_OFFLOAD_VLAN_EXTEND)
174 DPAA2_PMD_INFO("VLAN extend offload not supported");
181 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
182 enum rte_vlan_type vlan_type __rte_unused,
185 struct dpaa2_dev_priv *priv = dev->data->dev_private;
186 struct fsl_mc_io *dpni = dev->process_private;
189 PMD_INIT_FUNC_TRACE();
191 /* nothing to be done for standard vlan tpids */
192 if (tpid == 0x8100 || tpid == 0x88A8)
195 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
198 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
199 /* if already configured tpids, remove them first */
201 struct dpni_custom_tpid_cfg tpid_list = {0};
203 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
204 priv->token, &tpid_list);
207 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
208 priv->token, tpid_list.tpid1);
211 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
219 dpaa2_fw_version_get(struct rte_eth_dev *dev,
224 struct fsl_mc_io *dpni = dev->process_private;
225 struct mc_soc_version mc_plat_info = {0};
226 struct mc_version mc_ver_info = {0};
228 PMD_INIT_FUNC_TRACE();
230 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
231 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
233 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
234 DPAA2_PMD_WARN("\tmc_get_version failed");
236 ret = snprintf(fw_version, fw_size,
241 mc_ver_info.revision);
243 ret += 1; /* add the size of '\0' */
244 if (fw_size < (uint32_t)ret)
251 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
253 struct dpaa2_dev_priv *priv = dev->data->dev_private;
255 PMD_INIT_FUNC_TRACE();
257 dev_info->if_index = priv->hw_id;
259 dev_info->max_mac_addrs = priv->max_mac_filters;
260 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
261 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
262 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
263 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
264 dev_info->rx_offload_capa = dev_rx_offloads_sup |
265 dev_rx_offloads_nodis;
266 dev_info->tx_offload_capa = dev_tx_offloads_sup |
267 dev_tx_offloads_nodis;
268 dev_info->speed_capa = ETH_LINK_SPEED_1G |
269 ETH_LINK_SPEED_2_5G |
272 dev_info->max_hash_mac_addrs = 0;
273 dev_info->max_vfs = 0;
274 dev_info->max_vmdq_pools = ETH_16_POOLS;
275 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
281 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
283 struct dpaa2_dev_priv *priv = dev->data->dev_private;
286 uint8_t num_rxqueue_per_tc;
287 struct dpaa2_queue *mc_q, *mcq;
290 struct dpaa2_queue *dpaa2_q;
292 PMD_INIT_FUNC_TRACE();
294 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
295 if (priv->tx_conf_en)
296 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
298 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
299 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
300 RTE_CACHE_LINE_SIZE);
302 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
306 for (i = 0; i < priv->nb_rx_queues; i++) {
307 mc_q->eth_data = dev->data;
308 priv->rx_vq[i] = mc_q++;
309 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
310 dpaa2_q->q_storage = rte_malloc("dq_storage",
311 sizeof(struct queue_storage_info_t),
312 RTE_CACHE_LINE_SIZE);
313 if (!dpaa2_q->q_storage)
316 memset(dpaa2_q->q_storage, 0,
317 sizeof(struct queue_storage_info_t));
318 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
322 for (i = 0; i < priv->nb_tx_queues; i++) {
323 mc_q->eth_data = dev->data;
324 mc_q->flow_id = 0xffff;
325 priv->tx_vq[i] = mc_q++;
326 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
327 dpaa2_q->cscn = rte_malloc(NULL,
328 sizeof(struct qbman_result), 16);
333 if (priv->tx_conf_en) {
334 /*Setup tx confirmation queues*/
335 for (i = 0; i < priv->nb_tx_queues; i++) {
336 mc_q->eth_data = dev->data;
339 priv->tx_conf_vq[i] = mc_q++;
340 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
342 rte_malloc("dq_storage",
343 sizeof(struct queue_storage_info_t),
344 RTE_CACHE_LINE_SIZE);
345 if (!dpaa2_q->q_storage)
348 memset(dpaa2_q->q_storage, 0,
349 sizeof(struct queue_storage_info_t));
350 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
356 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
357 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
358 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
359 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
367 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
368 rte_free(dpaa2_q->q_storage);
369 priv->tx_conf_vq[i--] = NULL;
371 i = priv->nb_tx_queues;
375 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
376 rte_free(dpaa2_q->cscn);
377 priv->tx_vq[i--] = NULL;
379 i = priv->nb_rx_queues;
382 mc_q = priv->rx_vq[0];
384 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
385 dpaa2_free_dq_storage(dpaa2_q->q_storage);
386 rte_free(dpaa2_q->q_storage);
387 priv->rx_vq[i--] = NULL;
394 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
396 struct dpaa2_dev_priv *priv = dev->data->dev_private;
397 struct dpaa2_queue *dpaa2_q;
400 PMD_INIT_FUNC_TRACE();
402 /* Queue allocation base */
403 if (priv->rx_vq[0]) {
404 /* cleaning up queue storage */
405 for (i = 0; i < priv->nb_rx_queues; i++) {
406 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
407 if (dpaa2_q->q_storage)
408 rte_free(dpaa2_q->q_storage);
410 /* cleanup tx queue cscn */
411 for (i = 0; i < priv->nb_tx_queues; i++) {
412 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
413 rte_free(dpaa2_q->cscn);
415 if (priv->tx_conf_en) {
416 /* cleanup tx conf queue storage */
417 for (i = 0; i < priv->nb_tx_queues; i++) {
418 dpaa2_q = (struct dpaa2_queue *)
420 rte_free(dpaa2_q->q_storage);
423 /*free memory for all queues (RX+TX) */
424 rte_free(priv->rx_vq[0]);
425 priv->rx_vq[0] = NULL;
430 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
432 struct dpaa2_dev_priv *priv = dev->data->dev_private;
433 struct fsl_mc_io *dpni = dev->process_private;
434 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
435 uint64_t rx_offloads = eth_conf->rxmode.offloads;
436 uint64_t tx_offloads = eth_conf->txmode.offloads;
437 int rx_l3_csum_offload = false;
438 int rx_l4_csum_offload = false;
439 int tx_l3_csum_offload = false;
440 int tx_l4_csum_offload = false;
443 PMD_INIT_FUNC_TRACE();
445 /* Rx offloads which are enabled by default */
446 if (dev_rx_offloads_nodis & ~rx_offloads) {
448 "Some of rx offloads enabled by default - requested 0x%" PRIx64
449 " fixed are 0x%" PRIx64,
450 rx_offloads, dev_rx_offloads_nodis);
453 /* Tx offloads which are enabled by default */
454 if (dev_tx_offloads_nodis & ~tx_offloads) {
456 "Some of tx offloads enabled by default - requested 0x%" PRIx64
457 " fixed are 0x%" PRIx64,
458 tx_offloads, dev_tx_offloads_nodis);
461 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
462 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
463 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
464 priv->token, eth_conf->rxmode.max_rx_pkt_len
465 - RTE_ETHER_CRC_LEN);
468 "Unable to set mtu. check config");
472 dev->data->dev_conf.rxmode.max_rx_pkt_len -
473 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
480 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
481 ret = dpaa2_setup_flow_dist(dev,
482 eth_conf->rx_adv_conf.rss_conf.rss_hf);
484 DPAA2_PMD_ERR("Unable to set flow distribution."
485 "Check queue config");
490 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
491 rx_l3_csum_offload = true;
493 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
494 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
495 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
496 rx_l4_csum_offload = true;
498 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
499 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
501 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
505 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
506 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
508 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
512 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
513 dpaa2_enable_ts = true;
515 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
516 tx_l3_csum_offload = true;
518 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
519 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
520 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
521 tx_l4_csum_offload = true;
523 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
524 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
526 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
530 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
531 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
533 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
537 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
538 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
539 * to 0 for LS2 in the hardware thus disabling data/annotation
540 * stashing. For LX2 this is fixed in hardware and thus hash result and
541 * parse results can be received in FD using this option.
543 if (dpaa2_svr_family == SVR_LX2160A) {
544 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
545 DPNI_FLCTYPE_HASH, true);
547 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
552 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
553 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
555 /* update the current status */
556 dpaa2_dev_link_update(dev, 0);
561 /* Function to setup RX flow information. It contains traffic class ID,
562 * flow ID, destination configuration etc.
565 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
566 uint16_t rx_queue_id,
568 unsigned int socket_id __rte_unused,
569 const struct rte_eth_rxconf *rx_conf __rte_unused,
570 struct rte_mempool *mb_pool)
572 struct dpaa2_dev_priv *priv = dev->data->dev_private;
573 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
574 struct dpaa2_queue *dpaa2_q;
575 struct dpni_queue cfg;
581 PMD_INIT_FUNC_TRACE();
583 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
584 dev, rx_queue_id, mb_pool, rx_conf);
586 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
587 bpid = mempool_to_bpid(mb_pool);
588 ret = dpaa2_attach_bp_list(priv,
589 rte_dpaa2_bpid_info[bpid].bp_list);
593 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
594 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
595 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
597 /*Get the flow id from given VQ id*/
598 flow_id = dpaa2_q->flow_id;
599 memset(&cfg, 0, sizeof(struct dpni_queue));
601 options = options | DPNI_QUEUE_OPT_USER_CTX;
602 cfg.user_context = (size_t)(dpaa2_q);
604 /* check if a private cgr available. */
605 for (i = 0; i < priv->max_cgs; i++) {
606 if (!priv->cgid_in_use[i]) {
607 priv->cgid_in_use[i] = 1;
612 if (i < priv->max_cgs) {
613 options |= DPNI_QUEUE_OPT_SET_CGID;
615 dpaa2_q->cgid = cfg.cgid;
617 dpaa2_q->cgid = 0xff;
620 /*if ls2088 or rev2 device, enable the stashing */
622 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
623 options |= DPNI_QUEUE_OPT_FLC;
624 cfg.flc.stash_control = true;
625 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
626 /* 00 00 00 - last 6 bit represent annotation, context stashing,
627 * data stashing setting 01 01 00 (0x14)
628 * (in following order ->DS AS CS)
629 * to enable 1 line data, 1 line annotation.
630 * For LX2, this setting should be 01 00 00 (0x10)
632 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
633 cfg.flc.value |= 0x10;
635 cfg.flc.value |= 0x14;
637 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
638 dpaa2_q->tc_index, flow_id, options, &cfg);
640 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
644 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
645 struct dpni_taildrop taildrop;
649 /* Private CGR will use tail drop length as nb_rx_desc.
650 * for rest cases we can use standard byte based tail drop.
651 * There is no HW restriction, but number of CGRs are limited,
652 * hence this restriction is placed.
654 if (dpaa2_q->cgid != 0xff) {
655 /*enabling per rx queue congestion control */
656 taildrop.threshold = nb_rx_desc;
657 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
659 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
661 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
662 DPNI_CP_CONGESTION_GROUP,
667 /*enabling per rx queue congestion control */
668 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
669 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
670 taildrop.oal = CONG_RX_OAL;
671 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
673 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
674 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
675 dpaa2_q->tc_index, flow_id,
679 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
683 } else { /* Disable tail Drop */
684 struct dpni_taildrop taildrop = {0};
685 DPAA2_PMD_INFO("Tail drop is disabled on queue");
688 if (dpaa2_q->cgid != 0xff) {
689 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
690 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
694 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
695 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
696 dpaa2_q->tc_index, flow_id, &taildrop);
699 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
705 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
710 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
711 uint16_t tx_queue_id,
712 uint16_t nb_tx_desc __rte_unused,
713 unsigned int socket_id __rte_unused,
714 const struct rte_eth_txconf *tx_conf __rte_unused)
716 struct dpaa2_dev_priv *priv = dev->data->dev_private;
717 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
718 priv->tx_vq[tx_queue_id];
719 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
720 priv->tx_conf_vq[tx_queue_id];
721 struct fsl_mc_io *dpni = dev->process_private;
722 struct dpni_queue tx_conf_cfg;
723 struct dpni_queue tx_flow_cfg;
724 uint8_t options = 0, flow_id;
725 struct dpni_queue_id qid;
729 PMD_INIT_FUNC_TRACE();
731 /* Return if queue already configured */
732 if (dpaa2_q->flow_id != 0xffff) {
733 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
737 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
738 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
743 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
744 tc_id, flow_id, options, &tx_flow_cfg);
746 DPAA2_PMD_ERR("Error in setting the tx flow: "
747 "tc_id=%d, flow=%d err=%d",
748 tc_id, flow_id, ret);
752 dpaa2_q->flow_id = flow_id;
754 if (tx_queue_id == 0) {
755 /*Set tx-conf and error configuration*/
756 if (priv->tx_conf_en)
757 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
761 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
765 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
770 dpaa2_q->tc_index = tc_id;
772 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
773 DPNI_QUEUE_TX, dpaa2_q->tc_index,
774 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
776 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
779 dpaa2_q->fqid = qid.fqid;
781 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
782 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
784 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
785 cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD;
786 /* Notify that the queue is not congested when the data in
787 * the queue is below this thershold.
789 cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD;
790 cong_notif_cfg.message_ctx = 0;
791 cong_notif_cfg.message_iova =
792 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
793 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
794 cong_notif_cfg.notification_mode =
795 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
796 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
797 DPNI_CONG_OPT_COHERENT_WRITE;
798 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
800 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
807 "Error in setting tx congestion notification: "
812 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
813 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
815 if (priv->tx_conf_en) {
816 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
817 options = options | DPNI_QUEUE_OPT_USER_CTX;
818 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
819 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
820 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
821 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
823 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
824 "tc_index=%d, flow=%d err=%d",
825 dpaa2_tx_conf_q->tc_index,
826 dpaa2_tx_conf_q->flow_id, ret);
830 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
831 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
832 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
834 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
837 dpaa2_tx_conf_q->fqid = qid.fqid;
843 dpaa2_dev_rx_queue_release(void *q __rte_unused)
845 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
846 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
847 struct fsl_mc_io *dpni =
848 (struct fsl_mc_io *)priv->eth_dev->process_private;
851 struct dpni_queue cfg;
853 memset(&cfg, 0, sizeof(struct dpni_queue));
854 PMD_INIT_FUNC_TRACE();
855 if (dpaa2_q->cgid != 0xff) {
856 options = DPNI_QUEUE_OPT_CLEAR_CGID;
857 cfg.cgid = dpaa2_q->cgid;
859 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
861 dpaa2_q->tc_index, dpaa2_q->flow_id,
864 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
866 priv->cgid_in_use[dpaa2_q->cgid] = 0;
867 dpaa2_q->cgid = 0xff;
872 dpaa2_dev_tx_queue_release(void *q __rte_unused)
874 PMD_INIT_FUNC_TRACE();
878 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
881 struct dpaa2_dev_priv *priv = dev->data->dev_private;
882 struct dpaa2_queue *dpaa2_q;
883 struct qbman_swp *swp;
884 struct qbman_fq_query_np_rslt state;
885 uint32_t frame_cnt = 0;
887 PMD_INIT_FUNC_TRACE();
889 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
890 ret = dpaa2_affine_qbman_swp();
892 DPAA2_PMD_ERR("Failure in affining portal");
896 swp = DPAA2_PER_LCORE_PORTAL;
898 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
900 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
901 frame_cnt = qbman_fq_state_frame_count(&state);
902 DPAA2_PMD_DEBUG("RX frame count for q(%d) is %u",
903 rx_queue_id, frame_cnt);
908 static const uint32_t *
909 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
911 static const uint32_t ptypes[] = {
912 /*todo -= add more types */
915 RTE_PTYPE_L3_IPV4_EXT,
917 RTE_PTYPE_L3_IPV6_EXT,
925 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
926 dev->rx_pkt_burst == dpaa2_dev_rx ||
927 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
933 * Dpaa2 link Interrupt handler
936 * The address of parameter (struct rte_eth_dev *) regsitered before.
942 dpaa2_interrupt_handler(void *param)
944 struct rte_eth_dev *dev = param;
945 struct dpaa2_dev_priv *priv = dev->data->dev_private;
946 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
948 int irq_index = DPNI_IRQ_INDEX;
949 unsigned int status = 0, clear = 0;
951 PMD_INIT_FUNC_TRACE();
954 DPAA2_PMD_ERR("dpni is NULL");
958 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
961 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
966 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
967 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
968 dpaa2_dev_link_update(dev, 0);
969 /* calling all the apps registered for link status event */
970 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
974 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
977 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
981 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
984 struct dpaa2_dev_priv *priv = dev->data->dev_private;
985 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
986 int irq_index = DPNI_IRQ_INDEX;
987 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
989 PMD_INIT_FUNC_TRACE();
991 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
994 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
999 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1002 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1009 dpaa2_dev_start(struct rte_eth_dev *dev)
1011 struct rte_device *rdev = dev->device;
1012 struct rte_dpaa2_device *dpaa2_dev;
1013 struct rte_eth_dev_data *data = dev->data;
1014 struct dpaa2_dev_priv *priv = data->dev_private;
1015 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1016 struct dpni_queue cfg;
1017 struct dpni_error_cfg err_cfg;
1019 struct dpni_queue_id qid;
1020 struct dpaa2_queue *dpaa2_q;
1022 struct rte_intr_handle *intr_handle;
1024 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1025 intr_handle = &dpaa2_dev->intr_handle;
1027 PMD_INIT_FUNC_TRACE();
1029 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1031 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1036 /* Power up the phy. Needed to make the link go UP */
1037 dpaa2_dev_set_link_up(dev);
1039 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1040 DPNI_QUEUE_TX, &qdid);
1042 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1047 for (i = 0; i < data->nb_rx_queues; i++) {
1048 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1049 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1050 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1051 dpaa2_q->flow_id, &cfg, &qid);
1053 DPAA2_PMD_ERR("Error in getting flow information: "
1057 dpaa2_q->fqid = qid.fqid;
1060 /*checksum errors, send them to normal path and set it in annotation */
1061 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1062 err_cfg.errors |= DPNI_ERROR_PHE;
1064 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1065 err_cfg.set_frame_annotation = true;
1067 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1068 priv->token, &err_cfg);
1070 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1075 /* if the interrupts were configured on this devices*/
1076 if (intr_handle && (intr_handle->fd) &&
1077 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1078 /* Registering LSC interrupt handler */
1079 rte_intr_callback_register(intr_handle,
1080 dpaa2_interrupt_handler,
1083 /* enable vfio intr/eventfd mapping
1084 * Interrupt index 0 is required, so we can not use
1087 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1089 /* enable dpni_irqs */
1090 dpaa2_eth_setup_irqs(dev, 1);
1093 /* Change the tx burst function if ordered queues are used */
1094 if (priv->en_ordered)
1095 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1101 * This routine disables all traffic on the adapter by issuing a
1102 * global reset on the MAC.
1105 dpaa2_dev_stop(struct rte_eth_dev *dev)
1107 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1108 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1110 struct rte_eth_link link;
1111 struct rte_intr_handle *intr_handle = dev->intr_handle;
1113 PMD_INIT_FUNC_TRACE();
1115 /* reset interrupt callback */
1116 if (intr_handle && (intr_handle->fd) &&
1117 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1118 /*disable dpni irqs */
1119 dpaa2_eth_setup_irqs(dev, 0);
1121 /* disable vfio intr before callback unregister */
1122 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1124 /* Unregistering LSC interrupt handler */
1125 rte_intr_callback_unregister(intr_handle,
1126 dpaa2_interrupt_handler,
1130 dpaa2_dev_set_link_down(dev);
1132 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1134 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1139 /* clear the recorded link status */
1140 memset(&link, 0, sizeof(link));
1141 rte_eth_linkstatus_set(dev, &link);
1145 dpaa2_dev_close(struct rte_eth_dev *dev)
1147 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1148 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1150 struct rte_eth_link link;
1152 PMD_INIT_FUNC_TRACE();
1154 dpaa2_flow_clean(dev);
1156 /* Clean the device first */
1157 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1159 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1163 memset(&link, 0, sizeof(link));
1164 rte_eth_linkstatus_set(dev, &link);
1168 dpaa2_dev_promiscuous_enable(
1169 struct rte_eth_dev *dev)
1172 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1173 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1175 PMD_INIT_FUNC_TRACE();
1178 DPAA2_PMD_ERR("dpni is NULL");
1182 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1184 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1186 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1188 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1194 dpaa2_dev_promiscuous_disable(
1195 struct rte_eth_dev *dev)
1198 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1199 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1201 PMD_INIT_FUNC_TRACE();
1204 DPAA2_PMD_ERR("dpni is NULL");
1208 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1210 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1212 if (dev->data->all_multicast == 0) {
1213 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1214 priv->token, false);
1216 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1224 dpaa2_dev_allmulticast_enable(
1225 struct rte_eth_dev *dev)
1228 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1229 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1231 PMD_INIT_FUNC_TRACE();
1234 DPAA2_PMD_ERR("dpni is NULL");
1238 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1240 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1246 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1249 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1250 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1252 PMD_INIT_FUNC_TRACE();
1255 DPAA2_PMD_ERR("dpni is NULL");
1259 /* must remain on for all promiscuous */
1260 if (dev->data->promiscuous == 1)
1263 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1265 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1271 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1274 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1275 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1276 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1279 PMD_INIT_FUNC_TRACE();
1282 DPAA2_PMD_ERR("dpni is NULL");
1286 /* check that mtu is within the allowed range */
1287 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1290 if (frame_size > RTE_ETHER_MAX_LEN)
1291 dev->data->dev_conf.rxmode.offloads &=
1292 DEV_RX_OFFLOAD_JUMBO_FRAME;
1294 dev->data->dev_conf.rxmode.offloads &=
1295 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1297 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1299 /* Set the Max Rx frame length as 'mtu' +
1300 * Maximum Ethernet header length
1302 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1303 frame_size - RTE_ETHER_CRC_LEN);
1305 DPAA2_PMD_ERR("Setting the max frame length failed");
1308 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1313 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1314 struct rte_ether_addr *addr,
1315 __rte_unused uint32_t index,
1316 __rte_unused uint32_t pool)
1319 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1320 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1322 PMD_INIT_FUNC_TRACE();
1325 DPAA2_PMD_ERR("dpni is NULL");
1329 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1330 addr->addr_bytes, 0, 0, 0);
1333 "error: Adding the MAC ADDR failed: err = %d", ret);
1338 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1342 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1343 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1344 struct rte_eth_dev_data *data = dev->data;
1345 struct rte_ether_addr *macaddr;
1347 PMD_INIT_FUNC_TRACE();
1349 macaddr = &data->mac_addrs[index];
1352 DPAA2_PMD_ERR("dpni is NULL");
1356 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1357 priv->token, macaddr->addr_bytes);
1360 "error: Removing the MAC ADDR failed: err = %d", ret);
1364 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1365 struct rte_ether_addr *addr)
1368 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1369 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1371 PMD_INIT_FUNC_TRACE();
1374 DPAA2_PMD_ERR("dpni is NULL");
1378 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1379 priv->token, addr->addr_bytes);
1383 "error: Setting the MAC ADDR failed %d", ret);
1389 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1390 struct rte_eth_stats *stats)
1392 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1393 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1395 uint8_t page0 = 0, page1 = 1, page2 = 2;
1396 union dpni_statistics value;
1398 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1400 memset(&value, 0, sizeof(union dpni_statistics));
1402 PMD_INIT_FUNC_TRACE();
1405 DPAA2_PMD_ERR("dpni is NULL");
1410 DPAA2_PMD_ERR("stats is NULL");
1414 /*Get Counters from page_0*/
1415 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1420 stats->ipackets = value.page_0.ingress_all_frames;
1421 stats->ibytes = value.page_0.ingress_all_bytes;
1423 /*Get Counters from page_1*/
1424 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1429 stats->opackets = value.page_1.egress_all_frames;
1430 stats->obytes = value.page_1.egress_all_bytes;
1432 /*Get Counters from page_2*/
1433 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1438 /* Ingress drop frame count due to configured rules */
1439 stats->ierrors = value.page_2.ingress_filtered_frames;
1440 /* Ingress drop frame count due to error */
1441 stats->ierrors += value.page_2.ingress_discarded_frames;
1443 stats->oerrors = value.page_2.egress_discarded_frames;
1444 stats->imissed = value.page_2.ingress_nobuffer_discards;
1446 /* Fill in per queue stats */
1447 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1448 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1449 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1450 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1452 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1454 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1456 /* Byte counting is not implemented */
1457 stats->q_ibytes[i] = 0;
1458 stats->q_obytes[i] = 0;
1464 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1469 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1472 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1473 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1475 union dpni_statistics value[5] = {};
1476 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1484 /* Get Counters from page_0*/
1485 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1490 /* Get Counters from page_1*/
1491 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1496 /* Get Counters from page_2*/
1497 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1502 for (i = 0; i < priv->max_cgs; i++) {
1503 if (!priv->cgid_in_use[i]) {
1504 /* Get Counters from page_4*/
1505 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1514 for (i = 0; i < num; i++) {
1516 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1517 raw.counter[dpaa2_xstats_strings[i].stats_id];
1521 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1526 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1527 struct rte_eth_xstat_name *xstats_names,
1530 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1532 if (limit < stat_cnt)
1535 if (xstats_names != NULL)
1536 for (i = 0; i < stat_cnt; i++)
1537 strlcpy(xstats_names[i].name,
1538 dpaa2_xstats_strings[i].name,
1539 sizeof(xstats_names[i].name));
1545 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1546 uint64_t *values, unsigned int n)
1548 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1549 uint64_t values_copy[stat_cnt];
1552 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1553 struct fsl_mc_io *dpni =
1554 (struct fsl_mc_io *)dev->process_private;
1556 union dpni_statistics value[5] = {};
1564 /* Get Counters from page_0*/
1565 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1570 /* Get Counters from page_1*/
1571 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1576 /* Get Counters from page_2*/
1577 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1582 /* Get Counters from page_4*/
1583 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1588 for (i = 0; i < stat_cnt; i++) {
1589 values[i] = value[dpaa2_xstats_strings[i].page_id].
1590 raw.counter[dpaa2_xstats_strings[i].stats_id];
1595 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1597 for (i = 0; i < n; i++) {
1598 if (ids[i] >= stat_cnt) {
1599 DPAA2_PMD_ERR("xstats id value isn't valid");
1602 values[i] = values_copy[ids[i]];
1608 dpaa2_xstats_get_names_by_id(
1609 struct rte_eth_dev *dev,
1610 struct rte_eth_xstat_name *xstats_names,
1611 const uint64_t *ids,
1614 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1615 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1618 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1620 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1622 for (i = 0; i < limit; i++) {
1623 if (ids[i] >= stat_cnt) {
1624 DPAA2_PMD_ERR("xstats id value isn't valid");
1627 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1633 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1635 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1636 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1639 struct dpaa2_queue *dpaa2_q;
1641 PMD_INIT_FUNC_TRACE();
1644 DPAA2_PMD_ERR("dpni is NULL");
1648 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1652 /* Reset the per queue stats in dpaa2_queue structure */
1653 for (i = 0; i < priv->nb_rx_queues; i++) {
1654 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1656 dpaa2_q->rx_pkts = 0;
1659 for (i = 0; i < priv->nb_tx_queues; i++) {
1660 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1662 dpaa2_q->tx_pkts = 0;
1668 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1672 /* return 0 means link status changed, -1 means not changed */
1674 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1675 int wait_to_complete __rte_unused)
1678 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1679 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1680 struct rte_eth_link link;
1681 struct dpni_link_state state = {0};
1684 DPAA2_PMD_ERR("dpni is NULL");
1688 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1690 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1694 memset(&link, 0, sizeof(struct rte_eth_link));
1695 link.link_status = state.up;
1696 link.link_speed = state.rate;
1698 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1699 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1701 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1703 ret = rte_eth_linkstatus_set(dev, &link);
1705 DPAA2_PMD_DEBUG("No change in status");
1707 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1708 link.link_status ? "Up" : "Down");
1714 * Toggle the DPNI to enable, if not already enabled.
1715 * This is not strictly PHY up/down - it is more of logical toggling.
1718 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1721 struct dpaa2_dev_priv *priv;
1722 struct fsl_mc_io *dpni;
1724 struct dpni_link_state state = {0};
1726 priv = dev->data->dev_private;
1727 dpni = (struct fsl_mc_io *)dev->process_private;
1730 DPAA2_PMD_ERR("dpni is NULL");
1734 /* Check if DPNI is currently enabled */
1735 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1737 /* Unable to obtain dpni status; Not continuing */
1738 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1742 /* Enable link if not already enabled */
1744 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1746 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1750 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1752 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1756 /* changing tx burst function to start enqueues */
1757 dev->tx_pkt_burst = dpaa2_dev_tx;
1758 dev->data->dev_link.link_status = state.up;
1761 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1763 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1768 * Toggle the DPNI to disable, if not already disabled.
1769 * This is not strictly PHY up/down - it is more of logical toggling.
1772 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1775 struct dpaa2_dev_priv *priv;
1776 struct fsl_mc_io *dpni;
1777 int dpni_enabled = 0;
1780 PMD_INIT_FUNC_TRACE();
1782 priv = dev->data->dev_private;
1783 dpni = (struct fsl_mc_io *)dev->process_private;
1786 DPAA2_PMD_ERR("Device has not yet been configured");
1790 /*changing tx burst function to avoid any more enqueues */
1791 dev->tx_pkt_burst = dummy_dev_tx;
1793 /* Loop while dpni_disable() attempts to drain the egress FQs
1794 * and confirm them back to us.
1797 ret = dpni_disable(dpni, 0, priv->token);
1799 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1802 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1804 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1808 /* Allow the MC some slack */
1809 rte_delay_us(100 * 1000);
1810 } while (dpni_enabled && --retries);
1813 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1814 /* todo- we may have to manually cleanup queues.
1817 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1818 dev->data->port_id);
1821 dev->data->dev_link.link_status = 0;
1827 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1830 struct dpaa2_dev_priv *priv;
1831 struct fsl_mc_io *dpni;
1832 struct dpni_link_state state = {0};
1834 PMD_INIT_FUNC_TRACE();
1836 priv = dev->data->dev_private;
1837 dpni = (struct fsl_mc_io *)dev->process_private;
1839 if (dpni == NULL || fc_conf == NULL) {
1840 DPAA2_PMD_ERR("device not configured");
1844 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1846 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1850 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1851 if (state.options & DPNI_LINK_OPT_PAUSE) {
1852 /* DPNI_LINK_OPT_PAUSE set
1853 * if ASYM_PAUSE not set,
1854 * RX Side flow control (handle received Pause frame)
1855 * TX side flow control (send Pause frame)
1856 * if ASYM_PAUSE set,
1857 * RX Side flow control (handle received Pause frame)
1858 * No TX side flow control (send Pause frame disabled)
1860 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1861 fc_conf->mode = RTE_FC_FULL;
1863 fc_conf->mode = RTE_FC_RX_PAUSE;
1865 /* DPNI_LINK_OPT_PAUSE not set
1866 * if ASYM_PAUSE set,
1867 * TX side flow control (send Pause frame)
1868 * No RX side flow control (No action on pause frame rx)
1869 * if ASYM_PAUSE not set,
1870 * Flow control disabled
1872 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
1873 fc_conf->mode = RTE_FC_TX_PAUSE;
1875 fc_conf->mode = RTE_FC_NONE;
1882 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1885 struct dpaa2_dev_priv *priv;
1886 struct fsl_mc_io *dpni;
1887 struct dpni_link_state state = {0};
1888 struct dpni_link_cfg cfg = {0};
1890 PMD_INIT_FUNC_TRACE();
1892 priv = dev->data->dev_private;
1893 dpni = (struct fsl_mc_io *)dev->process_private;
1896 DPAA2_PMD_ERR("dpni is NULL");
1900 /* It is necessary to obtain the current state before setting fc_conf
1901 * as MC would return error in case rate, autoneg or duplex values are
1904 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1906 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
1910 /* Disable link before setting configuration */
1911 dpaa2_dev_set_link_down(dev);
1913 /* Based on fc_conf, update cfg */
1914 cfg.rate = state.rate;
1915 cfg.options = state.options;
1917 /* update cfg with fc_conf */
1918 switch (fc_conf->mode) {
1920 /* Full flow control;
1921 * OPT_PAUSE set, ASYM_PAUSE not set
1923 cfg.options |= DPNI_LINK_OPT_PAUSE;
1924 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1926 case RTE_FC_TX_PAUSE:
1927 /* Enable RX flow control
1928 * OPT_PAUSE not set;
1931 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1932 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1934 case RTE_FC_RX_PAUSE:
1935 /* Enable TX Flow control
1939 cfg.options |= DPNI_LINK_OPT_PAUSE;
1940 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1943 /* Disable Flow control
1945 * ASYM_PAUSE not set
1947 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1948 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1951 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
1956 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
1958 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
1962 dpaa2_dev_set_link_up(dev);
1968 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
1969 struct rte_eth_rss_conf *rss_conf)
1971 struct rte_eth_dev_data *data = dev->data;
1972 struct rte_eth_conf *eth_conf = &data->dev_conf;
1975 PMD_INIT_FUNC_TRACE();
1977 if (rss_conf->rss_hf) {
1978 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf);
1980 DPAA2_PMD_ERR("Unable to set flow dist");
1984 ret = dpaa2_remove_flow_dist(dev, 0);
1986 DPAA2_PMD_ERR("Unable to remove flow dist");
1990 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1995 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1996 struct rte_eth_rss_conf *rss_conf)
1998 struct rte_eth_dev_data *data = dev->data;
1999 struct rte_eth_conf *eth_conf = &data->dev_conf;
2001 /* dpaa2 does not support rss_key, so length should be 0*/
2002 rss_conf->rss_key_len = 0;
2003 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2007 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2008 int eth_rx_queue_id,
2009 struct dpaa2_dpcon_dev *dpcon,
2010 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2012 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2013 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2014 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2015 uint8_t flow_id = dpaa2_ethq->flow_id;
2016 struct dpni_queue cfg;
2017 uint8_t options, priority;
2020 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2021 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2022 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2023 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2024 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2025 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2029 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2030 (dpcon->num_priorities - 1);
2032 memset(&cfg, 0, sizeof(struct dpni_queue));
2033 options = DPNI_QUEUE_OPT_DEST;
2034 cfg.destination.type = DPNI_DEST_DPCON;
2035 cfg.destination.id = dpcon->dpcon_id;
2036 cfg.destination.priority = priority;
2038 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2039 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2040 cfg.destination.hold_active = 1;
2043 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2044 !eth_priv->en_ordered) {
2045 struct opr_cfg ocfg;
2047 /* Restoration window size = 256 frames */
2049 /* Restoration window size = 512 frames for LX2 */
2050 if (dpaa2_svr_family == SVR_LX2160A)
2052 /* Auto advance NESN window enabled */
2054 /* Late arrival window size disabled */
2056 /* ORL resource exhaustaion advance NESN disabled */
2058 /* Loose ordering enabled */
2060 eth_priv->en_loose_ordered = 1;
2061 /* Strict ordering enabled if explicitly set */
2062 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2064 eth_priv->en_loose_ordered = 0;
2067 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2068 dpaa2_ethq->tc_index, flow_id,
2069 OPR_OPT_CREATE, &ocfg);
2071 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2075 eth_priv->en_ordered = 1;
2078 options |= DPNI_QUEUE_OPT_USER_CTX;
2079 cfg.user_context = (size_t)(dpaa2_ethq);
2081 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2082 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2084 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2088 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2093 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2094 int eth_rx_queue_id)
2096 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2097 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2098 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2099 uint8_t flow_id = dpaa2_ethq->flow_id;
2100 struct dpni_queue cfg;
2104 memset(&cfg, 0, sizeof(struct dpni_queue));
2105 options = DPNI_QUEUE_OPT_DEST;
2106 cfg.destination.type = DPNI_DEST_NONE;
2108 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2109 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2111 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2117 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2121 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2122 if (dpaa2_supported_filter_ops[i] == filter_op)
2129 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2130 enum rte_filter_type filter_type,
2131 enum rte_filter_op filter_op,
2139 switch (filter_type) {
2140 case RTE_ETH_FILTER_GENERIC:
2141 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2145 *(const void **)arg = &dpaa2_flow_ops;
2146 dpaa2_filter_type |= filter_type;
2149 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2157 static struct eth_dev_ops dpaa2_ethdev_ops = {
2158 .dev_configure = dpaa2_eth_dev_configure,
2159 .dev_start = dpaa2_dev_start,
2160 .dev_stop = dpaa2_dev_stop,
2161 .dev_close = dpaa2_dev_close,
2162 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2163 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2164 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2165 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2166 .dev_set_link_up = dpaa2_dev_set_link_up,
2167 .dev_set_link_down = dpaa2_dev_set_link_down,
2168 .link_update = dpaa2_dev_link_update,
2169 .stats_get = dpaa2_dev_stats_get,
2170 .xstats_get = dpaa2_dev_xstats_get,
2171 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2172 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2173 .xstats_get_names = dpaa2_xstats_get_names,
2174 .stats_reset = dpaa2_dev_stats_reset,
2175 .xstats_reset = dpaa2_dev_stats_reset,
2176 .fw_version_get = dpaa2_fw_version_get,
2177 .dev_infos_get = dpaa2_dev_info_get,
2178 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2179 .mtu_set = dpaa2_dev_mtu_set,
2180 .vlan_filter_set = dpaa2_vlan_filter_set,
2181 .vlan_offload_set = dpaa2_vlan_offload_set,
2182 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2183 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2184 .rx_queue_release = dpaa2_dev_rx_queue_release,
2185 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2186 .tx_queue_release = dpaa2_dev_tx_queue_release,
2187 .rx_queue_count = dpaa2_dev_rx_queue_count,
2188 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2189 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2190 .mac_addr_add = dpaa2_dev_add_mac_addr,
2191 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2192 .mac_addr_set = dpaa2_dev_set_mac_addr,
2193 .rss_hash_update = dpaa2_dev_rss_hash_update,
2194 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2195 .filter_ctrl = dpaa2_dev_flow_ctrl,
2196 #if defined(RTE_LIBRTE_IEEE1588)
2197 .timesync_enable = dpaa2_timesync_enable,
2198 .timesync_disable = dpaa2_timesync_disable,
2199 .timesync_read_time = dpaa2_timesync_read_time,
2200 .timesync_write_time = dpaa2_timesync_write_time,
2201 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2202 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2203 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2207 /* Populate the mac address from physically available (u-boot/firmware) and/or
2208 * one set by higher layers like MC (restool) etc.
2209 * Returns the table of MAC entries (multiple entries)
2212 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2213 struct rte_ether_addr *mac_entry)
2216 struct rte_ether_addr phy_mac, prime_mac;
2218 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2219 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2221 /* Get the physical device MAC address */
2222 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2223 phy_mac.addr_bytes);
2225 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2229 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2230 prime_mac.addr_bytes);
2232 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2236 /* Now that both MAC have been obtained, do:
2237 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2239 * If empty_mac(phy), return prime.
2240 * if both are empty, create random MAC, set as prime and return
2242 if (!rte_is_zero_ether_addr(&phy_mac)) {
2243 /* If the addresses are not same, overwrite prime */
2244 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2245 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2247 phy_mac.addr_bytes);
2249 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2253 memcpy(&prime_mac, &phy_mac,
2254 sizeof(struct rte_ether_addr));
2256 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2257 /* In case phys and prime, both are zero, create random MAC */
2258 rte_eth_random_addr(prime_mac.addr_bytes);
2259 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2261 prime_mac.addr_bytes);
2263 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2268 /* prime_mac the final MAC address */
2269 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2277 check_devargs_handler(__rte_unused const char *key, const char *value,
2278 __rte_unused void *opaque)
2280 if (strcmp(value, "1"))
2287 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2289 struct rte_kvargs *kvlist;
2294 kvlist = rte_kvargs_parse(devargs->args, NULL);
2298 if (!rte_kvargs_count(kvlist, key)) {
2299 rte_kvargs_free(kvlist);
2303 if (rte_kvargs_process(kvlist, key,
2304 check_devargs_handler, NULL) < 0) {
2305 rte_kvargs_free(kvlist);
2308 rte_kvargs_free(kvlist);
2314 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2316 struct rte_device *dev = eth_dev->device;
2317 struct rte_dpaa2_device *dpaa2_dev;
2318 struct fsl_mc_io *dpni_dev;
2319 struct dpni_attr attr;
2320 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2321 struct dpni_buffer_layout layout;
2324 PMD_INIT_FUNC_TRACE();
2326 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2328 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2331 dpni_dev->regs = rte_mcp_ptr_list[0];
2332 eth_dev->process_private = (void *)dpni_dev;
2334 /* For secondary processes, the primary has done all the work */
2335 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2336 /* In case of secondary, only burst and ops API need to be
2339 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2340 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2341 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2342 else if (dpaa2_get_devargs(dev->devargs,
2343 DRIVER_NO_PREFETCH_MODE))
2344 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2346 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2347 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2351 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2353 hw_id = dpaa2_dev->object_id;
2354 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2357 "Failure in opening dpni@%d with err code %d",
2363 /* Clean the device first */
2364 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2366 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2371 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2374 "Failure in get dpni@%d attribute, err code %d",
2379 priv->num_rx_tc = attr.num_rx_tcs;
2380 /* only if the custom CG is enabled */
2381 if (attr.options & DPNI_OPT_CUSTOM_CG)
2382 priv->max_cgs = attr.num_cgs;
2386 for (i = 0; i < priv->max_cgs; i++)
2387 priv->cgid_in_use[i] = 0;
2389 for (i = 0; i < attr.num_rx_tcs; i++)
2390 priv->nb_rx_queues += attr.num_queues;
2392 /* Using number of TX queues as number of TX TCs */
2393 priv->nb_tx_queues = attr.num_tx_tcs;
2395 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2396 priv->num_rx_tc, priv->nb_rx_queues,
2397 priv->nb_tx_queues, priv->max_cgs);
2399 priv->hw = dpni_dev;
2400 priv->hw_id = hw_id;
2401 priv->options = attr.options;
2402 priv->max_mac_filters = attr.mac_filter_entries;
2403 priv->max_vlan_filters = attr.vlan_filter_entries;
2405 #if defined(RTE_LIBRTE_IEEE1588)
2406 priv->tx_conf_en = 1;
2408 priv->tx_conf_en = 0;
2411 /* Allocate memory for hardware structure for queues */
2412 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2414 DPAA2_PMD_ERR("Queue allocation Failed");
2418 /* Allocate memory for storing MAC addresses.
2419 * Table of mac_filter_entries size is allocated so that RTE ether lib
2420 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2422 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2423 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2424 if (eth_dev->data->mac_addrs == NULL) {
2426 "Failed to allocate %d bytes needed to store MAC addresses",
2427 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2432 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2434 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2435 rte_free(eth_dev->data->mac_addrs);
2436 eth_dev->data->mac_addrs = NULL;
2440 /* ... tx buffer layout ... */
2441 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2442 if (priv->tx_conf_en) {
2443 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2444 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2445 layout.pass_timestamp = true;
2447 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2449 layout.pass_frame_status = 1;
2450 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2451 DPNI_QUEUE_TX, &layout);
2453 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2457 /* ... tx-conf and error buffer layout ... */
2458 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2459 if (priv->tx_conf_en) {
2460 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2461 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2462 layout.pass_timestamp = true;
2464 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2466 layout.pass_frame_status = 1;
2467 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2468 DPNI_QUEUE_TX_CONFIRM, &layout);
2470 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2475 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2477 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2478 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2479 DPAA2_PMD_INFO("Loopback mode");
2480 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2481 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2482 DPAA2_PMD_INFO("No Prefetch mode");
2484 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2486 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2488 /*Init fields w.r.t. classficaition*/
2489 memset(&priv->extract.qos_key_cfg, 0, sizeof(struct dpkg_profile_cfg));
2490 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2491 if (!priv->extract.qos_extract_param) {
2492 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2493 " classificaiton ", ret);
2496 for (i = 0; i < MAX_TCS; i++) {
2497 memset(&priv->extract.fs_key_cfg[i], 0,
2498 sizeof(struct dpkg_profile_cfg));
2499 priv->extract.fs_extract_param[i] =
2500 (size_t)rte_malloc(NULL, 256, 64);
2501 if (!priv->extract.fs_extract_param[i]) {
2502 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2508 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2509 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2512 DPAA2_PMD_ERR("Unable to set mtu. check config");
2516 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2517 * with external entity to receive byte code for software sequence
2518 * and same will be offload to the H/W using MC interface.
2519 * Currently it is assumed that DPAA2 driver has byte code by some
2520 * mean and same if offloaded to H/W.
2522 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2523 WRIOP_SS_INITIALIZER(priv);
2524 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2526 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2531 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2534 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2539 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2542 dpaa2_dev_uninit(eth_dev);
2547 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev)
2549 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2550 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_dev->process_private;
2553 PMD_INIT_FUNC_TRACE();
2555 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2559 DPAA2_PMD_WARN("Already closed or not started");
2563 dpaa2_dev_close(eth_dev);
2565 dpaa2_free_rx_tx_queues(eth_dev);
2567 /* Close the device at underlying layer*/
2568 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
2571 "Failure closing dpni device with err code %d",
2575 /* Free the allocated memory for ethernet private data and dpni*/
2577 eth_dev->process_private = NULL;
2580 for (i = 0; i < MAX_TCS; i++) {
2581 if (priv->extract.fs_extract_param[i])
2582 rte_free((void *)(size_t)priv->extract.fs_extract_param[i]);
2585 if (priv->extract.qos_extract_param)
2586 rte_free((void *)(size_t)priv->extract.qos_extract_param);
2588 eth_dev->dev_ops = NULL;
2589 eth_dev->rx_pkt_burst = NULL;
2590 eth_dev->tx_pkt_burst = NULL;
2592 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name);
2597 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2598 struct rte_dpaa2_device *dpaa2_dev)
2600 struct rte_eth_dev *eth_dev;
2601 struct dpaa2_dev_priv *dev_priv;
2604 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2605 RTE_PKTMBUF_HEADROOM) {
2607 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2608 RTE_PKTMBUF_HEADROOM,
2609 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2614 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2615 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2618 dev_priv = rte_zmalloc("ethdev private structure",
2619 sizeof(struct dpaa2_dev_priv),
2620 RTE_CACHE_LINE_SIZE);
2621 if (dev_priv == NULL) {
2623 "Unable to allocate memory for private data");
2624 rte_eth_dev_release_port(eth_dev);
2627 eth_dev->data->dev_private = (void *)dev_priv;
2628 /* Store a pointer to eth_dev in dev_private */
2629 dev_priv->eth_dev = eth_dev;
2630 dev_priv->tx_conf_en = 0;
2632 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2634 DPAA2_PMD_DEBUG("returning enodev");
2639 eth_dev->device = &dpaa2_dev->device;
2641 dpaa2_dev->eth_dev = eth_dev;
2642 eth_dev->data->rx_mbuf_alloc_failed = 0;
2644 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2645 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2647 /* Invoke PMD device initialization function */
2648 diag = dpaa2_dev_init(eth_dev);
2650 rte_eth_dev_probing_finish(eth_dev);
2654 rte_eth_dev_release_port(eth_dev);
2659 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2661 struct rte_eth_dev *eth_dev;
2663 eth_dev = dpaa2_dev->eth_dev;
2664 dpaa2_dev_uninit(eth_dev);
2666 rte_eth_dev_release_port(eth_dev);
2671 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2672 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2673 .drv_type = DPAA2_ETH,
2674 .probe = rte_dpaa2_probe,
2675 .remove = rte_dpaa2_remove,
2678 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2679 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2680 DRIVER_LOOPBACK_MODE "=<int> "
2681 DRIVER_NO_PREFETCH_MODE "=<int>");
2682 RTE_INIT(dpaa2_pmd_init_log)
2684 dpaa2_logtype_pmd = rte_log_register("pmd.net.dpaa2");
2685 if (dpaa2_logtype_pmd >= 0)
2686 rte_log_set_level(dpaa2_logtype_pmd, RTE_LOG_NOTICE);