1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
12 #include <rte_ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
35 /* Supported Rx offloads */
36 static uint64_t dev_rx_offloads_sup =
37 DEV_RX_OFFLOAD_CHECKSUM |
38 DEV_RX_OFFLOAD_SCTP_CKSUM |
39 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
40 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
41 DEV_RX_OFFLOAD_VLAN_STRIP |
42 DEV_RX_OFFLOAD_VLAN_FILTER |
43 DEV_RX_OFFLOAD_JUMBO_FRAME |
44 DEV_RX_OFFLOAD_TIMESTAMP;
46 /* Rx offloads which cannot be disabled */
47 static uint64_t dev_rx_offloads_nodis =
48 DEV_RX_OFFLOAD_RSS_HASH |
49 DEV_RX_OFFLOAD_SCATTER;
51 /* Supported Tx offloads */
52 static uint64_t dev_tx_offloads_sup =
53 DEV_TX_OFFLOAD_VLAN_INSERT |
54 DEV_TX_OFFLOAD_IPV4_CKSUM |
55 DEV_TX_OFFLOAD_UDP_CKSUM |
56 DEV_TX_OFFLOAD_TCP_CKSUM |
57 DEV_TX_OFFLOAD_SCTP_CKSUM |
58 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
59 DEV_TX_OFFLOAD_MT_LOCKFREE |
60 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
62 /* Tx offloads which cannot be disabled */
63 static uint64_t dev_tx_offloads_nodis =
64 DEV_TX_OFFLOAD_MULTI_SEGS;
66 /* enable timestamp in mbuf */
67 enum pmd_dpaa2_ts dpaa2_enable_ts;
69 struct rte_dpaa2_xstats_name_off {
70 char name[RTE_ETH_XSTATS_NAME_SIZE];
71 uint8_t page_id; /* dpni statistics page id */
72 uint8_t stats_id; /* stats id in the given page */
75 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
76 {"ingress_multicast_frames", 0, 2},
77 {"ingress_multicast_bytes", 0, 3},
78 {"ingress_broadcast_frames", 0, 4},
79 {"ingress_broadcast_bytes", 0, 5},
80 {"egress_multicast_frames", 1, 2},
81 {"egress_multicast_bytes", 1, 3},
82 {"egress_broadcast_frames", 1, 4},
83 {"egress_broadcast_bytes", 1, 5},
84 {"ingress_filtered_frames", 2, 0},
85 {"ingress_discarded_frames", 2, 1},
86 {"ingress_nobuffer_discards", 2, 2},
87 {"egress_discarded_frames", 2, 3},
88 {"egress_confirmed_frames", 2, 4},
89 {"cgr_reject_frames", 4, 0},
90 {"cgr_reject_bytes", 4, 1},
93 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
95 RTE_ETH_FILTER_DELETE,
96 RTE_ETH_FILTER_UPDATE,
101 static struct rte_dpaa2_driver rte_dpaa2_pmd;
102 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev);
103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
104 int wait_to_complete);
105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
109 int dpaa2_logtype_pmd;
112 rte_pmd_dpaa2_set_timestamp(enum pmd_dpaa2_ts enable)
114 dpaa2_enable_ts = enable;
118 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
121 struct dpaa2_dev_priv *priv = dev->data->dev_private;
122 struct fsl_mc_io *dpni = dev->process_private;
124 PMD_INIT_FUNC_TRACE();
127 DPAA2_PMD_ERR("dpni is NULL");
132 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
135 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
136 priv->token, vlan_id);
139 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
140 ret, vlan_id, priv->hw_id);
146 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
148 struct dpaa2_dev_priv *priv = dev->data->dev_private;
149 struct fsl_mc_io *dpni = dev->process_private;
152 PMD_INIT_FUNC_TRACE();
154 if (mask & ETH_VLAN_FILTER_MASK) {
155 /* VLAN Filter not avaialble */
156 if (!priv->max_vlan_filters) {
157 DPAA2_PMD_INFO("VLAN filter not available");
161 if (dev->data->dev_conf.rxmode.offloads &
162 DEV_RX_OFFLOAD_VLAN_FILTER)
163 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
166 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
169 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
172 if (mask & ETH_VLAN_EXTEND_MASK) {
173 if (dev->data->dev_conf.rxmode.offloads &
174 DEV_RX_OFFLOAD_VLAN_EXTEND)
175 DPAA2_PMD_INFO("VLAN extend offload not supported");
182 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
183 enum rte_vlan_type vlan_type __rte_unused,
186 struct dpaa2_dev_priv *priv = dev->data->dev_private;
187 struct fsl_mc_io *dpni = dev->process_private;
190 PMD_INIT_FUNC_TRACE();
192 /* nothing to be done for standard vlan tpids */
193 if (tpid == 0x8100 || tpid == 0x88A8)
196 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
199 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
200 /* if already configured tpids, remove them first */
202 struct dpni_custom_tpid_cfg tpid_list = {0};
204 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
205 priv->token, &tpid_list);
208 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
209 priv->token, tpid_list.tpid1);
212 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
220 dpaa2_fw_version_get(struct rte_eth_dev *dev,
225 struct fsl_mc_io *dpni = dev->process_private;
226 struct mc_soc_version mc_plat_info = {0};
227 struct mc_version mc_ver_info = {0};
229 PMD_INIT_FUNC_TRACE();
231 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
232 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
234 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
235 DPAA2_PMD_WARN("\tmc_get_version failed");
237 ret = snprintf(fw_version, fw_size,
242 mc_ver_info.revision);
244 ret += 1; /* add the size of '\0' */
245 if (fw_size < (uint32_t)ret)
252 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
254 struct dpaa2_dev_priv *priv = dev->data->dev_private;
256 PMD_INIT_FUNC_TRACE();
258 dev_info->if_index = priv->hw_id;
260 dev_info->max_mac_addrs = priv->max_mac_filters;
261 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
262 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
263 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
264 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
265 dev_info->rx_offload_capa = dev_rx_offloads_sup |
266 dev_rx_offloads_nodis;
267 dev_info->tx_offload_capa = dev_tx_offloads_sup |
268 dev_tx_offloads_nodis;
269 dev_info->speed_capa = ETH_LINK_SPEED_1G |
270 ETH_LINK_SPEED_2_5G |
273 dev_info->max_hash_mac_addrs = 0;
274 dev_info->max_vfs = 0;
275 dev_info->max_vmdq_pools = ETH_16_POOLS;
276 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
278 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
279 /* same is rx size for best perf */
280 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
282 dev_info->default_rxportconf.nb_queues = 1;
283 dev_info->default_txportconf.nb_queues = 1;
284 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
285 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
291 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
293 struct dpaa2_dev_priv *priv = dev->data->dev_private;
296 uint8_t num_rxqueue_per_tc;
297 struct dpaa2_queue *mc_q, *mcq;
300 struct dpaa2_queue *dpaa2_q;
302 PMD_INIT_FUNC_TRACE();
304 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
305 if (priv->tx_conf_en)
306 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
308 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
309 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
310 RTE_CACHE_LINE_SIZE);
312 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
316 for (i = 0; i < priv->nb_rx_queues; i++) {
317 mc_q->eth_data = dev->data;
318 priv->rx_vq[i] = mc_q++;
319 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
320 dpaa2_q->q_storage = rte_malloc("dq_storage",
321 sizeof(struct queue_storage_info_t),
322 RTE_CACHE_LINE_SIZE);
323 if (!dpaa2_q->q_storage)
326 memset(dpaa2_q->q_storage, 0,
327 sizeof(struct queue_storage_info_t));
328 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
332 for (i = 0; i < priv->nb_tx_queues; i++) {
333 mc_q->eth_data = dev->data;
334 mc_q->flow_id = 0xffff;
335 priv->tx_vq[i] = mc_q++;
336 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
337 dpaa2_q->cscn = rte_malloc(NULL,
338 sizeof(struct qbman_result), 16);
343 if (priv->tx_conf_en) {
344 /*Setup tx confirmation queues*/
345 for (i = 0; i < priv->nb_tx_queues; i++) {
346 mc_q->eth_data = dev->data;
349 priv->tx_conf_vq[i] = mc_q++;
350 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
352 rte_malloc("dq_storage",
353 sizeof(struct queue_storage_info_t),
354 RTE_CACHE_LINE_SIZE);
355 if (!dpaa2_q->q_storage)
358 memset(dpaa2_q->q_storage, 0,
359 sizeof(struct queue_storage_info_t));
360 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
366 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
367 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
368 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
369 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
377 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
378 rte_free(dpaa2_q->q_storage);
379 priv->tx_conf_vq[i--] = NULL;
381 i = priv->nb_tx_queues;
385 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
386 rte_free(dpaa2_q->cscn);
387 priv->tx_vq[i--] = NULL;
389 i = priv->nb_rx_queues;
392 mc_q = priv->rx_vq[0];
394 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
395 dpaa2_free_dq_storage(dpaa2_q->q_storage);
396 rte_free(dpaa2_q->q_storage);
397 priv->rx_vq[i--] = NULL;
404 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
406 struct dpaa2_dev_priv *priv = dev->data->dev_private;
407 struct dpaa2_queue *dpaa2_q;
410 PMD_INIT_FUNC_TRACE();
412 /* Queue allocation base */
413 if (priv->rx_vq[0]) {
414 /* cleaning up queue storage */
415 for (i = 0; i < priv->nb_rx_queues; i++) {
416 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
417 if (dpaa2_q->q_storage)
418 rte_free(dpaa2_q->q_storage);
420 /* cleanup tx queue cscn */
421 for (i = 0; i < priv->nb_tx_queues; i++) {
422 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
423 rte_free(dpaa2_q->cscn);
425 if (priv->tx_conf_en) {
426 /* cleanup tx conf queue storage */
427 for (i = 0; i < priv->nb_tx_queues; i++) {
428 dpaa2_q = (struct dpaa2_queue *)
430 rte_free(dpaa2_q->q_storage);
433 /*free memory for all queues (RX+TX) */
434 rte_free(priv->rx_vq[0]);
435 priv->rx_vq[0] = NULL;
440 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
442 struct dpaa2_dev_priv *priv = dev->data->dev_private;
443 struct fsl_mc_io *dpni = dev->process_private;
444 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
445 uint64_t rx_offloads = eth_conf->rxmode.offloads;
446 uint64_t tx_offloads = eth_conf->txmode.offloads;
447 int rx_l3_csum_offload = false;
448 int rx_l4_csum_offload = false;
449 int tx_l3_csum_offload = false;
450 int tx_l4_csum_offload = false;
453 PMD_INIT_FUNC_TRACE();
455 /* Rx offloads which are enabled by default */
456 if (dev_rx_offloads_nodis & ~rx_offloads) {
458 "Some of rx offloads enabled by default - requested 0x%" PRIx64
459 " fixed are 0x%" PRIx64,
460 rx_offloads, dev_rx_offloads_nodis);
463 /* Tx offloads which are enabled by default */
464 if (dev_tx_offloads_nodis & ~tx_offloads) {
466 "Some of tx offloads enabled by default - requested 0x%" PRIx64
467 " fixed are 0x%" PRIx64,
468 tx_offloads, dev_tx_offloads_nodis);
471 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
472 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
473 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
474 priv->token, eth_conf->rxmode.max_rx_pkt_len
475 - RTE_ETHER_CRC_LEN);
478 "Unable to set mtu. check config");
482 dev->data->dev_conf.rxmode.max_rx_pkt_len -
483 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
490 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
491 ret = dpaa2_setup_flow_dist(dev,
492 eth_conf->rx_adv_conf.rss_conf.rss_hf);
494 DPAA2_PMD_ERR("Unable to set flow distribution."
495 "Check queue config");
500 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
501 rx_l3_csum_offload = true;
503 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
504 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
505 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
506 rx_l4_csum_offload = true;
508 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
509 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
511 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
515 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
516 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
518 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
522 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
523 dpaa2_enable_ts = true;
525 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
526 tx_l3_csum_offload = true;
528 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
529 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
530 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
531 tx_l4_csum_offload = true;
533 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
534 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
536 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
540 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
541 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
543 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
547 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
548 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
549 * to 0 for LS2 in the hardware thus disabling data/annotation
550 * stashing. For LX2 this is fixed in hardware and thus hash result and
551 * parse results can be received in FD using this option.
553 if (dpaa2_svr_family == SVR_LX2160A) {
554 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
555 DPNI_FLCTYPE_HASH, true);
557 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
562 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
563 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
568 /* Function to setup RX flow information. It contains traffic class ID,
569 * flow ID, destination configuration etc.
572 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
573 uint16_t rx_queue_id,
575 unsigned int socket_id __rte_unused,
576 const struct rte_eth_rxconf *rx_conf __rte_unused,
577 struct rte_mempool *mb_pool)
579 struct dpaa2_dev_priv *priv = dev->data->dev_private;
580 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
581 struct dpaa2_queue *dpaa2_q;
582 struct dpni_queue cfg;
588 PMD_INIT_FUNC_TRACE();
590 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
591 dev, rx_queue_id, mb_pool, rx_conf);
593 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
594 bpid = mempool_to_bpid(mb_pool);
595 ret = dpaa2_attach_bp_list(priv,
596 rte_dpaa2_bpid_info[bpid].bp_list);
600 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
601 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
602 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
604 /*Get the flow id from given VQ id*/
605 flow_id = dpaa2_q->flow_id;
606 memset(&cfg, 0, sizeof(struct dpni_queue));
608 options = options | DPNI_QUEUE_OPT_USER_CTX;
609 cfg.user_context = (size_t)(dpaa2_q);
611 /* check if a private cgr available. */
612 for (i = 0; i < priv->max_cgs; i++) {
613 if (!priv->cgid_in_use[i]) {
614 priv->cgid_in_use[i] = 1;
619 if (i < priv->max_cgs) {
620 options |= DPNI_QUEUE_OPT_SET_CGID;
622 dpaa2_q->cgid = cfg.cgid;
624 dpaa2_q->cgid = 0xff;
627 /*if ls2088 or rev2 device, enable the stashing */
629 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
630 options |= DPNI_QUEUE_OPT_FLC;
631 cfg.flc.stash_control = true;
632 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
633 /* 00 00 00 - last 6 bit represent annotation, context stashing,
634 * data stashing setting 01 01 00 (0x14)
635 * (in following order ->DS AS CS)
636 * to enable 1 line data, 1 line annotation.
637 * For LX2, this setting should be 01 00 00 (0x10)
639 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
640 cfg.flc.value |= 0x10;
642 cfg.flc.value |= 0x14;
644 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
645 dpaa2_q->tc_index, flow_id, options, &cfg);
647 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
651 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
652 struct dpni_taildrop taildrop;
656 /* Private CGR will use tail drop length as nb_rx_desc.
657 * for rest cases we can use standard byte based tail drop.
658 * There is no HW restriction, but number of CGRs are limited,
659 * hence this restriction is placed.
661 if (dpaa2_q->cgid != 0xff) {
662 /*enabling per rx queue congestion control */
663 taildrop.threshold = nb_rx_desc;
664 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
666 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
668 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
669 DPNI_CP_CONGESTION_GROUP,
674 /*enabling per rx queue congestion control */
675 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
676 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
677 taildrop.oal = CONG_RX_OAL;
678 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
680 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
681 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
682 dpaa2_q->tc_index, flow_id,
686 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
690 } else { /* Disable tail Drop */
691 struct dpni_taildrop taildrop = {0};
692 DPAA2_PMD_INFO("Tail drop is disabled on queue");
695 if (dpaa2_q->cgid != 0xff) {
696 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
697 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
701 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
702 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
703 dpaa2_q->tc_index, flow_id, &taildrop);
706 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
712 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
717 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
718 uint16_t tx_queue_id,
719 uint16_t nb_tx_desc __rte_unused,
720 unsigned int socket_id __rte_unused,
721 const struct rte_eth_txconf *tx_conf __rte_unused)
723 struct dpaa2_dev_priv *priv = dev->data->dev_private;
724 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
725 priv->tx_vq[tx_queue_id];
726 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
727 priv->tx_conf_vq[tx_queue_id];
728 struct fsl_mc_io *dpni = dev->process_private;
729 struct dpni_queue tx_conf_cfg;
730 struct dpni_queue tx_flow_cfg;
731 uint8_t options = 0, flow_id;
732 struct dpni_queue_id qid;
736 PMD_INIT_FUNC_TRACE();
738 /* Return if queue already configured */
739 if (dpaa2_q->flow_id != 0xffff) {
740 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
744 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
745 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
750 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
751 tc_id, flow_id, options, &tx_flow_cfg);
753 DPAA2_PMD_ERR("Error in setting the tx flow: "
754 "tc_id=%d, flow=%d err=%d",
755 tc_id, flow_id, ret);
759 dpaa2_q->flow_id = flow_id;
761 if (tx_queue_id == 0) {
762 /*Set tx-conf and error configuration*/
763 if (priv->tx_conf_en)
764 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
768 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
772 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
777 dpaa2_q->tc_index = tc_id;
779 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
780 DPNI_QUEUE_TX, dpaa2_q->tc_index,
781 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
783 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
786 dpaa2_q->fqid = qid.fqid;
788 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
789 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
791 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
792 cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD;
793 /* Notify that the queue is not congested when the data in
794 * the queue is below this thershold.
796 cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD;
797 cong_notif_cfg.message_ctx = 0;
798 cong_notif_cfg.message_iova =
799 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
800 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
801 cong_notif_cfg.notification_mode =
802 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
803 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
804 DPNI_CONG_OPT_COHERENT_WRITE;
805 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
807 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
814 "Error in setting tx congestion notification: "
819 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
820 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
822 if (priv->tx_conf_en) {
823 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
824 options = options | DPNI_QUEUE_OPT_USER_CTX;
825 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
826 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
827 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
828 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
830 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
831 "tc_index=%d, flow=%d err=%d",
832 dpaa2_tx_conf_q->tc_index,
833 dpaa2_tx_conf_q->flow_id, ret);
837 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
838 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
839 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
841 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
844 dpaa2_tx_conf_q->fqid = qid.fqid;
850 dpaa2_dev_rx_queue_release(void *q __rte_unused)
852 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
853 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
854 struct fsl_mc_io *dpni =
855 (struct fsl_mc_io *)priv->eth_dev->process_private;
858 struct dpni_queue cfg;
860 memset(&cfg, 0, sizeof(struct dpni_queue));
861 PMD_INIT_FUNC_TRACE();
862 if (dpaa2_q->cgid != 0xff) {
863 options = DPNI_QUEUE_OPT_CLEAR_CGID;
864 cfg.cgid = dpaa2_q->cgid;
866 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
868 dpaa2_q->tc_index, dpaa2_q->flow_id,
871 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
873 priv->cgid_in_use[dpaa2_q->cgid] = 0;
874 dpaa2_q->cgid = 0xff;
879 dpaa2_dev_tx_queue_release(void *q __rte_unused)
881 PMD_INIT_FUNC_TRACE();
885 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
888 struct dpaa2_dev_priv *priv = dev->data->dev_private;
889 struct dpaa2_queue *dpaa2_q;
890 struct qbman_swp *swp;
891 struct qbman_fq_query_np_rslt state;
892 uint32_t frame_cnt = 0;
894 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
895 ret = dpaa2_affine_qbman_swp();
898 "Failed to allocate IO portal, tid: %d\n",
903 swp = DPAA2_PER_LCORE_PORTAL;
905 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
907 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
908 frame_cnt = qbman_fq_state_frame_count(&state);
909 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
910 rx_queue_id, frame_cnt);
915 static const uint32_t *
916 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
918 static const uint32_t ptypes[] = {
919 /*todo -= add more types */
922 RTE_PTYPE_L3_IPV4_EXT,
924 RTE_PTYPE_L3_IPV6_EXT,
932 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
933 dev->rx_pkt_burst == dpaa2_dev_rx ||
934 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
940 * Dpaa2 link Interrupt handler
943 * The address of parameter (struct rte_eth_dev *) regsitered before.
949 dpaa2_interrupt_handler(void *param)
951 struct rte_eth_dev *dev = param;
952 struct dpaa2_dev_priv *priv = dev->data->dev_private;
953 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
955 int irq_index = DPNI_IRQ_INDEX;
956 unsigned int status = 0, clear = 0;
958 PMD_INIT_FUNC_TRACE();
961 DPAA2_PMD_ERR("dpni is NULL");
965 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
968 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
973 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
974 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
975 dpaa2_dev_link_update(dev, 0);
976 /* calling all the apps registered for link status event */
977 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
981 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
984 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
988 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
991 struct dpaa2_dev_priv *priv = dev->data->dev_private;
992 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
993 int irq_index = DPNI_IRQ_INDEX;
994 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
996 PMD_INIT_FUNC_TRACE();
998 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1001 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1006 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1009 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1016 dpaa2_dev_start(struct rte_eth_dev *dev)
1018 struct rte_device *rdev = dev->device;
1019 struct rte_dpaa2_device *dpaa2_dev;
1020 struct rte_eth_dev_data *data = dev->data;
1021 struct dpaa2_dev_priv *priv = data->dev_private;
1022 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1023 struct dpni_queue cfg;
1024 struct dpni_error_cfg err_cfg;
1026 struct dpni_queue_id qid;
1027 struct dpaa2_queue *dpaa2_q;
1029 struct rte_intr_handle *intr_handle;
1031 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1032 intr_handle = &dpaa2_dev->intr_handle;
1034 PMD_INIT_FUNC_TRACE();
1036 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1038 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1043 /* Power up the phy. Needed to make the link go UP */
1044 dpaa2_dev_set_link_up(dev);
1046 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1047 DPNI_QUEUE_TX, &qdid);
1049 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1054 for (i = 0; i < data->nb_rx_queues; i++) {
1055 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1056 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1057 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1058 dpaa2_q->flow_id, &cfg, &qid);
1060 DPAA2_PMD_ERR("Error in getting flow information: "
1064 dpaa2_q->fqid = qid.fqid;
1067 /*checksum errors, send them to normal path and set it in annotation */
1068 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1069 err_cfg.errors |= DPNI_ERROR_PHE;
1071 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1072 err_cfg.set_frame_annotation = true;
1074 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1075 priv->token, &err_cfg);
1077 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1082 /* if the interrupts were configured on this devices*/
1083 if (intr_handle && (intr_handle->fd) &&
1084 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1085 /* Registering LSC interrupt handler */
1086 rte_intr_callback_register(intr_handle,
1087 dpaa2_interrupt_handler,
1090 /* enable vfio intr/eventfd mapping
1091 * Interrupt index 0 is required, so we can not use
1094 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1096 /* enable dpni_irqs */
1097 dpaa2_eth_setup_irqs(dev, 1);
1100 /* Change the tx burst function if ordered queues are used */
1101 if (priv->en_ordered)
1102 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1108 * This routine disables all traffic on the adapter by issuing a
1109 * global reset on the MAC.
1112 dpaa2_dev_stop(struct rte_eth_dev *dev)
1114 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1115 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1117 struct rte_eth_link link;
1118 struct rte_intr_handle *intr_handle = dev->intr_handle;
1120 PMD_INIT_FUNC_TRACE();
1122 /* reset interrupt callback */
1123 if (intr_handle && (intr_handle->fd) &&
1124 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1125 /*disable dpni irqs */
1126 dpaa2_eth_setup_irqs(dev, 0);
1128 /* disable vfio intr before callback unregister */
1129 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1131 /* Unregistering LSC interrupt handler */
1132 rte_intr_callback_unregister(intr_handle,
1133 dpaa2_interrupt_handler,
1137 dpaa2_dev_set_link_down(dev);
1139 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1141 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1146 /* clear the recorded link status */
1147 memset(&link, 0, sizeof(link));
1148 rte_eth_linkstatus_set(dev, &link);
1152 dpaa2_dev_close(struct rte_eth_dev *dev)
1154 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1155 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1157 struct rte_eth_link link;
1159 PMD_INIT_FUNC_TRACE();
1161 dpaa2_flow_clean(dev);
1163 /* Clean the device first */
1164 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1166 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1170 memset(&link, 0, sizeof(link));
1171 rte_eth_linkstatus_set(dev, &link);
1175 dpaa2_dev_promiscuous_enable(
1176 struct rte_eth_dev *dev)
1179 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1180 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1182 PMD_INIT_FUNC_TRACE();
1185 DPAA2_PMD_ERR("dpni is NULL");
1189 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1191 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1193 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1195 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1201 dpaa2_dev_promiscuous_disable(
1202 struct rte_eth_dev *dev)
1205 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1206 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1208 PMD_INIT_FUNC_TRACE();
1211 DPAA2_PMD_ERR("dpni is NULL");
1215 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1217 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1219 if (dev->data->all_multicast == 0) {
1220 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1221 priv->token, false);
1223 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1231 dpaa2_dev_allmulticast_enable(
1232 struct rte_eth_dev *dev)
1235 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1236 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1238 PMD_INIT_FUNC_TRACE();
1241 DPAA2_PMD_ERR("dpni is NULL");
1245 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1247 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1253 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1256 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1257 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1259 PMD_INIT_FUNC_TRACE();
1262 DPAA2_PMD_ERR("dpni is NULL");
1266 /* must remain on for all promiscuous */
1267 if (dev->data->promiscuous == 1)
1270 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1272 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1278 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1281 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1282 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1283 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1286 PMD_INIT_FUNC_TRACE();
1289 DPAA2_PMD_ERR("dpni is NULL");
1293 /* check that mtu is within the allowed range */
1294 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1297 if (frame_size > RTE_ETHER_MAX_LEN)
1298 dev->data->dev_conf.rxmode.offloads |=
1299 DEV_RX_OFFLOAD_JUMBO_FRAME;
1301 dev->data->dev_conf.rxmode.offloads &=
1302 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1304 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1306 /* Set the Max Rx frame length as 'mtu' +
1307 * Maximum Ethernet header length
1309 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1310 frame_size - RTE_ETHER_CRC_LEN);
1312 DPAA2_PMD_ERR("Setting the max frame length failed");
1315 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1320 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1321 struct rte_ether_addr *addr,
1322 __rte_unused uint32_t index,
1323 __rte_unused uint32_t pool)
1326 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1327 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1329 PMD_INIT_FUNC_TRACE();
1332 DPAA2_PMD_ERR("dpni is NULL");
1336 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1337 addr->addr_bytes, 0, 0, 0);
1340 "error: Adding the MAC ADDR failed: err = %d", ret);
1345 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1349 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1350 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1351 struct rte_eth_dev_data *data = dev->data;
1352 struct rte_ether_addr *macaddr;
1354 PMD_INIT_FUNC_TRACE();
1356 macaddr = &data->mac_addrs[index];
1359 DPAA2_PMD_ERR("dpni is NULL");
1363 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1364 priv->token, macaddr->addr_bytes);
1367 "error: Removing the MAC ADDR failed: err = %d", ret);
1371 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1372 struct rte_ether_addr *addr)
1375 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1376 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1378 PMD_INIT_FUNC_TRACE();
1381 DPAA2_PMD_ERR("dpni is NULL");
1385 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1386 priv->token, addr->addr_bytes);
1390 "error: Setting the MAC ADDR failed %d", ret);
1396 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1397 struct rte_eth_stats *stats)
1399 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1400 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1402 uint8_t page0 = 0, page1 = 1, page2 = 2;
1403 union dpni_statistics value;
1405 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1407 memset(&value, 0, sizeof(union dpni_statistics));
1409 PMD_INIT_FUNC_TRACE();
1412 DPAA2_PMD_ERR("dpni is NULL");
1417 DPAA2_PMD_ERR("stats is NULL");
1421 /*Get Counters from page_0*/
1422 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1427 stats->ipackets = value.page_0.ingress_all_frames;
1428 stats->ibytes = value.page_0.ingress_all_bytes;
1430 /*Get Counters from page_1*/
1431 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1436 stats->opackets = value.page_1.egress_all_frames;
1437 stats->obytes = value.page_1.egress_all_bytes;
1439 /*Get Counters from page_2*/
1440 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1445 /* Ingress drop frame count due to configured rules */
1446 stats->ierrors = value.page_2.ingress_filtered_frames;
1447 /* Ingress drop frame count due to error */
1448 stats->ierrors += value.page_2.ingress_discarded_frames;
1450 stats->oerrors = value.page_2.egress_discarded_frames;
1451 stats->imissed = value.page_2.ingress_nobuffer_discards;
1453 /* Fill in per queue stats */
1454 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1455 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1456 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1457 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1459 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1461 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1463 /* Byte counting is not implemented */
1464 stats->q_ibytes[i] = 0;
1465 stats->q_obytes[i] = 0;
1471 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1476 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1479 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1480 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1482 union dpni_statistics value[5] = {};
1483 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1491 /* Get Counters from page_0*/
1492 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1497 /* Get Counters from page_1*/
1498 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1503 /* Get Counters from page_2*/
1504 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1509 for (i = 0; i < priv->max_cgs; i++) {
1510 if (!priv->cgid_in_use[i]) {
1511 /* Get Counters from page_4*/
1512 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1521 for (i = 0; i < num; i++) {
1523 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1524 raw.counter[dpaa2_xstats_strings[i].stats_id];
1528 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1533 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1534 struct rte_eth_xstat_name *xstats_names,
1537 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1539 if (limit < stat_cnt)
1542 if (xstats_names != NULL)
1543 for (i = 0; i < stat_cnt; i++)
1544 strlcpy(xstats_names[i].name,
1545 dpaa2_xstats_strings[i].name,
1546 sizeof(xstats_names[i].name));
1552 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1553 uint64_t *values, unsigned int n)
1555 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1556 uint64_t values_copy[stat_cnt];
1559 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1560 struct fsl_mc_io *dpni =
1561 (struct fsl_mc_io *)dev->process_private;
1563 union dpni_statistics value[5] = {};
1571 /* Get Counters from page_0*/
1572 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1577 /* Get Counters from page_1*/
1578 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1583 /* Get Counters from page_2*/
1584 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1589 /* Get Counters from page_4*/
1590 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1595 for (i = 0; i < stat_cnt; i++) {
1596 values[i] = value[dpaa2_xstats_strings[i].page_id].
1597 raw.counter[dpaa2_xstats_strings[i].stats_id];
1602 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1604 for (i = 0; i < n; i++) {
1605 if (ids[i] >= stat_cnt) {
1606 DPAA2_PMD_ERR("xstats id value isn't valid");
1609 values[i] = values_copy[ids[i]];
1615 dpaa2_xstats_get_names_by_id(
1616 struct rte_eth_dev *dev,
1617 struct rte_eth_xstat_name *xstats_names,
1618 const uint64_t *ids,
1621 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1622 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1625 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1627 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1629 for (i = 0; i < limit; i++) {
1630 if (ids[i] >= stat_cnt) {
1631 DPAA2_PMD_ERR("xstats id value isn't valid");
1634 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1640 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1642 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1643 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1646 struct dpaa2_queue *dpaa2_q;
1648 PMD_INIT_FUNC_TRACE();
1651 DPAA2_PMD_ERR("dpni is NULL");
1655 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1659 /* Reset the per queue stats in dpaa2_queue structure */
1660 for (i = 0; i < priv->nb_rx_queues; i++) {
1661 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1663 dpaa2_q->rx_pkts = 0;
1666 for (i = 0; i < priv->nb_tx_queues; i++) {
1667 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1669 dpaa2_q->tx_pkts = 0;
1675 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1679 /* return 0 means link status changed, -1 means not changed */
1681 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1682 int wait_to_complete __rte_unused)
1685 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1686 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1687 struct rte_eth_link link;
1688 struct dpni_link_state state = {0};
1691 DPAA2_PMD_ERR("dpni is NULL");
1695 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1697 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1701 memset(&link, 0, sizeof(struct rte_eth_link));
1702 link.link_status = state.up;
1703 link.link_speed = state.rate;
1705 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1706 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1708 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1710 ret = rte_eth_linkstatus_set(dev, &link);
1712 DPAA2_PMD_DEBUG("No change in status");
1714 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1715 link.link_status ? "Up" : "Down");
1721 * Toggle the DPNI to enable, if not already enabled.
1722 * This is not strictly PHY up/down - it is more of logical toggling.
1725 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1728 struct dpaa2_dev_priv *priv;
1729 struct fsl_mc_io *dpni;
1731 struct dpni_link_state state = {0};
1733 priv = dev->data->dev_private;
1734 dpni = (struct fsl_mc_io *)dev->process_private;
1737 DPAA2_PMD_ERR("dpni is NULL");
1741 /* Check if DPNI is currently enabled */
1742 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1744 /* Unable to obtain dpni status; Not continuing */
1745 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1749 /* Enable link if not already enabled */
1751 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1753 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1757 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1759 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1763 /* changing tx burst function to start enqueues */
1764 dev->tx_pkt_burst = dpaa2_dev_tx;
1765 dev->data->dev_link.link_status = state.up;
1766 dev->data->dev_link.link_speed = state.rate;
1769 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1771 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1776 * Toggle the DPNI to disable, if not already disabled.
1777 * This is not strictly PHY up/down - it is more of logical toggling.
1780 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1783 struct dpaa2_dev_priv *priv;
1784 struct fsl_mc_io *dpni;
1785 int dpni_enabled = 0;
1788 PMD_INIT_FUNC_TRACE();
1790 priv = dev->data->dev_private;
1791 dpni = (struct fsl_mc_io *)dev->process_private;
1794 DPAA2_PMD_ERR("Device has not yet been configured");
1798 /*changing tx burst function to avoid any more enqueues */
1799 dev->tx_pkt_burst = dummy_dev_tx;
1801 /* Loop while dpni_disable() attempts to drain the egress FQs
1802 * and confirm them back to us.
1805 ret = dpni_disable(dpni, 0, priv->token);
1807 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1810 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1812 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1816 /* Allow the MC some slack */
1817 rte_delay_us(100 * 1000);
1818 } while (dpni_enabled && --retries);
1821 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1822 /* todo- we may have to manually cleanup queues.
1825 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1826 dev->data->port_id);
1829 dev->data->dev_link.link_status = 0;
1835 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1838 struct dpaa2_dev_priv *priv;
1839 struct fsl_mc_io *dpni;
1840 struct dpni_link_state state = {0};
1842 PMD_INIT_FUNC_TRACE();
1844 priv = dev->data->dev_private;
1845 dpni = (struct fsl_mc_io *)dev->process_private;
1847 if (dpni == NULL || fc_conf == NULL) {
1848 DPAA2_PMD_ERR("device not configured");
1852 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1854 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1858 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1859 if (state.options & DPNI_LINK_OPT_PAUSE) {
1860 /* DPNI_LINK_OPT_PAUSE set
1861 * if ASYM_PAUSE not set,
1862 * RX Side flow control (handle received Pause frame)
1863 * TX side flow control (send Pause frame)
1864 * if ASYM_PAUSE set,
1865 * RX Side flow control (handle received Pause frame)
1866 * No TX side flow control (send Pause frame disabled)
1868 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1869 fc_conf->mode = RTE_FC_FULL;
1871 fc_conf->mode = RTE_FC_RX_PAUSE;
1873 /* DPNI_LINK_OPT_PAUSE not set
1874 * if ASYM_PAUSE set,
1875 * TX side flow control (send Pause frame)
1876 * No RX side flow control (No action on pause frame rx)
1877 * if ASYM_PAUSE not set,
1878 * Flow control disabled
1880 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
1881 fc_conf->mode = RTE_FC_TX_PAUSE;
1883 fc_conf->mode = RTE_FC_NONE;
1890 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1893 struct dpaa2_dev_priv *priv;
1894 struct fsl_mc_io *dpni;
1895 struct dpni_link_state state = {0};
1896 struct dpni_link_cfg cfg = {0};
1898 PMD_INIT_FUNC_TRACE();
1900 priv = dev->data->dev_private;
1901 dpni = (struct fsl_mc_io *)dev->process_private;
1904 DPAA2_PMD_ERR("dpni is NULL");
1908 /* It is necessary to obtain the current state before setting fc_conf
1909 * as MC would return error in case rate, autoneg or duplex values are
1912 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1914 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
1918 /* Disable link before setting configuration */
1919 dpaa2_dev_set_link_down(dev);
1921 /* Based on fc_conf, update cfg */
1922 cfg.rate = state.rate;
1923 cfg.options = state.options;
1925 /* update cfg with fc_conf */
1926 switch (fc_conf->mode) {
1928 /* Full flow control;
1929 * OPT_PAUSE set, ASYM_PAUSE not set
1931 cfg.options |= DPNI_LINK_OPT_PAUSE;
1932 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1934 case RTE_FC_TX_PAUSE:
1935 /* Enable RX flow control
1936 * OPT_PAUSE not set;
1939 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1940 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1942 case RTE_FC_RX_PAUSE:
1943 /* Enable TX Flow control
1947 cfg.options |= DPNI_LINK_OPT_PAUSE;
1948 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1951 /* Disable Flow control
1953 * ASYM_PAUSE not set
1955 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1956 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1959 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
1964 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
1966 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
1970 dpaa2_dev_set_link_up(dev);
1976 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
1977 struct rte_eth_rss_conf *rss_conf)
1979 struct rte_eth_dev_data *data = dev->data;
1980 struct rte_eth_conf *eth_conf = &data->dev_conf;
1983 PMD_INIT_FUNC_TRACE();
1985 if (rss_conf->rss_hf) {
1986 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf);
1988 DPAA2_PMD_ERR("Unable to set flow dist");
1992 ret = dpaa2_remove_flow_dist(dev, 0);
1994 DPAA2_PMD_ERR("Unable to remove flow dist");
1998 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2003 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2004 struct rte_eth_rss_conf *rss_conf)
2006 struct rte_eth_dev_data *data = dev->data;
2007 struct rte_eth_conf *eth_conf = &data->dev_conf;
2009 /* dpaa2 does not support rss_key, so length should be 0*/
2010 rss_conf->rss_key_len = 0;
2011 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2015 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2016 int eth_rx_queue_id,
2017 struct dpaa2_dpcon_dev *dpcon,
2018 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2020 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2021 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2022 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2023 uint8_t flow_id = dpaa2_ethq->flow_id;
2024 struct dpni_queue cfg;
2025 uint8_t options, priority;
2028 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2029 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2030 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2031 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2032 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2033 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2037 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2038 (dpcon->num_priorities - 1);
2040 memset(&cfg, 0, sizeof(struct dpni_queue));
2041 options = DPNI_QUEUE_OPT_DEST;
2042 cfg.destination.type = DPNI_DEST_DPCON;
2043 cfg.destination.id = dpcon->dpcon_id;
2044 cfg.destination.priority = priority;
2046 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2047 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2048 cfg.destination.hold_active = 1;
2051 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2052 !eth_priv->en_ordered) {
2053 struct opr_cfg ocfg;
2055 /* Restoration window size = 256 frames */
2057 /* Restoration window size = 512 frames for LX2 */
2058 if (dpaa2_svr_family == SVR_LX2160A)
2060 /* Auto advance NESN window enabled */
2062 /* Late arrival window size disabled */
2064 /* ORL resource exhaustaion advance NESN disabled */
2066 /* Loose ordering enabled */
2068 eth_priv->en_loose_ordered = 1;
2069 /* Strict ordering enabled if explicitly set */
2070 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2072 eth_priv->en_loose_ordered = 0;
2075 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2076 dpaa2_ethq->tc_index, flow_id,
2077 OPR_OPT_CREATE, &ocfg);
2079 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2083 eth_priv->en_ordered = 1;
2086 options |= DPNI_QUEUE_OPT_USER_CTX;
2087 cfg.user_context = (size_t)(dpaa2_ethq);
2089 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2090 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2092 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2096 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2101 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2102 int eth_rx_queue_id)
2104 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2105 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2106 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2107 uint8_t flow_id = dpaa2_ethq->flow_id;
2108 struct dpni_queue cfg;
2112 memset(&cfg, 0, sizeof(struct dpni_queue));
2113 options = DPNI_QUEUE_OPT_DEST;
2114 cfg.destination.type = DPNI_DEST_NONE;
2116 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2117 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2119 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2125 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2129 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2130 if (dpaa2_supported_filter_ops[i] == filter_op)
2137 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2138 enum rte_filter_type filter_type,
2139 enum rte_filter_op filter_op,
2147 switch (filter_type) {
2148 case RTE_ETH_FILTER_GENERIC:
2149 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2153 *(const void **)arg = &dpaa2_flow_ops;
2154 dpaa2_filter_type |= filter_type;
2157 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2165 static struct eth_dev_ops dpaa2_ethdev_ops = {
2166 .dev_configure = dpaa2_eth_dev_configure,
2167 .dev_start = dpaa2_dev_start,
2168 .dev_stop = dpaa2_dev_stop,
2169 .dev_close = dpaa2_dev_close,
2170 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2171 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2172 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2173 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2174 .dev_set_link_up = dpaa2_dev_set_link_up,
2175 .dev_set_link_down = dpaa2_dev_set_link_down,
2176 .link_update = dpaa2_dev_link_update,
2177 .stats_get = dpaa2_dev_stats_get,
2178 .xstats_get = dpaa2_dev_xstats_get,
2179 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2180 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2181 .xstats_get_names = dpaa2_xstats_get_names,
2182 .stats_reset = dpaa2_dev_stats_reset,
2183 .xstats_reset = dpaa2_dev_stats_reset,
2184 .fw_version_get = dpaa2_fw_version_get,
2185 .dev_infos_get = dpaa2_dev_info_get,
2186 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2187 .mtu_set = dpaa2_dev_mtu_set,
2188 .vlan_filter_set = dpaa2_vlan_filter_set,
2189 .vlan_offload_set = dpaa2_vlan_offload_set,
2190 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2191 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2192 .rx_queue_release = dpaa2_dev_rx_queue_release,
2193 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2194 .tx_queue_release = dpaa2_dev_tx_queue_release,
2195 .rx_queue_count = dpaa2_dev_rx_queue_count,
2196 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2197 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2198 .mac_addr_add = dpaa2_dev_add_mac_addr,
2199 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2200 .mac_addr_set = dpaa2_dev_set_mac_addr,
2201 .rss_hash_update = dpaa2_dev_rss_hash_update,
2202 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2203 .filter_ctrl = dpaa2_dev_flow_ctrl,
2204 #if defined(RTE_LIBRTE_IEEE1588)
2205 .timesync_enable = dpaa2_timesync_enable,
2206 .timesync_disable = dpaa2_timesync_disable,
2207 .timesync_read_time = dpaa2_timesync_read_time,
2208 .timesync_write_time = dpaa2_timesync_write_time,
2209 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2210 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2211 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2215 /* Populate the mac address from physically available (u-boot/firmware) and/or
2216 * one set by higher layers like MC (restool) etc.
2217 * Returns the table of MAC entries (multiple entries)
2220 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2221 struct rte_ether_addr *mac_entry)
2224 struct rte_ether_addr phy_mac, prime_mac;
2226 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2227 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2229 /* Get the physical device MAC address */
2230 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2231 phy_mac.addr_bytes);
2233 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2237 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2238 prime_mac.addr_bytes);
2240 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2244 /* Now that both MAC have been obtained, do:
2245 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2247 * If empty_mac(phy), return prime.
2248 * if both are empty, create random MAC, set as prime and return
2250 if (!rte_is_zero_ether_addr(&phy_mac)) {
2251 /* If the addresses are not same, overwrite prime */
2252 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2253 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2255 phy_mac.addr_bytes);
2257 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2261 memcpy(&prime_mac, &phy_mac,
2262 sizeof(struct rte_ether_addr));
2264 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2265 /* In case phys and prime, both are zero, create random MAC */
2266 rte_eth_random_addr(prime_mac.addr_bytes);
2267 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2269 prime_mac.addr_bytes);
2271 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2276 /* prime_mac the final MAC address */
2277 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2285 check_devargs_handler(__rte_unused const char *key, const char *value,
2286 __rte_unused void *opaque)
2288 if (strcmp(value, "1"))
2295 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2297 struct rte_kvargs *kvlist;
2302 kvlist = rte_kvargs_parse(devargs->args, NULL);
2306 if (!rte_kvargs_count(kvlist, key)) {
2307 rte_kvargs_free(kvlist);
2311 if (rte_kvargs_process(kvlist, key,
2312 check_devargs_handler, NULL) < 0) {
2313 rte_kvargs_free(kvlist);
2316 rte_kvargs_free(kvlist);
2322 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2324 struct rte_device *dev = eth_dev->device;
2325 struct rte_dpaa2_device *dpaa2_dev;
2326 struct fsl_mc_io *dpni_dev;
2327 struct dpni_attr attr;
2328 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2329 struct dpni_buffer_layout layout;
2332 PMD_INIT_FUNC_TRACE();
2334 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2336 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2339 dpni_dev->regs = rte_mcp_ptr_list[0];
2340 eth_dev->process_private = (void *)dpni_dev;
2342 /* For secondary processes, the primary has done all the work */
2343 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2344 /* In case of secondary, only burst and ops API need to be
2347 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2348 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2349 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2350 else if (dpaa2_get_devargs(dev->devargs,
2351 DRIVER_NO_PREFETCH_MODE))
2352 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2354 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2355 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2359 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2361 hw_id = dpaa2_dev->object_id;
2362 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2365 "Failure in opening dpni@%d with err code %d",
2371 /* Clean the device first */
2372 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2374 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2379 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2382 "Failure in get dpni@%d attribute, err code %d",
2387 priv->num_rx_tc = attr.num_rx_tcs;
2388 /* only if the custom CG is enabled */
2389 if (attr.options & DPNI_OPT_CUSTOM_CG)
2390 priv->max_cgs = attr.num_cgs;
2394 for (i = 0; i < priv->max_cgs; i++)
2395 priv->cgid_in_use[i] = 0;
2397 for (i = 0; i < attr.num_rx_tcs; i++)
2398 priv->nb_rx_queues += attr.num_queues;
2400 /* Using number of TX queues as number of TX TCs */
2401 priv->nb_tx_queues = attr.num_tx_tcs;
2403 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2404 priv->num_rx_tc, priv->nb_rx_queues,
2405 priv->nb_tx_queues, priv->max_cgs);
2407 priv->hw = dpni_dev;
2408 priv->hw_id = hw_id;
2409 priv->options = attr.options;
2410 priv->max_mac_filters = attr.mac_filter_entries;
2411 priv->max_vlan_filters = attr.vlan_filter_entries;
2413 #if defined(RTE_LIBRTE_IEEE1588)
2414 priv->tx_conf_en = 1;
2416 priv->tx_conf_en = 0;
2419 /* Allocate memory for hardware structure for queues */
2420 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2422 DPAA2_PMD_ERR("Queue allocation Failed");
2426 /* Allocate memory for storing MAC addresses.
2427 * Table of mac_filter_entries size is allocated so that RTE ether lib
2428 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2430 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2431 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2432 if (eth_dev->data->mac_addrs == NULL) {
2434 "Failed to allocate %d bytes needed to store MAC addresses",
2435 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2440 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2442 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2443 rte_free(eth_dev->data->mac_addrs);
2444 eth_dev->data->mac_addrs = NULL;
2448 /* ... tx buffer layout ... */
2449 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2450 if (priv->tx_conf_en) {
2451 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2452 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2453 layout.pass_timestamp = true;
2455 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2457 layout.pass_frame_status = 1;
2458 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2459 DPNI_QUEUE_TX, &layout);
2461 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2465 /* ... tx-conf and error buffer layout ... */
2466 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2467 if (priv->tx_conf_en) {
2468 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2469 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2470 layout.pass_timestamp = true;
2472 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2474 layout.pass_frame_status = 1;
2475 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2476 DPNI_QUEUE_TX_CONFIRM, &layout);
2478 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2483 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2485 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2486 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2487 DPAA2_PMD_INFO("Loopback mode");
2488 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2489 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2490 DPAA2_PMD_INFO("No Prefetch mode");
2492 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2494 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2496 /*Init fields w.r.t. classficaition*/
2497 memset(&priv->extract.qos_key_cfg, 0, sizeof(struct dpkg_profile_cfg));
2498 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2499 if (!priv->extract.qos_extract_param) {
2500 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2501 " classificaiton ", ret);
2504 for (i = 0; i < MAX_TCS; i++) {
2505 memset(&priv->extract.fs_key_cfg[i], 0,
2506 sizeof(struct dpkg_profile_cfg));
2507 priv->extract.fs_extract_param[i] =
2508 (size_t)rte_malloc(NULL, 256, 64);
2509 if (!priv->extract.fs_extract_param[i]) {
2510 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2516 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2517 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2520 DPAA2_PMD_ERR("Unable to set mtu. check config");
2524 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2525 * with external entity to receive byte code for software sequence
2526 * and same will be offload to the H/W using MC interface.
2527 * Currently it is assumed that DPAA2 driver has byte code by some
2528 * mean and same if offloaded to H/W.
2530 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2531 WRIOP_SS_INITIALIZER(priv);
2532 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2534 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2539 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2542 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2547 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2550 dpaa2_dev_uninit(eth_dev);
2555 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev)
2557 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2558 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_dev->process_private;
2561 PMD_INIT_FUNC_TRACE();
2563 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2567 DPAA2_PMD_WARN("Already closed or not started");
2571 dpaa2_dev_close(eth_dev);
2573 dpaa2_free_rx_tx_queues(eth_dev);
2575 /* Close the device at underlying layer*/
2576 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
2579 "Failure closing dpni device with err code %d",
2583 /* Free the allocated memory for ethernet private data and dpni*/
2585 eth_dev->process_private = NULL;
2588 for (i = 0; i < MAX_TCS; i++) {
2589 if (priv->extract.fs_extract_param[i])
2590 rte_free((void *)(size_t)priv->extract.fs_extract_param[i]);
2593 if (priv->extract.qos_extract_param)
2594 rte_free((void *)(size_t)priv->extract.qos_extract_param);
2596 eth_dev->dev_ops = NULL;
2597 eth_dev->rx_pkt_burst = NULL;
2598 eth_dev->tx_pkt_burst = NULL;
2600 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name);
2605 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2606 struct rte_dpaa2_device *dpaa2_dev)
2608 struct rte_eth_dev *eth_dev;
2609 struct dpaa2_dev_priv *dev_priv;
2612 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2613 RTE_PKTMBUF_HEADROOM) {
2615 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2616 RTE_PKTMBUF_HEADROOM,
2617 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2622 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2623 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2626 dev_priv = rte_zmalloc("ethdev private structure",
2627 sizeof(struct dpaa2_dev_priv),
2628 RTE_CACHE_LINE_SIZE);
2629 if (dev_priv == NULL) {
2631 "Unable to allocate memory for private data");
2632 rte_eth_dev_release_port(eth_dev);
2635 eth_dev->data->dev_private = (void *)dev_priv;
2636 /* Store a pointer to eth_dev in dev_private */
2637 dev_priv->eth_dev = eth_dev;
2638 dev_priv->tx_conf_en = 0;
2640 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2642 DPAA2_PMD_DEBUG("returning enodev");
2647 eth_dev->device = &dpaa2_dev->device;
2649 dpaa2_dev->eth_dev = eth_dev;
2650 eth_dev->data->rx_mbuf_alloc_failed = 0;
2652 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2653 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2655 /* Invoke PMD device initialization function */
2656 diag = dpaa2_dev_init(eth_dev);
2658 rte_eth_dev_probing_finish(eth_dev);
2662 rte_eth_dev_release_port(eth_dev);
2667 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2669 struct rte_eth_dev *eth_dev;
2671 eth_dev = dpaa2_dev->eth_dev;
2672 dpaa2_dev_uninit(eth_dev);
2674 rte_eth_dev_release_port(eth_dev);
2679 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2680 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2681 .drv_type = DPAA2_ETH,
2682 .probe = rte_dpaa2_probe,
2683 .remove = rte_dpaa2_remove,
2686 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2687 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2688 DRIVER_LOOPBACK_MODE "=<int> "
2689 DRIVER_NO_PREFETCH_MODE "=<int>");
2690 RTE_INIT(dpaa2_pmd_init_log)
2692 dpaa2_logtype_pmd = rte_log_register("pmd.net.dpaa2");
2693 if (dpaa2_logtype_pmd >= 0)
2694 rte_log_set_level(dpaa2_logtype_pmd, RTE_LOG_NOTICE);