drivers/net/dpaa2/dpaa2_ethdev.c

   1 /* * SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2021 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_cycles.h>
  17 #include <rte_kvargs.h>
  18 #include <rte_dev.h>
  19 #include <rte_fslmc.h>
  20 #include <rte_flow_driver.h>
  21 #include "rte_dpaa2_mempool.h"
  22
  23 #include "dpaa2_pmd_logs.h"
  24 #include <fslmc_vfio.h>
  25 #include <dpaa2_hw_pvt.h>
  26 #include <dpaa2_hw_mempool.h>
  27 #include <dpaa2_hw_dpio.h>
  28 #include <mc/fsl_dpmng.h>
  29 #include "dpaa2_ethdev.h"
  30 #include "dpaa2_sparser.h"
  31 #include <fsl_qbman_debug.h>
  32
  33 #define DRIVER_LOOPBACK_MODE "drv_loopback"
  34 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
  35 #define DRIVER_TX_CONF "drv_tx_conf"
  36 #define DRIVER_ERROR_QUEUE  "drv_err_queue"
  37 #define CHECK_INTERVAL         100  /* 100ms */
  38 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
  39
  40 /* Supported Rx offloads */
  41 static uint64_t dev_rx_offloads_sup =
  42                 RTE_ETH_RX_OFFLOAD_CHECKSUM |
  43                 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
  44                 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  45                 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
  46                 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
  47                 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
  48                 RTE_ETH_RX_OFFLOAD_TIMESTAMP;
  49
  50 /* Rx offloads which cannot be disabled */
  51 static uint64_t dev_rx_offloads_nodis =
  52                 RTE_ETH_RX_OFFLOAD_RSS_HASH |
  53                 RTE_ETH_RX_OFFLOAD_SCATTER;
  54
  55 /* Supported Tx offloads */
  56 static uint64_t dev_tx_offloads_sup =
  57                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
  58                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
  59                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
  60                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
  61                 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
  62                 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  63                 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |
  64                 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
  65
  66 /* Tx offloads which cannot be disabled */
  67 static uint64_t dev_tx_offloads_nodis =
  68                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
  69
  70 /* enable timestamp in mbuf */
  71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
  72 uint64_t dpaa2_timestamp_rx_dynflag;
  73 int dpaa2_timestamp_dynfield_offset = -1;
  74
  75 /* Enable error queue */
  76 bool dpaa2_enable_err_queue;
  77
  78 #define MAX_NB_RX_DESC          11264
  79 int total_nb_rx_desc;
  80
  81 struct rte_dpaa2_xstats_name_off {
  82         char name[RTE_ETH_XSTATS_NAME_SIZE];
  83         uint8_t page_id; /* dpni statistics page id */
  84         uint8_t stats_id; /* stats id in the given page */
  85 };
  86
  87 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
  88         {"ingress_multicast_frames", 0, 2},
  89         {"ingress_multicast_bytes", 0, 3},
  90         {"ingress_broadcast_frames", 0, 4},
  91         {"ingress_broadcast_bytes", 0, 5},
  92         {"egress_multicast_frames", 1, 2},
  93         {"egress_multicast_bytes", 1, 3},
  94         {"egress_broadcast_frames", 1, 4},
  95         {"egress_broadcast_bytes", 1, 5},
  96         {"ingress_filtered_frames", 2, 0},
  97         {"ingress_discarded_frames", 2, 1},
  98         {"ingress_nobuffer_discards", 2, 2},
  99         {"egress_discarded_frames", 2, 3},
 100         {"egress_confirmed_frames", 2, 4},
 101         {"cgr_reject_frames", 4, 0},
 102         {"cgr_reject_bytes", 4, 1},
 103 };
 104
 105 static struct rte_dpaa2_driver rte_dpaa2_pmd;
 106 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
 107                                  int wait_to_complete);
 108 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
 109 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
 110 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 111
 112 static int
 113 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 114 {
 115         int ret;
 116         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 117         struct fsl_mc_io *dpni = dev->process_private;
 118
 119         PMD_INIT_FUNC_TRACE();
 120
 121         if (dpni == NULL) {
 122                 DPAA2_PMD_ERR("dpni is NULL");
 123                 return -1;
 124         }
 125
 126         if (on)
 127                 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
 128                                        vlan_id, 0, 0, 0);
 129         else
 130                 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
 131                                           priv->token, vlan_id);
 132
 133         if (ret < 0)
 134                 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
 135                               ret, vlan_id, priv->hw_id);
 136
 137         return ret;
 138 }
 139
 140 static int
 141 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 142 {
 143         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 144         struct fsl_mc_io *dpni = dev->process_private;
 145         int ret = 0;
 146
 147         PMD_INIT_FUNC_TRACE();
 148
 149         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
 150                 /* VLAN Filter not available */
 151                 if (!priv->max_vlan_filters) {
 152                         DPAA2_PMD_INFO("VLAN filter not available");
 153                         return -ENOTSUP;
 154                 }
 155
 156                 if (dev->data->dev_conf.rxmode.offloads &
 157                         RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
 158                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 159                                                       priv->token, true);
 160                 else
 161                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 162                                                       priv->token, false);
 163                 if (ret < 0)
 164                         DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
 165         }
 166
 167         return ret;
 168 }
 169
 170 static int
 171 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
 172                       enum rte_vlan_type vlan_type __rte_unused,
 173                       uint16_t tpid)
 174 {
 175         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 176         struct fsl_mc_io *dpni = dev->process_private;
 177         int ret = -ENOTSUP;
 178
 179         PMD_INIT_FUNC_TRACE();
 180
 181         /* nothing to be done for standard vlan tpids */
 182         if (tpid == 0x8100 || tpid == 0x88A8)
 183                 return 0;
 184
 185         ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 186                                    priv->token, tpid);
 187         if (ret < 0)
 188                 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
 189         /* if already configured tpids, remove them first */
 190         if (ret == -EBUSY) {
 191                 struct dpni_custom_tpid_cfg tpid_list = {0};
 192
 193                 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
 194                                    priv->token, &tpid_list);
 195                 if (ret < 0)
 196                         goto fail;
 197                 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
 198                                    priv->token, tpid_list.tpid1);
 199                 if (ret < 0)
 200                         goto fail;
 201                 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 202                                            priv->token, tpid);
 203         }
 204 fail:
 205         return ret;
 206 }
 207
 208 static int
 209 dpaa2_fw_version_get(struct rte_eth_dev *dev,
 210                      char *fw_version,
 211                      size_t fw_size)
 212 {
 213         int ret;
 214         struct fsl_mc_io *dpni = dev->process_private;
 215         struct mc_soc_version mc_plat_info = {0};
 216         struct mc_version mc_ver_info = {0};
 217
 218         PMD_INIT_FUNC_TRACE();
 219
 220         if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
 221                 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
 222
 223         if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
 224                 DPAA2_PMD_WARN("\tmc_get_version failed");
 225
 226         ret = snprintf(fw_version, fw_size,
 227                        "%x-%d.%d.%d",
 228                        mc_plat_info.svr,
 229                        mc_ver_info.major,
 230                        mc_ver_info.minor,
 231                        mc_ver_info.revision);
 232         if (ret < 0)
 233                 return -EINVAL;
 234
 235         ret += 1; /* add the size of '\0' */
 236         if (fw_size < (size_t)ret)
 237                 return ret;
 238         else
 239                 return 0;
 240 }
 241
 242 static int
 243 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 244 {
 245         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 246
 247         PMD_INIT_FUNC_TRACE();
 248
 249         dev_info->max_mac_addrs = priv->max_mac_filters;
 250         dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
 251         dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
 252         dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
 253         dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
 254         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 255                                         dev_rx_offloads_nodis;
 256         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 257                                         dev_tx_offloads_nodis;
 258         dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G |
 259                         RTE_ETH_LINK_SPEED_2_5G |
 260                         RTE_ETH_LINK_SPEED_10G;
 261         dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 262
 263         dev_info->max_hash_mac_addrs = 0;
 264         dev_info->max_vfs = 0;
 265         dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
 266         dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
 267
 268         dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
 269         /* same is rx size for best perf */
 270         dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
 271
 272         dev_info->default_rxportconf.nb_queues = 1;
 273         dev_info->default_txportconf.nb_queues = 1;
 274         dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 275         dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 276
 277         if (dpaa2_svr_family == SVR_LX2160A) {
 278                 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G |
 279                                 RTE_ETH_LINK_SPEED_40G |
 280                                 RTE_ETH_LINK_SPEED_50G |
 281                                 RTE_ETH_LINK_SPEED_100G;
 282         }
 283
 284         return 0;
 285 }
 286
 287 static int
 288 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 289                         __rte_unused uint16_t queue_id,
 290                         struct rte_eth_burst_mode *mode)
 291 {
 292         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 293         int ret = -EINVAL;
 294         unsigned int i;
 295         const struct burst_info {
 296                 uint64_t flags;
 297                 const char *output;
 298         } rx_offload_map[] = {
 299                         {RTE_ETH_RX_OFFLOAD_CHECKSUM, " Checksum,"},
 300                         {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 301                         {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 302                         {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
 303                         {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
 304                         {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
 305                         {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
 306                         {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"},
 307                         {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}
 308         };
 309
 310         /* Update Rx offload info */
 311         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 312                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 313                         snprintf(mode->info, sizeof(mode->info), "%s",
 314                                 rx_offload_map[i].output);
 315                         ret = 0;
 316                         break;
 317                 }
 318         }
 319         return ret;
 320 }
 321
 322 static int
 323 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 324                         __rte_unused uint16_t queue_id,
 325                         struct rte_eth_burst_mode *mode)
 326 {
 327         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 328         int ret = -EINVAL;
 329         unsigned int i;
 330         const struct burst_info {
 331                 uint64_t flags;
 332                 const char *output;
 333         } tx_offload_map[] = {
 334                         {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
 335                         {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 336                         {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 337                         {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 338                         {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 339                         {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 340                         {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 341                         {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 342                         {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 343         };
 344
 345         /* Update Tx offload info */
 346         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 347                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 348                         snprintf(mode->info, sizeof(mode->info), "%s",
 349                                 tx_offload_map[i].output);
 350                         ret = 0;
 351                         break;
 352                 }
 353         }
 354         return ret;
 355 }
 356
 357 static int
 358 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 359 {
 360         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 361         uint16_t dist_idx;
 362         uint32_t vq_id;
 363         uint8_t num_rxqueue_per_tc;
 364         struct dpaa2_queue *mc_q, *mcq;
 365         uint32_t tot_queues;
 366         int i;
 367         struct dpaa2_queue *dpaa2_q;
 368
 369         PMD_INIT_FUNC_TRACE();
 370
 371         num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
 372         if (priv->flags & DPAA2_TX_CONF_ENABLE)
 373                 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
 374         else
 375                 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
 376         mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
 377                           RTE_CACHE_LINE_SIZE);
 378         if (!mc_q) {
 379                 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
 380                 return -1;
 381         }
 382
 383         for (i = 0; i < priv->nb_rx_queues; i++) {
 384                 mc_q->eth_data = dev->data;
 385                 priv->rx_vq[i] = mc_q++;
 386                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 387                 dpaa2_q->q_storage = rte_malloc("dq_storage",
 388                                         sizeof(struct queue_storage_info_t),
 389                                         RTE_CACHE_LINE_SIZE);
 390                 if (!dpaa2_q->q_storage)
 391                         goto fail;
 392
 393                 memset(dpaa2_q->q_storage, 0,
 394                        sizeof(struct queue_storage_info_t));
 395                 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 396                         goto fail;
 397         }
 398
 399         if (dpaa2_enable_err_queue) {
 400                 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
 401                         sizeof(struct dpaa2_queue), 0);
 402
 403                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 404                 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
 405                                         sizeof(struct queue_storage_info_t) *
 406                                         RTE_MAX_LCORE,
 407                                         RTE_CACHE_LINE_SIZE);
 408                 if (!dpaa2_q->q_storage)
 409                         goto fail;
 410
 411                 memset(dpaa2_q->q_storage, 0,
 412                        sizeof(struct queue_storage_info_t));
 413                 for (i = 0; i < RTE_MAX_LCORE; i++)
 414                         if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
 415                                 goto fail;
 416         }
 417
 418         for (i = 0; i < priv->nb_tx_queues; i++) {
 419                 mc_q->eth_data = dev->data;
 420                 mc_q->flow_id = 0xffff;
 421                 priv->tx_vq[i] = mc_q++;
 422                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 423                 dpaa2_q->cscn = rte_malloc(NULL,
 424                                            sizeof(struct qbman_result), 16);
 425                 if (!dpaa2_q->cscn)
 426                         goto fail_tx;
 427         }
 428
 429         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 430                 /*Setup tx confirmation queues*/
 431                 for (i = 0; i < priv->nb_tx_queues; i++) {
 432                         mc_q->eth_data = dev->data;
 433                         mc_q->tc_index = i;
 434                         mc_q->flow_id = 0;
 435                         priv->tx_conf_vq[i] = mc_q++;
 436                         dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 437                         dpaa2_q->q_storage =
 438                                 rte_malloc("dq_storage",
 439                                         sizeof(struct queue_storage_info_t),
 440                                         RTE_CACHE_LINE_SIZE);
 441                         if (!dpaa2_q->q_storage)
 442                                 goto fail_tx_conf;
 443
 444                         memset(dpaa2_q->q_storage, 0,
 445                                sizeof(struct queue_storage_info_t));
 446                         if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 447                                 goto fail_tx_conf;
 448                 }
 449         }
 450
 451         vq_id = 0;
 452         for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
 453                 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
 454                 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
 455                 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
 456                 vq_id++;
 457         }
 458
 459         return 0;
 460 fail_tx_conf:
 461         i -= 1;
 462         while (i >= 0) {
 463                 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 464                 rte_free(dpaa2_q->q_storage);
 465                 priv->tx_conf_vq[i--] = NULL;
 466         }
 467         i = priv->nb_tx_queues;
 468 fail_tx:
 469         i -= 1;
 470         while (i >= 0) {
 471                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 472                 rte_free(dpaa2_q->cscn);
 473                 priv->tx_vq[i--] = NULL;
 474         }
 475         i = priv->nb_rx_queues;
 476 fail:
 477         i -= 1;
 478         mc_q = priv->rx_vq[0];
 479         while (i >= 0) {
 480                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 481                 dpaa2_free_dq_storage(dpaa2_q->q_storage);
 482                 rte_free(dpaa2_q->q_storage);
 483                 priv->rx_vq[i--] = NULL;
 484         }
 485
 486         if (dpaa2_enable_err_queue) {
 487                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 488                 if (dpaa2_q->q_storage)
 489                         dpaa2_free_dq_storage(dpaa2_q->q_storage);
 490                 rte_free(dpaa2_q->q_storage);
 491         }
 492
 493         rte_free(mc_q);
 494         return -1;
 495 }
 496
 497 static void
 498 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
 499 {
 500         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 501         struct dpaa2_queue *dpaa2_q;
 502         int i;
 503
 504         PMD_INIT_FUNC_TRACE();
 505
 506         /* Queue allocation base */
 507         if (priv->rx_vq[0]) {
 508                 /* cleaning up queue storage */
 509                 for (i = 0; i < priv->nb_rx_queues; i++) {
 510                         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 511                         if (dpaa2_q->q_storage)
 512                                 rte_free(dpaa2_q->q_storage);
 513                 }
 514                 /* cleanup tx queue cscn */
 515                 for (i = 0; i < priv->nb_tx_queues; i++) {
 516                         dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 517                         rte_free(dpaa2_q->cscn);
 518                 }
 519                 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 520                         /* cleanup tx conf queue storage */
 521                         for (i = 0; i < priv->nb_tx_queues; i++) {
 522                                 dpaa2_q = (struct dpaa2_queue *)
 523                                                 priv->tx_conf_vq[i];
 524                                 rte_free(dpaa2_q->q_storage);
 525                         }
 526                 }
 527                 /*free memory for all queues (RX+TX) */
 528                 rte_free(priv->rx_vq[0]);
 529                 priv->rx_vq[0] = NULL;
 530         }
 531 }
 532
 533 static int
 534 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
 535 {
 536         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 537         struct fsl_mc_io *dpni = dev->process_private;
 538         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 539         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 540         uint64_t tx_offloads = eth_conf->txmode.offloads;
 541         int rx_l3_csum_offload = false;
 542         int rx_l4_csum_offload = false;
 543         int tx_l3_csum_offload = false;
 544         int tx_l4_csum_offload = false;
 545         int ret, tc_index;
 546         uint32_t max_rx_pktlen;
 547
 548         PMD_INIT_FUNC_TRACE();
 549
 550         /* Rx offloads which are enabled by default */
 551         if (dev_rx_offloads_nodis & ~rx_offloads) {
 552                 DPAA2_PMD_INFO(
 553                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 554                 " fixed are 0x%" PRIx64,
 555                 rx_offloads, dev_rx_offloads_nodis);
 556         }
 557
 558         /* Tx offloads which are enabled by default */
 559         if (dev_tx_offloads_nodis & ~tx_offloads) {
 560                 DPAA2_PMD_INFO(
 561                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 562                 " fixed are 0x%" PRIx64,
 563                 tx_offloads, dev_tx_offloads_nodis);
 564         }
 565
 566         max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN +
 567                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
 568         if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) {
 569                 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
 570                         priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN);
 571                 if (ret != 0) {
 572                         DPAA2_PMD_ERR("Unable to set mtu. check config");
 573                         return ret;
 574                 }
 575                 DPAA2_PMD_INFO("MTU configured for the device: %d",
 576                                 dev->data->mtu);
 577         } else {
 578                 return -1;
 579         }
 580
 581         if (eth_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {
 582                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
 583                         ret = dpaa2_setup_flow_dist(dev,
 584                                         eth_conf->rx_adv_conf.rss_conf.rss_hf,
 585                                         tc_index);
 586                         if (ret) {
 587                                 DPAA2_PMD_ERR(
 588                                         "Unable to set flow distribution on tc%d."
 589                                         "Check queue config", tc_index);
 590                                 return ret;
 591                         }
 592                 }
 593         }
 594
 595         if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM)
 596                 rx_l3_csum_offload = true;
 597
 598         if ((rx_offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) ||
 599                 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) ||
 600                 (rx_offloads & RTE_ETH_RX_OFFLOAD_SCTP_CKSUM))
 601                 rx_l4_csum_offload = true;
 602
 603         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 604                                DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
 605         if (ret) {
 606                 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
 607                 return ret;
 608         }
 609
 610         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 611                                DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
 612         if (ret) {
 613                 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
 614                 return ret;
 615         }
 616
 617 #if !defined(RTE_LIBRTE_IEEE1588)
 618         if (rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
 619 #endif
 620         {
 621                 ret = rte_mbuf_dyn_rx_timestamp_register(
 622                                 &dpaa2_timestamp_dynfield_offset,
 623                                 &dpaa2_timestamp_rx_dynflag);
 624                 if (ret != 0) {
 625                         DPAA2_PMD_ERR("Error to register timestamp field/flag");
 626                         return -rte_errno;
 627                 }
 628                 dpaa2_enable_ts[dev->data->port_id] = true;
 629         }
 630
 631         if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)
 632                 tx_l3_csum_offload = true;
 633
 634         if ((tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) ||
 635                 (tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) ||
 636                 (tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM))
 637                 tx_l4_csum_offload = true;
 638
 639         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 640                                DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
 641         if (ret) {
 642                 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
 643                 return ret;
 644         }
 645
 646         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 647                                DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
 648         if (ret) {
 649                 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
 650                 return ret;
 651         }
 652
 653         /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
 654          * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
 655          * to 0 for LS2 in the hardware thus disabling data/annotation
 656          * stashing. For LX2 this is fixed in hardware and thus hash result and
 657          * parse results can be received in FD using this option.
 658          */
 659         if (dpaa2_svr_family == SVR_LX2160A) {
 660                 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 661                                        DPNI_FLCTYPE_HASH, true);
 662                 if (ret) {
 663                         DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
 664                         return ret;
 665                 }
 666         }
 667
 668         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
 669                 dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK);
 670
 671         if (eth_conf->lpbk_mode) {
 672                 ret = dpaa2_dev_recycle_config(dev);
 673                 if (ret) {
 674                         DPAA2_PMD_ERR("Error to configure %s to recycle port.",
 675                                 dev->data->name);
 676
 677                         return ret;
 678                 }
 679         } else {
 680                 /** User may disable loopback mode by calling
 681                  * "dev_configure" with lpbk_mode cleared.
 682                  * No matter the port was configured recycle or not,
 683                  * recycle de-configure is called here.
 684                  * If port is not recycled, the de-configure will return directly.
 685                  */
 686                 ret = dpaa2_dev_recycle_deconfig(dev);
 687                 if (ret) {
 688                         DPAA2_PMD_ERR("Error to de-configure recycle port %s.",
 689                                 dev->data->name);
 690
 691                         return ret;
 692                 }
 693         }
 694
 695         dpaa2_tm_init(dev);
 696
 697         return 0;
 698 }
 699
 700 /* Function to setup RX flow information. It contains traffic class ID,
 701  * flow ID, destination configuration etc.
 702  */
 703 static int
 704 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 705                          uint16_t rx_queue_id,
 706                          uint16_t nb_rx_desc,
 707                          unsigned int socket_id __rte_unused,
 708                          const struct rte_eth_rxconf *rx_conf,
 709                          struct rte_mempool *mb_pool)
 710 {
 711         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 712         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 713         struct dpaa2_queue *dpaa2_q;
 714         struct dpni_queue cfg;
 715         uint8_t options = 0;
 716         uint8_t flow_id;
 717         uint32_t bpid;
 718         int i, ret;
 719
 720         PMD_INIT_FUNC_TRACE();
 721
 722         DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
 723                         dev, rx_queue_id, mb_pool, rx_conf);
 724
 725         total_nb_rx_desc += nb_rx_desc;
 726         if (total_nb_rx_desc > MAX_NB_RX_DESC) {
 727                 DPAA2_PMD_WARN("\nTotal nb_rx_desc exceeds %d limit. Please use Normal buffers",
 728                                MAX_NB_RX_DESC);
 729                 DPAA2_PMD_WARN("To use Normal buffers, run 'export DPNI_NORMAL_BUF=1' before running dynamic_dpl.sh script");
 730         }
 731
 732         /* Rx deferred start is not supported */
 733         if (rx_conf->rx_deferred_start) {
 734                 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
 735                                 (void *)dev);
 736                 return -EINVAL;
 737         }
 738
 739         if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
 740                 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 741                         ret = rte_dpaa2_bpid_info_init(mb_pool);
 742                         if (ret)
 743                                 return ret;
 744                 }
 745                 bpid = mempool_to_bpid(mb_pool);
 746                 ret = dpaa2_attach_bp_list(priv, dpni,
 747                                 rte_dpaa2_bpid_info[bpid].bp_list);
 748                 if (ret)
 749                         return ret;
 750         }
 751         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 752         dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
 753         dpaa2_q->bp_array = rte_dpaa2_bpid_info;
 754         dpaa2_q->nb_desc = UINT16_MAX;
 755         dpaa2_q->offloads = rx_conf->offloads;
 756
 757         /*Get the flow id from given VQ id*/
 758         flow_id = dpaa2_q->flow_id;
 759         memset(&cfg, 0, sizeof(struct dpni_queue));
 760
 761         options = options | DPNI_QUEUE_OPT_USER_CTX;
 762         cfg.user_context = (size_t)(dpaa2_q);
 763
 764         /* check if a private cgr available. */
 765         for (i = 0; i < priv->max_cgs; i++) {
 766                 if (!priv->cgid_in_use[i]) {
 767                         priv->cgid_in_use[i] = 1;
 768                         break;
 769                 }
 770         }
 771
 772         if (i < priv->max_cgs) {
 773                 options |= DPNI_QUEUE_OPT_SET_CGID;
 774                 cfg.cgid = i;
 775                 dpaa2_q->cgid = cfg.cgid;
 776         } else {
 777                 dpaa2_q->cgid = 0xff;
 778         }
 779
 780         /*if ls2088 or rev2 device, enable the stashing */
 781
 782         if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 783                 options |= DPNI_QUEUE_OPT_FLC;
 784                 cfg.flc.stash_control = true;
 785                 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
 786                 /* 00 00 00 - last 6 bit represent annotation, context stashing,
 787                  * data stashing setting 01 01 00 (0x14)
 788                  * (in following order ->DS AS CS)
 789                  * to enable 1 line data, 1 line annotation.
 790                  * For LX2, this setting should be 01 00 00 (0x10)
 791                  */
 792                 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
 793                         cfg.flc.value |= 0x10;
 794                 else
 795                         cfg.flc.value |= 0x14;
 796         }
 797         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 798                              dpaa2_q->tc_index, flow_id, options, &cfg);
 799         if (ret) {
 800                 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
 801                 return -1;
 802         }
 803
 804         if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
 805                 struct dpni_taildrop taildrop;
 806
 807                 taildrop.enable = 1;
 808                 dpaa2_q->nb_desc = nb_rx_desc;
 809                 /* Private CGR will use tail drop length as nb_rx_desc.
 810                  * for rest cases we can use standard byte based tail drop.
 811                  * There is no HW restriction, but number of CGRs are limited,
 812                  * hence this restriction is placed.
 813                  */
 814                 if (dpaa2_q->cgid != 0xff) {
 815                         /*enabling per rx queue congestion control */
 816                         taildrop.threshold = nb_rx_desc;
 817                         taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
 818                         taildrop.oal = 0;
 819                         DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
 820                                         rx_queue_id);
 821                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 822                                                 DPNI_CP_CONGESTION_GROUP,
 823                                                 DPNI_QUEUE_RX,
 824                                                 dpaa2_q->tc_index,
 825                                                 dpaa2_q->cgid, &taildrop);
 826                 } else {
 827                         /*enabling per rx queue congestion control */
 828                         taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
 829                         taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
 830                         taildrop.oal = CONG_RX_OAL;
 831                         DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
 832                                         rx_queue_id);
 833                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 834                                                 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 835                                                 dpaa2_q->tc_index, flow_id,
 836                                                 &taildrop);
 837                 }
 838                 if (ret) {
 839                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 840                                       ret);
 841                         return -1;
 842                 }
 843         } else { /* Disable tail Drop */
 844                 struct dpni_taildrop taildrop = {0};
 845                 DPAA2_PMD_INFO("Tail drop is disabled on queue");
 846
 847                 taildrop.enable = 0;
 848                 if (dpaa2_q->cgid != 0xff) {
 849                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 850                                         DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
 851                                         dpaa2_q->tc_index,
 852                                         dpaa2_q->cgid, &taildrop);
 853                 } else {
 854                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 855                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 856                                         dpaa2_q->tc_index, flow_id, &taildrop);
 857                 }
 858                 if (ret) {
 859                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 860                                       ret);
 861                         return -1;
 862                 }
 863         }
 864
 865         dev->data->rx_queues[rx_queue_id] = dpaa2_q;
 866         return 0;
 867 }
 868
 869 static int
 870 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
 871                          uint16_t tx_queue_id,
 872                          uint16_t nb_tx_desc,
 873                          unsigned int socket_id __rte_unused,
 874                          const struct rte_eth_txconf *tx_conf)
 875 {
 876         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 877         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
 878                 priv->tx_vq[tx_queue_id];
 879         struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
 880                 priv->tx_conf_vq[tx_queue_id];
 881         struct fsl_mc_io *dpni = dev->process_private;
 882         struct dpni_queue tx_conf_cfg;
 883         struct dpni_queue tx_flow_cfg;
 884         uint8_t options = 0, flow_id;
 885         uint16_t channel_id;
 886         struct dpni_queue_id qid;
 887         uint32_t tc_id;
 888         int ret;
 889
 890         PMD_INIT_FUNC_TRACE();
 891
 892         /* Tx deferred start is not supported */
 893         if (tx_conf->tx_deferred_start) {
 894                 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
 895                                 (void *)dev);
 896                 return -EINVAL;
 897         }
 898
 899         dpaa2_q->nb_desc = UINT16_MAX;
 900         dpaa2_q->offloads = tx_conf->offloads;
 901
 902         /* Return if queue already configured */
 903         if (dpaa2_q->flow_id != 0xffff) {
 904                 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 905                 return 0;
 906         }
 907
 908         memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
 909         memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 910
 911         if (tx_queue_id == 0) {
 912                 /*Set tx-conf and error configuration*/
 913                 if (priv->flags & DPAA2_TX_CONF_ENABLE)
 914                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 915                                                             priv->token,
 916                                                             DPNI_CONF_AFFINE);
 917                 else
 918                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 919                                                             priv->token,
 920                                                             DPNI_CONF_DISABLE);
 921                 if (ret) {
 922                         DPAA2_PMD_ERR("Error in set tx conf mode settings: "
 923                                       "err=%d", ret);
 924                         return -1;
 925                 }
 926         }
 927
 928         tc_id = tx_queue_id % priv->num_tx_tc;
 929         channel_id = (uint8_t)(tx_queue_id / priv->num_tx_tc) % priv->num_channels;
 930         flow_id = 0;
 931
 932         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
 933                         ((channel_id << 8) | tc_id), flow_id, options, &tx_flow_cfg);
 934         if (ret) {
 935                 DPAA2_PMD_ERR("Error in setting the tx flow: "
 936                         "tc_id=%d, flow=%d err=%d",
 937                         tc_id, flow_id, ret);
 938                         return -1;
 939         }
 940
 941         dpaa2_q->flow_id = flow_id;
 942
 943         dpaa2_q->tc_index = tc_id;
 944
 945         ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 946                              DPNI_QUEUE_TX, ((channel_id << 8) | dpaa2_q->tc_index),
 947                              dpaa2_q->flow_id, &tx_flow_cfg, &qid);
 948         if (ret) {
 949                 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 950                 return -1;
 951         }
 952         dpaa2_q->fqid = qid.fqid;
 953
 954         if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
 955                 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
 956
 957                 dpaa2_q->nb_desc = nb_tx_desc;
 958
 959                 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
 960                 cong_notif_cfg.threshold_entry = nb_tx_desc;
 961                 /* Notify that the queue is not congested when the data in
 962                  * the queue is below this threshold.(90% of value)
 963                  */
 964                 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
 965                 cong_notif_cfg.message_ctx = 0;
 966                 cong_notif_cfg.message_iova =
 967                                 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
 968                 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
 969                 cong_notif_cfg.notification_mode =
 970                                          DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
 971                                          DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
 972                                          DPNI_CONG_OPT_COHERENT_WRITE;
 973                 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
 974
 975                 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
 976                                                        priv->token,
 977                                                        DPNI_QUEUE_TX,
 978                                                        ((channel_id << 8) | tc_id),
 979                                                        &cong_notif_cfg);
 980                 if (ret) {
 981                         DPAA2_PMD_ERR(
 982                            "Error in setting tx congestion notification: "
 983                            "err=%d", ret);
 984                         return -ret;
 985                 }
 986         }
 987         dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
 988         dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 989
 990         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 991                 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
 992                 options = options | DPNI_QUEUE_OPT_USER_CTX;
 993                 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
 994                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 995                              DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index),
 996                              dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
 997                 if (ret) {
 998                         DPAA2_PMD_ERR("Error in setting the tx conf flow: "
 999                               "tc_index=%d, flow=%d err=%d",
1000                               dpaa2_tx_conf_q->tc_index,
1001                               dpaa2_tx_conf_q->flow_id, ret);
1002                         return -1;
1003                 }
1004
1005                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1006                              DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index),
1007                              dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
1008                 if (ret) {
1009                         DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
1010                         return -1;
1011                 }
1012                 dpaa2_tx_conf_q->fqid = qid.fqid;
1013         }
1014         return 0;
1015 }
1016
1017 static void
1018 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1019 {
1020         struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id];
1021         struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
1022         struct fsl_mc_io *dpni =
1023                 (struct fsl_mc_io *)priv->eth_dev->process_private;
1024         uint8_t options = 0;
1025         int ret;
1026         struct dpni_queue cfg;
1027
1028         memset(&cfg, 0, sizeof(struct dpni_queue));
1029         PMD_INIT_FUNC_TRACE();
1030
1031         total_nb_rx_desc -= dpaa2_q->nb_desc;
1032
1033         if (dpaa2_q->cgid != 0xff) {
1034                 options = DPNI_QUEUE_OPT_CLEAR_CGID;
1035                 cfg.cgid = dpaa2_q->cgid;
1036
1037                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
1038                                      DPNI_QUEUE_RX,
1039                                      dpaa2_q->tc_index, dpaa2_q->flow_id,
1040                                      options, &cfg);
1041                 if (ret)
1042                         DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
1043                                         dpaa2_q->fqid, ret);
1044                 priv->cgid_in_use[dpaa2_q->cgid] = 0;
1045                 dpaa2_q->cgid = 0xff;
1046         }
1047 }
1048
1049 static uint32_t
1050 dpaa2_dev_rx_queue_count(void *rx_queue)
1051 {
1052         int32_t ret;
1053         struct dpaa2_queue *dpaa2_q;
1054         struct qbman_swp *swp;
1055         struct qbman_fq_query_np_rslt state;
1056         uint32_t frame_cnt = 0;
1057
1058         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1059                 ret = dpaa2_affine_qbman_swp();
1060                 if (ret) {
1061                         DPAA2_PMD_ERR(
1062                                 "Failed to allocate IO portal, tid: %d\n",
1063                                 rte_gettid());
1064                         return -EINVAL;
1065                 }
1066         }
1067         swp = DPAA2_PER_LCORE_PORTAL;
1068
1069         dpaa2_q = rx_queue;
1070
1071         if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1072                 frame_cnt = qbman_fq_state_frame_count(&state);
1073                 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u",
1074                                 rx_queue, frame_cnt);
1075         }
1076         return frame_cnt;
1077 }
1078
1079 static const uint32_t *
1080 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1081 {
1082         static const uint32_t ptypes[] = {
1083                 /*todo -= add more types */
1084                 RTE_PTYPE_L2_ETHER,
1085                 RTE_PTYPE_L3_IPV4,
1086                 RTE_PTYPE_L3_IPV4_EXT,
1087                 RTE_PTYPE_L3_IPV6,
1088                 RTE_PTYPE_L3_IPV6_EXT,
1089                 RTE_PTYPE_L4_TCP,
1090                 RTE_PTYPE_L4_UDP,
1091                 RTE_PTYPE_L4_SCTP,
1092                 RTE_PTYPE_L4_ICMP,
1093                 RTE_PTYPE_UNKNOWN
1094         };
1095
1096         if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1097                 dev->rx_pkt_burst == dpaa2_dev_rx ||
1098                 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1099                 return ptypes;
1100         return NULL;
1101 }
1102
1103 /**
1104  * Dpaa2 link Interrupt handler
1105  *
1106  * @param param
1107  *  The address of parameter (struct rte_eth_dev *) registered before.
1108  *
1109  * @return
1110  *  void
1111  */
1112 static void
1113 dpaa2_interrupt_handler(void *param)
1114 {
1115         struct rte_eth_dev *dev = param;
1116         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1117         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1118         int ret;
1119         int irq_index = DPNI_IRQ_INDEX;
1120         unsigned int status = 0, clear = 0;
1121
1122         PMD_INIT_FUNC_TRACE();
1123
1124         if (dpni == NULL) {
1125                 DPAA2_PMD_ERR("dpni is NULL");
1126                 return;
1127         }
1128
1129         ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1130                                   irq_index, &status);
1131         if (unlikely(ret)) {
1132                 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1133                 clear = 0xffffffff;
1134                 goto out;
1135         }
1136
1137         if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1138                 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1139                 dpaa2_dev_link_update(dev, 0);
1140                 /* calling all the apps registered for link status event */
1141                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1142         }
1143 out:
1144         ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1145                                     irq_index, clear);
1146         if (unlikely(ret))
1147                 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1148 }
1149
1150 static int
1151 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1152 {
1153         int err = 0;
1154         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1155         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1156         int irq_index = DPNI_IRQ_INDEX;
1157         unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1158
1159         PMD_INIT_FUNC_TRACE();
1160
1161         err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1162                                 irq_index, mask);
1163         if (err < 0) {
1164                 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1165                               strerror(-err));
1166                 return err;
1167         }
1168
1169         err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1170                                   irq_index, enable);
1171         if (err < 0)
1172                 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1173                               strerror(-err));
1174
1175         return err;
1176 }
1177
1178 static int
1179 dpaa2_dev_start(struct rte_eth_dev *dev)
1180 {
1181         struct rte_device *rdev = dev->device;
1182         struct rte_dpaa2_device *dpaa2_dev;
1183         struct rte_eth_dev_data *data = dev->data;
1184         struct dpaa2_dev_priv *priv = data->dev_private;
1185         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1186         struct dpni_queue cfg;
1187         struct dpni_error_cfg   err_cfg;
1188         struct dpni_queue_id qid;
1189         struct dpaa2_queue *dpaa2_q;
1190         int ret, i;
1191         struct rte_intr_handle *intr_handle;
1192
1193         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1194         intr_handle = dpaa2_dev->intr_handle;
1195
1196         PMD_INIT_FUNC_TRACE();
1197         ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1198         if (ret) {
1199                 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1200                               priv->hw_id, ret);
1201                 return ret;
1202         }
1203
1204         /* Power up the phy. Needed to make the link go UP */
1205         dpaa2_dev_set_link_up(dev);
1206
1207         for (i = 0; i < data->nb_rx_queues; i++) {
1208                 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1209                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1210                                      DPNI_QUEUE_RX, dpaa2_q->tc_index,
1211                                        dpaa2_q->flow_id, &cfg, &qid);
1212                 if (ret) {
1213                         DPAA2_PMD_ERR("Error in getting flow information: "
1214                                       "err=%d", ret);
1215                         return ret;
1216                 }
1217                 dpaa2_q->fqid = qid.fqid;
1218         }
1219
1220         if (dpaa2_enable_err_queue) {
1221                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1222                                      DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1223                 if (ret) {
1224                         DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1225                                                 ret);
1226                         return ret;
1227                 }
1228                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1229                 dpaa2_q->fqid = qid.fqid;
1230                 dpaa2_q->eth_data = dev->data;
1231
1232                 err_cfg.errors =  DPNI_ERROR_DISC;
1233                 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1234         } else {
1235                 /* checksum errors, send them to normal path
1236                  * and set it in annotation
1237                  */
1238                 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1239
1240                 /* if packet with parse error are not to be dropped */
1241                 err_cfg.errors |= DPNI_ERROR_PHE;
1242
1243                 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1244         }
1245         err_cfg.set_frame_annotation = true;
1246
1247         ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1248                                        priv->token, &err_cfg);
1249         if (ret) {
1250                 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1251                               ret);
1252                 return ret;
1253         }
1254
1255         /* if the interrupts were configured on this devices*/
1256         if (intr_handle && rte_intr_fd_get(intr_handle) &&
1257             dev->data->dev_conf.intr_conf.lsc != 0) {
1258                 /* Registering LSC interrupt handler */
1259                 rte_intr_callback_register(intr_handle,
1260                                            dpaa2_interrupt_handler,
1261                                            (void *)dev);
1262
1263                 /* enable vfio intr/eventfd mapping
1264                  * Interrupt index 0 is required, so we can not use
1265                  * rte_intr_enable.
1266                  */
1267                 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1268
1269                 /* enable dpni_irqs */
1270                 dpaa2_eth_setup_irqs(dev, 1);
1271         }
1272
1273         /* Change the tx burst function if ordered queues are used */
1274         if (priv->en_ordered)
1275                 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1276
1277         return 0;
1278 }
1279
1280 /**
1281  *  This routine disables all traffic on the adapter by issuing a
1282  *  global reset on the MAC.
1283  */
1284 static int
1285 dpaa2_dev_stop(struct rte_eth_dev *dev)
1286 {
1287         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1288         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1289         int ret;
1290         struct rte_eth_link link;
1291         struct rte_device *rdev = dev->device;
1292         struct rte_intr_handle *intr_handle;
1293         struct rte_dpaa2_device *dpaa2_dev;
1294
1295         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1296         intr_handle = dpaa2_dev->intr_handle;
1297
1298         PMD_INIT_FUNC_TRACE();
1299
1300         /* reset interrupt callback  */
1301         if (intr_handle && rte_intr_fd_get(intr_handle) &&
1302             dev->data->dev_conf.intr_conf.lsc != 0) {
1303                 /*disable dpni irqs */
1304                 dpaa2_eth_setup_irqs(dev, 0);
1305
1306                 /* disable vfio intr before callback unregister */
1307                 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1308
1309                 /* Unregistering LSC interrupt handler */
1310                 rte_intr_callback_unregister(intr_handle,
1311                                              dpaa2_interrupt_handler,
1312                                              (void *)dev);
1313         }
1314
1315         dpaa2_dev_set_link_down(dev);
1316
1317         ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1318         if (ret) {
1319                 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1320                               ret, priv->hw_id);
1321                 return ret;
1322         }
1323
1324         /* clear the recorded link status */
1325         memset(&link, 0, sizeof(link));
1326         rte_eth_linkstatus_set(dev, &link);
1327
1328         return 0;
1329 }
1330
1331 static int
1332 dpaa2_dev_close(struct rte_eth_dev *dev)
1333 {
1334         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1335         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1336         int i, ret;
1337         struct rte_eth_link link;
1338
1339         PMD_INIT_FUNC_TRACE();
1340
1341         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1342                 return 0;
1343
1344         if (!dpni) {
1345                 DPAA2_PMD_WARN("Already closed or not started");
1346                 return -1;
1347         }
1348
1349         dpaa2_tm_deinit(dev);
1350         dpaa2_flow_clean(dev);
1351         /* Clean the device first */
1352         ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1353         if (ret) {
1354                 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1355                 return -1;
1356         }
1357
1358         memset(&link, 0, sizeof(link));
1359         rte_eth_linkstatus_set(dev, &link);
1360
1361         /* Free private queues memory */
1362         dpaa2_free_rx_tx_queues(dev);
1363         /* Close the device at underlying layer*/
1364         ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1365         if (ret) {
1366                 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1367                               ret);
1368         }
1369
1370         /* Free the allocated memory for ethernet private data and dpni*/
1371         priv->hw = NULL;
1372         dev->process_private = NULL;
1373         rte_free(dpni);
1374
1375         for (i = 0; i < MAX_TCS; i++)
1376                 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1377
1378         if (priv->extract.qos_extract_param)
1379                 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1380
1381         DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1382         return 0;
1383 }
1384
1385 static int
1386 dpaa2_dev_promiscuous_enable(
1387                 struct rte_eth_dev *dev)
1388 {
1389         int ret;
1390         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1391         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1392
1393         PMD_INIT_FUNC_TRACE();
1394
1395         if (dpni == NULL) {
1396                 DPAA2_PMD_ERR("dpni is NULL");
1397                 return -ENODEV;
1398         }
1399
1400         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1401         if (ret < 0)
1402                 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1403
1404         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1405         if (ret < 0)
1406                 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1407
1408         return ret;
1409 }
1410
1411 static int
1412 dpaa2_dev_promiscuous_disable(
1413                 struct rte_eth_dev *dev)
1414 {
1415         int ret;
1416         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1417         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1418
1419         PMD_INIT_FUNC_TRACE();
1420
1421         if (dpni == NULL) {
1422                 DPAA2_PMD_ERR("dpni is NULL");
1423                 return -ENODEV;
1424         }
1425
1426         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1427         if (ret < 0)
1428                 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1429
1430         if (dev->data->all_multicast == 0) {
1431                 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1432                                                  priv->token, false);
1433                 if (ret < 0)
1434                         DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1435                                       ret);
1436         }
1437
1438         return ret;
1439 }
1440
1441 static int
1442 dpaa2_dev_allmulticast_enable(
1443                 struct rte_eth_dev *dev)
1444 {
1445         int ret;
1446         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1447         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1448
1449         PMD_INIT_FUNC_TRACE();
1450
1451         if (dpni == NULL) {
1452                 DPAA2_PMD_ERR("dpni is NULL");
1453                 return -ENODEV;
1454         }
1455
1456         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1457         if (ret < 0)
1458                 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1459
1460         return ret;
1461 }
1462
1463 static int
1464 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1465 {
1466         int ret;
1467         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1468         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1469
1470         PMD_INIT_FUNC_TRACE();
1471
1472         if (dpni == NULL) {
1473                 DPAA2_PMD_ERR("dpni is NULL");
1474                 return -ENODEV;
1475         }
1476
1477         /* must remain on for all promiscuous */
1478         if (dev->data->promiscuous == 1)
1479                 return 0;
1480
1481         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1482         if (ret < 0)
1483                 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1484
1485         return ret;
1486 }
1487
1488 static int
1489 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1490 {
1491         int ret;
1492         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1493         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1494         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1495                                 + VLAN_TAG_SIZE;
1496
1497         PMD_INIT_FUNC_TRACE();
1498
1499         if (dpni == NULL) {
1500                 DPAA2_PMD_ERR("dpni is NULL");
1501                 return -EINVAL;
1502         }
1503
1504         /* Set the Max Rx frame length as 'mtu' +
1505          * Maximum Ethernet header length
1506          */
1507         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1508                                         frame_size - RTE_ETHER_CRC_LEN);
1509         if (ret) {
1510                 DPAA2_PMD_ERR("Setting the max frame length failed");
1511                 return -1;
1512         }
1513         DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1514         return 0;
1515 }
1516
1517 static int
1518 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1519                        struct rte_ether_addr *addr,
1520                        __rte_unused uint32_t index,
1521                        __rte_unused uint32_t pool)
1522 {
1523         int ret;
1524         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1525         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1526
1527         PMD_INIT_FUNC_TRACE();
1528
1529         if (dpni == NULL) {
1530                 DPAA2_PMD_ERR("dpni is NULL");
1531                 return -1;
1532         }
1533
1534         ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1535                                 addr->addr_bytes, 0, 0, 0);
1536         if (ret)
1537                 DPAA2_PMD_ERR(
1538                         "error: Adding the MAC ADDR failed: err = %d", ret);
1539         return 0;
1540 }
1541
1542 static void
1543 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1544                           uint32_t index)
1545 {
1546         int ret;
1547         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1548         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1549         struct rte_eth_dev_data *data = dev->data;
1550         struct rte_ether_addr *macaddr;
1551
1552         PMD_INIT_FUNC_TRACE();
1553
1554         macaddr = &data->mac_addrs[index];
1555
1556         if (dpni == NULL) {
1557                 DPAA2_PMD_ERR("dpni is NULL");
1558                 return;
1559         }
1560
1561         ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1562                                    priv->token, macaddr->addr_bytes);
1563         if (ret)
1564                 DPAA2_PMD_ERR(
1565                         "error: Removing the MAC ADDR failed: err = %d", ret);
1566 }
1567
1568 static int
1569 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1570                        struct rte_ether_addr *addr)
1571 {
1572         int ret;
1573         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1574         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1575
1576         PMD_INIT_FUNC_TRACE();
1577
1578         if (dpni == NULL) {
1579                 DPAA2_PMD_ERR("dpni is NULL");
1580                 return -EINVAL;
1581         }
1582
1583         ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1584                                         priv->token, addr->addr_bytes);
1585
1586         if (ret)
1587                 DPAA2_PMD_ERR(
1588                         "error: Setting the MAC ADDR failed %d", ret);
1589
1590         return ret;
1591 }
1592
1593 static
1594 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1595                          struct rte_eth_stats *stats)
1596 {
1597         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1598         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1599         int32_t  retcode;
1600         uint8_t page0 = 0, page1 = 1, page2 = 2;
1601         union dpni_statistics value;
1602         int i;
1603         struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1604
1605         memset(&value, 0, sizeof(union dpni_statistics));
1606
1607         PMD_INIT_FUNC_TRACE();
1608
1609         if (!dpni) {
1610                 DPAA2_PMD_ERR("dpni is NULL");
1611                 return -EINVAL;
1612         }
1613
1614         if (!stats) {
1615                 DPAA2_PMD_ERR("stats is NULL");
1616                 return -EINVAL;
1617         }
1618
1619         /*Get Counters from page_0*/
1620         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1621                                       page0, 0, &value);
1622         if (retcode)
1623                 goto err;
1624
1625         stats->ipackets = value.page_0.ingress_all_frames;
1626         stats->ibytes = value.page_0.ingress_all_bytes;
1627
1628         /*Get Counters from page_1*/
1629         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1630                                       page1, 0, &value);
1631         if (retcode)
1632                 goto err;
1633
1634         stats->opackets = value.page_1.egress_all_frames;
1635         stats->obytes = value.page_1.egress_all_bytes;
1636
1637         /*Get Counters from page_2*/
1638         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1639                                       page2, 0, &value);
1640         if (retcode)
1641                 goto err;
1642
1643         /* Ingress drop frame count due to configured rules */
1644         stats->ierrors = value.page_2.ingress_filtered_frames;
1645         /* Ingress drop frame count due to error */
1646         stats->ierrors += value.page_2.ingress_discarded_frames;
1647
1648         stats->oerrors = value.page_2.egress_discarded_frames;
1649         stats->imissed = value.page_2.ingress_nobuffer_discards;
1650
1651         /* Fill in per queue stats */
1652         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1653                 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1654                 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1655                 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1656                 if (dpaa2_rxq)
1657                         stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1658                 if (dpaa2_txq)
1659                         stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1660
1661                 /* Byte counting is not implemented */
1662                 stats->q_ibytes[i]   = 0;
1663                 stats->q_obytes[i]   = 0;
1664         }
1665
1666         return 0;
1667
1668 err:
1669         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1670         return retcode;
1671 };
1672
1673 static int
1674 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1675                      unsigned int n)
1676 {
1677         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1678         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1679         int32_t  retcode;
1680         union dpni_statistics value[5] = {};
1681         unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1682
1683         if (n < num)
1684                 return num;
1685
1686         if (xstats == NULL)
1687                 return 0;
1688
1689         /* Get Counters from page_0*/
1690         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1691                                       0, 0, &value[0]);
1692         if (retcode)
1693                 goto err;
1694
1695         /* Get Counters from page_1*/
1696         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1697                                       1, 0, &value[1]);
1698         if (retcode)
1699                 goto err;
1700
1701         /* Get Counters from page_2*/
1702         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1703                                       2, 0, &value[2]);
1704         if (retcode)
1705                 goto err;
1706
1707         for (i = 0; i < priv->max_cgs; i++) {
1708                 if (!priv->cgid_in_use[i]) {
1709                         /* Get Counters from page_4*/
1710                         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1711                                                       priv->token,
1712                                                       4, 0, &value[4]);
1713                         if (retcode)
1714                                 goto err;
1715                         break;
1716                 }
1717         }
1718
1719         for (i = 0; i < num; i++) {
1720                 xstats[i].id = i;
1721                 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1722                         raw.counter[dpaa2_xstats_strings[i].stats_id];
1723         }
1724         return i;
1725 err:
1726         DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1727         return retcode;
1728 }
1729
1730 static int
1731 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1732                        struct rte_eth_xstat_name *xstats_names,
1733                        unsigned int limit)
1734 {
1735         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1736
1737         if (limit < stat_cnt)
1738                 return stat_cnt;
1739
1740         if (xstats_names != NULL)
1741                 for (i = 0; i < stat_cnt; i++)
1742                         strlcpy(xstats_names[i].name,
1743                                 dpaa2_xstats_strings[i].name,
1744                                 sizeof(xstats_names[i].name));
1745
1746         return stat_cnt;
1747 }
1748
1749 static int
1750 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1751                        uint64_t *values, unsigned int n)
1752 {
1753         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1754         uint64_t values_copy[stat_cnt];
1755
1756         if (!ids) {
1757                 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1758                 struct fsl_mc_io *dpni =
1759                         (struct fsl_mc_io *)dev->process_private;
1760                 int32_t  retcode;
1761                 union dpni_statistics value[5] = {};
1762
1763                 if (n < stat_cnt)
1764                         return stat_cnt;
1765
1766                 if (!values)
1767                         return 0;
1768
1769                 /* Get Counters from page_0*/
1770                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1771                                               0, 0, &value[0]);
1772                 if (retcode)
1773                         return 0;
1774
1775                 /* Get Counters from page_1*/
1776                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1777                                               1, 0, &value[1]);
1778                 if (retcode)
1779                         return 0;
1780
1781                 /* Get Counters from page_2*/
1782                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1783                                               2, 0, &value[2]);
1784                 if (retcode)
1785                         return 0;
1786
1787                 /* Get Counters from page_4*/
1788                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1789                                               4, 0, &value[4]);
1790                 if (retcode)
1791                         return 0;
1792
1793                 for (i = 0; i < stat_cnt; i++) {
1794                         values[i] = value[dpaa2_xstats_strings[i].page_id].
1795                                 raw.counter[dpaa2_xstats_strings[i].stats_id];
1796                 }
1797                 return stat_cnt;
1798         }
1799
1800         dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1801
1802         for (i = 0; i < n; i++) {
1803                 if (ids[i] >= stat_cnt) {
1804                         DPAA2_PMD_ERR("xstats id value isn't valid");
1805                         return -1;
1806                 }
1807                 values[i] = values_copy[ids[i]];
1808         }
1809         return n;
1810 }
1811
1812 static int
1813 dpaa2_xstats_get_names_by_id(
1814         struct rte_eth_dev *dev,
1815         const uint64_t *ids,
1816         struct rte_eth_xstat_name *xstats_names,
1817         unsigned int limit)
1818 {
1819         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1820         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1821
1822         if (!ids)
1823                 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1824
1825         dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1826
1827         for (i = 0; i < limit; i++) {
1828                 if (ids[i] >= stat_cnt) {
1829                         DPAA2_PMD_ERR("xstats id value isn't valid");
1830                         return -1;
1831                 }
1832                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1833         }
1834         return limit;
1835 }
1836
1837 static int
1838 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1839 {
1840         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1841         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1842         int retcode;
1843         int i;
1844         struct dpaa2_queue *dpaa2_q;
1845
1846         PMD_INIT_FUNC_TRACE();
1847
1848         if (dpni == NULL) {
1849                 DPAA2_PMD_ERR("dpni is NULL");
1850                 return -EINVAL;
1851         }
1852
1853         retcode =  dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1854         if (retcode)
1855                 goto error;
1856
1857         /* Reset the per queue stats in dpaa2_queue structure */
1858         for (i = 0; i < priv->nb_rx_queues; i++) {
1859                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1860                 if (dpaa2_q)
1861                         dpaa2_q->rx_pkts = 0;
1862         }
1863
1864         for (i = 0; i < priv->nb_tx_queues; i++) {
1865                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1866                 if (dpaa2_q)
1867                         dpaa2_q->tx_pkts = 0;
1868         }
1869
1870         return 0;
1871
1872 error:
1873         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1874         return retcode;
1875 };
1876
1877 /* return 0 means link status changed, -1 means not changed */
1878 static int
1879 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1880                       int wait_to_complete)
1881 {
1882         int ret;
1883         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1884         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1885         struct rte_eth_link link;
1886         struct dpni_link_state state = {0};
1887         uint8_t count;
1888
1889         if (dpni == NULL) {
1890                 DPAA2_PMD_ERR("dpni is NULL");
1891                 return 0;
1892         }
1893
1894         for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1895                 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1896                                           &state);
1897                 if (ret < 0) {
1898                         DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1899                         return -1;
1900                 }
1901                 if (state.up == RTE_ETH_LINK_DOWN &&
1902                     wait_to_complete)
1903                         rte_delay_ms(CHECK_INTERVAL);
1904                 else
1905                         break;
1906         }
1907
1908         memset(&link, 0, sizeof(struct rte_eth_link));
1909         link.link_status = state.up;
1910         link.link_speed = state.rate;
1911
1912         if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1913                 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
1914         else
1915                 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1916
1917         ret = rte_eth_linkstatus_set(dev, &link);
1918         if (ret == -1)
1919                 DPAA2_PMD_DEBUG("No change in status");
1920         else
1921                 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1922                                link.link_status ? "Up" : "Down");
1923
1924         return ret;
1925 }
1926
1927 /**
1928  * Toggle the DPNI to enable, if not already enabled.
1929  * This is not strictly PHY up/down - it is more of logical toggling.
1930  */
1931 static int
1932 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1933 {
1934         int ret = -EINVAL;
1935         struct dpaa2_dev_priv *priv;
1936         struct fsl_mc_io *dpni;
1937         int en = 0;
1938         struct dpni_link_state state = {0};
1939
1940         priv = dev->data->dev_private;
1941         dpni = (struct fsl_mc_io *)dev->process_private;
1942
1943         if (dpni == NULL) {
1944                 DPAA2_PMD_ERR("dpni is NULL");
1945                 return ret;
1946         }
1947
1948         /* Check if DPNI is currently enabled */
1949         ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1950         if (ret) {
1951                 /* Unable to obtain dpni status; Not continuing */
1952                 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1953                 return -EINVAL;
1954         }
1955
1956         /* Enable link if not already enabled */
1957         if (!en) {
1958                 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1959                 if (ret) {
1960                         DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1961                         return -EINVAL;
1962                 }
1963         }
1964         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1965         if (ret < 0) {
1966                 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1967                 return -1;
1968         }
1969
1970         /* changing tx burst function to start enqueues */
1971         dev->tx_pkt_burst = dpaa2_dev_tx;
1972         dev->data->dev_link.link_status = state.up;
1973         dev->data->dev_link.link_speed = state.rate;
1974
1975         if (state.up)
1976                 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1977         else
1978                 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1979         return ret;
1980 }
1981
1982 /**
1983  * Toggle the DPNI to disable, if not already disabled.
1984  * This is not strictly PHY up/down - it is more of logical toggling.
1985  */
1986 static int
1987 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1988 {
1989         int ret = -EINVAL;
1990         struct dpaa2_dev_priv *priv;
1991         struct fsl_mc_io *dpni;
1992         int dpni_enabled = 0;
1993         int retries = 10;
1994
1995         PMD_INIT_FUNC_TRACE();
1996
1997         priv = dev->data->dev_private;
1998         dpni = (struct fsl_mc_io *)dev->process_private;
1999
2000         if (dpni == NULL) {
2001                 DPAA2_PMD_ERR("Device has not yet been configured");
2002                 return ret;
2003         }
2004
2005         /*changing  tx burst function to avoid any more enqueues */
2006         dev->tx_pkt_burst = dummy_dev_tx;
2007
2008         /* Loop while dpni_disable() attempts to drain the egress FQs
2009          * and confirm them back to us.
2010          */
2011         do {
2012                 ret = dpni_disable(dpni, 0, priv->token);
2013                 if (ret) {
2014                         DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
2015                         return ret;
2016                 }
2017                 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
2018                 if (ret) {
2019                         DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
2020                         return ret;
2021                 }
2022                 if (dpni_enabled)
2023                         /* Allow the MC some slack */
2024                         rte_delay_us(100 * 1000);
2025         } while (dpni_enabled && --retries);
2026
2027         if (!retries) {
2028                 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
2029                 /* todo- we may have to manually cleanup queues.
2030                  */
2031         } else {
2032                 DPAA2_PMD_INFO("Port %d Link DOWN successful",
2033                                dev->data->port_id);
2034         }
2035
2036         dev->data->dev_link.link_status = 0;
2037
2038         return ret;
2039 }
2040
2041 static int
2042 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2043 {
2044         int ret = -EINVAL;
2045         struct dpaa2_dev_priv *priv;
2046         struct fsl_mc_io *dpni;
2047         struct dpni_link_state state = {0};
2048
2049         PMD_INIT_FUNC_TRACE();
2050
2051         priv = dev->data->dev_private;
2052         dpni = (struct fsl_mc_io *)dev->process_private;
2053
2054         if (dpni == NULL || fc_conf == NULL) {
2055                 DPAA2_PMD_ERR("device not configured");
2056                 return ret;
2057         }
2058
2059         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2060         if (ret) {
2061                 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2062                 return ret;
2063         }
2064
2065         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2066         if (state.options & DPNI_LINK_OPT_PAUSE) {
2067                 /* DPNI_LINK_OPT_PAUSE set
2068                  *  if ASYM_PAUSE not set,
2069                  *      RX Side flow control (handle received Pause frame)
2070                  *      TX side flow control (send Pause frame)
2071                  *  if ASYM_PAUSE set,
2072                  *      RX Side flow control (handle received Pause frame)
2073                  *      No TX side flow control (send Pause frame disabled)
2074                  */
2075                 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2076                         fc_conf->mode = RTE_ETH_FC_FULL;
2077                 else
2078                         fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2079         } else {
2080                 /* DPNI_LINK_OPT_PAUSE not set
2081                  *  if ASYM_PAUSE set,
2082                  *      TX side flow control (send Pause frame)
2083                  *      No RX side flow control (No action on pause frame rx)
2084                  *  if ASYM_PAUSE not set,
2085                  *      Flow control disabled
2086                  */
2087                 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2088                         fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2089                 else
2090                         fc_conf->mode = RTE_ETH_FC_NONE;
2091         }
2092
2093         return ret;
2094 }
2095
2096 static int
2097 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2098 {
2099         int ret = -EINVAL;
2100         struct dpaa2_dev_priv *priv;
2101         struct fsl_mc_io *dpni;
2102         struct dpni_link_state state = {0};
2103         struct dpni_link_cfg cfg = {0};
2104
2105         PMD_INIT_FUNC_TRACE();
2106
2107         priv = dev->data->dev_private;
2108         dpni = (struct fsl_mc_io *)dev->process_private;
2109
2110         if (dpni == NULL) {
2111                 DPAA2_PMD_ERR("dpni is NULL");
2112                 return ret;
2113         }
2114
2115         /* It is necessary to obtain the current state before setting fc_conf
2116          * as MC would return error in case rate, autoneg or duplex values are
2117          * different.
2118          */
2119         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2120         if (ret) {
2121                 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2122                 return -1;
2123         }
2124
2125         /* Disable link before setting configuration */
2126         dpaa2_dev_set_link_down(dev);
2127
2128         /* Based on fc_conf, update cfg */
2129         cfg.rate = state.rate;
2130         cfg.options = state.options;
2131
2132         /* update cfg with fc_conf */
2133         switch (fc_conf->mode) {
2134         case RTE_ETH_FC_FULL:
2135                 /* Full flow control;
2136                  * OPT_PAUSE set, ASYM_PAUSE not set
2137                  */
2138                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2139                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2140                 break;
2141         case RTE_ETH_FC_TX_PAUSE:
2142                 /* Enable RX flow control
2143                  * OPT_PAUSE not set;
2144                  * ASYM_PAUSE set;
2145                  */
2146                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2147                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2148                 break;
2149         case RTE_ETH_FC_RX_PAUSE:
2150                 /* Enable TX Flow control
2151                  * OPT_PAUSE set
2152                  * ASYM_PAUSE set
2153                  */
2154                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2155                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2156                 break;
2157         case RTE_ETH_FC_NONE:
2158                 /* Disable Flow control
2159                  * OPT_PAUSE not set
2160                  * ASYM_PAUSE not set
2161                  */
2162                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2163                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2164                 break;
2165         default:
2166                 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2167                               fc_conf->mode);
2168                 return -1;
2169         }
2170
2171         ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2172         if (ret)
2173                 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2174                               ret);
2175
2176         /* Enable link */
2177         dpaa2_dev_set_link_up(dev);
2178
2179         return ret;
2180 }
2181
2182 static int
2183 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2184                           struct rte_eth_rss_conf *rss_conf)
2185 {
2186         struct rte_eth_dev_data *data = dev->data;
2187         struct dpaa2_dev_priv *priv = data->dev_private;
2188         struct rte_eth_conf *eth_conf = &data->dev_conf;
2189         int ret, tc_index;
2190
2191         PMD_INIT_FUNC_TRACE();
2192
2193         if (rss_conf->rss_hf) {
2194                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2195                         ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2196                                 tc_index);
2197                         if (ret) {
2198                                 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2199                                         tc_index);
2200                                 return ret;
2201                         }
2202                 }
2203         } else {
2204                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2205                         ret = dpaa2_remove_flow_dist(dev, tc_index);
2206                         if (ret) {
2207                                 DPAA2_PMD_ERR(
2208                                         "Unable to remove flow dist on tc%d",
2209                                         tc_index);
2210                                 return ret;
2211                         }
2212                 }
2213         }
2214         eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2215         return 0;
2216 }
2217
2218 static int
2219 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2220                             struct rte_eth_rss_conf *rss_conf)
2221 {
2222         struct rte_eth_dev_data *data = dev->data;
2223         struct rte_eth_conf *eth_conf = &data->dev_conf;
2224
2225         /* dpaa2 does not support rss_key, so length should be 0*/
2226         rss_conf->rss_key_len = 0;
2227         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2228         return 0;
2229 }
2230
2231 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2232                 int eth_rx_queue_id,
2233                 struct dpaa2_dpcon_dev *dpcon,
2234                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2235 {
2236         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2237         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2238         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2239         uint8_t flow_id = dpaa2_ethq->flow_id;
2240         struct dpni_queue cfg;
2241         uint8_t options, priority;
2242         int ret;
2243
2244         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2245                 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2246         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2247                 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2248         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2249                 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2250         else
2251                 return -EINVAL;
2252
2253         priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2254                    (dpcon->num_priorities - 1);
2255
2256         memset(&cfg, 0, sizeof(struct dpni_queue));
2257         options = DPNI_QUEUE_OPT_DEST;
2258         cfg.destination.type = DPNI_DEST_DPCON;
2259         cfg.destination.id = dpcon->dpcon_id;
2260         cfg.destination.priority = priority;
2261
2262         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2263                 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2264                 cfg.destination.hold_active = 1;
2265         }
2266
2267         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2268                         !eth_priv->en_ordered) {
2269                 struct opr_cfg ocfg;
2270
2271                 /* Restoration window size = 256 frames */
2272                 ocfg.oprrws = 3;
2273                 /* Restoration window size = 512 frames for LX2 */
2274                 if (dpaa2_svr_family == SVR_LX2160A)
2275                         ocfg.oprrws = 4;
2276                 /* Auto advance NESN window enabled */
2277                 ocfg.oa = 1;
2278                 /* Late arrival window size disabled */
2279                 ocfg.olws = 0;
2280                 /* ORL resource exhaustion advance NESN disabled */
2281                 ocfg.oeane = 0;
2282                 /* Loose ordering enabled */
2283                 ocfg.oloe = 1;
2284                 eth_priv->en_loose_ordered = 1;
2285                 /* Strict ordering enabled if explicitly set */
2286                 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2287                         ocfg.oloe = 0;
2288                         eth_priv->en_loose_ordered = 0;
2289                 }
2290
2291                 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2292                                    dpaa2_ethq->tc_index, flow_id,
2293                                    OPR_OPT_CREATE, &ocfg, 0);
2294                 if (ret) {
2295                         DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2296                         return ret;
2297                 }
2298
2299                 eth_priv->en_ordered = 1;
2300         }
2301
2302         options |= DPNI_QUEUE_OPT_USER_CTX;
2303         cfg.user_context = (size_t)(dpaa2_ethq);
2304
2305         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2306                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2307         if (ret) {
2308                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2309                 return ret;
2310         }
2311
2312         memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2313
2314         return 0;
2315 }
2316
2317 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2318                 int eth_rx_queue_id)
2319 {
2320         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2321         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2322         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2323         uint8_t flow_id = dpaa2_ethq->flow_id;
2324         struct dpni_queue cfg;
2325         uint8_t options;
2326         int ret;
2327
2328         memset(&cfg, 0, sizeof(struct dpni_queue));
2329         options = DPNI_QUEUE_OPT_DEST;
2330         cfg.destination.type = DPNI_DEST_NONE;
2331
2332         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2333                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2334         if (ret)
2335                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2336
2337         return ret;
2338 }
2339
2340 static int
2341 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev,
2342                        const struct rte_flow_ops **ops)
2343 {
2344         if (!dev)
2345                 return -ENODEV;
2346
2347         *ops = &dpaa2_flow_ops;
2348         return 0;
2349 }
2350
2351 static void
2352 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2353         struct rte_eth_rxq_info *qinfo)
2354 {
2355         struct dpaa2_queue *rxq;
2356         struct dpaa2_dev_priv *priv = dev->data->dev_private;
2357         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2358         uint16_t max_frame_length;
2359
2360         rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2361
2362         qinfo->mp = rxq->mb_pool;
2363         qinfo->scattered_rx = dev->data->scattered_rx;
2364         qinfo->nb_desc = rxq->nb_desc;
2365         if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2366                                 &max_frame_length) == 0)
2367                 qinfo->rx_buf_size = max_frame_length;
2368
2369         qinfo->conf.rx_free_thresh = 1;
2370         qinfo->conf.rx_drop_en = 1;
2371         qinfo->conf.rx_deferred_start = 0;
2372         qinfo->conf.offloads = rxq->offloads;
2373 }
2374
2375 static void
2376 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2377         struct rte_eth_txq_info *qinfo)
2378 {
2379         struct dpaa2_queue *txq;
2380
2381         txq = dev->data->tx_queues[queue_id];
2382
2383         qinfo->nb_desc = txq->nb_desc;
2384         qinfo->conf.tx_thresh.pthresh = 0;
2385         qinfo->conf.tx_thresh.hthresh = 0;
2386         qinfo->conf.tx_thresh.wthresh = 0;
2387
2388         qinfo->conf.tx_free_thresh = 0;
2389         qinfo->conf.tx_rs_thresh = 0;
2390         qinfo->conf.offloads = txq->offloads;
2391         qinfo->conf.tx_deferred_start = 0;
2392 }
2393
2394 static int
2395 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2396 {
2397         *(const void **)ops = &dpaa2_tm_ops;
2398
2399         return 0;
2400 }
2401
2402 void
2403 rte_pmd_dpaa2_thread_init(void)
2404 {
2405         int ret;
2406
2407         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
2408                 ret = dpaa2_affine_qbman_swp();
2409                 if (ret) {
2410                         DPAA2_PMD_ERR(
2411                                 "Failed to allocate IO portal, tid: %d\n",
2412                                 rte_gettid());
2413                         return;
2414                 }
2415         }
2416 }
2417
2418 static struct eth_dev_ops dpaa2_ethdev_ops = {
2419         .dev_configure    = dpaa2_eth_dev_configure,
2420         .dev_start            = dpaa2_dev_start,
2421         .dev_stop             = dpaa2_dev_stop,
2422         .dev_close            = dpaa2_dev_close,
2423         .promiscuous_enable   = dpaa2_dev_promiscuous_enable,
2424         .promiscuous_disable  = dpaa2_dev_promiscuous_disable,
2425         .allmulticast_enable  = dpaa2_dev_allmulticast_enable,
2426         .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2427         .dev_set_link_up      = dpaa2_dev_set_link_up,
2428         .dev_set_link_down    = dpaa2_dev_set_link_down,
2429         .link_update       = dpaa2_dev_link_update,
2430         .stats_get             = dpaa2_dev_stats_get,
2431         .xstats_get            = dpaa2_dev_xstats_get,
2432         .xstats_get_by_id     = dpaa2_xstats_get_by_id,
2433         .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2434         .xstats_get_names      = dpaa2_xstats_get_names,
2435         .stats_reset       = dpaa2_dev_stats_reset,
2436         .xstats_reset         = dpaa2_dev_stats_reset,
2437         .fw_version_get    = dpaa2_fw_version_get,
2438         .dev_infos_get     = dpaa2_dev_info_get,
2439         .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2440         .mtu_set           = dpaa2_dev_mtu_set,
2441         .vlan_filter_set      = dpaa2_vlan_filter_set,
2442         .vlan_offload_set     = dpaa2_vlan_offload_set,
2443         .vlan_tpid_set        = dpaa2_vlan_tpid_set,
2444         .rx_queue_setup    = dpaa2_dev_rx_queue_setup,
2445         .rx_queue_release  = dpaa2_dev_rx_queue_release,
2446         .tx_queue_setup    = dpaa2_dev_tx_queue_setup,
2447         .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2448         .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2449         .flow_ctrl_get        = dpaa2_flow_ctrl_get,
2450         .flow_ctrl_set        = dpaa2_flow_ctrl_set,
2451         .mac_addr_add         = dpaa2_dev_add_mac_addr,
2452         .mac_addr_remove      = dpaa2_dev_remove_mac_addr,
2453         .mac_addr_set         = dpaa2_dev_set_mac_addr,
2454         .rss_hash_update      = dpaa2_dev_rss_hash_update,
2455         .rss_hash_conf_get    = dpaa2_dev_rss_hash_conf_get,
2456         .flow_ops_get         = dpaa2_dev_flow_ops_get,
2457         .rxq_info_get         = dpaa2_rxq_info_get,
2458         .txq_info_get         = dpaa2_txq_info_get,
2459         .tm_ops_get           = dpaa2_tm_ops_get,
2460 #if defined(RTE_LIBRTE_IEEE1588)
2461         .timesync_enable      = dpaa2_timesync_enable,
2462         .timesync_disable     = dpaa2_timesync_disable,
2463         .timesync_read_time   = dpaa2_timesync_read_time,
2464         .timesync_write_time  = dpaa2_timesync_write_time,
2465         .timesync_adjust_time = dpaa2_timesync_adjust_time,
2466         .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2467         .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2468 #endif
2469 };
2470
2471 /* Populate the mac address from physically available (u-boot/firmware) and/or
2472  * one set by higher layers like MC (restool) etc.
2473  * Returns the table of MAC entries (multiple entries)
2474  */
2475 static int
2476 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2477                   struct rte_ether_addr *mac_entry)
2478 {
2479         int ret;
2480         struct rte_ether_addr phy_mac, prime_mac;
2481
2482         memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2483         memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2484
2485         /* Get the physical device MAC address */
2486         ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2487                                      phy_mac.addr_bytes);
2488         if (ret) {
2489                 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2490                 goto cleanup;
2491         }
2492
2493         ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2494                                         prime_mac.addr_bytes);
2495         if (ret) {
2496                 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2497                 goto cleanup;
2498         }
2499
2500         /* Now that both MAC have been obtained, do:
2501          *  if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2502          *     and return phy
2503          *  If empty_mac(phy), return prime.
2504          *  if both are empty, create random MAC, set as prime and return
2505          */
2506         if (!rte_is_zero_ether_addr(&phy_mac)) {
2507                 /* If the addresses are not same, overwrite prime */
2508                 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2509                         ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2510                                                         priv->token,
2511                                                         phy_mac.addr_bytes);
2512                         if (ret) {
2513                                 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2514                                               ret);
2515                                 goto cleanup;
2516                         }
2517                         memcpy(&prime_mac, &phy_mac,
2518                                 sizeof(struct rte_ether_addr));
2519                 }
2520         } else if (rte_is_zero_ether_addr(&prime_mac)) {
2521                 /* In case phys and prime, both are zero, create random MAC */
2522                 rte_eth_random_addr(prime_mac.addr_bytes);
2523                 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2524                                                 priv->token,
2525                                                 prime_mac.addr_bytes);
2526                 if (ret) {
2527                         DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2528                         goto cleanup;
2529                 }
2530         }
2531
2532         /* prime_mac the final MAC address */
2533         memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2534         return 0;
2535
2536 cleanup:
2537         return -1;
2538 }
2539
2540 static int
2541 check_devargs_handler(__rte_unused const char *key, const char *value,
2542                       __rte_unused void *opaque)
2543 {
2544         if (strcmp(value, "1"))
2545                 return -1;
2546
2547         return 0;
2548 }
2549
2550 static int
2551 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2552 {
2553         struct rte_kvargs *kvlist;
2554
2555         if (!devargs)
2556                 return 0;
2557
2558         kvlist = rte_kvargs_parse(devargs->args, NULL);
2559         if (!kvlist)
2560                 return 0;
2561
2562         if (!rte_kvargs_count(kvlist, key)) {
2563                 rte_kvargs_free(kvlist);
2564                 return 0;
2565         }
2566
2567         if (rte_kvargs_process(kvlist, key,
2568                                check_devargs_handler, NULL) < 0) {
2569                 rte_kvargs_free(kvlist);
2570                 return 0;
2571         }
2572         rte_kvargs_free(kvlist);
2573
2574         return 1;
2575 }
2576
2577 static int
2578 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2579 {
2580         struct rte_device *dev = eth_dev->device;
2581         struct rte_dpaa2_device *dpaa2_dev;
2582         struct fsl_mc_io *dpni_dev;
2583         struct dpni_attr attr;
2584         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2585         struct dpni_buffer_layout layout;
2586         int ret, hw_id, i;
2587
2588         PMD_INIT_FUNC_TRACE();
2589
2590         dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2591         if (!dpni_dev) {
2592                 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2593                 return -1;
2594         }
2595         dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2596         eth_dev->process_private = (void *)dpni_dev;
2597
2598         /* For secondary processes, the primary has done all the work */
2599         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2600                 /* In case of secondary, only burst and ops API need to be
2601                  * plugged.
2602                  */
2603                 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2604                 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2605                 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2606                         eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2607                 else if (dpaa2_get_devargs(dev->devargs,
2608                                         DRIVER_NO_PREFETCH_MODE))
2609                         eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2610                 else
2611                         eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2612                 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2613                 return 0;
2614         }
2615
2616         dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2617
2618         hw_id = dpaa2_dev->object_id;
2619         ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2620         if (ret) {
2621                 DPAA2_PMD_ERR(
2622                              "Failure in opening dpni@%d with err code %d",
2623                              hw_id, ret);
2624                 rte_free(dpni_dev);
2625                 return -1;
2626         }
2627
2628         if (eth_dev->data->dev_conf.lpbk_mode)
2629                 dpaa2_dev_recycle_deconfig(eth_dev);
2630
2631         /* Clean the device first */
2632         ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2633         if (ret) {
2634                 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2635                               hw_id, ret);
2636                 goto init_err;
2637         }
2638
2639         ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2640         if (ret) {
2641                 DPAA2_PMD_ERR(
2642                              "Failure in get dpni@%d attribute, err code %d",
2643                              hw_id, ret);
2644                 goto init_err;
2645         }
2646
2647         priv->num_rx_tc = attr.num_rx_tcs;
2648         priv->num_tx_tc = attr.num_tx_tcs;
2649         priv->qos_entries = attr.qos_entries;
2650         priv->fs_entries = attr.fs_entries;
2651         priv->dist_queues = attr.num_queues;
2652         priv->num_channels = attr.num_channels;
2653         priv->channel_inuse = 0;
2654         rte_spinlock_init(&priv->lpbk_qp_lock);
2655
2656         /* only if the custom CG is enabled */
2657         if (attr.options & DPNI_OPT_CUSTOM_CG)
2658                 priv->max_cgs = attr.num_cgs;
2659         else
2660                 priv->max_cgs = 0;
2661
2662         for (i = 0; i < priv->max_cgs; i++)
2663                 priv->cgid_in_use[i] = 0;
2664
2665         for (i = 0; i < attr.num_rx_tcs; i++)
2666                 priv->nb_rx_queues += attr.num_queues;
2667
2668         priv->nb_tx_queues = attr.num_tx_tcs * attr.num_channels;
2669
2670         DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2671                         priv->num_rx_tc, priv->nb_rx_queues,
2672                         priv->nb_tx_queues, priv->max_cgs);
2673
2674         priv->hw = dpni_dev;
2675         priv->hw_id = hw_id;
2676         priv->options = attr.options;
2677         priv->max_mac_filters = attr.mac_filter_entries;
2678         priv->max_vlan_filters = attr.vlan_filter_entries;
2679         priv->flags = 0;
2680 #if defined(RTE_LIBRTE_IEEE1588)
2681         printf("DPDK IEEE1588 is enabled\n");
2682         priv->flags |= DPAA2_TX_CONF_ENABLE;
2683 #endif
2684         /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2685         if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2686                 priv->flags |= DPAA2_TX_CONF_ENABLE;
2687                 DPAA2_PMD_INFO("TX_CONF Enabled");
2688         }
2689
2690         if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2691                 dpaa2_enable_err_queue = 1;
2692                 DPAA2_PMD_INFO("Enable error queue");
2693         }
2694
2695         /* Allocate memory for hardware structure for queues */
2696         ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2697         if (ret) {
2698                 DPAA2_PMD_ERR("Queue allocation Failed");
2699                 goto init_err;
2700         }
2701
2702         /* Allocate memory for storing MAC addresses.
2703          * Table of mac_filter_entries size is allocated so that RTE ether lib
2704          * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2705          */
2706         eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2707                 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2708         if (eth_dev->data->mac_addrs == NULL) {
2709                 DPAA2_PMD_ERR(
2710                    "Failed to allocate %d bytes needed to store MAC addresses",
2711                    RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2712                 ret = -ENOMEM;
2713                 goto init_err;
2714         }
2715
2716         ret = populate_mac_addr(dpni_dev, priv, &eth_dev->data->mac_addrs[0]);
2717         if (ret) {
2718                 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2719                 rte_free(eth_dev->data->mac_addrs);
2720                 eth_dev->data->mac_addrs = NULL;
2721                 goto init_err;
2722         }
2723
2724         /* ... tx buffer layout ... */
2725         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2726         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2727                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2728                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2729                 layout.pass_timestamp = true;
2730         } else {
2731                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2732         }
2733         layout.pass_frame_status = 1;
2734         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2735                                      DPNI_QUEUE_TX, &layout);
2736         if (ret) {
2737                 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2738                 goto init_err;
2739         }
2740
2741         /* ... tx-conf and error buffer layout ... */
2742         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2743         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2744                 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2745                 layout.pass_timestamp = true;
2746         }
2747         layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2748         layout.pass_frame_status = 1;
2749         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2750                                      DPNI_QUEUE_TX_CONFIRM, &layout);
2751         if (ret) {
2752                 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2753                              ret);
2754                 goto init_err;
2755         }
2756
2757         eth_dev->dev_ops = &dpaa2_ethdev_ops;
2758
2759         if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2760                 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2761                 DPAA2_PMD_INFO("Loopback mode");
2762         } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2763                 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2764                 DPAA2_PMD_INFO("No Prefetch mode");
2765         } else {
2766                 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2767         }
2768         eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2769
2770         /* Init fields w.r.t. classification */
2771         memset(&priv->extract.qos_key_extract, 0,
2772                 sizeof(struct dpaa2_key_extract));
2773         priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2774         if (!priv->extract.qos_extract_param) {
2775                 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2776                             " classification ", ret);
2777                 goto init_err;
2778         }
2779         priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2780                 IP_ADDRESS_OFFSET_INVALID;
2781         priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2782                 IP_ADDRESS_OFFSET_INVALID;
2783         priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2784                 IP_ADDRESS_OFFSET_INVALID;
2785         priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2786                 IP_ADDRESS_OFFSET_INVALID;
2787
2788         for (i = 0; i < MAX_TCS; i++) {
2789                 memset(&priv->extract.tc_key_extract[i], 0,
2790                         sizeof(struct dpaa2_key_extract));
2791                 priv->extract.tc_extract_param[i] =
2792                         (size_t)rte_malloc(NULL, 256, 64);
2793                 if (!priv->extract.tc_extract_param[i]) {
2794                         DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classification",
2795                                      ret);
2796                         goto init_err;
2797                 }
2798                 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2799                         IP_ADDRESS_OFFSET_INVALID;
2800                 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2801                         IP_ADDRESS_OFFSET_INVALID;
2802                 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2803                         IP_ADDRESS_OFFSET_INVALID;
2804                 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2805                         IP_ADDRESS_OFFSET_INVALID;
2806         }
2807
2808         ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2809                                         RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2810                                         + VLAN_TAG_SIZE);
2811         if (ret) {
2812                 DPAA2_PMD_ERR("Unable to set mtu. check config");
2813                 goto init_err;
2814         }
2815
2816         /*TODO To enable soft parser support DPAA2 driver needs to integrate
2817          * with external entity to receive byte code for software sequence
2818          * and same will be offload to the H/W using MC interface.
2819          * Currently it is assumed that DPAA2 driver has byte code by some
2820          * mean and same if offloaded to H/W.
2821          */
2822         if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2823                 WRIOP_SS_INITIALIZER(priv);
2824                 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2825                 if (ret < 0) {
2826                         DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2827                                       ret);
2828                         return ret;
2829                 }
2830
2831                 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2832                                                          DPNI_SS_INGRESS);
2833                 if (ret < 0) {
2834                         DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2835                                       ret);
2836                         return ret;
2837                 }
2838         }
2839         RTE_LOG(INFO, PMD, "%s: netdev created, connected to %s\n",
2840                 eth_dev->data->name, dpaa2_dev->ep_name);
2841
2842         return 0;
2843 init_err:
2844         dpaa2_dev_close(eth_dev);
2845
2846         return ret;
2847 }
2848
2849 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev)
2850 {
2851         return dev->device->driver == &rte_dpaa2_pmd.driver;
2852 }
2853
2854 static int
2855 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2856                 struct rte_dpaa2_device *dpaa2_dev)
2857 {
2858         struct rte_eth_dev *eth_dev;
2859         struct dpaa2_dev_priv *dev_priv;
2860         int diag;
2861
2862         if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2863                 RTE_PKTMBUF_HEADROOM) {
2864                 DPAA2_PMD_ERR(
2865                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2866                 RTE_PKTMBUF_HEADROOM,
2867                 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2868
2869                 return -1;
2870         }
2871
2872         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2873                 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2874                 if (!eth_dev)
2875                         return -ENODEV;
2876                 dev_priv = rte_zmalloc("ethdev private structure",
2877                                        sizeof(struct dpaa2_dev_priv),
2878                                        RTE_CACHE_LINE_SIZE);
2879                 if (dev_priv == NULL) {
2880                         DPAA2_PMD_CRIT(
2881                                 "Unable to allocate memory for private data");
2882                         rte_eth_dev_release_port(eth_dev);
2883                         return -ENOMEM;
2884                 }
2885                 eth_dev->data->dev_private = (void *)dev_priv;
2886                 /* Store a pointer to eth_dev in dev_private */
2887                 dev_priv->eth_dev = eth_dev;
2888         } else {
2889                 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2890                 if (!eth_dev) {
2891                         DPAA2_PMD_DEBUG("returning enodev");
2892                         return -ENODEV;
2893                 }
2894         }
2895
2896         eth_dev->device = &dpaa2_dev->device;
2897
2898         dpaa2_dev->eth_dev = eth_dev;
2899         eth_dev->data->rx_mbuf_alloc_failed = 0;
2900
2901         if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2902                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2903
2904         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2905
2906         /* Invoke PMD device initialization function */
2907         diag = dpaa2_dev_init(eth_dev);
2908         if (diag == 0) {
2909                 rte_eth_dev_probing_finish(eth_dev);
2910                 return 0;
2911         }
2912
2913         rte_eth_dev_release_port(eth_dev);
2914         return diag;
2915 }
2916
2917 static int
2918 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2919 {
2920         struct rte_eth_dev *eth_dev;
2921         int ret;
2922
2923         eth_dev = dpaa2_dev->eth_dev;
2924         dpaa2_dev_close(eth_dev);
2925         ret = rte_eth_dev_release_port(eth_dev);
2926
2927         return ret;
2928 }
2929
2930 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2931         .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2932         .drv_type = DPAA2_ETH,
2933         .probe = rte_dpaa2_probe,
2934         .remove = rte_dpaa2_remove,
2935 };
2936
2937 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd);
2938 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME,
2939                 DRIVER_LOOPBACK_MODE "=<int> "
2940                 DRIVER_NO_PREFETCH_MODE "=<int>"
2941                 DRIVER_TX_CONF "=<int>"
2942                 DRIVER_ERROR_QUEUE "=<int>");
2943 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);