1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
4 * Copyright 2016-2021 NXP
12 #include <ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
34 #define DRIVER_TX_CONF "drv_tx_conf"
35 #define DRIVER_ERROR_QUEUE "drv_err_queue"
36 #define CHECK_INTERVAL 100 /* 100ms */
37 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */
39 /* Supported Rx offloads */
40 static uint64_t dev_rx_offloads_sup =
41 DEV_RX_OFFLOAD_CHECKSUM |
42 DEV_RX_OFFLOAD_SCTP_CKSUM |
43 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
44 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
45 DEV_RX_OFFLOAD_VLAN_STRIP |
46 DEV_RX_OFFLOAD_VLAN_FILTER |
47 DEV_RX_OFFLOAD_JUMBO_FRAME |
48 DEV_RX_OFFLOAD_TIMESTAMP;
50 /* Rx offloads which cannot be disabled */
51 static uint64_t dev_rx_offloads_nodis =
52 DEV_RX_OFFLOAD_RSS_HASH |
53 DEV_RX_OFFLOAD_SCATTER;
55 /* Supported Tx offloads */
56 static uint64_t dev_tx_offloads_sup =
57 DEV_TX_OFFLOAD_VLAN_INSERT |
58 DEV_TX_OFFLOAD_IPV4_CKSUM |
59 DEV_TX_OFFLOAD_UDP_CKSUM |
60 DEV_TX_OFFLOAD_TCP_CKSUM |
61 DEV_TX_OFFLOAD_SCTP_CKSUM |
62 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
63 DEV_TX_OFFLOAD_MT_LOCKFREE |
64 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
66 /* Tx offloads which cannot be disabled */
67 static uint64_t dev_tx_offloads_nodis =
68 DEV_TX_OFFLOAD_MULTI_SEGS;
70 /* enable timestamp in mbuf */
71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
72 uint64_t dpaa2_timestamp_rx_dynflag;
73 int dpaa2_timestamp_dynfield_offset = -1;
75 /* Enable error queue */
76 bool dpaa2_enable_err_queue;
78 struct rte_dpaa2_xstats_name_off {
79 char name[RTE_ETH_XSTATS_NAME_SIZE];
80 uint8_t page_id; /* dpni statistics page id */
81 uint8_t stats_id; /* stats id in the given page */
84 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
85 {"ingress_multicast_frames", 0, 2},
86 {"ingress_multicast_bytes", 0, 3},
87 {"ingress_broadcast_frames", 0, 4},
88 {"ingress_broadcast_bytes", 0, 5},
89 {"egress_multicast_frames", 1, 2},
90 {"egress_multicast_bytes", 1, 3},
91 {"egress_broadcast_frames", 1, 4},
92 {"egress_broadcast_bytes", 1, 5},
93 {"ingress_filtered_frames", 2, 0},
94 {"ingress_discarded_frames", 2, 1},
95 {"ingress_nobuffer_discards", 2, 2},
96 {"egress_discarded_frames", 2, 3},
97 {"egress_confirmed_frames", 2, 4},
98 {"cgr_reject_frames", 4, 0},
99 {"cgr_reject_bytes", 4, 1},
102 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
106 static struct rte_dpaa2_driver rte_dpaa2_pmd;
107 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
108 int wait_to_complete);
109 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
110 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
111 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
114 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
117 struct dpaa2_dev_priv *priv = dev->data->dev_private;
118 struct fsl_mc_io *dpni = dev->process_private;
120 PMD_INIT_FUNC_TRACE();
123 DPAA2_PMD_ERR("dpni is NULL");
128 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
131 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
132 priv->token, vlan_id);
135 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
136 ret, vlan_id, priv->hw_id);
142 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
144 struct dpaa2_dev_priv *priv = dev->data->dev_private;
145 struct fsl_mc_io *dpni = dev->process_private;
148 PMD_INIT_FUNC_TRACE();
150 if (mask & ETH_VLAN_FILTER_MASK) {
151 /* VLAN Filter not avaialble */
152 if (!priv->max_vlan_filters) {
153 DPAA2_PMD_INFO("VLAN filter not available");
157 if (dev->data->dev_conf.rxmode.offloads &
158 DEV_RX_OFFLOAD_VLAN_FILTER)
159 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
162 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
165 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
172 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
173 enum rte_vlan_type vlan_type __rte_unused,
176 struct dpaa2_dev_priv *priv = dev->data->dev_private;
177 struct fsl_mc_io *dpni = dev->process_private;
180 PMD_INIT_FUNC_TRACE();
182 /* nothing to be done for standard vlan tpids */
183 if (tpid == 0x8100 || tpid == 0x88A8)
186 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
189 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
190 /* if already configured tpids, remove them first */
192 struct dpni_custom_tpid_cfg tpid_list = {0};
194 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
195 priv->token, &tpid_list);
198 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
199 priv->token, tpid_list.tpid1);
202 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
210 dpaa2_fw_version_get(struct rte_eth_dev *dev,
215 struct fsl_mc_io *dpni = dev->process_private;
216 struct mc_soc_version mc_plat_info = {0};
217 struct mc_version mc_ver_info = {0};
219 PMD_INIT_FUNC_TRACE();
221 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
222 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
224 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
225 DPAA2_PMD_WARN("\tmc_get_version failed");
227 ret = snprintf(fw_version, fw_size,
232 mc_ver_info.revision);
234 ret += 1; /* add the size of '\0' */
235 if (fw_size < (uint32_t)ret)
242 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
244 struct dpaa2_dev_priv *priv = dev->data->dev_private;
246 PMD_INIT_FUNC_TRACE();
248 dev_info->max_mac_addrs = priv->max_mac_filters;
249 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
250 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
251 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
252 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
253 dev_info->rx_offload_capa = dev_rx_offloads_sup |
254 dev_rx_offloads_nodis;
255 dev_info->tx_offload_capa = dev_tx_offloads_sup |
256 dev_tx_offloads_nodis;
257 dev_info->speed_capa = ETH_LINK_SPEED_1G |
258 ETH_LINK_SPEED_2_5G |
261 dev_info->max_hash_mac_addrs = 0;
262 dev_info->max_vfs = 0;
263 dev_info->max_vmdq_pools = ETH_16_POOLS;
264 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
266 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
267 /* same is rx size for best perf */
268 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
270 dev_info->default_rxportconf.nb_queues = 1;
271 dev_info->default_txportconf.nb_queues = 1;
272 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
273 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
275 if (dpaa2_svr_family == SVR_LX2160A) {
276 dev_info->speed_capa |= ETH_LINK_SPEED_25G |
286 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
287 __rte_unused uint16_t queue_id,
288 struct rte_eth_burst_mode *mode)
290 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
293 const struct burst_info {
296 } rx_offload_map[] = {
297 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"},
298 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
299 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
300 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
301 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
302 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
303 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"},
304 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
305 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"},
306 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"}
309 /* Update Rx offload info */
310 for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
311 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
312 snprintf(mode->info, sizeof(mode->info), "%s",
313 rx_offload_map[i].output);
322 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
323 __rte_unused uint16_t queue_id,
324 struct rte_eth_burst_mode *mode)
326 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
329 const struct burst_info {
332 } tx_offload_map[] = {
333 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
334 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
335 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
336 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
337 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
338 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
339 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
340 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
341 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
344 /* Update Tx offload info */
345 for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
346 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
347 snprintf(mode->info, sizeof(mode->info), "%s",
348 tx_offload_map[i].output);
357 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
359 struct dpaa2_dev_priv *priv = dev->data->dev_private;
362 uint8_t num_rxqueue_per_tc;
363 struct dpaa2_queue *mc_q, *mcq;
366 struct dpaa2_queue *dpaa2_q;
368 PMD_INIT_FUNC_TRACE();
370 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
371 if (priv->flags & DPAA2_TX_CONF_ENABLE)
372 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
374 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
375 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
376 RTE_CACHE_LINE_SIZE);
378 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
382 for (i = 0; i < priv->nb_rx_queues; i++) {
383 mc_q->eth_data = dev->data;
384 priv->rx_vq[i] = mc_q++;
385 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
386 dpaa2_q->q_storage = rte_malloc("dq_storage",
387 sizeof(struct queue_storage_info_t),
388 RTE_CACHE_LINE_SIZE);
389 if (!dpaa2_q->q_storage)
392 memset(dpaa2_q->q_storage, 0,
393 sizeof(struct queue_storage_info_t));
394 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
398 if (dpaa2_enable_err_queue) {
399 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
400 sizeof(struct dpaa2_queue), 0);
402 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
403 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
404 sizeof(struct queue_storage_info_t) *
406 RTE_CACHE_LINE_SIZE);
407 if (!dpaa2_q->q_storage)
410 memset(dpaa2_q->q_storage, 0,
411 sizeof(struct queue_storage_info_t));
412 for (i = 0; i < RTE_MAX_LCORE; i++)
413 if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
417 for (i = 0; i < priv->nb_tx_queues; i++) {
418 mc_q->eth_data = dev->data;
419 mc_q->flow_id = 0xffff;
420 priv->tx_vq[i] = mc_q++;
421 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
422 dpaa2_q->cscn = rte_malloc(NULL,
423 sizeof(struct qbman_result), 16);
428 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
429 /*Setup tx confirmation queues*/
430 for (i = 0; i < priv->nb_tx_queues; i++) {
431 mc_q->eth_data = dev->data;
434 priv->tx_conf_vq[i] = mc_q++;
435 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
437 rte_malloc("dq_storage",
438 sizeof(struct queue_storage_info_t),
439 RTE_CACHE_LINE_SIZE);
440 if (!dpaa2_q->q_storage)
443 memset(dpaa2_q->q_storage, 0,
444 sizeof(struct queue_storage_info_t));
445 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
451 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
452 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
453 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
454 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
462 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
463 rte_free(dpaa2_q->q_storage);
464 priv->tx_conf_vq[i--] = NULL;
466 i = priv->nb_tx_queues;
470 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
471 rte_free(dpaa2_q->cscn);
472 priv->tx_vq[i--] = NULL;
474 i = priv->nb_rx_queues;
477 mc_q = priv->rx_vq[0];
479 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
480 dpaa2_free_dq_storage(dpaa2_q->q_storage);
481 rte_free(dpaa2_q->q_storage);
482 priv->rx_vq[i--] = NULL;
485 if (dpaa2_enable_err_queue) {
486 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
487 if (dpaa2_q->q_storage)
488 dpaa2_free_dq_storage(dpaa2_q->q_storage);
489 rte_free(dpaa2_q->q_storage);
497 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
499 struct dpaa2_dev_priv *priv = dev->data->dev_private;
500 struct dpaa2_queue *dpaa2_q;
503 PMD_INIT_FUNC_TRACE();
505 /* Queue allocation base */
506 if (priv->rx_vq[0]) {
507 /* cleaning up queue storage */
508 for (i = 0; i < priv->nb_rx_queues; i++) {
509 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
510 if (dpaa2_q->q_storage)
511 rte_free(dpaa2_q->q_storage);
513 /* cleanup tx queue cscn */
514 for (i = 0; i < priv->nb_tx_queues; i++) {
515 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
516 rte_free(dpaa2_q->cscn);
518 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
519 /* cleanup tx conf queue storage */
520 for (i = 0; i < priv->nb_tx_queues; i++) {
521 dpaa2_q = (struct dpaa2_queue *)
523 rte_free(dpaa2_q->q_storage);
526 /*free memory for all queues (RX+TX) */
527 rte_free(priv->rx_vq[0]);
528 priv->rx_vq[0] = NULL;
533 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
535 struct dpaa2_dev_priv *priv = dev->data->dev_private;
536 struct fsl_mc_io *dpni = dev->process_private;
537 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
538 uint64_t rx_offloads = eth_conf->rxmode.offloads;
539 uint64_t tx_offloads = eth_conf->txmode.offloads;
540 int rx_l3_csum_offload = false;
541 int rx_l4_csum_offload = false;
542 int tx_l3_csum_offload = false;
543 int tx_l4_csum_offload = false;
546 PMD_INIT_FUNC_TRACE();
548 /* Rx offloads which are enabled by default */
549 if (dev_rx_offloads_nodis & ~rx_offloads) {
551 "Some of rx offloads enabled by default - requested 0x%" PRIx64
552 " fixed are 0x%" PRIx64,
553 rx_offloads, dev_rx_offloads_nodis);
556 /* Tx offloads which are enabled by default */
557 if (dev_tx_offloads_nodis & ~tx_offloads) {
559 "Some of tx offloads enabled by default - requested 0x%" PRIx64
560 " fixed are 0x%" PRIx64,
561 tx_offloads, dev_tx_offloads_nodis);
564 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
565 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
566 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
567 priv->token, eth_conf->rxmode.max_rx_pkt_len
568 - RTE_ETHER_CRC_LEN);
571 "Unable to set mtu. check config");
575 dev->data->dev_conf.rxmode.max_rx_pkt_len -
576 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
583 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
584 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
585 ret = dpaa2_setup_flow_dist(dev,
586 eth_conf->rx_adv_conf.rss_conf.rss_hf,
590 "Unable to set flow distribution on tc%d."
591 "Check queue config", tc_index);
597 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
598 rx_l3_csum_offload = true;
600 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
601 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
602 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
603 rx_l4_csum_offload = true;
605 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
606 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
608 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
612 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
613 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
615 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
619 #if !defined(RTE_LIBRTE_IEEE1588)
620 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
623 ret = rte_mbuf_dyn_rx_timestamp_register(
624 &dpaa2_timestamp_dynfield_offset,
625 &dpaa2_timestamp_rx_dynflag);
627 DPAA2_PMD_ERR("Error to register timestamp field/flag");
630 dpaa2_enable_ts[dev->data->port_id] = true;
633 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
634 tx_l3_csum_offload = true;
636 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
637 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
638 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
639 tx_l4_csum_offload = true;
641 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
642 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
644 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
648 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
649 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
651 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
655 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
656 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
657 * to 0 for LS2 in the hardware thus disabling data/annotation
658 * stashing. For LX2 this is fixed in hardware and thus hash result and
659 * parse results can be received in FD using this option.
661 if (dpaa2_svr_family == SVR_LX2160A) {
662 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
663 DPNI_FLCTYPE_HASH, true);
665 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
670 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
671 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
678 /* Function to setup RX flow information. It contains traffic class ID,
679 * flow ID, destination configuration etc.
682 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
683 uint16_t rx_queue_id,
685 unsigned int socket_id __rte_unused,
686 const struct rte_eth_rxconf *rx_conf,
687 struct rte_mempool *mb_pool)
689 struct dpaa2_dev_priv *priv = dev->data->dev_private;
690 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
691 struct dpaa2_queue *dpaa2_q;
692 struct dpni_queue cfg;
698 PMD_INIT_FUNC_TRACE();
700 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
701 dev, rx_queue_id, mb_pool, rx_conf);
703 /* Rx deferred start is not supported */
704 if (rx_conf->rx_deferred_start) {
705 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
710 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
711 bpid = mempool_to_bpid(mb_pool);
712 ret = dpaa2_attach_bp_list(priv,
713 rte_dpaa2_bpid_info[bpid].bp_list);
717 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
718 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
719 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
720 dpaa2_q->nb_desc = UINT16_MAX;
721 dpaa2_q->offloads = rx_conf->offloads;
723 /*Get the flow id from given VQ id*/
724 flow_id = dpaa2_q->flow_id;
725 memset(&cfg, 0, sizeof(struct dpni_queue));
727 options = options | DPNI_QUEUE_OPT_USER_CTX;
728 cfg.user_context = (size_t)(dpaa2_q);
730 /* check if a private cgr available. */
731 for (i = 0; i < priv->max_cgs; i++) {
732 if (!priv->cgid_in_use[i]) {
733 priv->cgid_in_use[i] = 1;
738 if (i < priv->max_cgs) {
739 options |= DPNI_QUEUE_OPT_SET_CGID;
741 dpaa2_q->cgid = cfg.cgid;
743 dpaa2_q->cgid = 0xff;
746 /*if ls2088 or rev2 device, enable the stashing */
748 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
749 options |= DPNI_QUEUE_OPT_FLC;
750 cfg.flc.stash_control = true;
751 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
752 /* 00 00 00 - last 6 bit represent annotation, context stashing,
753 * data stashing setting 01 01 00 (0x14)
754 * (in following order ->DS AS CS)
755 * to enable 1 line data, 1 line annotation.
756 * For LX2, this setting should be 01 00 00 (0x10)
758 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
759 cfg.flc.value |= 0x10;
761 cfg.flc.value |= 0x14;
763 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
764 dpaa2_q->tc_index, flow_id, options, &cfg);
766 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
770 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
771 struct dpni_taildrop taildrop;
774 dpaa2_q->nb_desc = nb_rx_desc;
775 /* Private CGR will use tail drop length as nb_rx_desc.
776 * for rest cases we can use standard byte based tail drop.
777 * There is no HW restriction, but number of CGRs are limited,
778 * hence this restriction is placed.
780 if (dpaa2_q->cgid != 0xff) {
781 /*enabling per rx queue congestion control */
782 taildrop.threshold = nb_rx_desc;
783 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
785 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
787 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
788 DPNI_CP_CONGESTION_GROUP,
791 dpaa2_q->cgid, &taildrop);
793 /*enabling per rx queue congestion control */
794 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
795 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
796 taildrop.oal = CONG_RX_OAL;
797 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
799 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
800 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
801 dpaa2_q->tc_index, flow_id,
805 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
809 } else { /* Disable tail Drop */
810 struct dpni_taildrop taildrop = {0};
811 DPAA2_PMD_INFO("Tail drop is disabled on queue");
814 if (dpaa2_q->cgid != 0xff) {
815 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
816 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
818 dpaa2_q->cgid, &taildrop);
820 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
821 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
822 dpaa2_q->tc_index, flow_id, &taildrop);
825 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
831 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
836 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
837 uint16_t tx_queue_id,
839 unsigned int socket_id __rte_unused,
840 const struct rte_eth_txconf *tx_conf)
842 struct dpaa2_dev_priv *priv = dev->data->dev_private;
843 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
844 priv->tx_vq[tx_queue_id];
845 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
846 priv->tx_conf_vq[tx_queue_id];
847 struct fsl_mc_io *dpni = dev->process_private;
848 struct dpni_queue tx_conf_cfg;
849 struct dpni_queue tx_flow_cfg;
850 uint8_t options = 0, flow_id;
851 struct dpni_queue_id qid;
855 PMD_INIT_FUNC_TRACE();
857 /* Tx deferred start is not supported */
858 if (tx_conf->tx_deferred_start) {
859 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
864 dpaa2_q->nb_desc = UINT16_MAX;
865 dpaa2_q->offloads = tx_conf->offloads;
867 /* Return if queue already configured */
868 if (dpaa2_q->flow_id != 0xffff) {
869 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
873 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
874 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
879 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
880 tc_id, flow_id, options, &tx_flow_cfg);
882 DPAA2_PMD_ERR("Error in setting the tx flow: "
883 "tc_id=%d, flow=%d err=%d",
884 tc_id, flow_id, ret);
888 dpaa2_q->flow_id = flow_id;
890 if (tx_queue_id == 0) {
891 /*Set tx-conf and error configuration*/
892 if (priv->flags & DPAA2_TX_CONF_ENABLE)
893 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
897 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
901 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
906 dpaa2_q->tc_index = tc_id;
908 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
909 DPNI_QUEUE_TX, dpaa2_q->tc_index,
910 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
912 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
915 dpaa2_q->fqid = qid.fqid;
917 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
918 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
920 dpaa2_q->nb_desc = nb_tx_desc;
922 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
923 cong_notif_cfg.threshold_entry = nb_tx_desc;
924 /* Notify that the queue is not congested when the data in
925 * the queue is below this thershold.(90% of value)
927 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
928 cong_notif_cfg.message_ctx = 0;
929 cong_notif_cfg.message_iova =
930 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
931 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
932 cong_notif_cfg.notification_mode =
933 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
934 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
935 DPNI_CONG_OPT_COHERENT_WRITE;
936 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
938 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
945 "Error in setting tx congestion notification: "
950 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
951 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
953 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
954 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
955 options = options | DPNI_QUEUE_OPT_USER_CTX;
956 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
957 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
958 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
959 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
961 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
962 "tc_index=%d, flow=%d err=%d",
963 dpaa2_tx_conf_q->tc_index,
964 dpaa2_tx_conf_q->flow_id, ret);
968 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
969 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
970 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
972 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
975 dpaa2_tx_conf_q->fqid = qid.fqid;
981 dpaa2_dev_rx_queue_release(void *q __rte_unused)
983 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
984 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
985 struct fsl_mc_io *dpni =
986 (struct fsl_mc_io *)priv->eth_dev->process_private;
989 struct dpni_queue cfg;
991 memset(&cfg, 0, sizeof(struct dpni_queue));
992 PMD_INIT_FUNC_TRACE();
993 if (dpaa2_q->cgid != 0xff) {
994 options = DPNI_QUEUE_OPT_CLEAR_CGID;
995 cfg.cgid = dpaa2_q->cgid;
997 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
999 dpaa2_q->tc_index, dpaa2_q->flow_id,
1002 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
1003 dpaa2_q->fqid, ret);
1004 priv->cgid_in_use[dpaa2_q->cgid] = 0;
1005 dpaa2_q->cgid = 0xff;
1010 dpaa2_dev_tx_queue_release(void *q __rte_unused)
1012 PMD_INIT_FUNC_TRACE();
1016 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1019 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1020 struct dpaa2_queue *dpaa2_q;
1021 struct qbman_swp *swp;
1022 struct qbman_fq_query_np_rslt state;
1023 uint32_t frame_cnt = 0;
1025 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1026 ret = dpaa2_affine_qbman_swp();
1029 "Failed to allocate IO portal, tid: %d\n",
1034 swp = DPAA2_PER_LCORE_PORTAL;
1036 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
1038 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1039 frame_cnt = qbman_fq_state_frame_count(&state);
1040 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u",
1041 rx_queue_id, frame_cnt);
1046 static const uint32_t *
1047 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1049 static const uint32_t ptypes[] = {
1050 /*todo -= add more types */
1053 RTE_PTYPE_L3_IPV4_EXT,
1055 RTE_PTYPE_L3_IPV6_EXT,
1063 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1064 dev->rx_pkt_burst == dpaa2_dev_rx ||
1065 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1071 * Dpaa2 link Interrupt handler
1074 * The address of parameter (struct rte_eth_dev *) regsitered before.
1080 dpaa2_interrupt_handler(void *param)
1082 struct rte_eth_dev *dev = param;
1083 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1084 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1086 int irq_index = DPNI_IRQ_INDEX;
1087 unsigned int status = 0, clear = 0;
1089 PMD_INIT_FUNC_TRACE();
1092 DPAA2_PMD_ERR("dpni is NULL");
1096 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1097 irq_index, &status);
1098 if (unlikely(ret)) {
1099 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1104 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1105 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1106 dpaa2_dev_link_update(dev, 0);
1107 /* calling all the apps registered for link status event */
1108 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1111 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1114 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1118 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1121 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1122 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1123 int irq_index = DPNI_IRQ_INDEX;
1124 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1126 PMD_INIT_FUNC_TRACE();
1128 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1131 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1136 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1139 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1146 dpaa2_dev_start(struct rte_eth_dev *dev)
1148 struct rte_device *rdev = dev->device;
1149 struct rte_dpaa2_device *dpaa2_dev;
1150 struct rte_eth_dev_data *data = dev->data;
1151 struct dpaa2_dev_priv *priv = data->dev_private;
1152 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1153 struct dpni_queue cfg;
1154 struct dpni_error_cfg err_cfg;
1156 struct dpni_queue_id qid;
1157 struct dpaa2_queue *dpaa2_q;
1159 struct rte_intr_handle *intr_handle;
1161 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1162 intr_handle = &dpaa2_dev->intr_handle;
1164 PMD_INIT_FUNC_TRACE();
1166 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1168 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1173 /* Power up the phy. Needed to make the link go UP */
1174 dpaa2_dev_set_link_up(dev);
1176 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1177 DPNI_QUEUE_TX, &qdid);
1179 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1184 for (i = 0; i < data->nb_rx_queues; i++) {
1185 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1186 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1187 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1188 dpaa2_q->flow_id, &cfg, &qid);
1190 DPAA2_PMD_ERR("Error in getting flow information: "
1194 dpaa2_q->fqid = qid.fqid;
1197 if (dpaa2_enable_err_queue) {
1198 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1199 DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1201 DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1205 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1206 dpaa2_q->fqid = qid.fqid;
1207 dpaa2_q->eth_data = dev->data;
1209 err_cfg.errors = DPNI_ERROR_DISC;
1210 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1212 /* checksum errors, send them to normal path
1213 * and set it in annotation
1215 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1217 /* if packet with parse error are not to be dropped */
1218 err_cfg.errors |= DPNI_ERROR_PHE;
1220 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1222 err_cfg.set_frame_annotation = true;
1224 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1225 priv->token, &err_cfg);
1227 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1232 /* if the interrupts were configured on this devices*/
1233 if (intr_handle && (intr_handle->fd) &&
1234 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1235 /* Registering LSC interrupt handler */
1236 rte_intr_callback_register(intr_handle,
1237 dpaa2_interrupt_handler,
1240 /* enable vfio intr/eventfd mapping
1241 * Interrupt index 0 is required, so we can not use
1244 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1246 /* enable dpni_irqs */
1247 dpaa2_eth_setup_irqs(dev, 1);
1250 /* Change the tx burst function if ordered queues are used */
1251 if (priv->en_ordered)
1252 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1258 * This routine disables all traffic on the adapter by issuing a
1259 * global reset on the MAC.
1262 dpaa2_dev_stop(struct rte_eth_dev *dev)
1264 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1265 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1267 struct rte_eth_link link;
1268 struct rte_intr_handle *intr_handle = dev->intr_handle;
1270 PMD_INIT_FUNC_TRACE();
1272 /* reset interrupt callback */
1273 if (intr_handle && (intr_handle->fd) &&
1274 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1275 /*disable dpni irqs */
1276 dpaa2_eth_setup_irqs(dev, 0);
1278 /* disable vfio intr before callback unregister */
1279 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1281 /* Unregistering LSC interrupt handler */
1282 rte_intr_callback_unregister(intr_handle,
1283 dpaa2_interrupt_handler,
1287 dpaa2_dev_set_link_down(dev);
1289 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1291 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1296 /* clear the recorded link status */
1297 memset(&link, 0, sizeof(link));
1298 rte_eth_linkstatus_set(dev, &link);
1304 dpaa2_dev_close(struct rte_eth_dev *dev)
1306 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1307 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1309 struct rte_eth_link link;
1311 PMD_INIT_FUNC_TRACE();
1313 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1317 DPAA2_PMD_WARN("Already closed or not started");
1321 dpaa2_tm_deinit(dev);
1322 dpaa2_flow_clean(dev);
1323 /* Clean the device first */
1324 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1326 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1330 memset(&link, 0, sizeof(link));
1331 rte_eth_linkstatus_set(dev, &link);
1333 /* Free private queues memory */
1334 dpaa2_free_rx_tx_queues(dev);
1335 /* Close the device at underlying layer*/
1336 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1338 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1342 /* Free the allocated memory for ethernet private data and dpni*/
1344 dev->process_private = NULL;
1347 for (i = 0; i < MAX_TCS; i++)
1348 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1350 if (priv->extract.qos_extract_param)
1351 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1353 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1358 dpaa2_dev_promiscuous_enable(
1359 struct rte_eth_dev *dev)
1362 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1363 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1365 PMD_INIT_FUNC_TRACE();
1368 DPAA2_PMD_ERR("dpni is NULL");
1372 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1374 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1376 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1378 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1384 dpaa2_dev_promiscuous_disable(
1385 struct rte_eth_dev *dev)
1388 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1389 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1391 PMD_INIT_FUNC_TRACE();
1394 DPAA2_PMD_ERR("dpni is NULL");
1398 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1400 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1402 if (dev->data->all_multicast == 0) {
1403 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1404 priv->token, false);
1406 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1414 dpaa2_dev_allmulticast_enable(
1415 struct rte_eth_dev *dev)
1418 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1419 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1421 PMD_INIT_FUNC_TRACE();
1424 DPAA2_PMD_ERR("dpni is NULL");
1428 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1430 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1436 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1439 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1440 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1442 PMD_INIT_FUNC_TRACE();
1445 DPAA2_PMD_ERR("dpni is NULL");
1449 /* must remain on for all promiscuous */
1450 if (dev->data->promiscuous == 1)
1453 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1455 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1461 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1464 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1465 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1466 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1469 PMD_INIT_FUNC_TRACE();
1472 DPAA2_PMD_ERR("dpni is NULL");
1476 /* check that mtu is within the allowed range */
1477 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1480 if (frame_size > DPAA2_ETH_MAX_LEN)
1481 dev->data->dev_conf.rxmode.offloads |=
1482 DEV_RX_OFFLOAD_JUMBO_FRAME;
1484 dev->data->dev_conf.rxmode.offloads &=
1485 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1487 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1489 /* Set the Max Rx frame length as 'mtu' +
1490 * Maximum Ethernet header length
1492 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1493 frame_size - RTE_ETHER_CRC_LEN);
1495 DPAA2_PMD_ERR("Setting the max frame length failed");
1498 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1503 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1504 struct rte_ether_addr *addr,
1505 __rte_unused uint32_t index,
1506 __rte_unused uint32_t pool)
1509 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1510 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1512 PMD_INIT_FUNC_TRACE();
1515 DPAA2_PMD_ERR("dpni is NULL");
1519 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1520 addr->addr_bytes, 0, 0, 0);
1523 "error: Adding the MAC ADDR failed: err = %d", ret);
1528 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1532 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1533 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1534 struct rte_eth_dev_data *data = dev->data;
1535 struct rte_ether_addr *macaddr;
1537 PMD_INIT_FUNC_TRACE();
1539 macaddr = &data->mac_addrs[index];
1542 DPAA2_PMD_ERR("dpni is NULL");
1546 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1547 priv->token, macaddr->addr_bytes);
1550 "error: Removing the MAC ADDR failed: err = %d", ret);
1554 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1555 struct rte_ether_addr *addr)
1558 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1559 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1561 PMD_INIT_FUNC_TRACE();
1564 DPAA2_PMD_ERR("dpni is NULL");
1568 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1569 priv->token, addr->addr_bytes);
1573 "error: Setting the MAC ADDR failed %d", ret);
1579 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1580 struct rte_eth_stats *stats)
1582 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1583 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1585 uint8_t page0 = 0, page1 = 1, page2 = 2;
1586 union dpni_statistics value;
1588 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1590 memset(&value, 0, sizeof(union dpni_statistics));
1592 PMD_INIT_FUNC_TRACE();
1595 DPAA2_PMD_ERR("dpni is NULL");
1600 DPAA2_PMD_ERR("stats is NULL");
1604 /*Get Counters from page_0*/
1605 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1610 stats->ipackets = value.page_0.ingress_all_frames;
1611 stats->ibytes = value.page_0.ingress_all_bytes;
1613 /*Get Counters from page_1*/
1614 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1619 stats->opackets = value.page_1.egress_all_frames;
1620 stats->obytes = value.page_1.egress_all_bytes;
1622 /*Get Counters from page_2*/
1623 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1628 /* Ingress drop frame count due to configured rules */
1629 stats->ierrors = value.page_2.ingress_filtered_frames;
1630 /* Ingress drop frame count due to error */
1631 stats->ierrors += value.page_2.ingress_discarded_frames;
1633 stats->oerrors = value.page_2.egress_discarded_frames;
1634 stats->imissed = value.page_2.ingress_nobuffer_discards;
1636 /* Fill in per queue stats */
1637 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1638 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1639 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1640 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1642 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1644 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1646 /* Byte counting is not implemented */
1647 stats->q_ibytes[i] = 0;
1648 stats->q_obytes[i] = 0;
1654 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1659 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1662 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1663 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1665 union dpni_statistics value[5] = {};
1666 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1674 /* Get Counters from page_0*/
1675 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1680 /* Get Counters from page_1*/
1681 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1686 /* Get Counters from page_2*/
1687 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1692 for (i = 0; i < priv->max_cgs; i++) {
1693 if (!priv->cgid_in_use[i]) {
1694 /* Get Counters from page_4*/
1695 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1704 for (i = 0; i < num; i++) {
1706 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1707 raw.counter[dpaa2_xstats_strings[i].stats_id];
1711 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1716 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1717 struct rte_eth_xstat_name *xstats_names,
1720 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1722 if (limit < stat_cnt)
1725 if (xstats_names != NULL)
1726 for (i = 0; i < stat_cnt; i++)
1727 strlcpy(xstats_names[i].name,
1728 dpaa2_xstats_strings[i].name,
1729 sizeof(xstats_names[i].name));
1735 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1736 uint64_t *values, unsigned int n)
1738 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1739 uint64_t values_copy[stat_cnt];
1742 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1743 struct fsl_mc_io *dpni =
1744 (struct fsl_mc_io *)dev->process_private;
1746 union dpni_statistics value[5] = {};
1754 /* Get Counters from page_0*/
1755 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1760 /* Get Counters from page_1*/
1761 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1766 /* Get Counters from page_2*/
1767 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1772 /* Get Counters from page_4*/
1773 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1778 for (i = 0; i < stat_cnt; i++) {
1779 values[i] = value[dpaa2_xstats_strings[i].page_id].
1780 raw.counter[dpaa2_xstats_strings[i].stats_id];
1785 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1787 for (i = 0; i < n; i++) {
1788 if (ids[i] >= stat_cnt) {
1789 DPAA2_PMD_ERR("xstats id value isn't valid");
1792 values[i] = values_copy[ids[i]];
1798 dpaa2_xstats_get_names_by_id(
1799 struct rte_eth_dev *dev,
1800 struct rte_eth_xstat_name *xstats_names,
1801 const uint64_t *ids,
1804 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1805 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1808 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1810 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1812 for (i = 0; i < limit; i++) {
1813 if (ids[i] >= stat_cnt) {
1814 DPAA2_PMD_ERR("xstats id value isn't valid");
1817 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1823 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1825 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1826 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1829 struct dpaa2_queue *dpaa2_q;
1831 PMD_INIT_FUNC_TRACE();
1834 DPAA2_PMD_ERR("dpni is NULL");
1838 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1842 /* Reset the per queue stats in dpaa2_queue structure */
1843 for (i = 0; i < priv->nb_rx_queues; i++) {
1844 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1846 dpaa2_q->rx_pkts = 0;
1849 for (i = 0; i < priv->nb_tx_queues; i++) {
1850 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1852 dpaa2_q->tx_pkts = 0;
1858 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1862 /* return 0 means link status changed, -1 means not changed */
1864 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1865 int wait_to_complete)
1868 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1869 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1870 struct rte_eth_link link;
1871 struct dpni_link_state state = {0};
1875 DPAA2_PMD_ERR("dpni is NULL");
1879 for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1880 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1883 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1886 if (state.up == ETH_LINK_DOWN &&
1888 rte_delay_ms(CHECK_INTERVAL);
1893 memset(&link, 0, sizeof(struct rte_eth_link));
1894 link.link_status = state.up;
1895 link.link_speed = state.rate;
1897 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1898 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1900 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1902 ret = rte_eth_linkstatus_set(dev, &link);
1904 DPAA2_PMD_DEBUG("No change in status");
1906 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1907 link.link_status ? "Up" : "Down");
1913 * Toggle the DPNI to enable, if not already enabled.
1914 * This is not strictly PHY up/down - it is more of logical toggling.
1917 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1920 struct dpaa2_dev_priv *priv;
1921 struct fsl_mc_io *dpni;
1923 struct dpni_link_state state = {0};
1925 priv = dev->data->dev_private;
1926 dpni = (struct fsl_mc_io *)dev->process_private;
1929 DPAA2_PMD_ERR("dpni is NULL");
1933 /* Check if DPNI is currently enabled */
1934 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1936 /* Unable to obtain dpni status; Not continuing */
1937 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1941 /* Enable link if not already enabled */
1943 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1945 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1949 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1951 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1955 /* changing tx burst function to start enqueues */
1956 dev->tx_pkt_burst = dpaa2_dev_tx;
1957 dev->data->dev_link.link_status = state.up;
1958 dev->data->dev_link.link_speed = state.rate;
1961 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1963 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1968 * Toggle the DPNI to disable, if not already disabled.
1969 * This is not strictly PHY up/down - it is more of logical toggling.
1972 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1975 struct dpaa2_dev_priv *priv;
1976 struct fsl_mc_io *dpni;
1977 int dpni_enabled = 0;
1980 PMD_INIT_FUNC_TRACE();
1982 priv = dev->data->dev_private;
1983 dpni = (struct fsl_mc_io *)dev->process_private;
1986 DPAA2_PMD_ERR("Device has not yet been configured");
1990 /*changing tx burst function to avoid any more enqueues */
1991 dev->tx_pkt_burst = dummy_dev_tx;
1993 /* Loop while dpni_disable() attempts to drain the egress FQs
1994 * and confirm them back to us.
1997 ret = dpni_disable(dpni, 0, priv->token);
1999 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
2002 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
2004 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
2008 /* Allow the MC some slack */
2009 rte_delay_us(100 * 1000);
2010 } while (dpni_enabled && --retries);
2013 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
2014 /* todo- we may have to manually cleanup queues.
2017 DPAA2_PMD_INFO("Port %d Link DOWN successful",
2018 dev->data->port_id);
2021 dev->data->dev_link.link_status = 0;
2027 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2030 struct dpaa2_dev_priv *priv;
2031 struct fsl_mc_io *dpni;
2032 struct dpni_link_state state = {0};
2034 PMD_INIT_FUNC_TRACE();
2036 priv = dev->data->dev_private;
2037 dpni = (struct fsl_mc_io *)dev->process_private;
2039 if (dpni == NULL || fc_conf == NULL) {
2040 DPAA2_PMD_ERR("device not configured");
2044 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2046 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2050 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2051 if (state.options & DPNI_LINK_OPT_PAUSE) {
2052 /* DPNI_LINK_OPT_PAUSE set
2053 * if ASYM_PAUSE not set,
2054 * RX Side flow control (handle received Pause frame)
2055 * TX side flow control (send Pause frame)
2056 * if ASYM_PAUSE set,
2057 * RX Side flow control (handle received Pause frame)
2058 * No TX side flow control (send Pause frame disabled)
2060 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2061 fc_conf->mode = RTE_FC_FULL;
2063 fc_conf->mode = RTE_FC_RX_PAUSE;
2065 /* DPNI_LINK_OPT_PAUSE not set
2066 * if ASYM_PAUSE set,
2067 * TX side flow control (send Pause frame)
2068 * No RX side flow control (No action on pause frame rx)
2069 * if ASYM_PAUSE not set,
2070 * Flow control disabled
2072 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2073 fc_conf->mode = RTE_FC_TX_PAUSE;
2075 fc_conf->mode = RTE_FC_NONE;
2082 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2085 struct dpaa2_dev_priv *priv;
2086 struct fsl_mc_io *dpni;
2087 struct dpni_link_state state = {0};
2088 struct dpni_link_cfg cfg = {0};
2090 PMD_INIT_FUNC_TRACE();
2092 priv = dev->data->dev_private;
2093 dpni = (struct fsl_mc_io *)dev->process_private;
2096 DPAA2_PMD_ERR("dpni is NULL");
2100 /* It is necessary to obtain the current state before setting fc_conf
2101 * as MC would return error in case rate, autoneg or duplex values are
2104 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2106 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2110 /* Disable link before setting configuration */
2111 dpaa2_dev_set_link_down(dev);
2113 /* Based on fc_conf, update cfg */
2114 cfg.rate = state.rate;
2115 cfg.options = state.options;
2117 /* update cfg with fc_conf */
2118 switch (fc_conf->mode) {
2120 /* Full flow control;
2121 * OPT_PAUSE set, ASYM_PAUSE not set
2123 cfg.options |= DPNI_LINK_OPT_PAUSE;
2124 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2126 case RTE_FC_TX_PAUSE:
2127 /* Enable RX flow control
2128 * OPT_PAUSE not set;
2131 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2132 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2134 case RTE_FC_RX_PAUSE:
2135 /* Enable TX Flow control
2139 cfg.options |= DPNI_LINK_OPT_PAUSE;
2140 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2143 /* Disable Flow control
2145 * ASYM_PAUSE not set
2147 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2148 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2151 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2156 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2158 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2162 dpaa2_dev_set_link_up(dev);
2168 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2169 struct rte_eth_rss_conf *rss_conf)
2171 struct rte_eth_dev_data *data = dev->data;
2172 struct dpaa2_dev_priv *priv = data->dev_private;
2173 struct rte_eth_conf *eth_conf = &data->dev_conf;
2176 PMD_INIT_FUNC_TRACE();
2178 if (rss_conf->rss_hf) {
2179 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2180 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2183 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2189 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2190 ret = dpaa2_remove_flow_dist(dev, tc_index);
2193 "Unable to remove flow dist on tc%d",
2199 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2204 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2205 struct rte_eth_rss_conf *rss_conf)
2207 struct rte_eth_dev_data *data = dev->data;
2208 struct rte_eth_conf *eth_conf = &data->dev_conf;
2210 /* dpaa2 does not support rss_key, so length should be 0*/
2211 rss_conf->rss_key_len = 0;
2212 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2216 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2217 int eth_rx_queue_id,
2218 struct dpaa2_dpcon_dev *dpcon,
2219 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2221 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2222 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2223 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2224 uint8_t flow_id = dpaa2_ethq->flow_id;
2225 struct dpni_queue cfg;
2226 uint8_t options, priority;
2229 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2230 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2231 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2232 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2233 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2234 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2238 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2239 (dpcon->num_priorities - 1);
2241 memset(&cfg, 0, sizeof(struct dpni_queue));
2242 options = DPNI_QUEUE_OPT_DEST;
2243 cfg.destination.type = DPNI_DEST_DPCON;
2244 cfg.destination.id = dpcon->dpcon_id;
2245 cfg.destination.priority = priority;
2247 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2248 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2249 cfg.destination.hold_active = 1;
2252 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2253 !eth_priv->en_ordered) {
2254 struct opr_cfg ocfg;
2256 /* Restoration window size = 256 frames */
2258 /* Restoration window size = 512 frames for LX2 */
2259 if (dpaa2_svr_family == SVR_LX2160A)
2261 /* Auto advance NESN window enabled */
2263 /* Late arrival window size disabled */
2265 /* ORL resource exhaustaion advance NESN disabled */
2267 /* Loose ordering enabled */
2269 eth_priv->en_loose_ordered = 1;
2270 /* Strict ordering enabled if explicitly set */
2271 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2273 eth_priv->en_loose_ordered = 0;
2276 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2277 dpaa2_ethq->tc_index, flow_id,
2278 OPR_OPT_CREATE, &ocfg);
2280 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2284 eth_priv->en_ordered = 1;
2287 options |= DPNI_QUEUE_OPT_USER_CTX;
2288 cfg.user_context = (size_t)(dpaa2_ethq);
2290 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2291 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2293 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2297 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2302 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2303 int eth_rx_queue_id)
2305 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2306 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2307 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2308 uint8_t flow_id = dpaa2_ethq->flow_id;
2309 struct dpni_queue cfg;
2313 memset(&cfg, 0, sizeof(struct dpni_queue));
2314 options = DPNI_QUEUE_OPT_DEST;
2315 cfg.destination.type = DPNI_DEST_NONE;
2317 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2318 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2320 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2326 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2330 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2331 if (dpaa2_supported_filter_ops[i] == filter_op)
2338 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2339 enum rte_filter_type filter_type,
2340 enum rte_filter_op filter_op,
2348 switch (filter_type) {
2349 case RTE_ETH_FILTER_GENERIC:
2350 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2354 *(const void **)arg = &dpaa2_flow_ops;
2355 dpaa2_filter_type |= filter_type;
2358 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2367 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2368 struct rte_eth_rxq_info *qinfo)
2370 struct dpaa2_queue *rxq;
2371 struct dpaa2_dev_priv *priv = dev->data->dev_private;
2372 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2373 uint16_t max_frame_length;
2375 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2377 qinfo->mp = rxq->mb_pool;
2378 qinfo->scattered_rx = dev->data->scattered_rx;
2379 qinfo->nb_desc = rxq->nb_desc;
2380 if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2381 &max_frame_length) == 0)
2382 qinfo->rx_buf_size = max_frame_length;
2384 qinfo->conf.rx_free_thresh = 1;
2385 qinfo->conf.rx_drop_en = 1;
2386 qinfo->conf.rx_deferred_start = 0;
2387 qinfo->conf.offloads = rxq->offloads;
2391 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2392 struct rte_eth_txq_info *qinfo)
2394 struct dpaa2_queue *txq;
2396 txq = dev->data->tx_queues[queue_id];
2398 qinfo->nb_desc = txq->nb_desc;
2399 qinfo->conf.tx_thresh.pthresh = 0;
2400 qinfo->conf.tx_thresh.hthresh = 0;
2401 qinfo->conf.tx_thresh.wthresh = 0;
2403 qinfo->conf.tx_free_thresh = 0;
2404 qinfo->conf.tx_rs_thresh = 0;
2405 qinfo->conf.offloads = txq->offloads;
2406 qinfo->conf.tx_deferred_start = 0;
2410 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2412 *(const void **)ops = &dpaa2_tm_ops;
2417 static struct eth_dev_ops dpaa2_ethdev_ops = {
2418 .dev_configure = dpaa2_eth_dev_configure,
2419 .dev_start = dpaa2_dev_start,
2420 .dev_stop = dpaa2_dev_stop,
2421 .dev_close = dpaa2_dev_close,
2422 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2423 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2424 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2425 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2426 .dev_set_link_up = dpaa2_dev_set_link_up,
2427 .dev_set_link_down = dpaa2_dev_set_link_down,
2428 .link_update = dpaa2_dev_link_update,
2429 .stats_get = dpaa2_dev_stats_get,
2430 .xstats_get = dpaa2_dev_xstats_get,
2431 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2432 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2433 .xstats_get_names = dpaa2_xstats_get_names,
2434 .stats_reset = dpaa2_dev_stats_reset,
2435 .xstats_reset = dpaa2_dev_stats_reset,
2436 .fw_version_get = dpaa2_fw_version_get,
2437 .dev_infos_get = dpaa2_dev_info_get,
2438 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2439 .mtu_set = dpaa2_dev_mtu_set,
2440 .vlan_filter_set = dpaa2_vlan_filter_set,
2441 .vlan_offload_set = dpaa2_vlan_offload_set,
2442 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2443 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2444 .rx_queue_release = dpaa2_dev_rx_queue_release,
2445 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2446 .tx_queue_release = dpaa2_dev_tx_queue_release,
2447 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2448 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2449 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2450 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2451 .mac_addr_add = dpaa2_dev_add_mac_addr,
2452 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2453 .mac_addr_set = dpaa2_dev_set_mac_addr,
2454 .rss_hash_update = dpaa2_dev_rss_hash_update,
2455 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2456 .filter_ctrl = dpaa2_dev_flow_ctrl,
2457 .rxq_info_get = dpaa2_rxq_info_get,
2458 .txq_info_get = dpaa2_txq_info_get,
2459 .tm_ops_get = dpaa2_tm_ops_get,
2460 #if defined(RTE_LIBRTE_IEEE1588)
2461 .timesync_enable = dpaa2_timesync_enable,
2462 .timesync_disable = dpaa2_timesync_disable,
2463 .timesync_read_time = dpaa2_timesync_read_time,
2464 .timesync_write_time = dpaa2_timesync_write_time,
2465 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2466 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2467 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2471 /* Populate the mac address from physically available (u-boot/firmware) and/or
2472 * one set by higher layers like MC (restool) etc.
2473 * Returns the table of MAC entries (multiple entries)
2476 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2477 struct rte_ether_addr *mac_entry)
2480 struct rte_ether_addr phy_mac, prime_mac;
2482 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2483 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2485 /* Get the physical device MAC address */
2486 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2487 phy_mac.addr_bytes);
2489 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2493 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2494 prime_mac.addr_bytes);
2496 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2500 /* Now that both MAC have been obtained, do:
2501 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2503 * If empty_mac(phy), return prime.
2504 * if both are empty, create random MAC, set as prime and return
2506 if (!rte_is_zero_ether_addr(&phy_mac)) {
2507 /* If the addresses are not same, overwrite prime */
2508 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2509 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2511 phy_mac.addr_bytes);
2513 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2517 memcpy(&prime_mac, &phy_mac,
2518 sizeof(struct rte_ether_addr));
2520 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2521 /* In case phys and prime, both are zero, create random MAC */
2522 rte_eth_random_addr(prime_mac.addr_bytes);
2523 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2525 prime_mac.addr_bytes);
2527 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2532 /* prime_mac the final MAC address */
2533 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2541 check_devargs_handler(__rte_unused const char *key, const char *value,
2542 __rte_unused void *opaque)
2544 if (strcmp(value, "1"))
2551 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2553 struct rte_kvargs *kvlist;
2558 kvlist = rte_kvargs_parse(devargs->args, NULL);
2562 if (!rte_kvargs_count(kvlist, key)) {
2563 rte_kvargs_free(kvlist);
2567 if (rte_kvargs_process(kvlist, key,
2568 check_devargs_handler, NULL) < 0) {
2569 rte_kvargs_free(kvlist);
2572 rte_kvargs_free(kvlist);
2578 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2580 struct rte_device *dev = eth_dev->device;
2581 struct rte_dpaa2_device *dpaa2_dev;
2582 struct fsl_mc_io *dpni_dev;
2583 struct dpni_attr attr;
2584 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2585 struct dpni_buffer_layout layout;
2588 PMD_INIT_FUNC_TRACE();
2590 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2592 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2595 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2596 eth_dev->process_private = (void *)dpni_dev;
2598 /* For secondary processes, the primary has done all the work */
2599 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2600 /* In case of secondary, only burst and ops API need to be
2603 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2604 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2605 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2606 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2607 else if (dpaa2_get_devargs(dev->devargs,
2608 DRIVER_NO_PREFETCH_MODE))
2609 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2611 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2612 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2616 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2618 hw_id = dpaa2_dev->object_id;
2619 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2622 "Failure in opening dpni@%d with err code %d",
2628 /* Clean the device first */
2629 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2631 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2636 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2639 "Failure in get dpni@%d attribute, err code %d",
2644 priv->num_rx_tc = attr.num_rx_tcs;
2645 priv->qos_entries = attr.qos_entries;
2646 priv->fs_entries = attr.fs_entries;
2647 priv->dist_queues = attr.num_queues;
2649 /* only if the custom CG is enabled */
2650 if (attr.options & DPNI_OPT_CUSTOM_CG)
2651 priv->max_cgs = attr.num_cgs;
2655 for (i = 0; i < priv->max_cgs; i++)
2656 priv->cgid_in_use[i] = 0;
2658 for (i = 0; i < attr.num_rx_tcs; i++)
2659 priv->nb_rx_queues += attr.num_queues;
2661 /* Using number of TX queues as number of TX TCs */
2662 priv->nb_tx_queues = attr.num_tx_tcs;
2664 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2665 priv->num_rx_tc, priv->nb_rx_queues,
2666 priv->nb_tx_queues, priv->max_cgs);
2668 priv->hw = dpni_dev;
2669 priv->hw_id = hw_id;
2670 priv->options = attr.options;
2671 priv->max_mac_filters = attr.mac_filter_entries;
2672 priv->max_vlan_filters = attr.vlan_filter_entries;
2674 #if defined(RTE_LIBRTE_IEEE1588)
2675 printf("DPDK IEEE1588 is enabled\n");
2676 priv->flags |= DPAA2_TX_CONF_ENABLE;
2678 /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2679 if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2680 priv->flags |= DPAA2_TX_CONF_ENABLE;
2681 DPAA2_PMD_INFO("TX_CONF Enabled");
2684 if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2685 dpaa2_enable_err_queue = 1;
2686 DPAA2_PMD_INFO("Enable error queue");
2689 /* Allocate memory for hardware structure for queues */
2690 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2692 DPAA2_PMD_ERR("Queue allocation Failed");
2696 /* Allocate memory for storing MAC addresses.
2697 * Table of mac_filter_entries size is allocated so that RTE ether lib
2698 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2700 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2701 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2702 if (eth_dev->data->mac_addrs == NULL) {
2704 "Failed to allocate %d bytes needed to store MAC addresses",
2705 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2710 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2712 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2713 rte_free(eth_dev->data->mac_addrs);
2714 eth_dev->data->mac_addrs = NULL;
2718 /* ... tx buffer layout ... */
2719 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2720 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2721 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2722 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2723 layout.pass_timestamp = true;
2725 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2727 layout.pass_frame_status = 1;
2728 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2729 DPNI_QUEUE_TX, &layout);
2731 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2735 /* ... tx-conf and error buffer layout ... */
2736 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2737 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2738 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2739 layout.pass_timestamp = true;
2741 layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2742 layout.pass_frame_status = 1;
2743 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2744 DPNI_QUEUE_TX_CONFIRM, &layout);
2746 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2751 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2753 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2754 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2755 DPAA2_PMD_INFO("Loopback mode");
2756 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2757 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2758 DPAA2_PMD_INFO("No Prefetch mode");
2760 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2762 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2764 /*Init fields w.r.t. classficaition*/
2765 memset(&priv->extract.qos_key_extract, 0,
2766 sizeof(struct dpaa2_key_extract));
2767 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2768 if (!priv->extract.qos_extract_param) {
2769 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2770 " classificaiton ", ret);
2773 priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2774 IP_ADDRESS_OFFSET_INVALID;
2775 priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2776 IP_ADDRESS_OFFSET_INVALID;
2777 priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2778 IP_ADDRESS_OFFSET_INVALID;
2779 priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2780 IP_ADDRESS_OFFSET_INVALID;
2782 for (i = 0; i < MAX_TCS; i++) {
2783 memset(&priv->extract.tc_key_extract[i], 0,
2784 sizeof(struct dpaa2_key_extract));
2785 priv->extract.tc_extract_param[i] =
2786 (size_t)rte_malloc(NULL, 256, 64);
2787 if (!priv->extract.tc_extract_param[i]) {
2788 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2792 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2793 IP_ADDRESS_OFFSET_INVALID;
2794 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2795 IP_ADDRESS_OFFSET_INVALID;
2796 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2797 IP_ADDRESS_OFFSET_INVALID;
2798 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2799 IP_ADDRESS_OFFSET_INVALID;
2802 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2803 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2806 DPAA2_PMD_ERR("Unable to set mtu. check config");
2810 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2811 * with external entity to receive byte code for software sequence
2812 * and same will be offload to the H/W using MC interface.
2813 * Currently it is assumed that DPAA2 driver has byte code by some
2814 * mean and same if offloaded to H/W.
2816 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2817 WRIOP_SS_INITIALIZER(priv);
2818 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2820 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2825 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2828 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2833 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2836 dpaa2_dev_close(eth_dev);
2842 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2843 struct rte_dpaa2_device *dpaa2_dev)
2845 struct rte_eth_dev *eth_dev;
2846 struct dpaa2_dev_priv *dev_priv;
2849 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2850 RTE_PKTMBUF_HEADROOM) {
2852 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2853 RTE_PKTMBUF_HEADROOM,
2854 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2859 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2860 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2863 dev_priv = rte_zmalloc("ethdev private structure",
2864 sizeof(struct dpaa2_dev_priv),
2865 RTE_CACHE_LINE_SIZE);
2866 if (dev_priv == NULL) {
2868 "Unable to allocate memory for private data");
2869 rte_eth_dev_release_port(eth_dev);
2872 eth_dev->data->dev_private = (void *)dev_priv;
2873 /* Store a pointer to eth_dev in dev_private */
2874 dev_priv->eth_dev = eth_dev;
2876 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2878 DPAA2_PMD_DEBUG("returning enodev");
2883 eth_dev->device = &dpaa2_dev->device;
2885 dpaa2_dev->eth_dev = eth_dev;
2886 eth_dev->data->rx_mbuf_alloc_failed = 0;
2888 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2889 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2891 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2893 /* Invoke PMD device initialization function */
2894 diag = dpaa2_dev_init(eth_dev);
2896 rte_eth_dev_probing_finish(eth_dev);
2900 rte_eth_dev_release_port(eth_dev);
2905 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2907 struct rte_eth_dev *eth_dev;
2910 eth_dev = dpaa2_dev->eth_dev;
2911 dpaa2_dev_close(eth_dev);
2912 ret = rte_eth_dev_release_port(eth_dev);
2917 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2918 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2919 .drv_type = DPAA2_ETH,
2920 .probe = rte_dpaa2_probe,
2921 .remove = rte_dpaa2_remove,
2924 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2925 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2926 DRIVER_LOOPBACK_MODE "=<int> "
2927 DRIVER_NO_PREFETCH_MODE "=<int>"
2928 DRIVER_TX_CONF "=<int>"
2929 DRIVER_ERROR_QUEUE "=<int>");
2930 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE);