drivers/net/dpaa2/dpaa2_ethdev.c

   1 /* * SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  *   Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
   4  *   Copyright 2016-2021 NXP
   5  *
   6  */
   7
   8 #include <time.h>
   9 #include <net/if.h>
  10
  11 #include <rte_mbuf.h>
  12 #include <ethdev_driver.h>
  13 #include <rte_malloc.h>
  14 #include <rte_memcpy.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_cycles.h>
  17 #include <rte_kvargs.h>
  18 #include <rte_dev.h>
  19 #include <rte_fslmc.h>
  20 #include <rte_flow_driver.h>
  21
  22 #include "dpaa2_pmd_logs.h"
  23 #include <fslmc_vfio.h>
  24 #include <dpaa2_hw_pvt.h>
  25 #include <dpaa2_hw_mempool.h>
  26 #include <dpaa2_hw_dpio.h>
  27 #include <mc/fsl_dpmng.h>
  28 #include "dpaa2_ethdev.h"
  29 #include "dpaa2_sparser.h"
  30 #include <fsl_qbman_debug.h>
  31
  32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
  33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
  34 #define DRIVER_TX_CONF "drv_tx_conf"
  35 #define DRIVER_ERROR_QUEUE  "drv_err_queue"
  36 #define CHECK_INTERVAL         100  /* 100ms */
  37 #define MAX_REPEAT_TIME        90   /* 9s (90 * 100ms) in total */
  38
  39 /* Supported Rx offloads */
  40 static uint64_t dev_rx_offloads_sup =
  41                 RTE_ETH_RX_OFFLOAD_CHECKSUM |
  42                 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM |
  43                 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
  44                 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM |
  45                 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
  46                 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
  47                 RTE_ETH_RX_OFFLOAD_TIMESTAMP;
  48
  49 /* Rx offloads which cannot be disabled */
  50 static uint64_t dev_rx_offloads_nodis =
  51                 RTE_ETH_RX_OFFLOAD_RSS_HASH |
  52                 RTE_ETH_RX_OFFLOAD_SCATTER;
  53
  54 /* Supported Tx offloads */
  55 static uint64_t dev_tx_offloads_sup =
  56                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
  57                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
  58                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
  59                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
  60                 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
  61                 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
  62                 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE |
  63                 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
  64
  65 /* Tx offloads which cannot be disabled */
  66 static uint64_t dev_tx_offloads_nodis =
  67                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS;
  68
  69 /* enable timestamp in mbuf */
  70 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS];
  71 uint64_t dpaa2_timestamp_rx_dynflag;
  72 int dpaa2_timestamp_dynfield_offset = -1;
  73
  74 /* Enable error queue */
  75 bool dpaa2_enable_err_queue;
  76
  77 struct rte_dpaa2_xstats_name_off {
  78         char name[RTE_ETH_XSTATS_NAME_SIZE];
  79         uint8_t page_id; /* dpni statistics page id */
  80         uint8_t stats_id; /* stats id in the given page */
  81 };
  82
  83 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
  84         {"ingress_multicast_frames", 0, 2},
  85         {"ingress_multicast_bytes", 0, 3},
  86         {"ingress_broadcast_frames", 0, 4},
  87         {"ingress_broadcast_bytes", 0, 5},
  88         {"egress_multicast_frames", 1, 2},
  89         {"egress_multicast_bytes", 1, 3},
  90         {"egress_broadcast_frames", 1, 4},
  91         {"egress_broadcast_bytes", 1, 5},
  92         {"ingress_filtered_frames", 2, 0},
  93         {"ingress_discarded_frames", 2, 1},
  94         {"ingress_nobuffer_discards", 2, 2},
  95         {"egress_discarded_frames", 2, 3},
  96         {"egress_confirmed_frames", 2, 4},
  97         {"cgr_reject_frames", 4, 0},
  98         {"cgr_reject_bytes", 4, 1},
  99 };
 100
 101 static struct rte_dpaa2_driver rte_dpaa2_pmd;
 102 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
 103                                  int wait_to_complete);
 104 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
 105 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
 106 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 107
 108 static int
 109 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 110 {
 111         int ret;
 112         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 113         struct fsl_mc_io *dpni = dev->process_private;
 114
 115         PMD_INIT_FUNC_TRACE();
 116
 117         if (dpni == NULL) {
 118                 DPAA2_PMD_ERR("dpni is NULL");
 119                 return -1;
 120         }
 121
 122         if (on)
 123                 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
 124                                        vlan_id, 0, 0, 0);
 125         else
 126                 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
 127                                           priv->token, vlan_id);
 128
 129         if (ret < 0)
 130                 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
 131                               ret, vlan_id, priv->hw_id);
 132
 133         return ret;
 134 }
 135
 136 static int
 137 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
 138 {
 139         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 140         struct fsl_mc_io *dpni = dev->process_private;
 141         int ret = 0;
 142
 143         PMD_INIT_FUNC_TRACE();
 144
 145         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
 146                 /* VLAN Filter not available */
 147                 if (!priv->max_vlan_filters) {
 148                         DPAA2_PMD_INFO("VLAN filter not available");
 149                         return -ENOTSUP;
 150                 }
 151
 152                 if (dev->data->dev_conf.rxmode.offloads &
 153                         RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
 154                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 155                                                       priv->token, true);
 156                 else
 157                         ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
 158                                                       priv->token, false);
 159                 if (ret < 0)
 160                         DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
 161         }
 162
 163         return ret;
 164 }
 165
 166 static int
 167 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
 168                       enum rte_vlan_type vlan_type __rte_unused,
 169                       uint16_t tpid)
 170 {
 171         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 172         struct fsl_mc_io *dpni = dev->process_private;
 173         int ret = -ENOTSUP;
 174
 175         PMD_INIT_FUNC_TRACE();
 176
 177         /* nothing to be done for standard vlan tpids */
 178         if (tpid == 0x8100 || tpid == 0x88A8)
 179                 return 0;
 180
 181         ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 182                                    priv->token, tpid);
 183         if (ret < 0)
 184                 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
 185         /* if already configured tpids, remove them first */
 186         if (ret == -EBUSY) {
 187                 struct dpni_custom_tpid_cfg tpid_list = {0};
 188
 189                 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
 190                                    priv->token, &tpid_list);
 191                 if (ret < 0)
 192                         goto fail;
 193                 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
 194                                    priv->token, tpid_list.tpid1);
 195                 if (ret < 0)
 196                         goto fail;
 197                 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
 198                                            priv->token, tpid);
 199         }
 200 fail:
 201         return ret;
 202 }
 203
 204 static int
 205 dpaa2_fw_version_get(struct rte_eth_dev *dev,
 206                      char *fw_version,
 207                      size_t fw_size)
 208 {
 209         int ret;
 210         struct fsl_mc_io *dpni = dev->process_private;
 211         struct mc_soc_version mc_plat_info = {0};
 212         struct mc_version mc_ver_info = {0};
 213
 214         PMD_INIT_FUNC_TRACE();
 215
 216         if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
 217                 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
 218
 219         if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
 220                 DPAA2_PMD_WARN("\tmc_get_version failed");
 221
 222         ret = snprintf(fw_version, fw_size,
 223                        "%x-%d.%d.%d",
 224                        mc_plat_info.svr,
 225                        mc_ver_info.major,
 226                        mc_ver_info.minor,
 227                        mc_ver_info.revision);
 228         if (ret < 0)
 229                 return -EINVAL;
 230
 231         ret += 1; /* add the size of '\0' */
 232         if (fw_size < (size_t)ret)
 233                 return ret;
 234         else
 235                 return 0;
 236 }
 237
 238 static int
 239 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 240 {
 241         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 242
 243         PMD_INIT_FUNC_TRACE();
 244
 245         dev_info->max_mac_addrs = priv->max_mac_filters;
 246         dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
 247         dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
 248         dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
 249         dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
 250         dev_info->rx_offload_capa = dev_rx_offloads_sup |
 251                                         dev_rx_offloads_nodis;
 252         dev_info->tx_offload_capa = dev_tx_offloads_sup |
 253                                         dev_tx_offloads_nodis;
 254         dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G |
 255                         RTE_ETH_LINK_SPEED_2_5G |
 256                         RTE_ETH_LINK_SPEED_10G;
 257         dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
 258
 259         dev_info->max_hash_mac_addrs = 0;
 260         dev_info->max_vfs = 0;
 261         dev_info->max_vmdq_pools = RTE_ETH_16_POOLS;
 262         dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
 263
 264         dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size;
 265         /* same is rx size for best perf */
 266         dev_info->default_txportconf.burst_size = dpaa2_dqrr_size;
 267
 268         dev_info->default_rxportconf.nb_queues = 1;
 269         dev_info->default_txportconf.nb_queues = 1;
 270         dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD;
 271         dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC;
 272
 273         if (dpaa2_svr_family == SVR_LX2160A) {
 274                 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G |
 275                                 RTE_ETH_LINK_SPEED_40G |
 276                                 RTE_ETH_LINK_SPEED_50G |
 277                                 RTE_ETH_LINK_SPEED_100G;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static int
 284 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev,
 285                         __rte_unused uint16_t queue_id,
 286                         struct rte_eth_burst_mode *mode)
 287 {
 288         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 289         int ret = -EINVAL;
 290         unsigned int i;
 291         const struct burst_info {
 292                 uint64_t flags;
 293                 const char *output;
 294         } rx_offload_map[] = {
 295                         {RTE_ETH_RX_OFFLOAD_CHECKSUM, " Checksum,"},
 296                         {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 297                         {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 298                         {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"},
 299                         {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"},
 300                         {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"},
 301                         {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"},
 302                         {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"},
 303                         {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}
 304         };
 305
 306         /* Update Rx offload info */
 307         for (i = 0; i < RTE_DIM(rx_offload_map); i++) {
 308                 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) {
 309                         snprintf(mode->info, sizeof(mode->info), "%s",
 310                                 rx_offload_map[i].output);
 311                         ret = 0;
 312                         break;
 313                 }
 314         }
 315         return ret;
 316 }
 317
 318 static int
 319 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev,
 320                         __rte_unused uint16_t queue_id,
 321                         struct rte_eth_burst_mode *mode)
 322 {
 323         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 324         int ret = -EINVAL;
 325         unsigned int i;
 326         const struct burst_info {
 327                 uint64_t flags;
 328                 const char *output;
 329         } tx_offload_map[] = {
 330                         {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"},
 331                         {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"},
 332                         {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"},
 333                         {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"},
 334                         {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"},
 335                         {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"},
 336                         {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"},
 337                         {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"},
 338                         {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"}
 339         };
 340
 341         /* Update Tx offload info */
 342         for (i = 0; i < RTE_DIM(tx_offload_map); i++) {
 343                 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) {
 344                         snprintf(mode->info, sizeof(mode->info), "%s",
 345                                 tx_offload_map[i].output);
 346                         ret = 0;
 347                         break;
 348                 }
 349         }
 350         return ret;
 351 }
 352
 353 static int
 354 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
 355 {
 356         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 357         uint16_t dist_idx;
 358         uint32_t vq_id;
 359         uint8_t num_rxqueue_per_tc;
 360         struct dpaa2_queue *mc_q, *mcq;
 361         uint32_t tot_queues;
 362         int i;
 363         struct dpaa2_queue *dpaa2_q;
 364
 365         PMD_INIT_FUNC_TRACE();
 366
 367         num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
 368         if (priv->flags & DPAA2_TX_CONF_ENABLE)
 369                 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
 370         else
 371                 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
 372         mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
 373                           RTE_CACHE_LINE_SIZE);
 374         if (!mc_q) {
 375                 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
 376                 return -1;
 377         }
 378
 379         for (i = 0; i < priv->nb_rx_queues; i++) {
 380                 mc_q->eth_data = dev->data;
 381                 priv->rx_vq[i] = mc_q++;
 382                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 383                 dpaa2_q->q_storage = rte_malloc("dq_storage",
 384                                         sizeof(struct queue_storage_info_t),
 385                                         RTE_CACHE_LINE_SIZE);
 386                 if (!dpaa2_q->q_storage)
 387                         goto fail;
 388
 389                 memset(dpaa2_q->q_storage, 0,
 390                        sizeof(struct queue_storage_info_t));
 391                 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 392                         goto fail;
 393         }
 394
 395         if (dpaa2_enable_err_queue) {
 396                 priv->rx_err_vq = rte_zmalloc("dpni_rx_err",
 397                         sizeof(struct dpaa2_queue), 0);
 398
 399                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 400                 dpaa2_q->q_storage = rte_malloc("err_dq_storage",
 401                                         sizeof(struct queue_storage_info_t) *
 402                                         RTE_MAX_LCORE,
 403                                         RTE_CACHE_LINE_SIZE);
 404                 if (!dpaa2_q->q_storage)
 405                         goto fail;
 406
 407                 memset(dpaa2_q->q_storage, 0,
 408                        sizeof(struct queue_storage_info_t));
 409                 for (i = 0; i < RTE_MAX_LCORE; i++)
 410                         if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i]))
 411                                 goto fail;
 412         }
 413
 414         for (i = 0; i < priv->nb_tx_queues; i++) {
 415                 mc_q->eth_data = dev->data;
 416                 mc_q->flow_id = 0xffff;
 417                 priv->tx_vq[i] = mc_q++;
 418                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 419                 dpaa2_q->cscn = rte_malloc(NULL,
 420                                            sizeof(struct qbman_result), 16);
 421                 if (!dpaa2_q->cscn)
 422                         goto fail_tx;
 423         }
 424
 425         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 426                 /*Setup tx confirmation queues*/
 427                 for (i = 0; i < priv->nb_tx_queues; i++) {
 428                         mc_q->eth_data = dev->data;
 429                         mc_q->tc_index = i;
 430                         mc_q->flow_id = 0;
 431                         priv->tx_conf_vq[i] = mc_q++;
 432                         dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 433                         dpaa2_q->q_storage =
 434                                 rte_malloc("dq_storage",
 435                                         sizeof(struct queue_storage_info_t),
 436                                         RTE_CACHE_LINE_SIZE);
 437                         if (!dpaa2_q->q_storage)
 438                                 goto fail_tx_conf;
 439
 440                         memset(dpaa2_q->q_storage, 0,
 441                                sizeof(struct queue_storage_info_t));
 442                         if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
 443                                 goto fail_tx_conf;
 444                 }
 445         }
 446
 447         vq_id = 0;
 448         for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
 449                 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
 450                 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
 451                 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
 452                 vq_id++;
 453         }
 454
 455         return 0;
 456 fail_tx_conf:
 457         i -= 1;
 458         while (i >= 0) {
 459                 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
 460                 rte_free(dpaa2_q->q_storage);
 461                 priv->tx_conf_vq[i--] = NULL;
 462         }
 463         i = priv->nb_tx_queues;
 464 fail_tx:
 465         i -= 1;
 466         while (i >= 0) {
 467                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 468                 rte_free(dpaa2_q->cscn);
 469                 priv->tx_vq[i--] = NULL;
 470         }
 471         i = priv->nb_rx_queues;
 472 fail:
 473         i -= 1;
 474         mc_q = priv->rx_vq[0];
 475         while (i >= 0) {
 476                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 477                 dpaa2_free_dq_storage(dpaa2_q->q_storage);
 478                 rte_free(dpaa2_q->q_storage);
 479                 priv->rx_vq[i--] = NULL;
 480         }
 481
 482         if (dpaa2_enable_err_queue) {
 483                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
 484                 if (dpaa2_q->q_storage)
 485                         dpaa2_free_dq_storage(dpaa2_q->q_storage);
 486                 rte_free(dpaa2_q->q_storage);
 487         }
 488
 489         rte_free(mc_q);
 490         return -1;
 491 }
 492
 493 static void
 494 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
 495 {
 496         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 497         struct dpaa2_queue *dpaa2_q;
 498         int i;
 499
 500         PMD_INIT_FUNC_TRACE();
 501
 502         /* Queue allocation base */
 503         if (priv->rx_vq[0]) {
 504                 /* cleaning up queue storage */
 505                 for (i = 0; i < priv->nb_rx_queues; i++) {
 506                         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
 507                         if (dpaa2_q->q_storage)
 508                                 rte_free(dpaa2_q->q_storage);
 509                 }
 510                 /* cleanup tx queue cscn */
 511                 for (i = 0; i < priv->nb_tx_queues; i++) {
 512                         dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
 513                         rte_free(dpaa2_q->cscn);
 514                 }
 515                 if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 516                         /* cleanup tx conf queue storage */
 517                         for (i = 0; i < priv->nb_tx_queues; i++) {
 518                                 dpaa2_q = (struct dpaa2_queue *)
 519                                                 priv->tx_conf_vq[i];
 520                                 rte_free(dpaa2_q->q_storage);
 521                         }
 522                 }
 523                 /*free memory for all queues (RX+TX) */
 524                 rte_free(priv->rx_vq[0]);
 525                 priv->rx_vq[0] = NULL;
 526         }
 527 }
 528
 529 static int
 530 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
 531 {
 532         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 533         struct fsl_mc_io *dpni = dev->process_private;
 534         struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
 535         uint64_t rx_offloads = eth_conf->rxmode.offloads;
 536         uint64_t tx_offloads = eth_conf->txmode.offloads;
 537         int rx_l3_csum_offload = false;
 538         int rx_l4_csum_offload = false;
 539         int tx_l3_csum_offload = false;
 540         int tx_l4_csum_offload = false;
 541         int ret, tc_index;
 542         uint32_t max_rx_pktlen;
 543
 544         PMD_INIT_FUNC_TRACE();
 545
 546         /* Rx offloads which are enabled by default */
 547         if (dev_rx_offloads_nodis & ~rx_offloads) {
 548                 DPAA2_PMD_INFO(
 549                 "Some of rx offloads enabled by default - requested 0x%" PRIx64
 550                 " fixed are 0x%" PRIx64,
 551                 rx_offloads, dev_rx_offloads_nodis);
 552         }
 553
 554         /* Tx offloads which are enabled by default */
 555         if (dev_tx_offloads_nodis & ~tx_offloads) {
 556                 DPAA2_PMD_INFO(
 557                 "Some of tx offloads enabled by default - requested 0x%" PRIx64
 558                 " fixed are 0x%" PRIx64,
 559                 tx_offloads, dev_tx_offloads_nodis);
 560         }
 561
 562         max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN +
 563                                 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE;
 564         if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) {
 565                 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
 566                         priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN);
 567                 if (ret != 0) {
 568                         DPAA2_PMD_ERR("Unable to set mtu. check config");
 569                         return ret;
 570                 }
 571                 DPAA2_PMD_INFO("MTU configured for the device: %d",
 572                                 dev->data->mtu);
 573         } else {
 574                 return -1;
 575         }
 576
 577         if (eth_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) {
 578                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
 579                         ret = dpaa2_setup_flow_dist(dev,
 580                                         eth_conf->rx_adv_conf.rss_conf.rss_hf,
 581                                         tc_index);
 582                         if (ret) {
 583                                 DPAA2_PMD_ERR(
 584                                         "Unable to set flow distribution on tc%d."
 585                                         "Check queue config", tc_index);
 586                                 return ret;
 587                         }
 588                 }
 589         }
 590
 591         if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM)
 592                 rx_l3_csum_offload = true;
 593
 594         if ((rx_offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) ||
 595                 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) ||
 596                 (rx_offloads & RTE_ETH_RX_OFFLOAD_SCTP_CKSUM))
 597                 rx_l4_csum_offload = true;
 598
 599         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 600                                DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
 601         if (ret) {
 602                 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
 603                 return ret;
 604         }
 605
 606         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 607                                DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
 608         if (ret) {
 609                 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
 610                 return ret;
 611         }
 612
 613 #if !defined(RTE_LIBRTE_IEEE1588)
 614         if (rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
 615 #endif
 616         {
 617                 ret = rte_mbuf_dyn_rx_timestamp_register(
 618                                 &dpaa2_timestamp_dynfield_offset,
 619                                 &dpaa2_timestamp_rx_dynflag);
 620                 if (ret != 0) {
 621                         DPAA2_PMD_ERR("Error to register timestamp field/flag");
 622                         return -rte_errno;
 623                 }
 624                 dpaa2_enable_ts[dev->data->port_id] = true;
 625         }
 626
 627         if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM)
 628                 tx_l3_csum_offload = true;
 629
 630         if ((tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) ||
 631                 (tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) ||
 632                 (tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM))
 633                 tx_l4_csum_offload = true;
 634
 635         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 636                                DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
 637         if (ret) {
 638                 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
 639                 return ret;
 640         }
 641
 642         ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 643                                DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
 644         if (ret) {
 645                 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
 646                 return ret;
 647         }
 648
 649         /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
 650          * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
 651          * to 0 for LS2 in the hardware thus disabling data/annotation
 652          * stashing. For LX2 this is fixed in hardware and thus hash result and
 653          * parse results can be received in FD using this option.
 654          */
 655         if (dpaa2_svr_family == SVR_LX2160A) {
 656                 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
 657                                        DPNI_FLCTYPE_HASH, true);
 658                 if (ret) {
 659                         DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
 660                         return ret;
 661                 }
 662         }
 663
 664         if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
 665                 dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK);
 666
 667         dpaa2_tm_init(dev);
 668
 669         return 0;
 670 }
 671
 672 /* Function to setup RX flow information. It contains traffic class ID,
 673  * flow ID, destination configuration etc.
 674  */
 675 static int
 676 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
 677                          uint16_t rx_queue_id,
 678                          uint16_t nb_rx_desc,
 679                          unsigned int socket_id __rte_unused,
 680                          const struct rte_eth_rxconf *rx_conf,
 681                          struct rte_mempool *mb_pool)
 682 {
 683         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 684         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
 685         struct dpaa2_queue *dpaa2_q;
 686         struct dpni_queue cfg;
 687         uint8_t options = 0;
 688         uint8_t flow_id;
 689         uint32_t bpid;
 690         int i, ret;
 691
 692         PMD_INIT_FUNC_TRACE();
 693
 694         DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
 695                         dev, rx_queue_id, mb_pool, rx_conf);
 696
 697         /* Rx deferred start is not supported */
 698         if (rx_conf->rx_deferred_start) {
 699                 DPAA2_PMD_ERR("%p:Rx deferred start not supported",
 700                                 (void *)dev);
 701                 return -EINVAL;
 702         }
 703
 704         if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
 705                 bpid = mempool_to_bpid(mb_pool);
 706                 ret = dpaa2_attach_bp_list(priv,
 707                                            rte_dpaa2_bpid_info[bpid].bp_list);
 708                 if (ret)
 709                         return ret;
 710         }
 711         dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
 712         dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
 713         dpaa2_q->bp_array = rte_dpaa2_bpid_info;
 714         dpaa2_q->nb_desc = UINT16_MAX;
 715         dpaa2_q->offloads = rx_conf->offloads;
 716
 717         /*Get the flow id from given VQ id*/
 718         flow_id = dpaa2_q->flow_id;
 719         memset(&cfg, 0, sizeof(struct dpni_queue));
 720
 721         options = options | DPNI_QUEUE_OPT_USER_CTX;
 722         cfg.user_context = (size_t)(dpaa2_q);
 723
 724         /* check if a private cgr available. */
 725         for (i = 0; i < priv->max_cgs; i++) {
 726                 if (!priv->cgid_in_use[i]) {
 727                         priv->cgid_in_use[i] = 1;
 728                         break;
 729                 }
 730         }
 731
 732         if (i < priv->max_cgs) {
 733                 options |= DPNI_QUEUE_OPT_SET_CGID;
 734                 cfg.cgid = i;
 735                 dpaa2_q->cgid = cfg.cgid;
 736         } else {
 737                 dpaa2_q->cgid = 0xff;
 738         }
 739
 740         /*if ls2088 or rev2 device, enable the stashing */
 741
 742         if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
 743                 options |= DPNI_QUEUE_OPT_FLC;
 744                 cfg.flc.stash_control = true;
 745                 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
 746                 /* 00 00 00 - last 6 bit represent annotation, context stashing,
 747                  * data stashing setting 01 01 00 (0x14)
 748                  * (in following order ->DS AS CS)
 749                  * to enable 1 line data, 1 line annotation.
 750                  * For LX2, this setting should be 01 00 00 (0x10)
 751                  */
 752                 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
 753                         cfg.flc.value |= 0x10;
 754                 else
 755                         cfg.flc.value |= 0x14;
 756         }
 757         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
 758                              dpaa2_q->tc_index, flow_id, options, &cfg);
 759         if (ret) {
 760                 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
 761                 return -1;
 762         }
 763
 764         if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
 765                 struct dpni_taildrop taildrop;
 766
 767                 taildrop.enable = 1;
 768                 dpaa2_q->nb_desc = nb_rx_desc;
 769                 /* Private CGR will use tail drop length as nb_rx_desc.
 770                  * for rest cases we can use standard byte based tail drop.
 771                  * There is no HW restriction, but number of CGRs are limited,
 772                  * hence this restriction is placed.
 773                  */
 774                 if (dpaa2_q->cgid != 0xff) {
 775                         /*enabling per rx queue congestion control */
 776                         taildrop.threshold = nb_rx_desc;
 777                         taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
 778                         taildrop.oal = 0;
 779                         DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
 780                                         rx_queue_id);
 781                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 782                                                 DPNI_CP_CONGESTION_GROUP,
 783                                                 DPNI_QUEUE_RX,
 784                                                 dpaa2_q->tc_index,
 785                                                 dpaa2_q->cgid, &taildrop);
 786                 } else {
 787                         /*enabling per rx queue congestion control */
 788                         taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
 789                         taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
 790                         taildrop.oal = CONG_RX_OAL;
 791                         DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
 792                                         rx_queue_id);
 793                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 794                                                 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 795                                                 dpaa2_q->tc_index, flow_id,
 796                                                 &taildrop);
 797                 }
 798                 if (ret) {
 799                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 800                                       ret);
 801                         return -1;
 802                 }
 803         } else { /* Disable tail Drop */
 804                 struct dpni_taildrop taildrop = {0};
 805                 DPAA2_PMD_INFO("Tail drop is disabled on queue");
 806
 807                 taildrop.enable = 0;
 808                 if (dpaa2_q->cgid != 0xff) {
 809                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 810                                         DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
 811                                         dpaa2_q->tc_index,
 812                                         dpaa2_q->cgid, &taildrop);
 813                 } else {
 814                         ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
 815                                         DPNI_CP_QUEUE, DPNI_QUEUE_RX,
 816                                         dpaa2_q->tc_index, flow_id, &taildrop);
 817                 }
 818                 if (ret) {
 819                         DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
 820                                       ret);
 821                         return -1;
 822                 }
 823         }
 824
 825         dev->data->rx_queues[rx_queue_id] = dpaa2_q;
 826         return 0;
 827 }
 828
 829 static int
 830 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
 831                          uint16_t tx_queue_id,
 832                          uint16_t nb_tx_desc,
 833                          unsigned int socket_id __rte_unused,
 834                          const struct rte_eth_txconf *tx_conf)
 835 {
 836         struct dpaa2_dev_priv *priv = dev->data->dev_private;
 837         struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
 838                 priv->tx_vq[tx_queue_id];
 839         struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
 840                 priv->tx_conf_vq[tx_queue_id];
 841         struct fsl_mc_io *dpni = dev->process_private;
 842         struct dpni_queue tx_conf_cfg;
 843         struct dpni_queue tx_flow_cfg;
 844         uint8_t options = 0, flow_id;
 845         struct dpni_queue_id qid;
 846         uint32_t tc_id;
 847         int ret;
 848
 849         PMD_INIT_FUNC_TRACE();
 850
 851         /* Tx deferred start is not supported */
 852         if (tx_conf->tx_deferred_start) {
 853                 DPAA2_PMD_ERR("%p:Tx deferred start not supported",
 854                                 (void *)dev);
 855                 return -EINVAL;
 856         }
 857
 858         dpaa2_q->nb_desc = UINT16_MAX;
 859         dpaa2_q->offloads = tx_conf->offloads;
 860
 861         /* Return if queue already configured */
 862         if (dpaa2_q->flow_id != 0xffff) {
 863                 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 864                 return 0;
 865         }
 866
 867         memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
 868         memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
 869
 870         tc_id = tx_queue_id;
 871         flow_id = 0;
 872
 873         ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
 874                         tc_id, flow_id, options, &tx_flow_cfg);
 875         if (ret) {
 876                 DPAA2_PMD_ERR("Error in setting the tx flow: "
 877                         "tc_id=%d, flow=%d err=%d",
 878                         tc_id, flow_id, ret);
 879                         return -1;
 880         }
 881
 882         dpaa2_q->flow_id = flow_id;
 883
 884         if (tx_queue_id == 0) {
 885                 /*Set tx-conf and error configuration*/
 886                 if (priv->flags & DPAA2_TX_CONF_ENABLE)
 887                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 888                                                             priv->token,
 889                                                             DPNI_CONF_AFFINE);
 890                 else
 891                         ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
 892                                                             priv->token,
 893                                                             DPNI_CONF_DISABLE);
 894                 if (ret) {
 895                         DPAA2_PMD_ERR("Error in set tx conf mode settings: "
 896                                       "err=%d", ret);
 897                         return -1;
 898                 }
 899         }
 900         dpaa2_q->tc_index = tc_id;
 901
 902         ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 903                              DPNI_QUEUE_TX, dpaa2_q->tc_index,
 904                              dpaa2_q->flow_id, &tx_flow_cfg, &qid);
 905         if (ret) {
 906                 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 907                 return -1;
 908         }
 909         dpaa2_q->fqid = qid.fqid;
 910
 911         if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
 912                 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
 913
 914                 dpaa2_q->nb_desc = nb_tx_desc;
 915
 916                 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
 917                 cong_notif_cfg.threshold_entry = nb_tx_desc;
 918                 /* Notify that the queue is not congested when the data in
 919                  * the queue is below this threshold.(90% of value)
 920                  */
 921                 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10;
 922                 cong_notif_cfg.message_ctx = 0;
 923                 cong_notif_cfg.message_iova =
 924                                 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
 925                 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
 926                 cong_notif_cfg.notification_mode =
 927                                          DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
 928                                          DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
 929                                          DPNI_CONG_OPT_COHERENT_WRITE;
 930                 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
 931
 932                 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
 933                                                        priv->token,
 934                                                        DPNI_QUEUE_TX,
 935                                                        tc_id,
 936                                                        &cong_notif_cfg);
 937                 if (ret) {
 938                         DPAA2_PMD_ERR(
 939                            "Error in setting tx congestion notification: "
 940                            "err=%d", ret);
 941                         return -ret;
 942                 }
 943         }
 944         dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
 945         dev->data->tx_queues[tx_queue_id] = dpaa2_q;
 946
 947         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
 948                 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
 949                 options = options | DPNI_QUEUE_OPT_USER_CTX;
 950                 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
 951                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 952                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 953                              dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
 954                 if (ret) {
 955                         DPAA2_PMD_ERR("Error in setting the tx conf flow: "
 956                               "tc_index=%d, flow=%d err=%d",
 957                               dpaa2_tx_conf_q->tc_index,
 958                               dpaa2_tx_conf_q->flow_id, ret);
 959                         return -1;
 960                 }
 961
 962                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
 963                              DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
 964                              dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
 965                 if (ret) {
 966                         DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
 967                         return -1;
 968                 }
 969                 dpaa2_tx_conf_q->fqid = qid.fqid;
 970         }
 971         return 0;
 972 }
 973
 974 static void
 975 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 976 {
 977         struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id];
 978         struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
 979         struct fsl_mc_io *dpni =
 980                 (struct fsl_mc_io *)priv->eth_dev->process_private;
 981         uint8_t options = 0;
 982         int ret;
 983         struct dpni_queue cfg;
 984
 985         memset(&cfg, 0, sizeof(struct dpni_queue));
 986         PMD_INIT_FUNC_TRACE();
 987         if (dpaa2_q->cgid != 0xff) {
 988                 options = DPNI_QUEUE_OPT_CLEAR_CGID;
 989                 cfg.cgid = dpaa2_q->cgid;
 990
 991                 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
 992                                      DPNI_QUEUE_RX,
 993                                      dpaa2_q->tc_index, dpaa2_q->flow_id,
 994                                      options, &cfg);
 995                 if (ret)
 996                         DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
 997                                         dpaa2_q->fqid, ret);
 998                 priv->cgid_in_use[dpaa2_q->cgid] = 0;
 999                 dpaa2_q->cgid = 0xff;
1000         }
1001 }
1002
1003 static uint32_t
1004 dpaa2_dev_rx_queue_count(void *rx_queue)
1005 {
1006         int32_t ret;
1007         struct dpaa2_queue *dpaa2_q;
1008         struct qbman_swp *swp;
1009         struct qbman_fq_query_np_rslt state;
1010         uint32_t frame_cnt = 0;
1011
1012         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
1013                 ret = dpaa2_affine_qbman_swp();
1014                 if (ret) {
1015                         DPAA2_PMD_ERR(
1016                                 "Failed to allocate IO portal, tid: %d\n",
1017                                 rte_gettid());
1018                         return -EINVAL;
1019                 }
1020         }
1021         swp = DPAA2_PER_LCORE_PORTAL;
1022
1023         dpaa2_q = rx_queue;
1024
1025         if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
1026                 frame_cnt = qbman_fq_state_frame_count(&state);
1027                 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u",
1028                                 rx_queue, frame_cnt);
1029         }
1030         return frame_cnt;
1031 }
1032
1033 static const uint32_t *
1034 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
1035 {
1036         static const uint32_t ptypes[] = {
1037                 /*todo -= add more types */
1038                 RTE_PTYPE_L2_ETHER,
1039                 RTE_PTYPE_L3_IPV4,
1040                 RTE_PTYPE_L3_IPV4_EXT,
1041                 RTE_PTYPE_L3_IPV6,
1042                 RTE_PTYPE_L3_IPV6_EXT,
1043                 RTE_PTYPE_L4_TCP,
1044                 RTE_PTYPE_L4_UDP,
1045                 RTE_PTYPE_L4_SCTP,
1046                 RTE_PTYPE_L4_ICMP,
1047                 RTE_PTYPE_UNKNOWN
1048         };
1049
1050         if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
1051                 dev->rx_pkt_burst == dpaa2_dev_rx ||
1052                 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
1053                 return ptypes;
1054         return NULL;
1055 }
1056
1057 /**
1058  * Dpaa2 link Interrupt handler
1059  *
1060  * @param param
1061  *  The address of parameter (struct rte_eth_dev *) registered before.
1062  *
1063  * @return
1064  *  void
1065  */
1066 static void
1067 dpaa2_interrupt_handler(void *param)
1068 {
1069         struct rte_eth_dev *dev = param;
1070         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1071         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1072         int ret;
1073         int irq_index = DPNI_IRQ_INDEX;
1074         unsigned int status = 0, clear = 0;
1075
1076         PMD_INIT_FUNC_TRACE();
1077
1078         if (dpni == NULL) {
1079                 DPAA2_PMD_ERR("dpni is NULL");
1080                 return;
1081         }
1082
1083         ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
1084                                   irq_index, &status);
1085         if (unlikely(ret)) {
1086                 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
1087                 clear = 0xffffffff;
1088                 goto out;
1089         }
1090
1091         if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
1092                 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
1093                 dpaa2_dev_link_update(dev, 0);
1094                 /* calling all the apps registered for link status event */
1095                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1096         }
1097 out:
1098         ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
1099                                     irq_index, clear);
1100         if (unlikely(ret))
1101                 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
1102 }
1103
1104 static int
1105 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
1106 {
1107         int err = 0;
1108         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1109         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1110         int irq_index = DPNI_IRQ_INDEX;
1111         unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
1112
1113         PMD_INIT_FUNC_TRACE();
1114
1115         err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
1116                                 irq_index, mask);
1117         if (err < 0) {
1118                 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1119                               strerror(-err));
1120                 return err;
1121         }
1122
1123         err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1124                                   irq_index, enable);
1125         if (err < 0)
1126                 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1127                               strerror(-err));
1128
1129         return err;
1130 }
1131
1132 static int
1133 dpaa2_dev_start(struct rte_eth_dev *dev)
1134 {
1135         struct rte_device *rdev = dev->device;
1136         struct rte_dpaa2_device *dpaa2_dev;
1137         struct rte_eth_dev_data *data = dev->data;
1138         struct dpaa2_dev_priv *priv = data->dev_private;
1139         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1140         struct dpni_queue cfg;
1141         struct dpni_error_cfg   err_cfg;
1142         uint16_t qdid;
1143         struct dpni_queue_id qid;
1144         struct dpaa2_queue *dpaa2_q;
1145         int ret, i;
1146         struct rte_intr_handle *intr_handle;
1147
1148         dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1149         intr_handle = dpaa2_dev->intr_handle;
1150
1151         PMD_INIT_FUNC_TRACE();
1152
1153         ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1154         if (ret) {
1155                 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1156                               priv->hw_id, ret);
1157                 return ret;
1158         }
1159
1160         /* Power up the phy. Needed to make the link go UP */
1161         dpaa2_dev_set_link_up(dev);
1162
1163         ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1164                             DPNI_QUEUE_TX, &qdid);
1165         if (ret) {
1166                 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1167                 return ret;
1168         }
1169         priv->qdid = qdid;
1170
1171         for (i = 0; i < data->nb_rx_queues; i++) {
1172                 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1173                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1174                                      DPNI_QUEUE_RX, dpaa2_q->tc_index,
1175                                        dpaa2_q->flow_id, &cfg, &qid);
1176                 if (ret) {
1177                         DPAA2_PMD_ERR("Error in getting flow information: "
1178                                       "err=%d", ret);
1179                         return ret;
1180                 }
1181                 dpaa2_q->fqid = qid.fqid;
1182         }
1183
1184         if (dpaa2_enable_err_queue) {
1185                 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1186                                      DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid);
1187                 if (ret) {
1188                         DPAA2_PMD_ERR("Error getting rx err flow information: err=%d",
1189                                                 ret);
1190                         return ret;
1191                 }
1192                 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq;
1193                 dpaa2_q->fqid = qid.fqid;
1194                 dpaa2_q->eth_data = dev->data;
1195
1196                 err_cfg.errors =  DPNI_ERROR_DISC;
1197                 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
1198         } else {
1199                 /* checksum errors, send them to normal path
1200                  * and set it in annotation
1201                  */
1202                 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1203
1204                 /* if packet with parse error are not to be dropped */
1205                 err_cfg.errors |= DPNI_ERROR_PHE;
1206
1207                 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1208         }
1209         err_cfg.set_frame_annotation = true;
1210
1211         ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1212                                        priv->token, &err_cfg);
1213         if (ret) {
1214                 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1215                               ret);
1216                 return ret;
1217         }
1218
1219         /* if the interrupts were configured on this devices*/
1220         if (intr_handle && rte_intr_fd_get(intr_handle) &&
1221             dev->data->dev_conf.intr_conf.lsc != 0) {
1222                 /* Registering LSC interrupt handler */
1223                 rte_intr_callback_register(intr_handle,
1224                                            dpaa2_interrupt_handler,
1225                                            (void *)dev);
1226
1227                 /* enable vfio intr/eventfd mapping
1228                  * Interrupt index 0 is required, so we can not use
1229                  * rte_intr_enable.
1230                  */
1231                 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1232
1233                 /* enable dpni_irqs */
1234                 dpaa2_eth_setup_irqs(dev, 1);
1235         }
1236
1237         /* Change the tx burst function if ordered queues are used */
1238         if (priv->en_ordered)
1239                 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1240
1241         return 0;
1242 }
1243
1244 /**
1245  *  This routine disables all traffic on the adapter by issuing a
1246  *  global reset on the MAC.
1247  */
1248 static int
1249 dpaa2_dev_stop(struct rte_eth_dev *dev)
1250 {
1251         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1252         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1253         int ret;
1254         struct rte_eth_link link;
1255         struct rte_intr_handle *intr_handle = dev->intr_handle;
1256
1257         PMD_INIT_FUNC_TRACE();
1258
1259         /* reset interrupt callback  */
1260         if (intr_handle && rte_intr_fd_get(intr_handle) &&
1261             dev->data->dev_conf.intr_conf.lsc != 0) {
1262                 /*disable dpni irqs */
1263                 dpaa2_eth_setup_irqs(dev, 0);
1264
1265                 /* disable vfio intr before callback unregister */
1266                 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1267
1268                 /* Unregistering LSC interrupt handler */
1269                 rte_intr_callback_unregister(intr_handle,
1270                                              dpaa2_interrupt_handler,
1271                                              (void *)dev);
1272         }
1273
1274         dpaa2_dev_set_link_down(dev);
1275
1276         ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1277         if (ret) {
1278                 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1279                               ret, priv->hw_id);
1280                 return ret;
1281         }
1282
1283         /* clear the recorded link status */
1284         memset(&link, 0, sizeof(link));
1285         rte_eth_linkstatus_set(dev, &link);
1286
1287         return 0;
1288 }
1289
1290 static int
1291 dpaa2_dev_close(struct rte_eth_dev *dev)
1292 {
1293         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1294         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1295         int i, ret;
1296         struct rte_eth_link link;
1297
1298         PMD_INIT_FUNC_TRACE();
1299
1300         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1301                 return 0;
1302
1303         if (!dpni) {
1304                 DPAA2_PMD_WARN("Already closed or not started");
1305                 return -1;
1306         }
1307
1308         dpaa2_tm_deinit(dev);
1309         dpaa2_flow_clean(dev);
1310         /* Clean the device first */
1311         ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1312         if (ret) {
1313                 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1314                 return -1;
1315         }
1316
1317         memset(&link, 0, sizeof(link));
1318         rte_eth_linkstatus_set(dev, &link);
1319
1320         /* Free private queues memory */
1321         dpaa2_free_rx_tx_queues(dev);
1322         /* Close the device at underlying layer*/
1323         ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
1324         if (ret) {
1325                 DPAA2_PMD_ERR("Failure closing dpni device with err code %d",
1326                               ret);
1327         }
1328
1329         /* Free the allocated memory for ethernet private data and dpni*/
1330         priv->hw = NULL;
1331         dev->process_private = NULL;
1332         rte_free(dpni);
1333
1334         for (i = 0; i < MAX_TCS; i++)
1335                 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]);
1336
1337         if (priv->extract.qos_extract_param)
1338                 rte_free((void *)(size_t)priv->extract.qos_extract_param);
1339
1340         DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name);
1341         return 0;
1342 }
1343
1344 static int
1345 dpaa2_dev_promiscuous_enable(
1346                 struct rte_eth_dev *dev)
1347 {
1348         int ret;
1349         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1350         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1351
1352         PMD_INIT_FUNC_TRACE();
1353
1354         if (dpni == NULL) {
1355                 DPAA2_PMD_ERR("dpni is NULL");
1356                 return -ENODEV;
1357         }
1358
1359         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1360         if (ret < 0)
1361                 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1362
1363         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1364         if (ret < 0)
1365                 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1366
1367         return ret;
1368 }
1369
1370 static int
1371 dpaa2_dev_promiscuous_disable(
1372                 struct rte_eth_dev *dev)
1373 {
1374         int ret;
1375         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1376         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1377
1378         PMD_INIT_FUNC_TRACE();
1379
1380         if (dpni == NULL) {
1381                 DPAA2_PMD_ERR("dpni is NULL");
1382                 return -ENODEV;
1383         }
1384
1385         ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1386         if (ret < 0)
1387                 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1388
1389         if (dev->data->all_multicast == 0) {
1390                 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1391                                                  priv->token, false);
1392                 if (ret < 0)
1393                         DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1394                                       ret);
1395         }
1396
1397         return ret;
1398 }
1399
1400 static int
1401 dpaa2_dev_allmulticast_enable(
1402                 struct rte_eth_dev *dev)
1403 {
1404         int ret;
1405         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1406         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1407
1408         PMD_INIT_FUNC_TRACE();
1409
1410         if (dpni == NULL) {
1411                 DPAA2_PMD_ERR("dpni is NULL");
1412                 return -ENODEV;
1413         }
1414
1415         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1416         if (ret < 0)
1417                 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1418
1419         return ret;
1420 }
1421
1422 static int
1423 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1424 {
1425         int ret;
1426         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1427         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1428
1429         PMD_INIT_FUNC_TRACE();
1430
1431         if (dpni == NULL) {
1432                 DPAA2_PMD_ERR("dpni is NULL");
1433                 return -ENODEV;
1434         }
1435
1436         /* must remain on for all promiscuous */
1437         if (dev->data->promiscuous == 1)
1438                 return 0;
1439
1440         ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1441         if (ret < 0)
1442                 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1443
1444         return ret;
1445 }
1446
1447 static int
1448 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1449 {
1450         int ret;
1451         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1452         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1453         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1454                                 + VLAN_TAG_SIZE;
1455
1456         PMD_INIT_FUNC_TRACE();
1457
1458         if (dpni == NULL) {
1459                 DPAA2_PMD_ERR("dpni is NULL");
1460                 return -EINVAL;
1461         }
1462
1463         /* Set the Max Rx frame length as 'mtu' +
1464          * Maximum Ethernet header length
1465          */
1466         ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1467                                         frame_size - RTE_ETHER_CRC_LEN);
1468         if (ret) {
1469                 DPAA2_PMD_ERR("Setting the max frame length failed");
1470                 return -1;
1471         }
1472         DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1473         return 0;
1474 }
1475
1476 static int
1477 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1478                        struct rte_ether_addr *addr,
1479                        __rte_unused uint32_t index,
1480                        __rte_unused uint32_t pool)
1481 {
1482         int ret;
1483         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1484         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1485
1486         PMD_INIT_FUNC_TRACE();
1487
1488         if (dpni == NULL) {
1489                 DPAA2_PMD_ERR("dpni is NULL");
1490                 return -1;
1491         }
1492
1493         ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1494                                 addr->addr_bytes, 0, 0, 0);
1495         if (ret)
1496                 DPAA2_PMD_ERR(
1497                         "error: Adding the MAC ADDR failed: err = %d", ret);
1498         return 0;
1499 }
1500
1501 static void
1502 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1503                           uint32_t index)
1504 {
1505         int ret;
1506         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1507         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1508         struct rte_eth_dev_data *data = dev->data;
1509         struct rte_ether_addr *macaddr;
1510
1511         PMD_INIT_FUNC_TRACE();
1512
1513         macaddr = &data->mac_addrs[index];
1514
1515         if (dpni == NULL) {
1516                 DPAA2_PMD_ERR("dpni is NULL");
1517                 return;
1518         }
1519
1520         ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1521                                    priv->token, macaddr->addr_bytes);
1522         if (ret)
1523                 DPAA2_PMD_ERR(
1524                         "error: Removing the MAC ADDR failed: err = %d", ret);
1525 }
1526
1527 static int
1528 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1529                        struct rte_ether_addr *addr)
1530 {
1531         int ret;
1532         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1533         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1534
1535         PMD_INIT_FUNC_TRACE();
1536
1537         if (dpni == NULL) {
1538                 DPAA2_PMD_ERR("dpni is NULL");
1539                 return -EINVAL;
1540         }
1541
1542         ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1543                                         priv->token, addr->addr_bytes);
1544
1545         if (ret)
1546                 DPAA2_PMD_ERR(
1547                         "error: Setting the MAC ADDR failed %d", ret);
1548
1549         return ret;
1550 }
1551
1552 static
1553 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1554                          struct rte_eth_stats *stats)
1555 {
1556         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1557         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1558         int32_t  retcode;
1559         uint8_t page0 = 0, page1 = 1, page2 = 2;
1560         union dpni_statistics value;
1561         int i;
1562         struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1563
1564         memset(&value, 0, sizeof(union dpni_statistics));
1565
1566         PMD_INIT_FUNC_TRACE();
1567
1568         if (!dpni) {
1569                 DPAA2_PMD_ERR("dpni is NULL");
1570                 return -EINVAL;
1571         }
1572
1573         if (!stats) {
1574                 DPAA2_PMD_ERR("stats is NULL");
1575                 return -EINVAL;
1576         }
1577
1578         /*Get Counters from page_0*/
1579         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1580                                       page0, 0, &value);
1581         if (retcode)
1582                 goto err;
1583
1584         stats->ipackets = value.page_0.ingress_all_frames;
1585         stats->ibytes = value.page_0.ingress_all_bytes;
1586
1587         /*Get Counters from page_1*/
1588         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1589                                       page1, 0, &value);
1590         if (retcode)
1591                 goto err;
1592
1593         stats->opackets = value.page_1.egress_all_frames;
1594         stats->obytes = value.page_1.egress_all_bytes;
1595
1596         /*Get Counters from page_2*/
1597         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1598                                       page2, 0, &value);
1599         if (retcode)
1600                 goto err;
1601
1602         /* Ingress drop frame count due to configured rules */
1603         stats->ierrors = value.page_2.ingress_filtered_frames;
1604         /* Ingress drop frame count due to error */
1605         stats->ierrors += value.page_2.ingress_discarded_frames;
1606
1607         stats->oerrors = value.page_2.egress_discarded_frames;
1608         stats->imissed = value.page_2.ingress_nobuffer_discards;
1609
1610         /* Fill in per queue stats */
1611         for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1612                 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1613                 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1614                 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1615                 if (dpaa2_rxq)
1616                         stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1617                 if (dpaa2_txq)
1618                         stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1619
1620                 /* Byte counting is not implemented */
1621                 stats->q_ibytes[i]   = 0;
1622                 stats->q_obytes[i]   = 0;
1623         }
1624
1625         return 0;
1626
1627 err:
1628         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1629         return retcode;
1630 };
1631
1632 static int
1633 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1634                      unsigned int n)
1635 {
1636         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1637         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1638         int32_t  retcode;
1639         union dpni_statistics value[5] = {};
1640         unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1641
1642         if (n < num)
1643                 return num;
1644
1645         if (xstats == NULL)
1646                 return 0;
1647
1648         /* Get Counters from page_0*/
1649         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1650                                       0, 0, &value[0]);
1651         if (retcode)
1652                 goto err;
1653
1654         /* Get Counters from page_1*/
1655         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1656                                       1, 0, &value[1]);
1657         if (retcode)
1658                 goto err;
1659
1660         /* Get Counters from page_2*/
1661         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1662                                       2, 0, &value[2]);
1663         if (retcode)
1664                 goto err;
1665
1666         for (i = 0; i < priv->max_cgs; i++) {
1667                 if (!priv->cgid_in_use[i]) {
1668                         /* Get Counters from page_4*/
1669                         retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1670                                                       priv->token,
1671                                                       4, 0, &value[4]);
1672                         if (retcode)
1673                                 goto err;
1674                         break;
1675                 }
1676         }
1677
1678         for (i = 0; i < num; i++) {
1679                 xstats[i].id = i;
1680                 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1681                         raw.counter[dpaa2_xstats_strings[i].stats_id];
1682         }
1683         return i;
1684 err:
1685         DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1686         return retcode;
1687 }
1688
1689 static int
1690 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1691                        struct rte_eth_xstat_name *xstats_names,
1692                        unsigned int limit)
1693 {
1694         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1695
1696         if (limit < stat_cnt)
1697                 return stat_cnt;
1698
1699         if (xstats_names != NULL)
1700                 for (i = 0; i < stat_cnt; i++)
1701                         strlcpy(xstats_names[i].name,
1702                                 dpaa2_xstats_strings[i].name,
1703                                 sizeof(xstats_names[i].name));
1704
1705         return stat_cnt;
1706 }
1707
1708 static int
1709 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1710                        uint64_t *values, unsigned int n)
1711 {
1712         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1713         uint64_t values_copy[stat_cnt];
1714
1715         if (!ids) {
1716                 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1717                 struct fsl_mc_io *dpni =
1718                         (struct fsl_mc_io *)dev->process_private;
1719                 int32_t  retcode;
1720                 union dpni_statistics value[5] = {};
1721
1722                 if (n < stat_cnt)
1723                         return stat_cnt;
1724
1725                 if (!values)
1726                         return 0;
1727
1728                 /* Get Counters from page_0*/
1729                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1730                                               0, 0, &value[0]);
1731                 if (retcode)
1732                         return 0;
1733
1734                 /* Get Counters from page_1*/
1735                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1736                                               1, 0, &value[1]);
1737                 if (retcode)
1738                         return 0;
1739
1740                 /* Get Counters from page_2*/
1741                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1742                                               2, 0, &value[2]);
1743                 if (retcode)
1744                         return 0;
1745
1746                 /* Get Counters from page_4*/
1747                 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1748                                               4, 0, &value[4]);
1749                 if (retcode)
1750                         return 0;
1751
1752                 for (i = 0; i < stat_cnt; i++) {
1753                         values[i] = value[dpaa2_xstats_strings[i].page_id].
1754                                 raw.counter[dpaa2_xstats_strings[i].stats_id];
1755                 }
1756                 return stat_cnt;
1757         }
1758
1759         dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1760
1761         for (i = 0; i < n; i++) {
1762                 if (ids[i] >= stat_cnt) {
1763                         DPAA2_PMD_ERR("xstats id value isn't valid");
1764                         return -1;
1765                 }
1766                 values[i] = values_copy[ids[i]];
1767         }
1768         return n;
1769 }
1770
1771 static int
1772 dpaa2_xstats_get_names_by_id(
1773         struct rte_eth_dev *dev,
1774         const uint64_t *ids,
1775         struct rte_eth_xstat_name *xstats_names,
1776         unsigned int limit)
1777 {
1778         unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1779         struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1780
1781         if (!ids)
1782                 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1783
1784         dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1785
1786         for (i = 0; i < limit; i++) {
1787                 if (ids[i] >= stat_cnt) {
1788                         DPAA2_PMD_ERR("xstats id value isn't valid");
1789                         return -1;
1790                 }
1791                 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1792         }
1793         return limit;
1794 }
1795
1796 static int
1797 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1798 {
1799         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1800         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1801         int retcode;
1802         int i;
1803         struct dpaa2_queue *dpaa2_q;
1804
1805         PMD_INIT_FUNC_TRACE();
1806
1807         if (dpni == NULL) {
1808                 DPAA2_PMD_ERR("dpni is NULL");
1809                 return -EINVAL;
1810         }
1811
1812         retcode =  dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1813         if (retcode)
1814                 goto error;
1815
1816         /* Reset the per queue stats in dpaa2_queue structure */
1817         for (i = 0; i < priv->nb_rx_queues; i++) {
1818                 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1819                 if (dpaa2_q)
1820                         dpaa2_q->rx_pkts = 0;
1821         }
1822
1823         for (i = 0; i < priv->nb_tx_queues; i++) {
1824                 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1825                 if (dpaa2_q)
1826                         dpaa2_q->tx_pkts = 0;
1827         }
1828
1829         return 0;
1830
1831 error:
1832         DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1833         return retcode;
1834 };
1835
1836 /* return 0 means link status changed, -1 means not changed */
1837 static int
1838 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1839                       int wait_to_complete)
1840 {
1841         int ret;
1842         struct dpaa2_dev_priv *priv = dev->data->dev_private;
1843         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1844         struct rte_eth_link link;
1845         struct dpni_link_state state = {0};
1846         uint8_t count;
1847
1848         if (dpni == NULL) {
1849                 DPAA2_PMD_ERR("dpni is NULL");
1850                 return 0;
1851         }
1852
1853         for (count = 0; count <= MAX_REPEAT_TIME; count++) {
1854                 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token,
1855                                           &state);
1856                 if (ret < 0) {
1857                         DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1858                         return -1;
1859                 }
1860                 if (state.up == RTE_ETH_LINK_DOWN &&
1861                     wait_to_complete)
1862                         rte_delay_ms(CHECK_INTERVAL);
1863                 else
1864                         break;
1865         }
1866
1867         memset(&link, 0, sizeof(struct rte_eth_link));
1868         link.link_status = state.up;
1869         link.link_speed = state.rate;
1870
1871         if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1872                 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX;
1873         else
1874                 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
1875
1876         ret = rte_eth_linkstatus_set(dev, &link);
1877         if (ret == -1)
1878                 DPAA2_PMD_DEBUG("No change in status");
1879         else
1880                 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1881                                link.link_status ? "Up" : "Down");
1882
1883         return ret;
1884 }
1885
1886 /**
1887  * Toggle the DPNI to enable, if not already enabled.
1888  * This is not strictly PHY up/down - it is more of logical toggling.
1889  */
1890 static int
1891 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1892 {
1893         int ret = -EINVAL;
1894         struct dpaa2_dev_priv *priv;
1895         struct fsl_mc_io *dpni;
1896         int en = 0;
1897         struct dpni_link_state state = {0};
1898
1899         priv = dev->data->dev_private;
1900         dpni = (struct fsl_mc_io *)dev->process_private;
1901
1902         if (dpni == NULL) {
1903                 DPAA2_PMD_ERR("dpni is NULL");
1904                 return ret;
1905         }
1906
1907         /* Check if DPNI is currently enabled */
1908         ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1909         if (ret) {
1910                 /* Unable to obtain dpni status; Not continuing */
1911                 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1912                 return -EINVAL;
1913         }
1914
1915         /* Enable link if not already enabled */
1916         if (!en) {
1917                 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1918                 if (ret) {
1919                         DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1920                         return -EINVAL;
1921                 }
1922         }
1923         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1924         if (ret < 0) {
1925                 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1926                 return -1;
1927         }
1928
1929         /* changing tx burst function to start enqueues */
1930         dev->tx_pkt_burst = dpaa2_dev_tx;
1931         dev->data->dev_link.link_status = state.up;
1932         dev->data->dev_link.link_speed = state.rate;
1933
1934         if (state.up)
1935                 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1936         else
1937                 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1938         return ret;
1939 }
1940
1941 /**
1942  * Toggle the DPNI to disable, if not already disabled.
1943  * This is not strictly PHY up/down - it is more of logical toggling.
1944  */
1945 static int
1946 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1947 {
1948         int ret = -EINVAL;
1949         struct dpaa2_dev_priv *priv;
1950         struct fsl_mc_io *dpni;
1951         int dpni_enabled = 0;
1952         int retries = 10;
1953
1954         PMD_INIT_FUNC_TRACE();
1955
1956         priv = dev->data->dev_private;
1957         dpni = (struct fsl_mc_io *)dev->process_private;
1958
1959         if (dpni == NULL) {
1960                 DPAA2_PMD_ERR("Device has not yet been configured");
1961                 return ret;
1962         }
1963
1964         /*changing  tx burst function to avoid any more enqueues */
1965         dev->tx_pkt_burst = dummy_dev_tx;
1966
1967         /* Loop while dpni_disable() attempts to drain the egress FQs
1968          * and confirm them back to us.
1969          */
1970         do {
1971                 ret = dpni_disable(dpni, 0, priv->token);
1972                 if (ret) {
1973                         DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1974                         return ret;
1975                 }
1976                 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1977                 if (ret) {
1978                         DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1979                         return ret;
1980                 }
1981                 if (dpni_enabled)
1982                         /* Allow the MC some slack */
1983                         rte_delay_us(100 * 1000);
1984         } while (dpni_enabled && --retries);
1985
1986         if (!retries) {
1987                 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1988                 /* todo- we may have to manually cleanup queues.
1989                  */
1990         } else {
1991                 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1992                                dev->data->port_id);
1993         }
1994
1995         dev->data->dev_link.link_status = 0;
1996
1997         return ret;
1998 }
1999
2000 static int
2001 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2002 {
2003         int ret = -EINVAL;
2004         struct dpaa2_dev_priv *priv;
2005         struct fsl_mc_io *dpni;
2006         struct dpni_link_state state = {0};
2007
2008         PMD_INIT_FUNC_TRACE();
2009
2010         priv = dev->data->dev_private;
2011         dpni = (struct fsl_mc_io *)dev->process_private;
2012
2013         if (dpni == NULL || fc_conf == NULL) {
2014                 DPAA2_PMD_ERR("device not configured");
2015                 return ret;
2016         }
2017
2018         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2019         if (ret) {
2020                 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
2021                 return ret;
2022         }
2023
2024         memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
2025         if (state.options & DPNI_LINK_OPT_PAUSE) {
2026                 /* DPNI_LINK_OPT_PAUSE set
2027                  *  if ASYM_PAUSE not set,
2028                  *      RX Side flow control (handle received Pause frame)
2029                  *      TX side flow control (send Pause frame)
2030                  *  if ASYM_PAUSE set,
2031                  *      RX Side flow control (handle received Pause frame)
2032                  *      No TX side flow control (send Pause frame disabled)
2033                  */
2034                 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
2035                         fc_conf->mode = RTE_ETH_FC_FULL;
2036                 else
2037                         fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
2038         } else {
2039                 /* DPNI_LINK_OPT_PAUSE not set
2040                  *  if ASYM_PAUSE set,
2041                  *      TX side flow control (send Pause frame)
2042                  *      No RX side flow control (No action on pause frame rx)
2043                  *  if ASYM_PAUSE not set,
2044                  *      Flow control disabled
2045                  */
2046                 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
2047                         fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
2048                 else
2049                         fc_conf->mode = RTE_ETH_FC_NONE;
2050         }
2051
2052         return ret;
2053 }
2054
2055 static int
2056 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2057 {
2058         int ret = -EINVAL;
2059         struct dpaa2_dev_priv *priv;
2060         struct fsl_mc_io *dpni;
2061         struct dpni_link_state state = {0};
2062         struct dpni_link_cfg cfg = {0};
2063
2064         PMD_INIT_FUNC_TRACE();
2065
2066         priv = dev->data->dev_private;
2067         dpni = (struct fsl_mc_io *)dev->process_private;
2068
2069         if (dpni == NULL) {
2070                 DPAA2_PMD_ERR("dpni is NULL");
2071                 return ret;
2072         }
2073
2074         /* It is necessary to obtain the current state before setting fc_conf
2075          * as MC would return error in case rate, autoneg or duplex values are
2076          * different.
2077          */
2078         ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
2079         if (ret) {
2080                 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
2081                 return -1;
2082         }
2083
2084         /* Disable link before setting configuration */
2085         dpaa2_dev_set_link_down(dev);
2086
2087         /* Based on fc_conf, update cfg */
2088         cfg.rate = state.rate;
2089         cfg.options = state.options;
2090
2091         /* update cfg with fc_conf */
2092         switch (fc_conf->mode) {
2093         case RTE_ETH_FC_FULL:
2094                 /* Full flow control;
2095                  * OPT_PAUSE set, ASYM_PAUSE not set
2096                  */
2097                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2098                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2099                 break;
2100         case RTE_ETH_FC_TX_PAUSE:
2101                 /* Enable RX flow control
2102                  * OPT_PAUSE not set;
2103                  * ASYM_PAUSE set;
2104                  */
2105                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2106                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2107                 break;
2108         case RTE_ETH_FC_RX_PAUSE:
2109                 /* Enable TX Flow control
2110                  * OPT_PAUSE set
2111                  * ASYM_PAUSE set
2112                  */
2113                 cfg.options |= DPNI_LINK_OPT_PAUSE;
2114                 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
2115                 break;
2116         case RTE_ETH_FC_NONE:
2117                 /* Disable Flow control
2118                  * OPT_PAUSE not set
2119                  * ASYM_PAUSE not set
2120                  */
2121                 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
2122                 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
2123                 break;
2124         default:
2125                 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
2126                               fc_conf->mode);
2127                 return -1;
2128         }
2129
2130         ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
2131         if (ret)
2132                 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
2133                               ret);
2134
2135         /* Enable link */
2136         dpaa2_dev_set_link_up(dev);
2137
2138         return ret;
2139 }
2140
2141 static int
2142 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
2143                           struct rte_eth_rss_conf *rss_conf)
2144 {
2145         struct rte_eth_dev_data *data = dev->data;
2146         struct dpaa2_dev_priv *priv = data->dev_private;
2147         struct rte_eth_conf *eth_conf = &data->dev_conf;
2148         int ret, tc_index;
2149
2150         PMD_INIT_FUNC_TRACE();
2151
2152         if (rss_conf->rss_hf) {
2153                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2154                         ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf,
2155                                 tc_index);
2156                         if (ret) {
2157                                 DPAA2_PMD_ERR("Unable to set flow dist on tc%d",
2158                                         tc_index);
2159                                 return ret;
2160                         }
2161                 }
2162         } else {
2163                 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) {
2164                         ret = dpaa2_remove_flow_dist(dev, tc_index);
2165                         if (ret) {
2166                                 DPAA2_PMD_ERR(
2167                                         "Unable to remove flow dist on tc%d",
2168                                         tc_index);
2169                                 return ret;
2170                         }
2171                 }
2172         }
2173         eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
2174         return 0;
2175 }
2176
2177 static int
2178 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2179                             struct rte_eth_rss_conf *rss_conf)
2180 {
2181         struct rte_eth_dev_data *data = dev->data;
2182         struct rte_eth_conf *eth_conf = &data->dev_conf;
2183
2184         /* dpaa2 does not support rss_key, so length should be 0*/
2185         rss_conf->rss_key_len = 0;
2186         rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2187         return 0;
2188 }
2189
2190 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2191                 int eth_rx_queue_id,
2192                 struct dpaa2_dpcon_dev *dpcon,
2193                 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2194 {
2195         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2196         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2197         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2198         uint8_t flow_id = dpaa2_ethq->flow_id;
2199         struct dpni_queue cfg;
2200         uint8_t options, priority;
2201         int ret;
2202
2203         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2204                 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2205         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2206                 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2207         else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2208                 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2209         else
2210                 return -EINVAL;
2211
2212         priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2213                    (dpcon->num_priorities - 1);
2214
2215         memset(&cfg, 0, sizeof(struct dpni_queue));
2216         options = DPNI_QUEUE_OPT_DEST;
2217         cfg.destination.type = DPNI_DEST_DPCON;
2218         cfg.destination.id = dpcon->dpcon_id;
2219         cfg.destination.priority = priority;
2220
2221         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2222                 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2223                 cfg.destination.hold_active = 1;
2224         }
2225
2226         if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2227                         !eth_priv->en_ordered) {
2228                 struct opr_cfg ocfg;
2229
2230                 /* Restoration window size = 256 frames */
2231                 ocfg.oprrws = 3;
2232                 /* Restoration window size = 512 frames for LX2 */
2233                 if (dpaa2_svr_family == SVR_LX2160A)
2234                         ocfg.oprrws = 4;
2235                 /* Auto advance NESN window enabled */
2236                 ocfg.oa = 1;
2237                 /* Late arrival window size disabled */
2238                 ocfg.olws = 0;
2239                 /* ORL resource exhaustion advance NESN disabled */
2240                 ocfg.oeane = 0;
2241                 /* Loose ordering enabled */
2242                 ocfg.oloe = 1;
2243                 eth_priv->en_loose_ordered = 1;
2244                 /* Strict ordering enabled if explicitly set */
2245                 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2246                         ocfg.oloe = 0;
2247                         eth_priv->en_loose_ordered = 0;
2248                 }
2249
2250                 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2251                                    dpaa2_ethq->tc_index, flow_id,
2252                                    OPR_OPT_CREATE, &ocfg, 0);
2253                 if (ret) {
2254                         DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2255                         return ret;
2256                 }
2257
2258                 eth_priv->en_ordered = 1;
2259         }
2260
2261         options |= DPNI_QUEUE_OPT_USER_CTX;
2262         cfg.user_context = (size_t)(dpaa2_ethq);
2263
2264         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2265                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2266         if (ret) {
2267                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2268                 return ret;
2269         }
2270
2271         memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2272
2273         return 0;
2274 }
2275
2276 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2277                 int eth_rx_queue_id)
2278 {
2279         struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2280         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2281         struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2282         uint8_t flow_id = dpaa2_ethq->flow_id;
2283         struct dpni_queue cfg;
2284         uint8_t options;
2285         int ret;
2286
2287         memset(&cfg, 0, sizeof(struct dpni_queue));
2288         options = DPNI_QUEUE_OPT_DEST;
2289         cfg.destination.type = DPNI_DEST_NONE;
2290
2291         ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2292                              dpaa2_ethq->tc_index, flow_id, options, &cfg);
2293         if (ret)
2294                 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2295
2296         return ret;
2297 }
2298
2299 static int
2300 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev,
2301                        const struct rte_flow_ops **ops)
2302 {
2303         if (!dev)
2304                 return -ENODEV;
2305
2306         *ops = &dpaa2_flow_ops;
2307         return 0;
2308 }
2309
2310 static void
2311 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2312         struct rte_eth_rxq_info *qinfo)
2313 {
2314         struct dpaa2_queue *rxq;
2315         struct dpaa2_dev_priv *priv = dev->data->dev_private;
2316         struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2317         uint16_t max_frame_length;
2318
2319         rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id];
2320
2321         qinfo->mp = rxq->mb_pool;
2322         qinfo->scattered_rx = dev->data->scattered_rx;
2323         qinfo->nb_desc = rxq->nb_desc;
2324         if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
2325                                 &max_frame_length) == 0)
2326                 qinfo->rx_buf_size = max_frame_length;
2327
2328         qinfo->conf.rx_free_thresh = 1;
2329         qinfo->conf.rx_drop_en = 1;
2330         qinfo->conf.rx_deferred_start = 0;
2331         qinfo->conf.offloads = rxq->offloads;
2332 }
2333
2334 static void
2335 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2336         struct rte_eth_txq_info *qinfo)
2337 {
2338         struct dpaa2_queue *txq;
2339
2340         txq = dev->data->tx_queues[queue_id];
2341
2342         qinfo->nb_desc = txq->nb_desc;
2343         qinfo->conf.tx_thresh.pthresh = 0;
2344         qinfo->conf.tx_thresh.hthresh = 0;
2345         qinfo->conf.tx_thresh.wthresh = 0;
2346
2347         qinfo->conf.tx_free_thresh = 0;
2348         qinfo->conf.tx_rs_thresh = 0;
2349         qinfo->conf.offloads = txq->offloads;
2350         qinfo->conf.tx_deferred_start = 0;
2351 }
2352
2353 static int
2354 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops)
2355 {
2356         *(const void **)ops = &dpaa2_tm_ops;
2357
2358         return 0;
2359 }
2360
2361 void
2362 rte_pmd_dpaa2_thread_init(void)
2363 {
2364         int ret;
2365
2366         if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
2367                 ret = dpaa2_affine_qbman_swp();
2368                 if (ret) {
2369                         DPAA2_PMD_ERR(
2370                                 "Failed to allocate IO portal, tid: %d\n",
2371                                 rte_gettid());
2372                         return;
2373                 }
2374         }
2375 }
2376
2377 static struct eth_dev_ops dpaa2_ethdev_ops = {
2378         .dev_configure    = dpaa2_eth_dev_configure,
2379         .dev_start            = dpaa2_dev_start,
2380         .dev_stop             = dpaa2_dev_stop,
2381         .dev_close            = dpaa2_dev_close,
2382         .promiscuous_enable   = dpaa2_dev_promiscuous_enable,
2383         .promiscuous_disable  = dpaa2_dev_promiscuous_disable,
2384         .allmulticast_enable  = dpaa2_dev_allmulticast_enable,
2385         .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2386         .dev_set_link_up      = dpaa2_dev_set_link_up,
2387         .dev_set_link_down    = dpaa2_dev_set_link_down,
2388         .link_update       = dpaa2_dev_link_update,
2389         .stats_get             = dpaa2_dev_stats_get,
2390         .xstats_get            = dpaa2_dev_xstats_get,
2391         .xstats_get_by_id     = dpaa2_xstats_get_by_id,
2392         .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2393         .xstats_get_names      = dpaa2_xstats_get_names,
2394         .stats_reset       = dpaa2_dev_stats_reset,
2395         .xstats_reset         = dpaa2_dev_stats_reset,
2396         .fw_version_get    = dpaa2_fw_version_get,
2397         .dev_infos_get     = dpaa2_dev_info_get,
2398         .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2399         .mtu_set           = dpaa2_dev_mtu_set,
2400         .vlan_filter_set      = dpaa2_vlan_filter_set,
2401         .vlan_offload_set     = dpaa2_vlan_offload_set,
2402         .vlan_tpid_set        = dpaa2_vlan_tpid_set,
2403         .rx_queue_setup    = dpaa2_dev_rx_queue_setup,
2404         .rx_queue_release  = dpaa2_dev_rx_queue_release,
2405         .tx_queue_setup    = dpaa2_dev_tx_queue_setup,
2406         .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get,
2407         .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get,
2408         .flow_ctrl_get        = dpaa2_flow_ctrl_get,
2409         .flow_ctrl_set        = dpaa2_flow_ctrl_set,
2410         .mac_addr_add         = dpaa2_dev_add_mac_addr,
2411         .mac_addr_remove      = dpaa2_dev_remove_mac_addr,
2412         .mac_addr_set         = dpaa2_dev_set_mac_addr,
2413         .rss_hash_update      = dpaa2_dev_rss_hash_update,
2414         .rss_hash_conf_get    = dpaa2_dev_rss_hash_conf_get,
2415         .flow_ops_get         = dpaa2_dev_flow_ops_get,
2416         .rxq_info_get         = dpaa2_rxq_info_get,
2417         .txq_info_get         = dpaa2_txq_info_get,
2418         .tm_ops_get           = dpaa2_tm_ops_get,
2419 #if defined(RTE_LIBRTE_IEEE1588)
2420         .timesync_enable      = dpaa2_timesync_enable,
2421         .timesync_disable     = dpaa2_timesync_disable,
2422         .timesync_read_time   = dpaa2_timesync_read_time,
2423         .timesync_write_time  = dpaa2_timesync_write_time,
2424         .timesync_adjust_time = dpaa2_timesync_adjust_time,
2425         .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2426         .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2427 #endif
2428 };
2429
2430 /* Populate the mac address from physically available (u-boot/firmware) and/or
2431  * one set by higher layers like MC (restool) etc.
2432  * Returns the table of MAC entries (multiple entries)
2433  */
2434 static int
2435 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2436                   struct rte_ether_addr *mac_entry)
2437 {
2438         int ret;
2439         struct rte_ether_addr phy_mac, prime_mac;
2440
2441         memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2442         memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2443
2444         /* Get the physical device MAC address */
2445         ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2446                                      phy_mac.addr_bytes);
2447         if (ret) {
2448                 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2449                 goto cleanup;
2450         }
2451
2452         ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2453                                         prime_mac.addr_bytes);
2454         if (ret) {
2455                 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2456                 goto cleanup;
2457         }
2458
2459         /* Now that both MAC have been obtained, do:
2460          *  if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2461          *     and return phy
2462          *  If empty_mac(phy), return prime.
2463          *  if both are empty, create random MAC, set as prime and return
2464          */
2465         if (!rte_is_zero_ether_addr(&phy_mac)) {
2466                 /* If the addresses are not same, overwrite prime */
2467                 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2468                         ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2469                                                         priv->token,
2470                                                         phy_mac.addr_bytes);
2471                         if (ret) {
2472                                 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2473                                               ret);
2474                                 goto cleanup;
2475                         }
2476                         memcpy(&prime_mac, &phy_mac,
2477                                 sizeof(struct rte_ether_addr));
2478                 }
2479         } else if (rte_is_zero_ether_addr(&prime_mac)) {
2480                 /* In case phys and prime, both are zero, create random MAC */
2481                 rte_eth_random_addr(prime_mac.addr_bytes);
2482                 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2483                                                 priv->token,
2484                                                 prime_mac.addr_bytes);
2485                 if (ret) {
2486                         DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2487                         goto cleanup;
2488                 }
2489         }
2490
2491         /* prime_mac the final MAC address */
2492         memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2493         return 0;
2494
2495 cleanup:
2496         return -1;
2497 }
2498
2499 static int
2500 check_devargs_handler(__rte_unused const char *key, const char *value,
2501                       __rte_unused void *opaque)
2502 {
2503         if (strcmp(value, "1"))
2504                 return -1;
2505
2506         return 0;
2507 }
2508
2509 static int
2510 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2511 {
2512         struct rte_kvargs *kvlist;
2513
2514         if (!devargs)
2515                 return 0;
2516
2517         kvlist = rte_kvargs_parse(devargs->args, NULL);
2518         if (!kvlist)
2519                 return 0;
2520
2521         if (!rte_kvargs_count(kvlist, key)) {
2522                 rte_kvargs_free(kvlist);
2523                 return 0;
2524         }
2525
2526         if (rte_kvargs_process(kvlist, key,
2527                                check_devargs_handler, NULL) < 0) {
2528                 rte_kvargs_free(kvlist);
2529                 return 0;
2530         }
2531         rte_kvargs_free(kvlist);
2532
2533         return 1;
2534 }
2535
2536 static int
2537 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2538 {
2539         struct rte_device *dev = eth_dev->device;
2540         struct rte_dpaa2_device *dpaa2_dev;
2541         struct fsl_mc_io *dpni_dev;
2542         struct dpni_attr attr;
2543         struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2544         struct dpni_buffer_layout layout;
2545         int ret, hw_id, i;
2546
2547         PMD_INIT_FUNC_TRACE();
2548
2549         dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2550         if (!dpni_dev) {
2551                 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2552                 return -1;
2553         }
2554         dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX);
2555         eth_dev->process_private = (void *)dpni_dev;
2556
2557         /* For secondary processes, the primary has done all the work */
2558         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2559                 /* In case of secondary, only burst and ops API need to be
2560                  * plugged.
2561                  */
2562                 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2563                 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count;
2564                 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2565                         eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2566                 else if (dpaa2_get_devargs(dev->devargs,
2567                                         DRIVER_NO_PREFETCH_MODE))
2568                         eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2569                 else
2570                         eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2571                 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2572                 return 0;
2573         }
2574
2575         dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2576
2577         hw_id = dpaa2_dev->object_id;
2578         ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2579         if (ret) {
2580                 DPAA2_PMD_ERR(
2581                              "Failure in opening dpni@%d with err code %d",
2582                              hw_id, ret);
2583                 rte_free(dpni_dev);
2584                 return -1;
2585         }
2586
2587         /* Clean the device first */
2588         ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2589         if (ret) {
2590                 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2591                               hw_id, ret);
2592                 goto init_err;
2593         }
2594
2595         ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2596         if (ret) {
2597                 DPAA2_PMD_ERR(
2598                              "Failure in get dpni@%d attribute, err code %d",
2599                              hw_id, ret);
2600                 goto init_err;
2601         }
2602
2603         priv->num_rx_tc = attr.num_rx_tcs;
2604         priv->qos_entries = attr.qos_entries;
2605         priv->fs_entries = attr.fs_entries;
2606         priv->dist_queues = attr.num_queues;
2607
2608         /* only if the custom CG is enabled */
2609         if (attr.options & DPNI_OPT_CUSTOM_CG)
2610                 priv->max_cgs = attr.num_cgs;
2611         else
2612                 priv->max_cgs = 0;
2613
2614         for (i = 0; i < priv->max_cgs; i++)
2615                 priv->cgid_in_use[i] = 0;
2616
2617         for (i = 0; i < attr.num_rx_tcs; i++)
2618                 priv->nb_rx_queues += attr.num_queues;
2619
2620         /* Using number of TX queues as number of TX TCs */
2621         priv->nb_tx_queues = attr.num_tx_tcs;
2622
2623         DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2624                         priv->num_rx_tc, priv->nb_rx_queues,
2625                         priv->nb_tx_queues, priv->max_cgs);
2626
2627         priv->hw = dpni_dev;
2628         priv->hw_id = hw_id;
2629         priv->options = attr.options;
2630         priv->max_mac_filters = attr.mac_filter_entries;
2631         priv->max_vlan_filters = attr.vlan_filter_entries;
2632         priv->flags = 0;
2633 #if defined(RTE_LIBRTE_IEEE1588)
2634         printf("DPDK IEEE1588 is enabled\n");
2635         priv->flags |= DPAA2_TX_CONF_ENABLE;
2636 #endif
2637         /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */
2638         if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) {
2639                 priv->flags |= DPAA2_TX_CONF_ENABLE;
2640                 DPAA2_PMD_INFO("TX_CONF Enabled");
2641         }
2642
2643         if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) {
2644                 dpaa2_enable_err_queue = 1;
2645                 DPAA2_PMD_INFO("Enable error queue");
2646         }
2647
2648         /* Allocate memory for hardware structure for queues */
2649         ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2650         if (ret) {
2651                 DPAA2_PMD_ERR("Queue allocation Failed");
2652                 goto init_err;
2653         }
2654
2655         /* Allocate memory for storing MAC addresses.
2656          * Table of mac_filter_entries size is allocated so that RTE ether lib
2657          * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2658          */
2659         eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2660                 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2661         if (eth_dev->data->mac_addrs == NULL) {
2662                 DPAA2_PMD_ERR(
2663                    "Failed to allocate %d bytes needed to store MAC addresses",
2664                    RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2665                 ret = -ENOMEM;
2666                 goto init_err;
2667         }
2668
2669         ret = populate_mac_addr(dpni_dev, priv, &eth_dev->data->mac_addrs[0]);
2670         if (ret) {
2671                 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2672                 rte_free(eth_dev->data->mac_addrs);
2673                 eth_dev->data->mac_addrs = NULL;
2674                 goto init_err;
2675         }
2676
2677         /* ... tx buffer layout ... */
2678         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2679         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2680                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2681                                  DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2682                 layout.pass_timestamp = true;
2683         } else {
2684                 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2685         }
2686         layout.pass_frame_status = 1;
2687         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2688                                      DPNI_QUEUE_TX, &layout);
2689         if (ret) {
2690                 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2691                 goto init_err;
2692         }
2693
2694         /* ... tx-conf and error buffer layout ... */
2695         memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2696         if (priv->flags & DPAA2_TX_CONF_ENABLE) {
2697                 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2698                 layout.pass_timestamp = true;
2699         }
2700         layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2701         layout.pass_frame_status = 1;
2702         ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2703                                      DPNI_QUEUE_TX_CONFIRM, &layout);
2704         if (ret) {
2705                 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2706                              ret);
2707                 goto init_err;
2708         }
2709
2710         eth_dev->dev_ops = &dpaa2_ethdev_ops;
2711
2712         if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2713                 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2714                 DPAA2_PMD_INFO("Loopback mode");
2715         } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2716                 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2717                 DPAA2_PMD_INFO("No Prefetch mode");
2718         } else {
2719                 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2720         }
2721         eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2722
2723         /* Init fields w.r.t. classification */
2724         memset(&priv->extract.qos_key_extract, 0,
2725                 sizeof(struct dpaa2_key_extract));
2726         priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2727         if (!priv->extract.qos_extract_param) {
2728                 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2729                             " classification ", ret);
2730                 goto init_err;
2731         }
2732         priv->extract.qos_key_extract.key_info.ipv4_src_offset =
2733                 IP_ADDRESS_OFFSET_INVALID;
2734         priv->extract.qos_key_extract.key_info.ipv4_dst_offset =
2735                 IP_ADDRESS_OFFSET_INVALID;
2736         priv->extract.qos_key_extract.key_info.ipv6_src_offset =
2737                 IP_ADDRESS_OFFSET_INVALID;
2738         priv->extract.qos_key_extract.key_info.ipv6_dst_offset =
2739                 IP_ADDRESS_OFFSET_INVALID;
2740
2741         for (i = 0; i < MAX_TCS; i++) {
2742                 memset(&priv->extract.tc_key_extract[i], 0,
2743                         sizeof(struct dpaa2_key_extract));
2744                 priv->extract.tc_extract_param[i] =
2745                         (size_t)rte_malloc(NULL, 256, 64);
2746                 if (!priv->extract.tc_extract_param[i]) {
2747                         DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classification",
2748                                      ret);
2749                         goto init_err;
2750                 }
2751                 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset =
2752                         IP_ADDRESS_OFFSET_INVALID;
2753                 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset =
2754                         IP_ADDRESS_OFFSET_INVALID;
2755                 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset =
2756                         IP_ADDRESS_OFFSET_INVALID;
2757                 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset =
2758                         IP_ADDRESS_OFFSET_INVALID;
2759         }
2760
2761         ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2762                                         RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2763                                         + VLAN_TAG_SIZE);
2764         if (ret) {
2765                 DPAA2_PMD_ERR("Unable to set mtu. check config");
2766                 goto init_err;
2767         }
2768
2769         /*TODO To enable soft parser support DPAA2 driver needs to integrate
2770          * with external entity to receive byte code for software sequence
2771          * and same will be offload to the H/W using MC interface.
2772          * Currently it is assumed that DPAA2 driver has byte code by some
2773          * mean and same if offloaded to H/W.
2774          */
2775         if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2776                 WRIOP_SS_INITIALIZER(priv);
2777                 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2778                 if (ret < 0) {
2779                         DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2780                                       ret);
2781                         return ret;
2782                 }
2783
2784                 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2785                                                          DPNI_SS_INGRESS);
2786                 if (ret < 0) {
2787                         DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2788                                       ret);
2789                         return ret;
2790                 }
2791         }
2792         RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2793         return 0;
2794 init_err:
2795         dpaa2_dev_close(eth_dev);
2796
2797         return ret;
2798 }
2799
2800 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev)
2801 {
2802         return dev->device->driver == &rte_dpaa2_pmd.driver;
2803 }
2804
2805 static int
2806 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2807                 struct rte_dpaa2_device *dpaa2_dev)
2808 {
2809         struct rte_eth_dev *eth_dev;
2810         struct dpaa2_dev_priv *dev_priv;
2811         int diag;
2812
2813         if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2814                 RTE_PKTMBUF_HEADROOM) {
2815                 DPAA2_PMD_ERR(
2816                 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2817                 RTE_PKTMBUF_HEADROOM,
2818                 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2819
2820                 return -1;
2821         }
2822
2823         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2824                 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2825                 if (!eth_dev)
2826                         return -ENODEV;
2827                 dev_priv = rte_zmalloc("ethdev private structure",
2828                                        sizeof(struct dpaa2_dev_priv),
2829                                        RTE_CACHE_LINE_SIZE);
2830                 if (dev_priv == NULL) {
2831                         DPAA2_PMD_CRIT(
2832                                 "Unable to allocate memory for private data");
2833                         rte_eth_dev_release_port(eth_dev);
2834                         return -ENOMEM;
2835                 }
2836                 eth_dev->data->dev_private = (void *)dev_priv;
2837                 /* Store a pointer to eth_dev in dev_private */
2838                 dev_priv->eth_dev = eth_dev;
2839         } else {
2840                 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2841                 if (!eth_dev) {
2842                         DPAA2_PMD_DEBUG("returning enodev");
2843                         return -ENODEV;
2844                 }
2845         }
2846
2847         eth_dev->device = &dpaa2_dev->device;
2848
2849         dpaa2_dev->eth_dev = eth_dev;
2850         eth_dev->data->rx_mbuf_alloc_failed = 0;
2851
2852         if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2853                 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2854
2855         eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2856
2857         /* Invoke PMD device initialization function */
2858         diag = dpaa2_dev_init(eth_dev);
2859         if (diag == 0) {
2860                 rte_eth_dev_probing_finish(eth_dev);
2861                 return 0;
2862         }
2863
2864         rte_eth_dev_release_port(eth_dev);
2865         return diag;
2866 }
2867
2868 static int
2869 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2870 {
2871         struct rte_eth_dev *eth_dev;
2872         int ret;
2873
2874         eth_dev = dpaa2_dev->eth_dev;
2875         dpaa2_dev_close(eth_dev);
2876         ret = rte_eth_dev_release_port(eth_dev);
2877
2878         return ret;
2879 }
2880
2881 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2882         .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2883         .drv_type = DPAA2_ETH,
2884         .probe = rte_dpaa2_probe,
2885         .remove = rte_dpaa2_remove,
2886 };
2887
2888 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd);
2889 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME,
2890                 DRIVER_LOOPBACK_MODE "=<int> "
2891                 DRIVER_NO_PREFETCH_MODE "=<int>"
2892                 DRIVER_TX_CONF "=<int>"
2893                 DRIVER_ERROR_QUEUE "=<int>");
2894 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE);