1 /* * SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
12 #include <rte_ethdev_driver.h>
13 #include <rte_malloc.h>
14 #include <rte_memcpy.h>
15 #include <rte_string_fns.h>
16 #include <rte_cycles.h>
17 #include <rte_kvargs.h>
19 #include <rte_fslmc.h>
20 #include <rte_flow_driver.h>
22 #include "dpaa2_pmd_logs.h"
23 #include <fslmc_vfio.h>
24 #include <dpaa2_hw_pvt.h>
25 #include <dpaa2_hw_mempool.h>
26 #include <dpaa2_hw_dpio.h>
27 #include <mc/fsl_dpmng.h>
28 #include "dpaa2_ethdev.h"
29 #include "dpaa2_sparser.h"
30 #include <fsl_qbman_debug.h>
32 #define DRIVER_LOOPBACK_MODE "drv_loopback"
33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch"
35 /* Supported Rx offloads */
36 static uint64_t dev_rx_offloads_sup =
37 DEV_RX_OFFLOAD_CHECKSUM |
38 DEV_RX_OFFLOAD_SCTP_CKSUM |
39 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
40 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM |
41 DEV_RX_OFFLOAD_VLAN_STRIP |
42 DEV_RX_OFFLOAD_VLAN_FILTER |
43 DEV_RX_OFFLOAD_JUMBO_FRAME |
44 DEV_RX_OFFLOAD_TIMESTAMP;
46 /* Rx offloads which cannot be disabled */
47 static uint64_t dev_rx_offloads_nodis =
48 DEV_RX_OFFLOAD_RSS_HASH |
49 DEV_RX_OFFLOAD_SCATTER;
51 /* Supported Tx offloads */
52 static uint64_t dev_tx_offloads_sup =
53 DEV_TX_OFFLOAD_VLAN_INSERT |
54 DEV_TX_OFFLOAD_IPV4_CKSUM |
55 DEV_TX_OFFLOAD_UDP_CKSUM |
56 DEV_TX_OFFLOAD_TCP_CKSUM |
57 DEV_TX_OFFLOAD_SCTP_CKSUM |
58 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
59 DEV_TX_OFFLOAD_MT_LOCKFREE |
60 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
62 /* Tx offloads which cannot be disabled */
63 static uint64_t dev_tx_offloads_nodis =
64 DEV_TX_OFFLOAD_MULTI_SEGS;
66 /* enable timestamp in mbuf */
67 enum pmd_dpaa2_ts dpaa2_enable_ts;
69 struct rte_dpaa2_xstats_name_off {
70 char name[RTE_ETH_XSTATS_NAME_SIZE];
71 uint8_t page_id; /* dpni statistics page id */
72 uint8_t stats_id; /* stats id in the given page */
75 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = {
76 {"ingress_multicast_frames", 0, 2},
77 {"ingress_multicast_bytes", 0, 3},
78 {"ingress_broadcast_frames", 0, 4},
79 {"ingress_broadcast_bytes", 0, 5},
80 {"egress_multicast_frames", 1, 2},
81 {"egress_multicast_bytes", 1, 3},
82 {"egress_broadcast_frames", 1, 4},
83 {"egress_broadcast_bytes", 1, 5},
84 {"ingress_filtered_frames", 2, 0},
85 {"ingress_discarded_frames", 2, 1},
86 {"ingress_nobuffer_discards", 2, 2},
87 {"egress_discarded_frames", 2, 3},
88 {"egress_confirmed_frames", 2, 4},
89 {"cgr_reject_frames", 4, 0},
90 {"cgr_reject_bytes", 4, 1},
93 static const enum rte_filter_op dpaa2_supported_filter_ops[] = {
95 RTE_ETH_FILTER_DELETE,
96 RTE_ETH_FILTER_UPDATE,
101 static struct rte_dpaa2_driver rte_dpaa2_pmd;
102 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev);
103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev,
104 int wait_to_complete);
105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev);
106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev);
107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
109 int dpaa2_logtype_pmd;
112 rte_pmd_dpaa2_set_timestamp(enum pmd_dpaa2_ts enable)
114 dpaa2_enable_ts = enable;
118 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
121 struct dpaa2_dev_priv *priv = dev->data->dev_private;
122 struct fsl_mc_io *dpni = dev->process_private;
124 PMD_INIT_FUNC_TRACE();
127 DPAA2_PMD_ERR("dpni is NULL");
132 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token,
135 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW,
136 priv->token, vlan_id);
139 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d",
140 ret, vlan_id, priv->hw_id);
146 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask)
148 struct dpaa2_dev_priv *priv = dev->data->dev_private;
149 struct fsl_mc_io *dpni = dev->process_private;
152 PMD_INIT_FUNC_TRACE();
154 if (mask & ETH_VLAN_FILTER_MASK) {
155 /* VLAN Filter not avaialble */
156 if (!priv->max_vlan_filters) {
157 DPAA2_PMD_INFO("VLAN filter not available");
161 if (dev->data->dev_conf.rxmode.offloads &
162 DEV_RX_OFFLOAD_VLAN_FILTER)
163 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
166 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW,
169 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret);
172 if (mask & ETH_VLAN_EXTEND_MASK) {
173 if (dev->data->dev_conf.rxmode.offloads &
174 DEV_RX_OFFLOAD_VLAN_EXTEND)
175 DPAA2_PMD_INFO("VLAN extend offload not supported");
182 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev,
183 enum rte_vlan_type vlan_type __rte_unused,
186 struct dpaa2_dev_priv *priv = dev->data->dev_private;
187 struct fsl_mc_io *dpni = dev->process_private;
190 PMD_INIT_FUNC_TRACE();
192 /* nothing to be done for standard vlan tpids */
193 if (tpid == 0x8100 || tpid == 0x88A8)
196 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
199 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret);
200 /* if already configured tpids, remove them first */
202 struct dpni_custom_tpid_cfg tpid_list = {0};
204 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW,
205 priv->token, &tpid_list);
208 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW,
209 priv->token, tpid_list.tpid1);
212 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW,
220 dpaa2_fw_version_get(struct rte_eth_dev *dev,
225 struct fsl_mc_io *dpni = dev->process_private;
226 struct mc_soc_version mc_plat_info = {0};
227 struct mc_version mc_ver_info = {0};
229 PMD_INIT_FUNC_TRACE();
231 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info))
232 DPAA2_PMD_WARN("\tmc_get_soc_version failed");
234 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info))
235 DPAA2_PMD_WARN("\tmc_get_version failed");
237 ret = snprintf(fw_version, fw_size,
242 mc_ver_info.revision);
244 ret += 1; /* add the size of '\0' */
245 if (fw_size < (uint32_t)ret)
252 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
254 struct dpaa2_dev_priv *priv = dev->data->dev_private;
256 PMD_INIT_FUNC_TRACE();
258 dev_info->if_index = priv->hw_id;
260 dev_info->max_mac_addrs = priv->max_mac_filters;
261 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN;
262 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE;
263 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues;
264 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues;
265 dev_info->rx_offload_capa = dev_rx_offloads_sup |
266 dev_rx_offloads_nodis;
267 dev_info->tx_offload_capa = dev_tx_offloads_sup |
268 dev_tx_offloads_nodis;
269 dev_info->speed_capa = ETH_LINK_SPEED_1G |
270 ETH_LINK_SPEED_2_5G |
273 dev_info->max_hash_mac_addrs = 0;
274 dev_info->max_vfs = 0;
275 dev_info->max_vmdq_pools = ETH_16_POOLS;
276 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL;
282 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev)
284 struct dpaa2_dev_priv *priv = dev->data->dev_private;
287 uint8_t num_rxqueue_per_tc;
288 struct dpaa2_queue *mc_q, *mcq;
291 struct dpaa2_queue *dpaa2_q;
293 PMD_INIT_FUNC_TRACE();
295 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc);
296 if (priv->tx_conf_en)
297 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues;
299 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues;
300 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues,
301 RTE_CACHE_LINE_SIZE);
303 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues");
307 for (i = 0; i < priv->nb_rx_queues; i++) {
308 mc_q->eth_data = dev->data;
309 priv->rx_vq[i] = mc_q++;
310 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
311 dpaa2_q->q_storage = rte_malloc("dq_storage",
312 sizeof(struct queue_storage_info_t),
313 RTE_CACHE_LINE_SIZE);
314 if (!dpaa2_q->q_storage)
317 memset(dpaa2_q->q_storage, 0,
318 sizeof(struct queue_storage_info_t));
319 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
323 for (i = 0; i < priv->nb_tx_queues; i++) {
324 mc_q->eth_data = dev->data;
325 mc_q->flow_id = 0xffff;
326 priv->tx_vq[i] = mc_q++;
327 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
328 dpaa2_q->cscn = rte_malloc(NULL,
329 sizeof(struct qbman_result), 16);
334 if (priv->tx_conf_en) {
335 /*Setup tx confirmation queues*/
336 for (i = 0; i < priv->nb_tx_queues; i++) {
337 mc_q->eth_data = dev->data;
340 priv->tx_conf_vq[i] = mc_q++;
341 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
343 rte_malloc("dq_storage",
344 sizeof(struct queue_storage_info_t),
345 RTE_CACHE_LINE_SIZE);
346 if (!dpaa2_q->q_storage)
349 memset(dpaa2_q->q_storage, 0,
350 sizeof(struct queue_storage_info_t));
351 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage))
357 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) {
358 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id];
359 mcq->tc_index = dist_idx / num_rxqueue_per_tc;
360 mcq->flow_id = dist_idx % num_rxqueue_per_tc;
368 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i];
369 rte_free(dpaa2_q->q_storage);
370 priv->tx_conf_vq[i--] = NULL;
372 i = priv->nb_tx_queues;
376 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
377 rte_free(dpaa2_q->cscn);
378 priv->tx_vq[i--] = NULL;
380 i = priv->nb_rx_queues;
383 mc_q = priv->rx_vq[0];
385 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
386 dpaa2_free_dq_storage(dpaa2_q->q_storage);
387 rte_free(dpaa2_q->q_storage);
388 priv->rx_vq[i--] = NULL;
395 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev)
397 struct dpaa2_dev_priv *priv = dev->data->dev_private;
398 struct dpaa2_queue *dpaa2_q;
401 PMD_INIT_FUNC_TRACE();
403 /* Queue allocation base */
404 if (priv->rx_vq[0]) {
405 /* cleaning up queue storage */
406 for (i = 0; i < priv->nb_rx_queues; i++) {
407 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
408 if (dpaa2_q->q_storage)
409 rte_free(dpaa2_q->q_storage);
411 /* cleanup tx queue cscn */
412 for (i = 0; i < priv->nb_tx_queues; i++) {
413 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
414 rte_free(dpaa2_q->cscn);
416 if (priv->tx_conf_en) {
417 /* cleanup tx conf queue storage */
418 for (i = 0; i < priv->nb_tx_queues; i++) {
419 dpaa2_q = (struct dpaa2_queue *)
421 rte_free(dpaa2_q->q_storage);
424 /*free memory for all queues (RX+TX) */
425 rte_free(priv->rx_vq[0]);
426 priv->rx_vq[0] = NULL;
431 dpaa2_eth_dev_configure(struct rte_eth_dev *dev)
433 struct dpaa2_dev_priv *priv = dev->data->dev_private;
434 struct fsl_mc_io *dpni = dev->process_private;
435 struct rte_eth_conf *eth_conf = &dev->data->dev_conf;
436 uint64_t rx_offloads = eth_conf->rxmode.offloads;
437 uint64_t tx_offloads = eth_conf->txmode.offloads;
438 int rx_l3_csum_offload = false;
439 int rx_l4_csum_offload = false;
440 int tx_l3_csum_offload = false;
441 int tx_l4_csum_offload = false;
444 PMD_INIT_FUNC_TRACE();
446 /* Rx offloads which are enabled by default */
447 if (dev_rx_offloads_nodis & ~rx_offloads) {
449 "Some of rx offloads enabled by default - requested 0x%" PRIx64
450 " fixed are 0x%" PRIx64,
451 rx_offloads, dev_rx_offloads_nodis);
454 /* Tx offloads which are enabled by default */
455 if (dev_tx_offloads_nodis & ~tx_offloads) {
457 "Some of tx offloads enabled by default - requested 0x%" PRIx64
458 " fixed are 0x%" PRIx64,
459 tx_offloads, dev_tx_offloads_nodis);
462 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
463 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) {
464 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW,
465 priv->token, eth_conf->rxmode.max_rx_pkt_len
466 - RTE_ETHER_CRC_LEN);
469 "Unable to set mtu. check config");
473 dev->data->dev_conf.rxmode.max_rx_pkt_len -
474 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN -
481 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) {
482 ret = dpaa2_setup_flow_dist(dev,
483 eth_conf->rx_adv_conf.rss_conf.rss_hf);
485 DPAA2_PMD_ERR("Unable to set flow distribution."
486 "Check queue config");
491 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM)
492 rx_l3_csum_offload = true;
494 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) ||
495 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) ||
496 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM))
497 rx_l4_csum_offload = true;
499 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
500 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload);
502 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret);
506 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
507 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload);
509 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret);
513 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP)
514 dpaa2_enable_ts = true;
516 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)
517 tx_l3_csum_offload = true;
519 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) ||
520 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) ||
521 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM))
522 tx_l4_csum_offload = true;
524 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
525 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload);
527 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret);
531 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
532 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload);
534 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret);
538 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in
539 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC]
540 * to 0 for LS2 in the hardware thus disabling data/annotation
541 * stashing. For LX2 this is fixed in hardware and thus hash result and
542 * parse results can be received in FD using this option.
544 if (dpaa2_svr_family == SVR_LX2160A) {
545 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token,
546 DPNI_FLCTYPE_HASH, true);
548 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret);
553 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
554 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK);
556 /* update the current status */
557 dpaa2_dev_link_update(dev, 0);
562 /* Function to setup RX flow information. It contains traffic class ID,
563 * flow ID, destination configuration etc.
566 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev,
567 uint16_t rx_queue_id,
569 unsigned int socket_id __rte_unused,
570 const struct rte_eth_rxconf *rx_conf __rte_unused,
571 struct rte_mempool *mb_pool)
573 struct dpaa2_dev_priv *priv = dev->data->dev_private;
574 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
575 struct dpaa2_queue *dpaa2_q;
576 struct dpni_queue cfg;
582 PMD_INIT_FUNC_TRACE();
584 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p",
585 dev, rx_queue_id, mb_pool, rx_conf);
587 if (!priv->bp_list || priv->bp_list->mp != mb_pool) {
588 bpid = mempool_to_bpid(mb_pool);
589 ret = dpaa2_attach_bp_list(priv,
590 rte_dpaa2_bpid_info[bpid].bp_list);
594 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
595 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */
596 dpaa2_q->bp_array = rte_dpaa2_bpid_info;
598 /*Get the flow id from given VQ id*/
599 flow_id = dpaa2_q->flow_id;
600 memset(&cfg, 0, sizeof(struct dpni_queue));
602 options = options | DPNI_QUEUE_OPT_USER_CTX;
603 cfg.user_context = (size_t)(dpaa2_q);
605 /* check if a private cgr available. */
606 for (i = 0; i < priv->max_cgs; i++) {
607 if (!priv->cgid_in_use[i]) {
608 priv->cgid_in_use[i] = 1;
613 if (i < priv->max_cgs) {
614 options |= DPNI_QUEUE_OPT_SET_CGID;
616 dpaa2_q->cgid = cfg.cgid;
618 dpaa2_q->cgid = 0xff;
621 /*if ls2088 or rev2 device, enable the stashing */
623 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) {
624 options |= DPNI_QUEUE_OPT_FLC;
625 cfg.flc.stash_control = true;
626 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0;
627 /* 00 00 00 - last 6 bit represent annotation, context stashing,
628 * data stashing setting 01 01 00 (0x14)
629 * (in following order ->DS AS CS)
630 * to enable 1 line data, 1 line annotation.
631 * For LX2, this setting should be 01 00 00 (0x10)
633 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A)
634 cfg.flc.value |= 0x10;
636 cfg.flc.value |= 0x14;
638 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX,
639 dpaa2_q->tc_index, flow_id, options, &cfg);
641 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret);
645 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) {
646 struct dpni_taildrop taildrop;
650 /* Private CGR will use tail drop length as nb_rx_desc.
651 * for rest cases we can use standard byte based tail drop.
652 * There is no HW restriction, but number of CGRs are limited,
653 * hence this restriction is placed.
655 if (dpaa2_q->cgid != 0xff) {
656 /*enabling per rx queue congestion control */
657 taildrop.threshold = nb_rx_desc;
658 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES;
660 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d",
662 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
663 DPNI_CP_CONGESTION_GROUP,
668 /*enabling per rx queue congestion control */
669 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q;
670 taildrop.units = DPNI_CONGESTION_UNIT_BYTES;
671 taildrop.oal = CONG_RX_OAL;
672 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d",
674 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
675 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
676 dpaa2_q->tc_index, flow_id,
680 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
684 } else { /* Disable tail Drop */
685 struct dpni_taildrop taildrop = {0};
686 DPAA2_PMD_INFO("Tail drop is disabled on queue");
689 if (dpaa2_q->cgid != 0xff) {
690 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
691 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX,
695 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token,
696 DPNI_CP_QUEUE, DPNI_QUEUE_RX,
697 dpaa2_q->tc_index, flow_id, &taildrop);
700 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)",
706 dev->data->rx_queues[rx_queue_id] = dpaa2_q;
711 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev,
712 uint16_t tx_queue_id,
713 uint16_t nb_tx_desc __rte_unused,
714 unsigned int socket_id __rte_unused,
715 const struct rte_eth_txconf *tx_conf __rte_unused)
717 struct dpaa2_dev_priv *priv = dev->data->dev_private;
718 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)
719 priv->tx_vq[tx_queue_id];
720 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *)
721 priv->tx_conf_vq[tx_queue_id];
722 struct fsl_mc_io *dpni = dev->process_private;
723 struct dpni_queue tx_conf_cfg;
724 struct dpni_queue tx_flow_cfg;
725 uint8_t options = 0, flow_id;
726 struct dpni_queue_id qid;
730 PMD_INIT_FUNC_TRACE();
732 /* Return if queue already configured */
733 if (dpaa2_q->flow_id != 0xffff) {
734 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
738 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue));
739 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue));
744 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX,
745 tc_id, flow_id, options, &tx_flow_cfg);
747 DPAA2_PMD_ERR("Error in setting the tx flow: "
748 "tc_id=%d, flow=%d err=%d",
749 tc_id, flow_id, ret);
753 dpaa2_q->flow_id = flow_id;
755 if (tx_queue_id == 0) {
756 /*Set tx-conf and error configuration*/
757 if (priv->tx_conf_en)
758 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
762 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW,
766 DPAA2_PMD_ERR("Error in set tx conf mode settings: "
771 dpaa2_q->tc_index = tc_id;
773 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
774 DPNI_QUEUE_TX, dpaa2_q->tc_index,
775 dpaa2_q->flow_id, &tx_flow_cfg, &qid);
777 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
780 dpaa2_q->fqid = qid.fqid;
782 if (!(priv->flags & DPAA2_TX_CGR_OFF)) {
783 struct dpni_congestion_notification_cfg cong_notif_cfg = {0};
785 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES;
786 cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD;
787 /* Notify that the queue is not congested when the data in
788 * the queue is below this thershold.
790 cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD;
791 cong_notif_cfg.message_ctx = 0;
792 cong_notif_cfg.message_iova =
793 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn);
794 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE;
795 cong_notif_cfg.notification_mode =
796 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER |
797 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT |
798 DPNI_CONG_OPT_COHERENT_WRITE;
799 cong_notif_cfg.cg_point = DPNI_CP_QUEUE;
801 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW,
808 "Error in setting tx congestion notification: "
813 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf;
814 dev->data->tx_queues[tx_queue_id] = dpaa2_q;
816 if (priv->tx_conf_en) {
817 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q;
818 options = options | DPNI_QUEUE_OPT_USER_CTX;
819 tx_conf_cfg.user_context = (size_t)(dpaa2_q);
820 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
821 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
822 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg);
824 DPAA2_PMD_ERR("Error in setting the tx conf flow: "
825 "tc_index=%d, flow=%d err=%d",
826 dpaa2_tx_conf_q->tc_index,
827 dpaa2_tx_conf_q->flow_id, ret);
831 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
832 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index,
833 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid);
835 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret);
838 dpaa2_tx_conf_q->fqid = qid.fqid;
844 dpaa2_dev_rx_queue_release(void *q __rte_unused)
846 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q;
847 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private;
848 struct fsl_mc_io *dpni =
849 (struct fsl_mc_io *)priv->eth_dev->process_private;
852 struct dpni_queue cfg;
854 memset(&cfg, 0, sizeof(struct dpni_queue));
855 PMD_INIT_FUNC_TRACE();
856 if (dpaa2_q->cgid != 0xff) {
857 options = DPNI_QUEUE_OPT_CLEAR_CGID;
858 cfg.cgid = dpaa2_q->cgid;
860 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token,
862 dpaa2_q->tc_index, dpaa2_q->flow_id,
865 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d",
867 priv->cgid_in_use[dpaa2_q->cgid] = 0;
868 dpaa2_q->cgid = 0xff;
873 dpaa2_dev_tx_queue_release(void *q __rte_unused)
875 PMD_INIT_FUNC_TRACE();
879 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
882 struct dpaa2_dev_priv *priv = dev->data->dev_private;
883 struct dpaa2_queue *dpaa2_q;
884 struct qbman_swp *swp;
885 struct qbman_fq_query_np_rslt state;
886 uint32_t frame_cnt = 0;
888 PMD_INIT_FUNC_TRACE();
890 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
891 ret = dpaa2_affine_qbman_swp();
893 DPAA2_PMD_ERR("Failure in affining portal");
897 swp = DPAA2_PER_LCORE_PORTAL;
899 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id];
901 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) {
902 frame_cnt = qbman_fq_state_frame_count(&state);
903 DPAA2_PMD_DEBUG("RX frame count for q(%d) is %u",
904 rx_queue_id, frame_cnt);
909 static const uint32_t *
910 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev)
912 static const uint32_t ptypes[] = {
913 /*todo -= add more types */
916 RTE_PTYPE_L3_IPV4_EXT,
918 RTE_PTYPE_L3_IPV6_EXT,
926 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx ||
927 dev->rx_pkt_burst == dpaa2_dev_rx ||
928 dev->rx_pkt_burst == dpaa2_dev_loopback_rx)
934 * Dpaa2 link Interrupt handler
937 * The address of parameter (struct rte_eth_dev *) regsitered before.
943 dpaa2_interrupt_handler(void *param)
945 struct rte_eth_dev *dev = param;
946 struct dpaa2_dev_priv *priv = dev->data->dev_private;
947 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
949 int irq_index = DPNI_IRQ_INDEX;
950 unsigned int status = 0, clear = 0;
952 PMD_INIT_FUNC_TRACE();
955 DPAA2_PMD_ERR("dpni is NULL");
959 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token,
962 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret);
967 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) {
968 clear = DPNI_IRQ_EVENT_LINK_CHANGED;
969 dpaa2_dev_link_update(dev, 0);
970 /* calling all the apps registered for link status event */
971 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
975 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token,
978 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret);
982 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable)
985 struct dpaa2_dev_priv *priv = dev->data->dev_private;
986 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
987 int irq_index = DPNI_IRQ_INDEX;
988 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED;
990 PMD_INIT_FUNC_TRACE();
992 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token,
995 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err,
1000 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token,
1003 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err,
1010 dpaa2_dev_start(struct rte_eth_dev *dev)
1012 struct rte_device *rdev = dev->device;
1013 struct rte_dpaa2_device *dpaa2_dev;
1014 struct rte_eth_dev_data *data = dev->data;
1015 struct dpaa2_dev_priv *priv = data->dev_private;
1016 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1017 struct dpni_queue cfg;
1018 struct dpni_error_cfg err_cfg;
1020 struct dpni_queue_id qid;
1021 struct dpaa2_queue *dpaa2_q;
1023 struct rte_intr_handle *intr_handle;
1025 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device);
1026 intr_handle = &dpaa2_dev->intr_handle;
1028 PMD_INIT_FUNC_TRACE();
1030 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1032 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d",
1037 /* Power up the phy. Needed to make the link go UP */
1038 dpaa2_dev_set_link_up(dev);
1040 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token,
1041 DPNI_QUEUE_TX, &qdid);
1043 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret);
1048 for (i = 0; i < data->nb_rx_queues; i++) {
1049 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i];
1050 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token,
1051 DPNI_QUEUE_RX, dpaa2_q->tc_index,
1052 dpaa2_q->flow_id, &cfg, &qid);
1054 DPAA2_PMD_ERR("Error in getting flow information: "
1058 dpaa2_q->fqid = qid.fqid;
1061 /*checksum errors, send them to normal path and set it in annotation */
1062 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE;
1063 err_cfg.errors |= DPNI_ERROR_PHE;
1065 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE;
1066 err_cfg.set_frame_annotation = true;
1068 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW,
1069 priv->token, &err_cfg);
1071 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d",
1076 /* if the interrupts were configured on this devices*/
1077 if (intr_handle && (intr_handle->fd) &&
1078 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1079 /* Registering LSC interrupt handler */
1080 rte_intr_callback_register(intr_handle,
1081 dpaa2_interrupt_handler,
1084 /* enable vfio intr/eventfd mapping
1085 * Interrupt index 0 is required, so we can not use
1088 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX);
1090 /* enable dpni_irqs */
1091 dpaa2_eth_setup_irqs(dev, 1);
1094 /* Change the tx burst function if ordered queues are used */
1095 if (priv->en_ordered)
1096 dev->tx_pkt_burst = dpaa2_dev_tx_ordered;
1102 * This routine disables all traffic on the adapter by issuing a
1103 * global reset on the MAC.
1106 dpaa2_dev_stop(struct rte_eth_dev *dev)
1108 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1109 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1111 struct rte_eth_link link;
1112 struct rte_intr_handle *intr_handle = dev->intr_handle;
1114 PMD_INIT_FUNC_TRACE();
1116 /* reset interrupt callback */
1117 if (intr_handle && (intr_handle->fd) &&
1118 (dev->data->dev_conf.intr_conf.lsc != 0)) {
1119 /*disable dpni irqs */
1120 dpaa2_eth_setup_irqs(dev, 0);
1122 /* disable vfio intr before callback unregister */
1123 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX);
1125 /* Unregistering LSC interrupt handler */
1126 rte_intr_callback_unregister(intr_handle,
1127 dpaa2_interrupt_handler,
1131 dpaa2_dev_set_link_down(dev);
1133 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token);
1135 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev",
1140 /* clear the recorded link status */
1141 memset(&link, 0, sizeof(link));
1142 rte_eth_linkstatus_set(dev, &link);
1146 dpaa2_dev_close(struct rte_eth_dev *dev)
1148 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1149 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1151 struct rte_eth_link link;
1153 PMD_INIT_FUNC_TRACE();
1155 dpaa2_flow_clean(dev);
1157 /* Clean the device first */
1158 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token);
1160 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret);
1164 memset(&link, 0, sizeof(link));
1165 rte_eth_linkstatus_set(dev, &link);
1169 dpaa2_dev_promiscuous_enable(
1170 struct rte_eth_dev *dev)
1173 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1174 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1176 PMD_INIT_FUNC_TRACE();
1179 DPAA2_PMD_ERR("dpni is NULL");
1183 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1185 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret);
1187 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1189 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret);
1195 dpaa2_dev_promiscuous_disable(
1196 struct rte_eth_dev *dev)
1199 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1200 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1202 PMD_INIT_FUNC_TRACE();
1205 DPAA2_PMD_ERR("dpni is NULL");
1209 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1211 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret);
1213 if (dev->data->all_multicast == 0) {
1214 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW,
1215 priv->token, false);
1217 DPAA2_PMD_ERR("Unable to disable M promisc mode %d",
1225 dpaa2_dev_allmulticast_enable(
1226 struct rte_eth_dev *dev)
1229 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1230 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1232 PMD_INIT_FUNC_TRACE();
1235 DPAA2_PMD_ERR("dpni is NULL");
1239 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true);
1241 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret);
1247 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev)
1250 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1251 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1253 PMD_INIT_FUNC_TRACE();
1256 DPAA2_PMD_ERR("dpni is NULL");
1260 /* must remain on for all promiscuous */
1261 if (dev->data->promiscuous == 1)
1264 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false);
1266 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret);
1272 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1275 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1276 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1277 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN
1280 PMD_INIT_FUNC_TRACE();
1283 DPAA2_PMD_ERR("dpni is NULL");
1287 /* check that mtu is within the allowed range */
1288 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN)
1291 if (frame_size > RTE_ETHER_MAX_LEN)
1292 dev->data->dev_conf.rxmode.offloads |=
1293 DEV_RX_OFFLOAD_JUMBO_FRAME;
1295 dev->data->dev_conf.rxmode.offloads &=
1296 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1298 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1300 /* Set the Max Rx frame length as 'mtu' +
1301 * Maximum Ethernet header length
1303 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token,
1304 frame_size - RTE_ETHER_CRC_LEN);
1306 DPAA2_PMD_ERR("Setting the max frame length failed");
1309 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu);
1314 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev,
1315 struct rte_ether_addr *addr,
1316 __rte_unused uint32_t index,
1317 __rte_unused uint32_t pool)
1320 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1321 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1323 PMD_INIT_FUNC_TRACE();
1326 DPAA2_PMD_ERR("dpni is NULL");
1330 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token,
1331 addr->addr_bytes, 0, 0, 0);
1334 "error: Adding the MAC ADDR failed: err = %d", ret);
1339 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev,
1343 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1344 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1345 struct rte_eth_dev_data *data = dev->data;
1346 struct rte_ether_addr *macaddr;
1348 PMD_INIT_FUNC_TRACE();
1350 macaddr = &data->mac_addrs[index];
1353 DPAA2_PMD_ERR("dpni is NULL");
1357 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW,
1358 priv->token, macaddr->addr_bytes);
1361 "error: Removing the MAC ADDR failed: err = %d", ret);
1365 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev,
1366 struct rte_ether_addr *addr)
1369 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1370 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1372 PMD_INIT_FUNC_TRACE();
1375 DPAA2_PMD_ERR("dpni is NULL");
1379 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW,
1380 priv->token, addr->addr_bytes);
1384 "error: Setting the MAC ADDR failed %d", ret);
1390 int dpaa2_dev_stats_get(struct rte_eth_dev *dev,
1391 struct rte_eth_stats *stats)
1393 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1394 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1396 uint8_t page0 = 0, page1 = 1, page2 = 2;
1397 union dpni_statistics value;
1399 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq;
1401 memset(&value, 0, sizeof(union dpni_statistics));
1403 PMD_INIT_FUNC_TRACE();
1406 DPAA2_PMD_ERR("dpni is NULL");
1411 DPAA2_PMD_ERR("stats is NULL");
1415 /*Get Counters from page_0*/
1416 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1421 stats->ipackets = value.page_0.ingress_all_frames;
1422 stats->ibytes = value.page_0.ingress_all_bytes;
1424 /*Get Counters from page_1*/
1425 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1430 stats->opackets = value.page_1.egress_all_frames;
1431 stats->obytes = value.page_1.egress_all_bytes;
1433 /*Get Counters from page_2*/
1434 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1439 /* Ingress drop frame count due to configured rules */
1440 stats->ierrors = value.page_2.ingress_filtered_frames;
1441 /* Ingress drop frame count due to error */
1442 stats->ierrors += value.page_2.ingress_discarded_frames;
1444 stats->oerrors = value.page_2.egress_discarded_frames;
1445 stats->imissed = value.page_2.ingress_nobuffer_discards;
1447 /* Fill in per queue stats */
1448 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) &&
1449 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) {
1450 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i];
1451 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i];
1453 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts;
1455 stats->q_opackets[i] = dpaa2_txq->tx_pkts;
1457 /* Byte counting is not implemented */
1458 stats->q_ibytes[i] = 0;
1459 stats->q_obytes[i] = 0;
1465 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1470 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1473 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1474 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1476 union dpni_statistics value[5] = {};
1477 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings);
1485 /* Get Counters from page_0*/
1486 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1491 /* Get Counters from page_1*/
1492 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1497 /* Get Counters from page_2*/
1498 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1503 for (i = 0; i < priv->max_cgs; i++) {
1504 if (!priv->cgid_in_use[i]) {
1505 /* Get Counters from page_4*/
1506 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW,
1515 for (i = 0; i < num; i++) {
1517 xstats[i].value = value[dpaa2_xstats_strings[i].page_id].
1518 raw.counter[dpaa2_xstats_strings[i].stats_id];
1522 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode);
1527 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1528 struct rte_eth_xstat_name *xstats_names,
1531 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1533 if (limit < stat_cnt)
1536 if (xstats_names != NULL)
1537 for (i = 0; i < stat_cnt; i++)
1538 strlcpy(xstats_names[i].name,
1539 dpaa2_xstats_strings[i].name,
1540 sizeof(xstats_names[i].name));
1546 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
1547 uint64_t *values, unsigned int n)
1549 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1550 uint64_t values_copy[stat_cnt];
1553 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1554 struct fsl_mc_io *dpni =
1555 (struct fsl_mc_io *)dev->process_private;
1557 union dpni_statistics value[5] = {};
1565 /* Get Counters from page_0*/
1566 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1571 /* Get Counters from page_1*/
1572 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1577 /* Get Counters from page_2*/
1578 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1583 /* Get Counters from page_4*/
1584 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token,
1589 for (i = 0; i < stat_cnt; i++) {
1590 values[i] = value[dpaa2_xstats_strings[i].page_id].
1591 raw.counter[dpaa2_xstats_strings[i].stats_id];
1596 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt);
1598 for (i = 0; i < n; i++) {
1599 if (ids[i] >= stat_cnt) {
1600 DPAA2_PMD_ERR("xstats id value isn't valid");
1603 values[i] = values_copy[ids[i]];
1609 dpaa2_xstats_get_names_by_id(
1610 struct rte_eth_dev *dev,
1611 struct rte_eth_xstat_name *xstats_names,
1612 const uint64_t *ids,
1615 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings);
1616 struct rte_eth_xstat_name xstats_names_copy[stat_cnt];
1619 return dpaa2_xstats_get_names(dev, xstats_names, limit);
1621 dpaa2_xstats_get_names(dev, xstats_names_copy, limit);
1623 for (i = 0; i < limit; i++) {
1624 if (ids[i] >= stat_cnt) {
1625 DPAA2_PMD_ERR("xstats id value isn't valid");
1628 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
1634 dpaa2_dev_stats_reset(struct rte_eth_dev *dev)
1636 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1637 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1640 struct dpaa2_queue *dpaa2_q;
1642 PMD_INIT_FUNC_TRACE();
1645 DPAA2_PMD_ERR("dpni is NULL");
1649 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token);
1653 /* Reset the per queue stats in dpaa2_queue structure */
1654 for (i = 0; i < priv->nb_rx_queues; i++) {
1655 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i];
1657 dpaa2_q->rx_pkts = 0;
1660 for (i = 0; i < priv->nb_tx_queues; i++) {
1661 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i];
1663 dpaa2_q->tx_pkts = 0;
1669 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode);
1673 /* return 0 means link status changed, -1 means not changed */
1675 dpaa2_dev_link_update(struct rte_eth_dev *dev,
1676 int wait_to_complete __rte_unused)
1679 struct dpaa2_dev_priv *priv = dev->data->dev_private;
1680 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
1681 struct rte_eth_link link;
1682 struct dpni_link_state state = {0};
1685 DPAA2_PMD_ERR("dpni is NULL");
1689 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1691 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret);
1695 memset(&link, 0, sizeof(struct rte_eth_link));
1696 link.link_status = state.up;
1697 link.link_speed = state.rate;
1699 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX)
1700 link.link_duplex = ETH_LINK_HALF_DUPLEX;
1702 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1704 ret = rte_eth_linkstatus_set(dev, &link);
1706 DPAA2_PMD_DEBUG("No change in status");
1708 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id,
1709 link.link_status ? "Up" : "Down");
1715 * Toggle the DPNI to enable, if not already enabled.
1716 * This is not strictly PHY up/down - it is more of logical toggling.
1719 dpaa2_dev_set_link_up(struct rte_eth_dev *dev)
1722 struct dpaa2_dev_priv *priv;
1723 struct fsl_mc_io *dpni;
1725 struct dpni_link_state state = {0};
1727 priv = dev->data->dev_private;
1728 dpni = (struct fsl_mc_io *)dev->process_private;
1731 DPAA2_PMD_ERR("dpni is NULL");
1735 /* Check if DPNI is currently enabled */
1736 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en);
1738 /* Unable to obtain dpni status; Not continuing */
1739 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1743 /* Enable link if not already enabled */
1745 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token);
1747 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret);
1751 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1753 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret);
1757 /* changing tx burst function to start enqueues */
1758 dev->tx_pkt_burst = dpaa2_dev_tx;
1759 dev->data->dev_link.link_status = state.up;
1762 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id);
1764 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id);
1769 * Toggle the DPNI to disable, if not already disabled.
1770 * This is not strictly PHY up/down - it is more of logical toggling.
1773 dpaa2_dev_set_link_down(struct rte_eth_dev *dev)
1776 struct dpaa2_dev_priv *priv;
1777 struct fsl_mc_io *dpni;
1778 int dpni_enabled = 0;
1781 PMD_INIT_FUNC_TRACE();
1783 priv = dev->data->dev_private;
1784 dpni = (struct fsl_mc_io *)dev->process_private;
1787 DPAA2_PMD_ERR("Device has not yet been configured");
1791 /*changing tx burst function to avoid any more enqueues */
1792 dev->tx_pkt_burst = dummy_dev_tx;
1794 /* Loop while dpni_disable() attempts to drain the egress FQs
1795 * and confirm them back to us.
1798 ret = dpni_disable(dpni, 0, priv->token);
1800 DPAA2_PMD_ERR("dpni disable failed (%d)", ret);
1803 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled);
1805 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret);
1809 /* Allow the MC some slack */
1810 rte_delay_us(100 * 1000);
1811 } while (dpni_enabled && --retries);
1814 DPAA2_PMD_WARN("Retry count exceeded disabling dpni");
1815 /* todo- we may have to manually cleanup queues.
1818 DPAA2_PMD_INFO("Port %d Link DOWN successful",
1819 dev->data->port_id);
1822 dev->data->dev_link.link_status = 0;
1828 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1831 struct dpaa2_dev_priv *priv;
1832 struct fsl_mc_io *dpni;
1833 struct dpni_link_state state = {0};
1835 PMD_INIT_FUNC_TRACE();
1837 priv = dev->data->dev_private;
1838 dpni = (struct fsl_mc_io *)dev->process_private;
1840 if (dpni == NULL || fc_conf == NULL) {
1841 DPAA2_PMD_ERR("device not configured");
1845 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1847 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret);
1851 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf));
1852 if (state.options & DPNI_LINK_OPT_PAUSE) {
1853 /* DPNI_LINK_OPT_PAUSE set
1854 * if ASYM_PAUSE not set,
1855 * RX Side flow control (handle received Pause frame)
1856 * TX side flow control (send Pause frame)
1857 * if ASYM_PAUSE set,
1858 * RX Side flow control (handle received Pause frame)
1859 * No TX side flow control (send Pause frame disabled)
1861 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE))
1862 fc_conf->mode = RTE_FC_FULL;
1864 fc_conf->mode = RTE_FC_RX_PAUSE;
1866 /* DPNI_LINK_OPT_PAUSE not set
1867 * if ASYM_PAUSE set,
1868 * TX side flow control (send Pause frame)
1869 * No RX side flow control (No action on pause frame rx)
1870 * if ASYM_PAUSE not set,
1871 * Flow control disabled
1873 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE)
1874 fc_conf->mode = RTE_FC_TX_PAUSE;
1876 fc_conf->mode = RTE_FC_NONE;
1883 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1886 struct dpaa2_dev_priv *priv;
1887 struct fsl_mc_io *dpni;
1888 struct dpni_link_state state = {0};
1889 struct dpni_link_cfg cfg = {0};
1891 PMD_INIT_FUNC_TRACE();
1893 priv = dev->data->dev_private;
1894 dpni = (struct fsl_mc_io *)dev->process_private;
1897 DPAA2_PMD_ERR("dpni is NULL");
1901 /* It is necessary to obtain the current state before setting fc_conf
1902 * as MC would return error in case rate, autoneg or duplex values are
1905 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state);
1907 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret);
1911 /* Disable link before setting configuration */
1912 dpaa2_dev_set_link_down(dev);
1914 /* Based on fc_conf, update cfg */
1915 cfg.rate = state.rate;
1916 cfg.options = state.options;
1918 /* update cfg with fc_conf */
1919 switch (fc_conf->mode) {
1921 /* Full flow control;
1922 * OPT_PAUSE set, ASYM_PAUSE not set
1924 cfg.options |= DPNI_LINK_OPT_PAUSE;
1925 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1927 case RTE_FC_TX_PAUSE:
1928 /* Enable RX flow control
1929 * OPT_PAUSE not set;
1932 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1933 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1935 case RTE_FC_RX_PAUSE:
1936 /* Enable TX Flow control
1940 cfg.options |= DPNI_LINK_OPT_PAUSE;
1941 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE;
1944 /* Disable Flow control
1946 * ASYM_PAUSE not set
1948 cfg.options &= ~DPNI_LINK_OPT_PAUSE;
1949 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE;
1952 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)",
1957 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg);
1959 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)",
1963 dpaa2_dev_set_link_up(dev);
1969 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev,
1970 struct rte_eth_rss_conf *rss_conf)
1972 struct rte_eth_dev_data *data = dev->data;
1973 struct rte_eth_conf *eth_conf = &data->dev_conf;
1976 PMD_INIT_FUNC_TRACE();
1978 if (rss_conf->rss_hf) {
1979 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf);
1981 DPAA2_PMD_ERR("Unable to set flow dist");
1985 ret = dpaa2_remove_flow_dist(dev, 0);
1987 DPAA2_PMD_ERR("Unable to remove flow dist");
1991 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf;
1996 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
1997 struct rte_eth_rss_conf *rss_conf)
1999 struct rte_eth_dev_data *data = dev->data;
2000 struct rte_eth_conf *eth_conf = &data->dev_conf;
2002 /* dpaa2 does not support rss_key, so length should be 0*/
2003 rss_conf->rss_key_len = 0;
2004 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf;
2008 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev,
2009 int eth_rx_queue_id,
2010 struct dpaa2_dpcon_dev *dpcon,
2011 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
2013 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2014 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2015 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2016 uint8_t flow_id = dpaa2_ethq->flow_id;
2017 struct dpni_queue cfg;
2018 uint8_t options, priority;
2021 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL)
2022 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event;
2023 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC)
2024 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event;
2025 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED)
2026 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event;
2030 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) *
2031 (dpcon->num_priorities - 1);
2033 memset(&cfg, 0, sizeof(struct dpni_queue));
2034 options = DPNI_QUEUE_OPT_DEST;
2035 cfg.destination.type = DPNI_DEST_DPCON;
2036 cfg.destination.id = dpcon->dpcon_id;
2037 cfg.destination.priority = priority;
2039 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) {
2040 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE;
2041 cfg.destination.hold_active = 1;
2044 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED &&
2045 !eth_priv->en_ordered) {
2046 struct opr_cfg ocfg;
2048 /* Restoration window size = 256 frames */
2050 /* Restoration window size = 512 frames for LX2 */
2051 if (dpaa2_svr_family == SVR_LX2160A)
2053 /* Auto advance NESN window enabled */
2055 /* Late arrival window size disabled */
2057 /* ORL resource exhaustaion advance NESN disabled */
2059 /* Loose ordering enabled */
2061 eth_priv->en_loose_ordered = 1;
2062 /* Strict ordering enabled if explicitly set */
2063 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) {
2065 eth_priv->en_loose_ordered = 0;
2068 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token,
2069 dpaa2_ethq->tc_index, flow_id,
2070 OPR_OPT_CREATE, &ocfg);
2072 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret);
2076 eth_priv->en_ordered = 1;
2079 options |= DPNI_QUEUE_OPT_USER_CTX;
2080 cfg.user_context = (size_t)(dpaa2_ethq);
2082 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2083 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2085 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2089 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event));
2094 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev,
2095 int eth_rx_queue_id)
2097 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private;
2098 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private;
2099 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id];
2100 uint8_t flow_id = dpaa2_ethq->flow_id;
2101 struct dpni_queue cfg;
2105 memset(&cfg, 0, sizeof(struct dpni_queue));
2106 options = DPNI_QUEUE_OPT_DEST;
2107 cfg.destination.type = DPNI_DEST_NONE;
2109 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX,
2110 dpaa2_ethq->tc_index, flow_id, options, &cfg);
2112 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret);
2118 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op)
2122 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) {
2123 if (dpaa2_supported_filter_ops[i] == filter_op)
2130 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev,
2131 enum rte_filter_type filter_type,
2132 enum rte_filter_op filter_op,
2140 switch (filter_type) {
2141 case RTE_ETH_FILTER_GENERIC:
2142 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) {
2146 *(const void **)arg = &dpaa2_flow_ops;
2147 dpaa2_filter_type |= filter_type;
2150 RTE_LOG(ERR, PMD, "Filter type (%d) not supported",
2158 static struct eth_dev_ops dpaa2_ethdev_ops = {
2159 .dev_configure = dpaa2_eth_dev_configure,
2160 .dev_start = dpaa2_dev_start,
2161 .dev_stop = dpaa2_dev_stop,
2162 .dev_close = dpaa2_dev_close,
2163 .promiscuous_enable = dpaa2_dev_promiscuous_enable,
2164 .promiscuous_disable = dpaa2_dev_promiscuous_disable,
2165 .allmulticast_enable = dpaa2_dev_allmulticast_enable,
2166 .allmulticast_disable = dpaa2_dev_allmulticast_disable,
2167 .dev_set_link_up = dpaa2_dev_set_link_up,
2168 .dev_set_link_down = dpaa2_dev_set_link_down,
2169 .link_update = dpaa2_dev_link_update,
2170 .stats_get = dpaa2_dev_stats_get,
2171 .xstats_get = dpaa2_dev_xstats_get,
2172 .xstats_get_by_id = dpaa2_xstats_get_by_id,
2173 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id,
2174 .xstats_get_names = dpaa2_xstats_get_names,
2175 .stats_reset = dpaa2_dev_stats_reset,
2176 .xstats_reset = dpaa2_dev_stats_reset,
2177 .fw_version_get = dpaa2_fw_version_get,
2178 .dev_infos_get = dpaa2_dev_info_get,
2179 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get,
2180 .mtu_set = dpaa2_dev_mtu_set,
2181 .vlan_filter_set = dpaa2_vlan_filter_set,
2182 .vlan_offload_set = dpaa2_vlan_offload_set,
2183 .vlan_tpid_set = dpaa2_vlan_tpid_set,
2184 .rx_queue_setup = dpaa2_dev_rx_queue_setup,
2185 .rx_queue_release = dpaa2_dev_rx_queue_release,
2186 .tx_queue_setup = dpaa2_dev_tx_queue_setup,
2187 .tx_queue_release = dpaa2_dev_tx_queue_release,
2188 .rx_queue_count = dpaa2_dev_rx_queue_count,
2189 .flow_ctrl_get = dpaa2_flow_ctrl_get,
2190 .flow_ctrl_set = dpaa2_flow_ctrl_set,
2191 .mac_addr_add = dpaa2_dev_add_mac_addr,
2192 .mac_addr_remove = dpaa2_dev_remove_mac_addr,
2193 .mac_addr_set = dpaa2_dev_set_mac_addr,
2194 .rss_hash_update = dpaa2_dev_rss_hash_update,
2195 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get,
2196 .filter_ctrl = dpaa2_dev_flow_ctrl,
2197 #if defined(RTE_LIBRTE_IEEE1588)
2198 .timesync_enable = dpaa2_timesync_enable,
2199 .timesync_disable = dpaa2_timesync_disable,
2200 .timesync_read_time = dpaa2_timesync_read_time,
2201 .timesync_write_time = dpaa2_timesync_write_time,
2202 .timesync_adjust_time = dpaa2_timesync_adjust_time,
2203 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp,
2204 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp,
2208 /* Populate the mac address from physically available (u-boot/firmware) and/or
2209 * one set by higher layers like MC (restool) etc.
2210 * Returns the table of MAC entries (multiple entries)
2213 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv,
2214 struct rte_ether_addr *mac_entry)
2217 struct rte_ether_addr phy_mac, prime_mac;
2219 memset(&phy_mac, 0, sizeof(struct rte_ether_addr));
2220 memset(&prime_mac, 0, sizeof(struct rte_ether_addr));
2222 /* Get the physical device MAC address */
2223 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2224 phy_mac.addr_bytes);
2226 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret);
2230 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token,
2231 prime_mac.addr_bytes);
2233 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret);
2237 /* Now that both MAC have been obtained, do:
2238 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy
2240 * If empty_mac(phy), return prime.
2241 * if both are empty, create random MAC, set as prime and return
2243 if (!rte_is_zero_ether_addr(&phy_mac)) {
2244 /* If the addresses are not same, overwrite prime */
2245 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) {
2246 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2248 phy_mac.addr_bytes);
2250 DPAA2_PMD_ERR("Unable to set MAC Address: %d",
2254 memcpy(&prime_mac, &phy_mac,
2255 sizeof(struct rte_ether_addr));
2257 } else if (rte_is_zero_ether_addr(&prime_mac)) {
2258 /* In case phys and prime, both are zero, create random MAC */
2259 rte_eth_random_addr(prime_mac.addr_bytes);
2260 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW,
2262 prime_mac.addr_bytes);
2264 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret);
2269 /* prime_mac the final MAC address */
2270 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr));
2278 check_devargs_handler(__rte_unused const char *key, const char *value,
2279 __rte_unused void *opaque)
2281 if (strcmp(value, "1"))
2288 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key)
2290 struct rte_kvargs *kvlist;
2295 kvlist = rte_kvargs_parse(devargs->args, NULL);
2299 if (!rte_kvargs_count(kvlist, key)) {
2300 rte_kvargs_free(kvlist);
2304 if (rte_kvargs_process(kvlist, key,
2305 check_devargs_handler, NULL) < 0) {
2306 rte_kvargs_free(kvlist);
2309 rte_kvargs_free(kvlist);
2315 dpaa2_dev_init(struct rte_eth_dev *eth_dev)
2317 struct rte_device *dev = eth_dev->device;
2318 struct rte_dpaa2_device *dpaa2_dev;
2319 struct fsl_mc_io *dpni_dev;
2320 struct dpni_attr attr;
2321 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2322 struct dpni_buffer_layout layout;
2325 PMD_INIT_FUNC_TRACE();
2327 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0);
2329 DPAA2_PMD_ERR("Memory allocation failed for dpni device");
2332 dpni_dev->regs = rte_mcp_ptr_list[0];
2333 eth_dev->process_private = (void *)dpni_dev;
2335 /* For secondary processes, the primary has done all the work */
2336 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2337 /* In case of secondary, only burst and ops API need to be
2340 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2341 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE))
2342 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2343 else if (dpaa2_get_devargs(dev->devargs,
2344 DRIVER_NO_PREFETCH_MODE))
2345 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2347 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2348 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2352 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device);
2354 hw_id = dpaa2_dev->object_id;
2355 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token);
2358 "Failure in opening dpni@%d with err code %d",
2364 /* Clean the device first */
2365 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token);
2367 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d",
2372 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr);
2375 "Failure in get dpni@%d attribute, err code %d",
2380 priv->num_rx_tc = attr.num_rx_tcs;
2381 /* only if the custom CG is enabled */
2382 if (attr.options & DPNI_OPT_CUSTOM_CG)
2383 priv->max_cgs = attr.num_cgs;
2387 for (i = 0; i < priv->max_cgs; i++)
2388 priv->cgid_in_use[i] = 0;
2390 for (i = 0; i < attr.num_rx_tcs; i++)
2391 priv->nb_rx_queues += attr.num_queues;
2393 /* Using number of TX queues as number of TX TCs */
2394 priv->nb_tx_queues = attr.num_tx_tcs;
2396 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d",
2397 priv->num_rx_tc, priv->nb_rx_queues,
2398 priv->nb_tx_queues, priv->max_cgs);
2400 priv->hw = dpni_dev;
2401 priv->hw_id = hw_id;
2402 priv->options = attr.options;
2403 priv->max_mac_filters = attr.mac_filter_entries;
2404 priv->max_vlan_filters = attr.vlan_filter_entries;
2406 #if defined(RTE_LIBRTE_IEEE1588)
2407 priv->tx_conf_en = 1;
2409 priv->tx_conf_en = 0;
2412 /* Allocate memory for hardware structure for queues */
2413 ret = dpaa2_alloc_rx_tx_queues(eth_dev);
2415 DPAA2_PMD_ERR("Queue allocation Failed");
2419 /* Allocate memory for storing MAC addresses.
2420 * Table of mac_filter_entries size is allocated so that RTE ether lib
2421 * can add MAC entries when rte_eth_dev_mac_addr_add is called.
2423 eth_dev->data->mac_addrs = rte_zmalloc("dpni",
2424 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0);
2425 if (eth_dev->data->mac_addrs == NULL) {
2427 "Failed to allocate %d bytes needed to store MAC addresses",
2428 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries);
2433 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]);
2435 DPAA2_PMD_ERR("Unable to fetch MAC Address for device");
2436 rte_free(eth_dev->data->mac_addrs);
2437 eth_dev->data->mac_addrs = NULL;
2441 /* ... tx buffer layout ... */
2442 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2443 if (priv->tx_conf_en) {
2444 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2445 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2446 layout.pass_timestamp = true;
2448 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2450 layout.pass_frame_status = 1;
2451 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2452 DPNI_QUEUE_TX, &layout);
2454 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret);
2458 /* ... tx-conf and error buffer layout ... */
2459 memset(&layout, 0, sizeof(struct dpni_buffer_layout));
2460 if (priv->tx_conf_en) {
2461 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS |
2462 DPNI_BUF_LAYOUT_OPT_TIMESTAMP;
2463 layout.pass_timestamp = true;
2465 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS;
2467 layout.pass_frame_status = 1;
2468 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token,
2469 DPNI_QUEUE_TX_CONFIRM, &layout);
2471 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout",
2476 eth_dev->dev_ops = &dpaa2_ethdev_ops;
2478 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) {
2479 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx;
2480 DPAA2_PMD_INFO("Loopback mode");
2481 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) {
2482 eth_dev->rx_pkt_burst = dpaa2_dev_rx;
2483 DPAA2_PMD_INFO("No Prefetch mode");
2485 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx;
2487 eth_dev->tx_pkt_burst = dpaa2_dev_tx;
2489 /*Init fields w.r.t. classficaition*/
2490 memset(&priv->extract.qos_key_cfg, 0, sizeof(struct dpkg_profile_cfg));
2491 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64);
2492 if (!priv->extract.qos_extract_param) {
2493 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow "
2494 " classificaiton ", ret);
2497 for (i = 0; i < MAX_TCS; i++) {
2498 memset(&priv->extract.fs_key_cfg[i], 0,
2499 sizeof(struct dpkg_profile_cfg));
2500 priv->extract.fs_extract_param[i] =
2501 (size_t)rte_malloc(NULL, 256, 64);
2502 if (!priv->extract.fs_extract_param[i]) {
2503 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton",
2509 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token,
2510 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN
2513 DPAA2_PMD_ERR("Unable to set mtu. check config");
2517 /*TODO To enable soft parser support DPAA2 driver needs to integrate
2518 * with external entity to receive byte code for software sequence
2519 * and same will be offload to the H/W using MC interface.
2520 * Currently it is assumed that DPAA2 driver has byte code by some
2521 * mean and same if offloaded to H/W.
2523 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
2524 WRIOP_SS_INITIALIZER(priv);
2525 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
2527 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
2532 ret = dpaa2_eth_enable_wriop_soft_parser(priv,
2535 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
2540 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
2543 dpaa2_dev_uninit(eth_dev);
2548 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev)
2550 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private;
2551 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_dev->process_private;
2554 PMD_INIT_FUNC_TRACE();
2556 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2560 DPAA2_PMD_WARN("Already closed or not started");
2564 dpaa2_dev_close(eth_dev);
2566 dpaa2_free_rx_tx_queues(eth_dev);
2568 /* Close the device at underlying layer*/
2569 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token);
2572 "Failure closing dpni device with err code %d",
2576 /* Free the allocated memory for ethernet private data and dpni*/
2578 eth_dev->process_private = NULL;
2581 for (i = 0; i < MAX_TCS; i++) {
2582 if (priv->extract.fs_extract_param[i])
2583 rte_free((void *)(size_t)priv->extract.fs_extract_param[i]);
2586 if (priv->extract.qos_extract_param)
2587 rte_free((void *)(size_t)priv->extract.qos_extract_param);
2589 eth_dev->dev_ops = NULL;
2590 eth_dev->rx_pkt_burst = NULL;
2591 eth_dev->tx_pkt_burst = NULL;
2593 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name);
2598 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv,
2599 struct rte_dpaa2_device *dpaa2_dev)
2601 struct rte_eth_dev *eth_dev;
2602 struct dpaa2_dev_priv *dev_priv;
2605 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) >
2606 RTE_PKTMBUF_HEADROOM) {
2608 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)",
2609 RTE_PKTMBUF_HEADROOM,
2610 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE);
2615 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2616 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name);
2619 dev_priv = rte_zmalloc("ethdev private structure",
2620 sizeof(struct dpaa2_dev_priv),
2621 RTE_CACHE_LINE_SIZE);
2622 if (dev_priv == NULL) {
2624 "Unable to allocate memory for private data");
2625 rte_eth_dev_release_port(eth_dev);
2628 eth_dev->data->dev_private = (void *)dev_priv;
2629 /* Store a pointer to eth_dev in dev_private */
2630 dev_priv->eth_dev = eth_dev;
2631 dev_priv->tx_conf_en = 0;
2633 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name);
2635 DPAA2_PMD_DEBUG("returning enodev");
2640 eth_dev->device = &dpaa2_dev->device;
2642 dpaa2_dev->eth_dev = eth_dev;
2643 eth_dev->data->rx_mbuf_alloc_failed = 0;
2645 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC)
2646 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC;
2648 /* Invoke PMD device initialization function */
2649 diag = dpaa2_dev_init(eth_dev);
2651 rte_eth_dev_probing_finish(eth_dev);
2655 rte_eth_dev_release_port(eth_dev);
2660 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev)
2662 struct rte_eth_dev *eth_dev;
2664 eth_dev = dpaa2_dev->eth_dev;
2665 dpaa2_dev_uninit(eth_dev);
2667 rte_eth_dev_release_port(eth_dev);
2672 static struct rte_dpaa2_driver rte_dpaa2_pmd = {
2673 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA,
2674 .drv_type = DPAA2_ETH,
2675 .probe = rte_dpaa2_probe,
2676 .remove = rte_dpaa2_remove,
2679 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd);
2680 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2,
2681 DRIVER_LOOPBACK_MODE "=<int> "
2682 DRIVER_NO_PREFETCH_MODE "=<int>");
2683 RTE_INIT(dpaa2_pmd_init_log)
2685 dpaa2_logtype_pmd = rte_log_register("pmd.net.dpaa2");
2686 if (dpaa2_logtype_pmd >= 0)
2687 rte_log_set_level(dpaa2_logtype_pmd, RTE_LOG_NOTICE);